CN111224575A - Inverter circuit - Google Patents

Inverter circuit Download PDF

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Publication number
CN111224575A
CN111224575A CN202010042144.9A CN202010042144A CN111224575A CN 111224575 A CN111224575 A CN 111224575A CN 202010042144 A CN202010042144 A CN 202010042144A CN 111224575 A CN111224575 A CN 111224575A
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China
Prior art keywords
switch
capacitor
circuit
sub
inductor
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CN202010042144.9A
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Chinese (zh)
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CN111224575B (en
Inventor
王含冠
刘圆圆
舒天宇
贾河顺
赵建国
李帅
方帅
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Yuanshan Jinan Electronic Technology Co ltd
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Beijing Tianyue Jingcheng Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Abstract

The application discloses inverter circuit to solve the problem that current low pass filter is bulky and limited by mains voltage. The inverter circuit comprises a primary circuit and a secondary circuit, wherein a first switch and a second switch in the primary circuit are connected with a power supply in series; one end of the first inductor is connected with the first switch and the second switch, and the other end of the first inductor is connected with the power supply; one end of the first capacitor is connected with the power supply, and the other end of the first capacitor is connected with the second switch; one end of the second capacitor is connected with the power supply, and the other end of the second capacitor is connected with the second switch. The secondary circuit comprises a plurality of sub-circuits; the sub-circuit comprises a full-bridge switch group, a sub-module and an output capacitor; a third switch and a fourth switch in the sub-module are connected with the full-bridge switch group in series; one end of the third capacitor is connected with the third switch, and the other end of the third capacitor is connected with the fourth switch; one end of the second inductor is connected with the third switch and the fourth switch, and the other end of the second inductor is connected with the first output capacitor; one end of the output capacitor is connected with the second inductor, and the other end of the output capacitor is connected with the full-bridge type switch group.

Description

Inverter circuit
Technical Field
The present application relates to the field of electronic circuits, and more particularly, to an inverter circuit.
Background
An inverter is a power electronic device that converts direct current into alternating current, and has a very wide range of applications. For example, photovoltaic applications, motor drive applications, and the like.
At present, during the current conversion process, the inverter generally adopts a sinusoidal pulse width modulation method, obtains power from a constant direct current voltage source, and generates an alternating current voltage with amplitude lower than that of the direct current voltage source. Generally, the inverter needs to be used in combination with a low-pass filter, which processes the ac voltage generated by the inverter to adjust the square wave to a sine wave.
However, since the conventional non-multilevel bridge inverter circuit can only generate a square wave with a fixed peak value and a variable pulse width on the inverter side, as shown in fig. 1. Therefore, in order to adjust the square wave to a sine wave, a large low-pass filter is required, and the total harmonic distortion ratio is also large. Furthermore, when the voltage of the dc power supply is low, the maximum amplitude of the generated ac voltage is greatly limited.
Disclosure of Invention
The embodiment of the application provides an inverter circuit, which is used for solving the problems that the existing low-pass filter is large in size and limited by power supply voltage.
The inverter circuit provided by the embodiment of the application comprises a primary circuit and a secondary circuit:
the primary circuit includes a direct current power supply, a first switch (Q17), a second switch (Q18), a first inductor (L1), a first capacitor (C1), and a second capacitor (C2);
the first switch and the second switch are connected with the direct current power supply in series; one end of the first inductor is connected with the first switch and the second switch respectively, and the other end of the first inductor is connected with the direct-current power supply; one end of the first capacitor is connected with the direct-current power supply, and the other end of the first capacitor is connected with the second switch; one end of the second capacitor is connected with the direct-current power supply, and the other end of the second capacitor is connected with the second switch;
the secondary circuit comprises a plurality of sub-circuits; each sub-circuit comprises a full-bridge switch group, a sub-module, an output capacitor (C5);
the submodule comprises a third switch (Q5), a fourth switch (Q6), a third capacitor (C3) and a second inductor (L2), and the third switch and the fourth switch are connected in series to be connected with the first end of the full-bridge switch group; one end of the third capacitor is connected with the third switch, and the other end of the third capacitor is connected with the fourth switch; one end of the second inductor is connected with the third switch and the fourth switch respectively, and the other end of the second inductor is connected with the output capacitor; and one end of the output capacitor is connected with the second end of the full-bridge type switch group.
The embodiment of the application provides an inverter circuit, which can boost the voltage of a direct current power supply through the design of a primary circuit, so as to generate a higher and stable direct current voltage at the output end of the primary circuit. This makes it possible to increase the amplitude of the output voltage of the inverter circuit without the amplitude of the output voltage of the inverter circuit being limited by the voltage of the direct-current power supply. Through the control of the submodule in the secondary circuit, the secondary circuit can output voltages with different amplitudes and generate a step voltage waveform with a plurality of peak values similar to a sine waveform. Therefore, the processing of the inverter circuit on the output waveform is simplified, the size of the inverter is reduced, the total harmonic distortion rate is reduced, and part of the structure of the circuit can be flexibly set according to the requirement.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.
In the drawings:
FIG. 1 is a schematic diagram of an AC square wave output by a conventional bridge inverter;
fig. 2 is a schematic diagram of an inverter circuit provided in an embodiment of the present application;
fig. 3 is a first-stage circuit schematic diagram of an inverter circuit provided in an embodiment of the present application;
fig. 4 is a schematic diagram of a two-stage circuit of an inverter circuit provided in an embodiment of the present application;
fig. 5 is a schematic diagram of input and output voltages of a primary circuit of an inverter provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of the working components of the secondary circuit provided in the embodiment of the present application in a state of an input-output voltage conversion ratio;
FIG. 7 is a schematic diagram of an operating component of a secondary circuit according to an embodiment of the present disclosure in another input-output voltage conversion ratio state;
FIG. 8 is a schematic diagram of an operating component of a secondary circuit according to an embodiment of the present disclosure in another input-output voltage conversion ratio state;
FIG. 9 is a schematic diagram of an operating component of a secondary circuit according to an embodiment of the present disclosure in another input-output voltage conversion ratio state;
FIG. 10 is a schematic diagram of an operating component of a secondary circuit according to an embodiment of the present disclosure in another state of input-output voltage conversion ratio;
FIG. 11 is a schematic diagram of an operating component of a secondary circuit according to an embodiment of the present disclosure in another input-output voltage conversion ratio state;
FIG. 12(a) is a schematic diagram of waveforms illustrating a ratio of output voltage to input voltage of a secondary circuit according to an embodiment of the present application;
fig. 12(b) is a schematic diagram of an output voltage waveform of the inverter circuit according to the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 2 is a schematic diagram of an inverter circuit provided in an embodiment of the present application, fig. 3 is a schematic diagram of a primary circuit of the inverter circuit provided in the embodiment of the present application, and fig. 4 is a schematic diagram of a secondary circuit of the inverter circuit provided in the embodiment of the present application.
As shown in fig. 2 to 4, the inverter circuit includes a primary circuit and a secondary circuit.
The primary circuit includes a dc power supply, a switch Q17, a switch Q18, an inductor L1, a capacitor C1, and a capacitor C2. The switch Q17 and the switch Q18 are connected with the direct-current power supply in series; one end of the inductor L1 is connected with the switch Q17 and the switch Q18 respectively, and the other end is connected with a direct current power supply; one end of the capacitor C1 is connected with a power supply, and the other end is connected with the switch Q18; capacitor C2 has one end connected to the power supply and the other end connected to switch Q18.
In the working process of the primary circuit, when the switch Q17 is turned on and the switch Q18 is turned off, a closed loop is formed among the direct-current power supply, the switch Q17 and the inductor L1, and the power supply charges the inductor L1, so that a certain amount of energy is stored in the inductor L1. When the switch Q17 is turned off and the switch Q18 is turned on, the capacitor C1 is connected in parallel with the capacitor C2, the power supply is absent in the closed loop, and the inductor L1 discharges power to the circuit, namely, the capacitor C1 and the capacitor C2 are supplied with power. After the inductor L1 supplies power to the capacitor C1 and the capacitor C2, the voltage across the capacitor C1 and the capacitor C2 may be higher than the voltage of the power supply, as shown in fig. 5. In fig. 5, the axis of abscissa indicates time and the axis of ordinate indicates voltage. VbusRepresenting the supply voltage, VmidShowing the voltage across capacitor C1 or capacitor C5, and fig. 5 shows the boosting effect of the primary circuit.
The secondary circuit includes a plurality of sub-circuits, each sub-circuit including a full bridge switch set, a sub-module, and an output capacitor. The embodiment of the present application is described by taking an example that the secondary circuit includes two sub-circuits.
As shown in fig. 2 and 4, the first sub-circuit is the upper half circuit in fig. 4, and the second sub-circuit is the lower half circuit in fig. 4.
In the first sub-circuit, the full-bridge switch set may include a switch Q1, a switch Q2, a switch Q3, and a switch Q4; the switch Q1 is connected in series with the switch Q2, the switch Q3 is connected in series with the switch Q4, and the two sets of switches are connected in parallel across the capacitor C1, respectively.
The sub-modules of the first sub-circuit may comprise a plurality of groups. By setting the number of the sub-modules, the amplitude of the output voltage of the first sub-circuit can be changed, so that the amplitude range of the voltage output by the whole secondary circuit is further changed.
In one possible implementation, the first sub-circuit may comprise two sub-modules. The first submodule may include a switch Q5, a switch Q6, a capacitor C3, and an inductor L2. One end of the switch Q5 is respectively connected with the switch Q3 and the switch Q4, and the other end is connected with the switch Q6; one end of the capacitor C3 is connected with the switch Q5, and the other end is connected with the switch Q6; one end of the inductor L2 is connected to the switch Q5 and the switch Q6, respectively, and the other end is connected to the switch Q7 of the second submodule. The second submodule may include a switch Q7, a switch Q8, a capacitor C4, and an inductor L3. One end of the switch Q7 is connected with the inductor L2 of the first submodule, and the other end is connected with the switch Q8; one end of the capacitor C4 is connected with the switch Q7, and the other end is connected with the switch Q8; inductor L3 has one end connected to switch Q7 and switch Q8, respectively, and the other end connected to output capacitor C5.
One end of the output capacitor C5 is connected to the switch Q1 and the switch Q2, respectively.
Similarly, in the second sub-circuit, the full-bridge switch set includes a switch Q9, a switch Q10, a switch Q11, and a switch Q12; the switch Q9 is connected in series with the switch Q10, the switch Q11 is connected in series with the switch Q12, and the two sets of switches are connected in parallel across the capacitor C2, respectively.
In a possible implementation, the second sub-circuit may also comprise two sub-modules. The first submodule may include a switch Q13, a switch Q14, a capacitor C6, and an inductor L4. One end of the switch Q13 is respectively connected with the switch Q11 and the switch Q12, and the other end is connected with the switch Q14; one end of the capacitor C6 is connected with the switch Q13, and the other end is connected with the switch Q14; one end of the inductor L4 is connected to the switch Q13 and the switch Q14, respectively, and the other end is connected to the switch Q15 of the second submodule. The second submodule may include a switch Q15, a switch Q16, a capacitor C7, and an inductor L5. One end of the switch Q15 is connected with the switch Q16; one end of the capacitor C7 is connected with the switch Q15, and the other end is connected with the switch Q16; inductor L5 has one end connected to switch Q15 and switch Q16, respectively, and the other end connected to output capacitor C8.
One end of the output capacitor C8 is connected to the switch Q9 and the switch Q10, respectively.
In the secondary circuit, taking a sub-module circuit composed of a switch Q5, a switch Q6 and a capacitor C3 as an example, when the switch Q5 is turned on and the switch Q6 is turned off, the capacitor C3 is bypassed, and when the switch Q5 is turned off and the switch Q6 is turned on, the capacitor C3 is connected. Thus, by controlling the conduction or disconnection of the switches in the secondary circuit, the capacitors in the respective sub-modules may be controlled to be connected or bypassed, thereby further controlling the voltage across the output capacitors in the respective sub-circuits.
In the embodiment of the present application, the capacitor and the inductor in the sub-module may constitute a resonant circuit to realize the on and off of the switch by means of soft switching. The current or the voltage can generate electromagnetic field to generate interference to the external circuit due to electromagnetic effect when changing sharply in a short time, and the soft switching technology can avoid the current from generating sharp change at the moment of switching on or switching off the switch, thereby effectively reducing the electromagnetic interference of the switch to the external, improving the electromagnetic compatibility and reducing the power loss of the switch.
In the embodiment of the present application, the present inverter circuit may further include a control unit. The control unit is connected with each switch in the circuit, sends control signals to each switch, controls the on or off of each switch, and controls the generation of the sine alternating current.
Specifically, in the primary circuit, the control unit can control the on/off of the switch Q17 and the switch Q18 to function as a booster in the primary circuit, so that the output voltage of the primary circuit (i.e., the voltage across the capacitor C1 or the capacitor C2) is higher than the voltage of the dc power supply, thereby preventing the output voltage of the inverter control circuit from being limited by the power supply voltage.
In the secondary circuit, the control unit may control the connection or bypassing of the capacitors in each sub-module by sending control signals to the switches of each sub-module, and generate different voltages at the output of the secondary circuit.
The specific implementation mode is as follows:
fig. 6 is a schematic diagram of an operating component of a secondary circuit in a state of an input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 6, during a period of time, the switch Q13 and the switch Q15 are turned on, the capacitor C6 and the capacitor C7 are bypassed, the switch Q5, the switch Q6, the switch Q7 and the switch Q8 are turned on or off, the capacitor C3 and the capacitor C4 are connected or bypassed in the circuit, and the switches Q1 to Q4 and the switches Q9 to Q12 are turned on or off. The voltage amplitude generated across the output capacitor C5 of the first sub-circuit is 3VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 0Vmid. Thus, the secondary circuit generates a signal having an amplitude of +3V at the output (i.e., across capacitor C5 and capacitor C8)midThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 7 is a schematic diagram of an operating component of a secondary circuit in another state of input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 7, during a period of time, the switch Q15 is turned on, the capacitor C7 is bypassed, the switch Q5, the switch Q6, the switch Q7, the switch Q8, the switch Q13, and the switch Q14 are turned on or off, the capacitor C3, the capacitor C4, and the capacitor C6 are connected or bypassed in the circuit, and the switches Q1 to Q4, and the switches Q9 to Q12 are turned on or off. The voltage amplitude generated across the output capacitor C5 of the first sub-circuit is 3VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 1Vmid. Thus, the secondary circuit generates a signal having an amplitude of +2V at the output (i.e., across capacitor C5 and capacitor C8)midThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 8 is a schematic diagram of an operating component of a secondary circuit in another state of input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 8, during a period of time, the switch Q7, the switch Q13 and the switch Q15 are turned on, and the capacitor C4, the capacitor C6 and the capacitor are turned onC7 is bypassed, and the switch Q5 and the switch Q6 are turned on or off to connect or bypass the capacitor C3 in the circuit, and the switches Q1 to Q4 and the switches Q9 to Q12 are turned on or off. The voltage generated across the output capacitor C5 of the first sub-circuit has an amplitude of 1VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 0Vmid. Thus, the secondary circuit generates a signal having an amplitude of +1V at the output (i.e., across capacitor C5 and capacitor C8)midThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 9 is a schematic diagram of an operating component of a secondary circuit in another state of input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 9, during a period of time, the switch Q6, the switch Q7, and the switch Q15 are turned on, the capacitor C3, the capacitor C4, and the capacitor C7 are bypassed, the switch Q13 and the switch Q14 are turned on or off, the capacitor C6 is turned on or bypassed in the circuit, and the switches Q1 to Q4 and the switches Q9 to Q12 are turned on or off. The voltage amplitude generated across the output capacitor C5 of the first sub-circuit is 0VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 1Vmid. Thus, the secondary circuit produces a signal having an amplitude of-1V at the output (i.e., across capacitor C5 and capacitor C8)midThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 10 is a schematic diagram of an operating component of a secondary circuit in another state of input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 10, during a period of time, the switch Q7 is turned on, the capacitor C4 is bypassed, the switch Q5, the switch Q6, the switch Q13, the switch Q14, the switch Q15, and the switch Q16 are turned on or off, the capacitor C3, the capacitor C6, and the capacitor C7 are connected or bypassed in the circuit, and the switches Q1 to Q4, and the switches Q9 to Q12 are turned on or off. The voltage generated across the output capacitor C5 of the first sub-circuit has an amplitude of 1VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 3Vmid. The secondary circuit is then at the output (i.e. the capacitor)Across capacitor C5 and capacitor C8) to have an amplitude of-2VmidThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 11 is a schematic diagram of an operating component of a secondary circuit in another state of input-output voltage conversion ratio according to an embodiment of the present application. As shown in fig. 4 and 11, during a period of time, the switch Q5 and the switch Q7 are turned on, the capacitor C3 and the capacitor C4 are bypassed, the switch Q13, the switch Q14, the switch Q15 and the switch Q16 are turned on or off, the capacitor C6 and the capacitor C7 are connected or bypassed in the circuit, and the switches Q1 to Q4 and the switches Q9 to Q12 are turned on or off. The voltage amplitude generated across the output capacitor C5 of the first sub-circuit is 0VmidThe voltage amplitude generated across the output capacitor C8 of the second sub-circuit is 3Vmid. Thus, the secondary circuit produces a signal having an amplitude of-3V at the output (i.e., across capacitor C5 and capacitor C8)midThe voltage of (c). Wherein, VmidRepresenting the voltage across capacitor C1 or capacitor C2.
Fig. 12(a) is a waveform diagram illustrating a ratio of an output voltage to an input voltage of a secondary circuit according to an embodiment of the present application. In fig. 12(a), the axis of abscissa indicates time, and the axis of ordinate indicates the output voltage VoutAnd a primary circuit voltage VmidThe ratio of (a) to (b). As described above, in the embodiment of the present application, according to the control of the switches in the secondary circuit by the control unit, the output terminal of the secondary circuit can generate +3V with amplitudemid、+2Vmid、+1Vmid、-3Vmid、-2Vmid、-1VmidThe voltage of (c). Wherein, VoutRepresenting the output voltage of the secondary circuit, i.e., the voltage across capacitors C5 and C8.
Further, as shown in fig. 2, a total output capacitor C9 may also be included in the present inverter circuit. The total output capacitor C9 has one end connected to the inductor L6 and the other end connected to the inductor L7. The inductor L6 is connected to the output capacitor C5 of the first sub-circuit, and the inductor L7 is connected to the output capacitor C8 of the second sub-circuit.
The inductor L6, the inductor L7 and the total output capacitor C9 can form a low-pass filterAnd processing the voltage generated by the secondary circuit. As shown in fig. 12(a), the voltage waveform generated by the secondary circuit is a staircase-shaped electric wave having a plurality of peaks. The stepped electric wave can be processed into a sine wave by the processing of a low-pass filter composed of an inductor L6, an inductor L7, and a total output capacitor C9. Fig. 12(b) is a schematic voltage waveform generated by the inverter circuit according to the embodiment of the present application. In fig. 12(b), the axis of abscissa indicates time, and the axis of ordinate indicates the output voltage V of the inverter circuitac。
In the embodiment of the present application, through the design of the primary circuit in the inverter circuit, the dc power supply with a lower voltage can be boosted to obtain an output voltage of the higher primary circuit. And, the low pass filter composed of the capacitor C1, the capacitor C2 and the inductor L1 can process the fluctuating voltage of the dc power supply to form a stable dc voltage between the primary circuit and the secondary circuit. By the mode, the input voltage of the secondary circuit can be increased, so that the amplitude of the output voltage of the secondary circuit is increased, and the amplitude of the output voltage of the secondary circuit is not limited by the power supply voltage.
Through the design of a secondary circuit in the inverter circuit, the control unit controls the switches in each submodule, so that the communication and the bypass of the corresponding capacitor are controlled, different voltage amplitudes generated by the secondary circuit are further controlled, and a sine waveform is generated.
As shown in fig. 12(a), the voltage waveform output by the secondary circuit is similar to a sinusoidal waveform, and compared with the square wave shown in fig. 1, the smoothing process for low-pass filtering the voltage waveform output by the secondary circuit is simpler, and the volume of the required low-pass filter can be greatly reduced, thereby facilitating simplification of circuit design. And because the voltage waveform output by the secondary circuit is similar to the sine waveform, the voltage distortion and the current distortion are smaller, the improvement of harmonic waves is facilitated, and the total harmonic distortion rate is reduced.
Finally, through the smoothing treatment of the primary circuit, the secondary circuit and the low-pass filtering, the inverter circuit can output smooth sinusoidal voltage. And the amplitude of the output voltage of the secondary circuit can be adjusted by adjusting the number of the sub-circuits or the sub-modules so as to meet different requirements.
It should be noted that, the capacitors mentioned in the above embodiments may be a capacitor bank, and the capacitor bank may include a plurality of capacitors connected in parallel to compensate the reactive power of the inductive load of the power system, so as to improve the capacity. The inductors mentioned in the above embodiments may be inductor groups, and the inductor groups may include a plurality of inductors connected in series. In one possible implementation, the inductors in the inductor bank may be parasitic inductances generated by the circuit-carrying structure.
In addition, the switches mentioned in the above embodiments may be MOSFETs. The grid electrode in each MOSFET receives a control signal generated by the control unit, and the drain electrode and the source electrode are respectively connected with corresponding components. In one possible implementation, each MOSFET may be an N-channel MOSFET.
Further, the present inverter circuit may be constructed on a circuit support structure, such as a printed circuit board or the like.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (9)

1. An inverter circuit, comprising a primary circuit and a secondary circuit:
the primary circuit includes a direct current power supply, a first switch (Q17), a second switch (Q18), a first inductor (L1), a first capacitor (C1), and a second capacitor (C2);
the first switch and the second switch are connected with the direct current power supply in series; one end of the first inductor is connected with the first switch and the second switch respectively, and the other end of the first inductor is connected with the direct-current power supply; one end of the first capacitor is connected with the direct-current power supply, and the other end of the first capacitor is connected with the second switch; one end of the second capacitor is connected with the direct-current power supply, and the other end of the second capacitor is connected with the second switch;
the secondary circuit comprises a plurality of sub-circuits; each sub-circuit comprises a full-bridge switch group, a sub-module, an output capacitor (C5);
the submodule comprises a third switch (Q5), a fourth switch (Q6), a third capacitor (C3) and a second inductor (L2), and the third switch and the fourth switch are connected in series to be connected with the first end of the full-bridge switch group; one end of the third capacitor is connected with the third switch, and the other end of the third capacitor is connected with the fourth switch; one end of the second inductor is connected with the third switch and the fourth switch respectively, and the other end of the second inductor is connected with the output capacitor; and one end of the output capacitor is connected with the second end of the full-bridge type switch group.
2. The circuit of claim 1, wherein the full-bridge switch set comprises a fifth switch (Q1), a sixth switch (Q2), a seventh switch (Q3), and an eighth switch (Q4); and after the fifth switch is connected with the sixth switch in series, the fifth switch is connected with the seventh switch and the eighth switch in parallel.
3. The circuit of claim 1, wherein for each sub-circuit, the sub-circuit comprises a first sub-module and a second sub-module, the first sub-module and the second sub-module being connected in series; the first sub-module is connected with the first end of the full-bridge switch group, and the second sub-module is connected with the output capacitor.
4. The circuit of claim 1, wherein the secondary circuit comprises a first sub-circuit and a second sub-circuit; the first sub-circuit is connected in parallel across the first capacitor (C1), and the second sub-circuit is connected in parallel across the second capacitor (C2).
5. The circuit of claim 4,
the inverter circuit further includes a total output capacitor (C9), a third inductor (L6), a fourth inductor (L7); one end of the third inductor is connected with the output capacitor of the first sub-circuit, and the other end of the third inductor is connected with the total output capacitor; one end of the fourth inductor is connected with the output capacitor of the second sub-circuit, and the other end of the fourth inductor is connected with the total output capacitor.
6. The circuit of claim 1, wherein the inverter circuit further comprises a control unit; the control unit is connected with each switch in the inverter circuit;
the control unit is used for sending control signals to the first switch and the second switch so as to control the voltage at two ends of the first capacitor and the second capacitor.
7. The circuit of claim 6, wherein the control unit is further configured to send control signals to switches in each sub-module to connect or bypass capacitors in each sub-module to control the voltage across the output capacitor in the corresponding sub-circuit.
8. The circuit of claim 6, wherein each switch in the inverter circuit is a MOSFET and the control unit is connected to the gate of each switch.
9. The circuit of claim 1,
the third capacitor (C3) is a capacitor bank comprising a plurality of capacitors connected in parallel;
the second inductor (L2) is an inductor bank comprising a plurality of series connected inductors.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214824A1 (en) * 2000-08-16 2003-11-20 Corzine Keith Allen Cascaded multi-level h-bridge drive
CN102005958A (en) * 2010-11-25 2011-04-06 河北工业大学 Photovoltaic grid-connected three-level inverter
CN102185511A (en) * 2011-05-09 2011-09-14 浙江金贝能源科技有限公司 Noninsulated type converting circuit from direct-current voltage to alternating-current voltage
CN107834888A (en) * 2017-10-17 2018-03-23 国网江苏省电力公司盐城供电公司 A kind of Transformer-free single-phase photovoltaic inverter of voltage hybrid clamp

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214824A1 (en) * 2000-08-16 2003-11-20 Corzine Keith Allen Cascaded multi-level h-bridge drive
CN102005958A (en) * 2010-11-25 2011-04-06 河北工业大学 Photovoltaic grid-connected three-level inverter
CN102185511A (en) * 2011-05-09 2011-09-14 浙江金贝能源科技有限公司 Noninsulated type converting circuit from direct-current voltage to alternating-current voltage
CN107834888A (en) * 2017-10-17 2018-03-23 国网江苏省电力公司盐城供电公司 A kind of Transformer-free single-phase photovoltaic inverter of voltage hybrid clamp

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