CN111181431B - Multi-level boost inverter - Google Patents

Multi-level boost inverter Download PDF

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Publication number
CN111181431B
CN111181431B CN202010041469.5A CN202010041469A CN111181431B CN 111181431 B CN111181431 B CN 111181431B CN 202010041469 A CN202010041469 A CN 202010041469A CN 111181431 B CN111181431 B CN 111181431B
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switch
voltage
output circuit
capacitor
voltage output
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CN111181431A (en
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方帅
刘圆圆
舒天宇
王含冠
赵建国
李帅
贾河顺
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Yuanshan Jinan Electronic Technology Co ltd
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Jinan Xinghuo Technology Development Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application discloses many level boost inverter includes: the device comprises a direct current power supply, a control logic module, a low-pass filter circuit, a first voltage output circuit and a second voltage output circuit. The positive pole of the direct current power supply is respectively connected with the first input ends of the first voltage output circuit and the second voltage output circuit, and the negative pole of the direct current power supply is respectively connected with the second input ends of the first voltage output circuit and the second voltage output circuit; the control logic module controls the first voltage output circuit to generate a plurality of first voltages and controls the second voltage output circuit to generate a plurality of second voltages through a plurality of control signals generated by the control logic module; one end of the low-pass filter circuit is connected with the output end of the first voltage output circuit, and the other end of the low-pass filter circuit is connected with the output end of the second voltage output circuit; the low-pass filter circuit filters the step wave formed by the first voltage and the second voltage into alternating current voltage. The method and the device can reduce the total harmonic distortion rate of the output alternating voltage, and effectively reduce the electromagnetic interference generated to the outside and the power loss of the switch.

Description

Multi-level boost inverter
Technical Field
The application relates to the technical field of electronics, in particular to a multi-level boost inverter.
Background
Inverters that convert dc voltage to ac voltage have a wide range of applications, such as electric vehicle drives and renewable energy applications.
A conventional single-phase inverter consists of two half-bridge circuits connected in parallel. Also, conventional three-phase inverters employ three parallel half-bridge circuits, each half-bridge circuit including two switches connected in series.
The traditional inverter can only generate two voltages with equal amplitude and adjustable pulse width at an alternating current output end, and then the generated voltages are processed by a low-pass filter to obtain a sine wave voltage waveform close to a standard, so that the total harmonic distortion rate of the output current and the voltage of the inverter is high.
Disclosure of Invention
In order to solve the above problems, embodiments of the present application provide a multi-level boost inverter capable of reducing a total harmonic distortion rate of an output ac voltage, and effectively reducing electromagnetic interference generated to the outside and power loss of switches of the inverter.
The embodiment of the application provides a multi-level boost inverter, includes:
a direct current power supply;
the positive pole of the direct current power supply is respectively connected with the first input end of the first voltage output circuit and the first input end of the second voltage output circuit, and the negative pole of the direct current power supply is respectively connected with the second input end of the first voltage output circuit and the second input end of the second voltage output circuit; the first output end of the first voltage output circuit is connected with the first output end of the second voltage output circuit;
the control logic module is used for generating a plurality of control signals, controlling the first voltage output circuit through the plurality of control signals to generate a plurality of first voltages and controlling the second voltage output circuit to generate a plurality of second voltages, wherein the first voltages and the second voltages have opposite polarities, the maximum first voltage in the plurality of first voltages is the same as the maximum second voltage in the plurality of second voltages in amplitude, and the minimum first voltage is the same as the minimum second voltage in amplitude;
one end of the low-pass filter circuit is connected with the second output end of the first voltage output circuit, and the other end of the low-pass filter circuit is connected with the second output end of the second voltage output circuit; the low-pass filter circuit filters step waves formed by the first voltage and the second voltage into alternating-current voltage.
In one example, the first voltage output circuit includes: eight switches, two capacitor banks and two inductor banks;
the second voltage output circuit includes: eight switches, two capacitor banks and two inductor banks;
each capacitor group comprises one capacitor or a plurality of capacitors connected in parallel; each inductance group comprises one inductance or a plurality of inductances connected in series.
In one example, the first voltage output circuit further comprises a first capacitor, and the second voltage output circuit further comprises a second capacitor;
one end of the first capacitor is connected with the positive electrode of the direct current power supply and the first input end of the first voltage output circuit, and the other end of the first capacitor is connected with one end of the second capacitor, the negative electrode of the direct current power supply and the second input end of the first voltage output circuit; one end of the second capacitor is connected with the negative electrode of the direct current power supply and the second input end of the first voltage output circuit, and the other end of the second capacitor is connected with the positive electrode of the direct current power supply and the first input end of the second voltage output circuit.
In one example, in the first voltage output circuit, a first end of a first switch is connected with a first end of a third switch and one end of the first capacitor, and a second end of the first switch is connected with a first end of a second switch;
the second end of the second switch is connected with the second end of the fourth switch and the other end of the first capacitor;
the second end of the third switch is connected with the first end of the fourth switch, the second end of the fifth switch and one end of the first capacitor bank;
the first end of the fifth switch is connected with the second end of the sixth switch and one end of the first inductance group;
the first end of the sixth switch is connected with the other end of the first capacitor bank;
the other end of the first inductor group is connected with the second end of the seventh switch and one end of the second capacitor group;
the first end of the seventh switch is connected with the second end of the eighth switch and one end of the second inductance group;
the eighth switch is connected with the other end of the second capacitor bank;
the other end of the second inductance group is connected with one end of a third capacitor;
the other end of the third capacitor is connected with the second end of the first switch.
In the second voltage output circuit, a second end of a ninth switch is connected with a second end of an eleventh switch and one end of the second capacitor, and a first end of the ninth switch is connected with a second end of a tenth switch;
a first end of the tenth switch is connected with a first end of the twelfth switch and the other end of the second capacitor;
a first end of the eleventh switch is connected with a second end of the twelfth switch, a second end of the thirteenth switch and one end of the third capacitor bank;
the first end of the thirteenth switch is connected with the second end of the fourteenth switch and one end of the third inductance group;
a first end of the fourteenth switch is connected to the other end of the third capacitor bank;
the other end of the third inductance group is connected with the second end of the fifteenth switch and one end of the fourth capacitance group;
the first end of the fifteenth switch is connected with the second end of the sixteenth switch and one end of the fourth inductance group;
the sixteenth switch is connected with the other end of the fourth capacitor bank;
the other end of the fourth inductor group is connected with one end of a fourth capacitor;
the other end of the fourth capacitor is connected with the first end of the ninth switch.
In one example, the control signal controls each of the switches to perform zero current switching.
In one example, the inductors in each of the inductor groups include: parasitic inductance of the circuit carrier or a separate inductor.
In one example, each of the switches is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), the first end is a drain of the MOSFET, the second end is a source of the MOSFET, a gate of the MOSFET is a control end, the control logic module is connected to a control end of each of the switches, and the control end is configured to receive the control signal; each MOSFET is connected with a diode in reverse parallel.
In one example, the control logic generates a control signal for causing the first voltage output circuit to generate a first voltage value 3 times the dc input voltage and to equalize the first voltage value with the dc input voltage.
In one example, the control logic generates control signals for closing the first, fourth, sixth, and eighth switches and opening the second, third, fifth, and seventh switches; or
The control logic module generates a control signal for turning on and off the second switch, the third switch, the fifth switch and the eighth switch, and turning off the first switch, the fourth switch, the sixth switch and the seventh switch; or
The control logic module generates a control signal for closing the second switch, the third switch, the sixth switch and the seventh switch, and opening the first switch, the fourth switch, the fifth switch and the eighth switch; and
the control logic module generates a control signal for enabling the seventh switch to be normally closed and the eighth switch to be normally open.
In one example, the control logic generates a control signal for causing the second voltage output circuit to generate a second voltage value 3 times the dc input voltage and to equalize the second voltage value with the dc input voltage.
In one example, the control logic generates control signals for closing the tenth, eleventh, fourteenth and sixteenth switches and opening the ninth, twelfth, thirteenth and fifteenth switches; or
The control logic module generates a control signal for closing the ninth switch, the twelfth switch, the thirteenth switch and the sixteenth switch and opening the tenth switch, the eleventh switch, the fourteenth switch and the fifteenth switch; or
The control logic module generates a control signal for closing the ninth switch, the twelfth switch, the fourteenth switch and the fifteenth switch and opening the tenth switch, the eleventh switch, the thirteenth switch and the sixteenth switch; and
the control logic module generates a control signal for making the fifteenth switch normally closed and the sixteenth switch normally open.
The embodiment of the application provides a multi-level boost inverter, wherein a control logic module generates a plurality of control signals, controls a first voltage output circuit through the plurality of control signals, generates a plurality of first voltages, and controls a second voltage output circuit to generate a plurality of second voltages. Since the first voltage and the second voltage have opposite polarities, and the largest first voltage of the plurality of first voltages is the same as the largest second voltage of the plurality of second voltages, the smallest first voltage is the same as the smallest second voltage. Therefore, the inverter provided by the embodiment of the application can obtain a plurality of voltage levels by using the first voltage and the second voltage with different values, so that the low-pass filter circuit can more easily convert the step wave formed by the first voltage and the second voltage into a normal alternating current waveform, thereby reducing the total harmonic distortion of the output alternating current voltage and effectively reducing the electromagnetic interference generated to the outside and the power loss of the switch of the inverter.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a circuit diagram of a single-phase dc-ac inverter according to an embodiment of the present application;
fig. 2 is a top half of a circuit diagram of a single-phase dc-ac inverter according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram of a sub-circuit of the upper half circuit of the inverter according to the embodiment of the present application;
fig. 4 is a circuit diagram of another sub-circuit of the upper half circuit of the inverter according to the embodiment of the present application;
fig. 5 is a circuit diagram of another sub-circuit of the upper half circuit of the inverter according to the embodiment of the present application;
FIG. 6 is an equivalent circuit topology with a voltage input to output ratio of one according to an embodiment of the present application;
fig. 7 is a voltage waveform diagram of an output of a multi-level boost inverter according to an embodiment of the present application.
Detailed Description
In order to more clearly explain the overall concept of the present application, the following detailed description is given by way of example in conjunction with the accompanying drawings.
The embodiment of the application discloses a multi-level boost inverter, the circuit topology of which is shown in fig. 1, and the circuit is formed on a circuit bearing structure such as a printed circuit board.
The circuit includes: DC power supply VinThe circuit comprises a plurality of inductor groups L1-L4, a plurality of capacitor groups C1-C8, inductors L5 and L6, a plurality of switches Q1-Q16 and a control logic module. Each inductance group may be composed of one inductor or may be a plurality of inductances connected in series. In addition, the inductance in the inductance group includes a parasitic inductance that the circuit carrier has or a separate inductor. Each capacitor group can be composed of one capacitor or a plurality of capacitors connected together in parallel.
The switches Q1-Q16 are each a MOSFET reverse parallel diode having a first terminal, a second terminal and a control terminal. The first end is an MOSFET drain electrode, the second end is an MOSFET source electrode, and the control end is an MOSFET grid electrode.
The capacitor groups C1, C2, C5 and C7, the inductor groups L1 and L2 and the switches Q1-Q8 form a first voltage output circuit. Capacitor bank C3, C4, C6 and C8, inductor bank L3 and L4, and switches Q9-Q16 constitute a second voltage output circuit. A capacitor is connected between the inductors L5 and L6 to form a low-pass filter circuit. The control logic module is connected with the gates of the switches Q1-Q16 to realize that the first voltage output circuit is controlled to generate a plurality of first voltages and the second voltage output circuit is controlled to generate a plurality of second voltages through a plurality of control signals, the polarities of the first voltages are opposite to that of the second voltages, the maximum first voltage in the plurality of first voltages is the same as the maximum second voltage in the plurality of second voltages, and the minimum first voltage is the same as the minimum second voltage.
It should be noted that any other type of switch may be used for the switches Q1-Q16, and the MOSFET antiparallel diode is selected as the control switch of the circuit in the present application in order to reduce the power loss of the switch. The control logic module can be any chip or device with logic control function, and is electrically connected with the switches Q1-Q16.
In the embodiment of the application, in the first voltage output circuit, a first end of Q1 is connected with a first end of Q3 and a C7 end, and a second end of Q1 is connected with a first end of Q2; a second terminal of Q2 is connected to the second terminal of Q4 and the other end of C7; a second terminal of Q3 is connected to the first terminal of Q4, the second terminal of Q5 and one terminal of C1; a first end of Q5 connects the second end of Q6 and one end of L1; a first end of Q6 is connected with the other end of C1; the other end of L1 is connected with the second end of Q7 and one end of C2; a first end of Q7 connects the second end of Q8 and one end of L2; q8 is connected with the other end of C2; the other end of L2 is connected with one end of C5; the other end of C5 is connected to the second end of Q1.
In the embodiment of the application, in the second voltage output circuit, the second end of the Q9 is connected with the second end of the Q11 and one end of the C8, and the first end of the Q9 is connected with the second end of the Q10; a first end of Q10 connects a first end of Q12 and the other end of C8; a first end of Q11 is connected to a second end of Q12, a second end of Q13, and an end of C3; a first end of Q13 connects the second end of Q14 and one end of L3; a first end of Q14 is connected with the other end of C3; the other end of L3 is connected with the second end of Q15 and one end of C4; a first end of Q15 connects the second end of Q16 and one end of L4; q16 is connected with the other end of C4; the other end of L4 is connected with one end of C6; the other end of C6 is connected to the first end of Q9.
In the embodiment of the present application, the circuit of the inverter can be divided into an upper part and a lower part, and the circuit in fig. 2 is the upper half part of the circuit diagram of the inverter. As shown in fig. 2, the upper half of the circuit of the inverter includes: DC power supply VinCapacitor groups C1, C2, C5 and C7, inductor groups L1 and L2 and switches Q1-Q8. The lower half of the circuit diagram of the corresponding inverter includes: DC power supply VinCapacitor groups C3, C4, C6 and C8, inductor groups L3 and L4 and switches Q9-Q16. The elements included in the upper half part and the lower half part of the circuit of the inverter correspond to each other, and the functions of the elements are completely the same, except that the connection mode of the drain and the source of the switches Q1-Q4 is opposite to the connection mode of the drain and the source of the switches Q9-Q12, so that the positive and negative poles of the capacitor group C5 and the capacitor group C6 are opposite, that is, when the control signals are the same, the first voltage and the second voltage are the same in magnitude and opposite in voltage direction. The correspondence relationship of the respective elements is as follows: the capacitor groups C1 and C2 at the upper part correspond to the capacitor groups C3 and C4 at the lower part in sequence, the capacitor groups C5 and C7 at the upper part correspond to the capacitor groups C6 and C8 at the lower part in sequence, and the inductor groups L1 and L2 at the upper part correspond to the inductor groups L3 and L4 at the lower part in sequence. The switches Q1-Q8 of the upper part and the switches Q9-Q16 of the lower part are mirror images, namely the switches Q1-Q4 respectively correspond to Q10, Q9, Q12 and Q11, and the switches Q5-Q8 respectively correspond to Q13-Q16 in sequence. The design realizes that the waveform of the alternating current output voltage of the inverter is a sine wave.
For example, in the first half of a cycle, the control logic controls the output voltage U1 of the upper half circuit through the first set of control signals, and controls the output voltage U2 of the lower half circuit through the second set of control signals, so that the AC output voltage of the inverter is U1-U2. Since the elements included in the upper half part and the lower half part of the circuit of the inverter are corresponding to each other and the functions of the elements are completely the same, in the second half period of the period, the control logic module controls the output voltage U2 of the upper half part circuit through the second group of control signals, and controls the output voltage U1 of the lower half part circuit through the first group of control signals, so that the alternating current output voltage of the inverter is U2-U1, namely the alternating current output voltage in the second half period is the same as the voltage in the first half period but opposite in direction, and the alternating current output voltage with a sine wave shape is obtained.
The following describes the sub-circuits corresponding to the first voltages specifically by taking the upper half circuit as an example, as shown in fig. 3 to 6:
fig. 3 is a circuit diagram of a sub-circuit of an upper half circuit of an inverter according to an embodiment of the present application. In fig. 3, switches Q1, Q4, Q6, and Q8 are closed, and switches Q2, Q3, Q5, and Q7 are open. At this time, the capacitor banks C1 and C2 are in the loop, and are charged or discharged, and the output voltage of the upper half part is 3 times of the DC input voltage, namely Vout＝3Vin。
Fig. 4 is a circuit diagram of another sub-circuit of the upper half circuit of the inverter according to the embodiment of the present application. In fig. 4, switches Q2, Q3, Q5, and Q8 are closed, and switches Q1, Q4, Q6, and Q7 are open. At this time, the capacitor bank C1 is bypassed, and only the capacitor bank C2 is charging or discharging, and the output voltage of the upper half is 3 times of the dc input voltage, i.e., Vout＝3Vin。
Fig. 5 is a circuit diagram of another sub-circuit of the upper half circuit of the inverter according to the embodiment of the present application. In fig. 5, switches Q2, Q3, Q6, and Q7 are closed, and switches Q1, Q4, Q5, and Q8 are open. At this time, the capacitor bank C2 is bypassed, and only the capacitor bank C1 is charging or discharging, and the output voltage of the upper half is 3 times of the dc input voltage, i.e., Vout＝3Vin。
Fig. 6 is an equivalent circuit topology with a voltage input/output ratio of one according to an embodiment of the present application. In fig. 6, the switch Q7 is normally closed, and the switch Q8 is normally open. At this time, the other six switches can be in any state, and the output voltage of the upper half part is the same as the direct current input voltage, namely Vout＝Vin。
Therefore, the upper half part of the circuit of the inverter can output 3Vin、VinAnd 0 three kinds of electricityThe lower half of the circuit of the corresponding inverter can output 3V at a low voltage levelin、VinAnd 0, but in the opposite direction from the upper half. Meanwhile, each capacitor, each inductor and each switch are only connected into each sub-circuit through two respective nodes, and no additional connection node exists. In addition, each sub-circuit is a resonance circuit consisting of a capacitor and an inductor so as to realize zero current switching of each switch, and electromagnetic interference generated to the outside and power loss of the switch of the inverter can be effectively reduced. Since the switches Q1-Q8 of the upper portion and the switches Q9-Q16 of the lower portion are mirror images, the sub-circuits corresponding to the second voltage can be seen in fig. 3 to 6.
In the embodiment of the present application, the ac output voltage of the inverter is the difference between the upper half level and the lower half level of the circuit of the inverter, which is specifically shown in table 1:
Figure BDA0002367906680000091
TABLE 1
From table 1, a voltage waveform diagram of the output of the multilevel boost inverter as shown in fig. 7 can be obtained. As can be seen from fig. 7, compared with the conventional two-level inverter, the voltage waveform diagram obtained in the embodiment of the present application is closer to the standard sine wave, and therefore the technical solution proposed in the present application can reduce the total harmonic distortion of the output ac voltage.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (7)

1. A multi-level boost inverter, comprising:
a direct current power supply;
the positive pole of the direct current power supply is respectively connected with the first input end of the first voltage output circuit and the first input end of the second voltage output circuit, and the negative pole of the direct current power supply is respectively connected with the second input end of the first voltage output circuit and the second input end of the second voltage output circuit; the first output end of the first voltage output circuit is connected with the first output end of the second voltage output circuit;
the control logic module is used for generating a plurality of control signals, controlling the first voltage output circuit through the plurality of control signals to generate a plurality of first voltages and controlling the second voltage output circuit to generate a plurality of second voltages, wherein the first voltages and the second voltages have opposite polarities, the maximum first voltage in the plurality of first voltages is the same as the maximum second voltage in the plurality of second voltages in amplitude, and the minimum first voltage is the same as the minimum second voltage in amplitude;
one end of the low-pass filter circuit is connected with the second output end of the first voltage output circuit, and the other end of the low-pass filter circuit is connected with the second output end of the second voltage output circuit; the low-pass filter circuit filters step waves formed by the first voltage and the second voltage into alternating-current voltage;
the first voltage output circuit includes: eight switches, two capacitor banks and two inductor banks;
the second voltage output circuit includes: eight switches, two capacitor banks and two inductor banks;
each capacitor group comprises one capacitor or a plurality of capacitors connected in parallel; each inductance group comprises one inductance or a plurality of inductances connected in series;
the first voltage output circuit further comprises a first capacitor, and the second voltage output circuit further comprises a second capacitor;
one end of the first capacitor is connected with the positive electrode of the direct current power supply and the first input end of the first voltage output circuit, and the other end of the first capacitor is connected with one end of the second capacitor, the negative electrode of the direct current power supply and the second input end of the first voltage output circuit; one end of the second capacitor is connected with the negative electrode of the direct current power supply and the second input end of the first voltage output circuit, and the other end of the second capacitor is connected with the positive electrode of the direct current power supply and the first input end of the second voltage output circuit;
in the first voltage output circuit, a first end of a first switch is connected with a first end of a third switch and one end of the first capacitor, and a second end of the first switch is connected with a first end of a second switch;
the second end of the second switch is connected with the second end of the fourth switch and the other end of the first capacitor;
the second end of the third switch is connected with the first end of the fourth switch, the second end of the fifth switch and one end of the first capacitor bank;
the first end of the fifth switch is connected with the second end of the sixth switch and one end of the first inductance group;
the first end of the sixth switch is connected with the other end of the first capacitor bank;
the other end of the first inductor group is connected with the second end of the seventh switch and one end of the second capacitor group;
the first end of the seventh switch is connected with the second end of the eighth switch and one end of the second inductance group;
the eighth switch is connected with the other end of the second capacitor bank;
the other end of the second inductance group is connected with one end of a third capacitor;
the other end of the third capacitor is connected with the second end of the first switch.
2. The inverter of claim 1,
in the second voltage output circuit, a second end of a ninth switch is connected with a second end of an eleventh switch and one end of the second capacitor, and a first end of the ninth switch is connected with a second end of a tenth switch;
a first end of the tenth switch is connected with a first end of the twelfth switch and the other end of the second capacitor;
a first end of the eleventh switch is connected with a second end of the twelfth switch, a second end of the thirteenth switch and one end of the third capacitor bank;
the first end of the thirteenth switch is connected with the second end of the fourteenth switch and one end of the third inductance group;
a first end of the fourteenth switch is connected to the other end of the third capacitor bank;
the other end of the third inductance group is connected with the second end of the fifteenth switch and one end of the fourth capacitance group;
the first end of the fifteenth switch is connected with the second end of the sixteenth switch and one end of the fourth inductance group;
the sixteenth switch is connected with the other end of the fourth capacitor bank;
the other end of the fourth inductor group is connected with one end of a fourth capacitor;
the other end of the fourth capacitor is connected with the first end of the ninth switch.
3. The inverter of claim 2, wherein the control signals control the switches to perform zero current switching, and wherein the inductors of each of the inductor sets comprise: parasitic inductance of the circuit carrier or a separate inductor.
4. The inverter of claim 2, wherein each of the switches is a metal-oxide-semiconductor field effect transistor (MOSFET), the first terminal is a drain of the MOSFET, the second terminal is a source of the MOSFET, a gate of the MOSFET is a control terminal, the control logic module is connected to the control terminal of each of the switches, and the control terminal is configured to receive the control signal; each MOSFET is connected with a diode in reverse parallel.
5. The inverter of claim 2,
the control logic module is used for generating a control signal which is used for enabling a first voltage value generated by the first voltage output circuit to be three times of a direct current input voltage and enabling the first voltage value to be equal to the direct current input voltage; and
the control logic module generates a control signal for enabling the second voltage value generated by the second voltage output circuit to be three times of the direct current input voltage and enabling the second voltage value to be equal to the direct current input voltage.
6. The inverter of claim 5,
the control logic module generates a control signal for closing the first switch, the fourth switch, the sixth switch and the eighth switch and opening the second switch, the third switch, the fifth switch and the seventh switch; or
The control logic module generates a control signal for turning on and off the second switch, the third switch, the fifth switch and the eighth switch, and turning off the first switch, the fourth switch, the sixth switch and the seventh switch; or
The control logic module generates a control signal for closing the second switch, the third switch, the sixth switch and the seventh switch and opening the first switch, the fourth switch, the fifth switch and the eighth switch; and
the control logic module generates a control signal for enabling the seventh switch to be normally closed and the eighth switch to be normally open.
7. The inverter of claim 5,
the control logic module generates a control signal for closing the tenth switch, the eleventh switch, the fourteenth switch and the sixteenth switch and opening the ninth switch, the twelfth switch, the thirteenth switch and the fifteenth switch; or
The control logic module generates a control signal for closing the ninth switch, the twelfth switch, the thirteenth switch and the sixteenth switch and opening the tenth switch, the eleventh switch, the fourteenth switch and the fifteenth switch; or
The control logic module generates a control signal for closing the ninth switch, the twelfth switch, the fourteenth switch and the fifteenth switch and opening the tenth switch, the eleventh switch, the thirteenth switch and the sixteenth switch; and
the control logic module generates a control signal for making the fifteenth switch normally closed and the sixteenth switch normally open.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005788A (en) * 1998-02-13 1999-12-21 Wisconsin Alumni Research Foundation Hybrid topology for multilevel power conversion
CN103683876A (en) * 2013-12-30 2014-03-26 阳光电源股份有限公司 Seven-level inverter
CN104377960A (en) * 2013-08-15 2015-02-25 南京博兰得电子科技有限公司 Resonant converter and control method thereof
CN107124104A (en) * 2016-02-25 2017-09-01 株式会社村田制作所 DC/DC conversion equipments

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005788A (en) * 1998-02-13 1999-12-21 Wisconsin Alumni Research Foundation Hybrid topology for multilevel power conversion
CN104377960A (en) * 2013-08-15 2015-02-25 南京博兰得电子科技有限公司 Resonant converter and control method thereof
CN103683876A (en) * 2013-12-30 2014-03-26 阳光电源股份有限公司 Seven-level inverter
CN107124104A (en) * 2016-02-25 2017-09-01 株式会社村田制作所 DC/DC conversion equipments

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