CN110429850B

CN110429850B - High-efficiency GaN three-phase inverter module for new energy power generation system

Info

Publication number: CN110429850B
Application number: CN201910739446.9A
Authority: CN
Inventors: 周德金
Original assignee: Wuxi Paiwei Technology Co ltd
Current assignee: Zhuhai Jiadan Technology Co.,Ltd.
Priority date: 2019-08-12
Filing date: 2019-08-12
Publication date: 2021-02-23
Anticipated expiration: 2039-08-12
Also published as: CN110429850A

Abstract

The invention relates to a high-efficiency GaN three-phase inverter module for a new energy power generation system, which comprises a controller, a first GaN half-bridge circuit, a second GaN half-bridge circuit, a third GaN half-bridge circuit, a detection circuit and a feedback circuit, wherein the controller is connected with the first GaN half-bridge circuit and the second GaN half-bridge circuit; the first GaN half-bridge circuit comprises a first grid driving circuit H, a second grid driving circuit L, GaN power switch MH, a GaN power switch ML and current-limiting resistors RH and RL; the second GaN half-bridge circuit comprises a third gate drive circuit H1, a fourth gate drive circuit L1, a GaN power switch MH1, a GaN power switch ML1, and current-limiting resistors RH1 and RL 1; the third GaN half-bridge circuit comprises a fifth gate drive circuit H2, a sixth gate drive circuit L2, a GaN power switch MH2, a GaN power switch ML2, and current-limiting resistors RH2 and RL 2. The invention realizes the high frequency of the full-bridge inverter by adopting the GaN HEMT device packaged by the LGA, further adopts a multi-tube parallel structure for improving the power level, and adopts a double-sided layout structure for improving the reliability to realize high-density power integration and high efficiency.

Description

High-efficiency GaN three-phase inverter module for new energy power generation system

Technical Field

The invention relates to a high-efficiency GaN three-phase inverter module for a new energy power generation system, and belongs to the field of power electronics.

Background

In the 21 st century, under the traction of emerging industries such as smart grid, mobile communication and new energy automobile, power electronic application systems require further improvement of system efficiency, miniaturization and added functions, and particularly require trade-offs between circuit application size, quality, power and efficiency, such as server power management, battery charger and micro-inverter of solar electric field. The above applications require power electronics systems to be efficient in design>95% of the total power, and also has high power density (>500W/in³I.e. 30.5W/cm³) High specific power (10 kW/lb, 22kW/kg) and high total load point(s) ((>1000W). With the emergence and application popularization of super junction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), the device performance gradually approaches the limit of silicon materials, the rule that the power density is increased by 1 time every four years tends to saturate (moore's law in the field of power electronics), and the development of silicon-based power semiconductor devices with power densities of only single digit is difficult due to the reasons mentioned above.

In recent years, third-generation semiconductor power devices represented by gallium nitride (GaN) have significantly better performance than first-generation and second-generation semiconductor materials such as Si, Ge, GaAs, and the like in the microelectronic field of high power, high temperature, high frequency, and radiation resistance and the short-wavelength photoelectron field due to high forbidden bandwidth, high breakdown electric field intensity, and high electron saturation velocity. GaN power devices have superior on-state characteristics and superior switching characteristics compared to Si devices, and thus attract attention of the industry in a short time, and researchers engaged in application research have also conducted a lot of research works to apply them to low-voltage and low-power supply devices such as POL, DC/DC, and the like. Research shows that the switching frequency can be greatly improved by replacing a Si device with a GaN device, and good efficiency indexes are kept. Certainly, GaN devices will be more and more commonly used in low voltage, low power applications, and greatly contribute to the performance improvement of power supply devices in these fields in terms of power density, efficiency, and the like.

The solar cell panel in the solar photovoltaic power generation system obtains direct current voltage through photoelectric effect conversion. The voltage is influenced by factors such as the illumination intensity of the photovoltaic cell panel, the output current value and the like. Therefore, the photovoltaic power generation system needs to convert the dc voltage into an ac voltage meeting the quality standard of the electric energy through an inverter system based on a power electronic converter to be connected to a power grid or supplied to a load. The main technical indexes of the photovoltaic inverter system comprise: the inversion efficiency, the waveform distortion rate of the output current, the power factor, the maximum power point tracking efficiency and other important indexes. Among the above indexes, the inverter efficiency is one of the important indexes for evaluating the photovoltaic inverter system. With the continuous development of power electronic technology and modern control theory, the photovoltaic inverter system is developing towards the direction of high performance, high efficiency, high power density. The power generation of the photovoltaic cell panel is affected by the installation position, orientation and surrounding environment, such as illumination intensity, installation inclination angle and the like, so that the efficiency of the photovoltaic cell panel is low, which is about 20%.

With the wide application of the photovoltaic inverter system, the suppression of the harmonic current thereof is also receiving more and more attention. Relevant standards are made by various countries, and the content of each subharmonic current injected into a power grid by the photovoltaic grid-connected inverter and the total harmonic current content are limited. The efficiency and the power density of the photovoltaic inverter are important indexes of manufacturing, research and development of the photovoltaic inverter, are directly related to the efficiency of the whole photovoltaic inverter system, and are an important research field of the current photovoltaic inverter system. The loss of the photovoltaic inverter system mainly comprises three parts: high frequency switching losses, magnetic element losses, and line conduction losses. The power switching device is the most important part in the photovoltaic inverter system, and the power loss, the switching frequency and the reliability of the power switching device directly influence the efficiency, the product volume and the service life of the inverter. Taking a photovoltaic grid-connected inverter in the photovoltaic power generation industry as an example, a photovoltaic product developer can put a large amount of research and development capacity into consideration, and the improved efficiency has greater competitiveness. Therefore, reducing losses would allow for new device and circuit technologies to be used in these links. How to provide higher and higher output power under the condition of smaller and smaller space, and the inverter module has ultrahigh-speed transient response and optimal cost performance, and is a comprehensive bottleneck problem of the design of a new generation of inverter modules. The main approach to achieve miniaturization and power density enhancement is to increase the switching frequency of the power supply system.

The characteristics of GaN devices make the gate drive charge (Qg) of GaN devices very small, the junction capacitance very small, the switching speed much faster than Si devices, the use of GaN switching devices enables the boost and inverter stages to operate at frequencies above 100kHz, and conventional Insulated Gate Bipolar Transistor (IGBT) designs operate at frequencies below 20 kHz. The increase in switching frequency can greatly reduce the volume and weight of peripheral components, since higher frequencies greatly reduce the size of large magnets in the inverter. The inherently low switching losses of GaN power stages allow efficiencies of over 99%. Higher efficiency means smaller heat sinks and less heat dissipation is required, making the design more compact and cost effective.

However, the power density is increased by increasing the switching frequency, and two bottleneck problems need to be faced: firstly, the current change of a switch branch circuit in the switching process of a GaN device is very rapid, the di/dt is very high, and because parasitic inductance inevitably exists in a power loop, when the current changes rapidly, very high peak overvoltage can be generated at two ends of the switch device. If the voltage is light, the malfunction of the circuit and the EMI exceeding standard are caused, and if the voltage is heavy, the breakdown and the damage of the device are caused. The very high switching speed of GaN devices results in parasitic oscillations and overvoltage phenomena during their switching process that are much more pronounced than Si devices. GaN devices are more sensitive to parasitic inductance in the circuit due to faster switching speeds. If the wiring is not optimized enough and the parasitic inductance is large, the normal operation of the circuit can be directly influenced. Secondly, as the power density of the GaN power module is improved, the heat dissipation requirement of the power device is stricter. The reason is that the module size is reduced, and the choice of the heat sink structure and the placement of the position are more sensitive to the performance impact of the power module than conventional power modules.

Disclosure of Invention

Aiming at the application challenge faced when a GaN power device is adopted for power integration, the invention carries out optimization design on the aspects of a gate drive circuit, device layout, heat dissipation and the like, and provides a high-efficiency three-phase inverter power module which is applied to a photovoltaic power generation system and adopts the GaN power device.

According to the technical scheme provided by the invention, the high-efficiency GaN three-phase inverter module for the new energy power generation system comprises: the GaN-based LED driving circuit comprises a controller, a first GaN half-bridge circuit, a second GaN half-bridge circuit, a third GaN half-bridge circuit, a detection circuit and a feedback circuit; the first GaN half-bridge circuit comprises a first gate drive circuit, a second gate drive circuit, a GaN power switch MH, a GaN power switch ML, a current-limiting resistor RH connected between the first gate drive circuit and the GaN power switch MH, and a current-limiting resistor RL connected between the second gate drive circuit and the GaN power switch ML; the second GaN half-bridge circuit comprises a third gate drive circuit, a fourth gate drive circuit, a GaN power switch MH1 and a GaN power switch ML1, a current-limiting resistor RH1 connected between the third gate drive circuit and the GaN power switch MH1, and a current-limiting resistor RL1 connected between the fourth gate drive circuit and the GaN power switch ML 1; the third GaN half-bridge circuit comprises a fifth gate drive circuit, a sixth gate drive circuit, a GaN power switch MH2 and a GaN power switch ML2, a current-limiting resistor RH2 connected between the fifth gate drive circuit and the GaN power switch MH2, and a current-limiting resistor RL2 connected between the sixth gate drive circuit and the GaN power switch ML 2;

the connection relationship of the circuit is as follows: a first pulse width signal PWH output end of the controller is connected to an input end of the first gate driving circuit, a second pulse width signal PWL output end of the controller is connected to an input end of the second gate driving circuit, a third pulse width signal PWH1 output end of the controller is connected to an input end of the third gate driving circuit, a fourth pulse width signal PWL1 output end of the controller is connected to an input end of the fourth gate driving circuit, a fifth pulse width signal PWH2 output end of the controller is connected to an input end of the fifth gate driving circuit, and a sixth pulse width signal PWL2 output end of the controller is connected to an input end of the sixth gate driving circuit;

the source end of a GaN power switch MH is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH is a half-bridge output HB, the half-bridge output HB is connected to the drain end of a GaN power switch ML and the left end of an inductor Lc1, and the source end of the GaN power switch ML is connected to the lower ends of an input low-voltage bus Vgnd and a capacitor C1; the source end of a GaN power switch MH1 is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH1 is a half-bridge output HB1, the half-bridge output HB1 is connected to the drain end of the GaN power switch ML1 and the left end of an inductor Lc2, and the source end of the GaN power switch ML1 is connected to the lower ends of the input low-voltage bus Vgnd and a capacitor C2; the source end of a GaN power switch MH2 is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH2 is a half-bridge output HB2, the half-bridge output HB2 is connected to the drain end of the GaN power switch ML2 and the left end of an inductor Lc3, and the source end of the GaN power switch ML2 is connected to the lower ends of the input low-voltage bus Vgnd and a capacitor C3;

the right end of the inductor Lc1 is connected to the upper end of the capacitor C1, the first input port of the detection circuit, the upper end of the output capacitor C4, the lower end of the output capacitor C6 and the first-phase output high-voltage bus UO; the right end of the inductor Lc2 is connected to the upper end of the capacitor C2, the second input port of the detection circuit, the lower end of the output capacitor C4, the upper end of the output capacitor C5 and the second-phase output high-voltage bus Vo; the right end of the inductor Lc3 is connected to the upper end of the capacitor C3, the third input port of the detection circuit, the lower end of the output capacitor C5, the upper end of the output capacitor C6 and the third-phase output high-voltage bus Wo; the voltage detection signal, the current detection signal and the temperature detection signal which are output by the detection circuit and are used for the three-phase inverter module are respectively connected to the input end of the feedback circuit; the feedback circuit respectively processes the voltage detection signal, the current detection signal and the temperature detection signal into feedback signals and outputs the feedback signals to the controller.

Specifically, the circuit adopts two-sided layout structure when the territory is realized, two-sided layout structure includes: the GaN-based detection circuit comprises a first GaN half-bridge layout area, a second GaN half-bridge layout area, a third GaN half-bridge layout area, a detection circuit layout area, an output capacitor C4 layout area, an output capacitor C5 layout area, an output capacitor C6 layout area and a low-voltage power supply area, wherein the first GaN half-bridge layout area, the second GaN half-bridge layout area and the third GaN half-bridge layout area are distributed on the front side; all PWM pulse width signals and all detection signals between the front side and the back side are connected with signals through holes;

the first GaN half-bridge layout area, the second GaN half-bridge layout area and the third GaN half-bridge layout area adopt the same layout mode of the GaN half-bridge layout areas, namely, the interior of each area comprises a gate drive circuit layout area, a current limiting resistor layout area, a GaN power switch layout area, a radiator layout area, a half-bridge output layout area, an inductor layout area, a capacitor layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the radiator layout areas are distributed in the half-bridge output layout area;

an output capacitor C4 layout area is bridged between the first GaN half-bridge layout area and the second GaN half-bridge layout area, an output capacitor C5 layout area is bridged between the second GaN half-bridge layout area and the third GaN half-bridge layout area, and an output capacitor C6 layout area is bridged between the first GaN half-bridge layout area and the third GaN half-bridge layout area;

the low-voltage power supply area comprises a controller layout area, a feedback circuit layout area and a low-voltage ground wire layout area.

Specifically, all the GaN power switches adopt a plurality of low-current GaN power switches which are connected in parallel to realize high-current output; and all adopt HEMT devices in the form of LGA packages.

Specifically, input high voltage bus Vbus version district and input high voltage ground wire Vgnd version district all include C type semi-surrounding structure, and it has to distribute in the space that every C type semi-surrounding structure encloses: the HEMT device comprises a through hole layout area, a gate drive circuit layout area, a current limiting resistor layout area and an HEMT device layout area;

the space surrounded by the C-shaped semi-surrounding structure of the input high-voltage bus Vbus layout area in the first GaN half-bridge layout area is distributed with: a through hole P _ PWH layout area, a first gate drive circuit H layout area, a current limiting resistor RH layout area, a HEMT device MH11 layout area and a HEMT device MH12 layout area; the left side of the HEMT device MH11 layout area and the left side of the HEMT device MH12 layout area face the right end of the current-limiting resistor RH;

two end parts of the input high-voltage bus Vbus version area C-shaped semi-surrounding structure are of right-angled triangle structures, and the hypotenuses of the 2 triangles are opposite and are respectively connected with a source electrode of an HEMT device MH11 version area and a source electrode of an HEMT device MH12 version area; the upper left corner of a half-bridge output HB layout area is clamped between drain electrodes of the HEMT device MH11 layout area and the HEMT device MH12 layout area, and the upper left corner is in the shape of an isosceles triangle with an acute angle towards the left;

the space surrounded by the C-shaped semi-surrounding structure of the input high-voltage ground wire Vgnd layout area in the first GaN half-bridge layout area is distributed with: the HEMT device comprises a through hole P _ PWL layout area, a second gate drive circuit L layout area, a current limiting resistor RL layout area, a HEMT device ML11 layout area and a HEMT device ML12 layout area; the left side of the layout area of the HEMT device ML11 and the left side of the layout area of the HEMT device ML12 face the right end of the current limiting resistor RL;

two end parts of the input high-voltage ground wire Vgnd layout area C-type semi-surrounding structure are of right-angled triangle structures, and the hypotenuses of the 2 triangles are opposite and are respectively connected with a source electrode of an HEMT device ML11 layout area and a source electrode of an HEMT device ML12 layout area; the left lower corner of the half-bridge output HB layout area is clamped between the drain electrodes of the HEMT device ML11 layout area and the HEMT device ML12 layout area, and the shape of the left lower corner is an isosceles triangle with an acute angle towards the left;

and the input high-voltage bus Vbus layout area and the input high-voltage ground wire Vgnd layout area in the second GaN half-bridge layout area and the third GaN half-bridge layout area both adopt a C-shaped semi-surrounding structure which is the same as that of the first GaN half-bridge layout area.

Specifically, the lengths of a metal wire from the right end of the current-limiting resistor RH to the grid end of the HEMT device MH11 and a metal wire from the right end of the current-limiting resistor RH to the grid end of the HEMT device MH12 are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees; the lengths of a metal wire from the right end of the current-limiting resistor RL to the grid end of the HEMT device ML11 and a metal wire from the right end of the current-limiting resistor RL to the grid end of the HEMT device ML12 are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees.

Specifically, the two metal wires responsible for transmitting the first pulse width signal PWH and the second pulse width signal PWL, the two metal wires responsible for transmitting the third pulse width signal PWH1 and the fourth pulse width signal PWL1, and the two metal wires responsible for transmitting the fifth pulse width signal PWH2 and the sixth pulse width signal PWL2 have the following requirements:

the length, width and thickness of the first and second metal wires must be strictly equal;

secondly, two metal wires need to adopt a parallel wiring mode, and the vertical distance between the two metal wires is not more than 2 mm;

and thirdly, the area passed by the layout of the two metal wires must be isolated and protected by a low-voltage ground wire.

The invention has the advantages that: the GaN HEMT device packaged by the LGA realizes the high frequency of the full-bridge inverter, further adopts a multi-tube parallel structure for improving the power level, adopts a double-sided layout structure for improving the reliability to carry out optimization design on a gate drive circuit, the HEMT device, a power bus and a heat dissipation layout, thereby realizing high-density power integration and high efficiency, and being widely applied to a photovoltaic power generation system.

Drawings

Fig. 1 is a circuit configuration diagram of a GaN three-phase inverter module according to the present invention.

Fig. 2 is a waveform diagram of an output current of the GaN three-phase inverter module according to the present invention.

FIG. 3 is a double-sided layout of the present invention.

FIG. 4 is a detailed layout of the GaN half-bridge layout area of the present invention.

FIG. 5 is a diagram showing an actual layout of a GaN half-bridge layout area in the embodiment.

FIG. 6 is a diagram showing an actual layout of a low voltage power supply region according to an embodiment.

FIG. 7 shows test waveforms according to an embodiment of the present invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings and examples.

As shown in fig. 1, the circuit structure of the high-efficiency GaN three-phase inverter module for a new energy power generation system according to the present invention includes: the GaN circuit comprises a controller U1, a first GaN half bridge circuit 1, an inductor Lc1, a capacitor C1, a second GaN half bridge circuit 2, an inductor Lc2, a capacitor C2, a third GaN half bridge circuit 3, an inductor Lc3, a capacitor C3, an output capacitor C4, an output capacitor C5, an output capacitor C6, a detection circuit U2 and a feedback circuit U3. The first GaN half-bridge circuit 1 comprises a first grid drive circuit H, a second grid drive circuit L, GaN power switch MH, a GaN power switch ML, and a current limiting resistor RH and a current limiting resistor RL which are respectively connected with grid ends of MH and ML; the second GaN half-bridge circuit 2 comprises a third gate drive circuit H1, a fourth gate drive circuit L1, a GaN power switch MH1, a GaN power switch ML1, a current-limiting resistor RH1 and a current-limiting resistor RL1 which are respectively connected to the gate ends of MH1 and ML 1; the third GaN half-bridge circuit 3 includes a fifth gate driving circuit H2, a sixth gate driving circuit L2, a GaN power switch MH2, a GaN power switch ML2, and a current limiting resistor RH2 and a current limiting resistor RL2 respectively connected to gate ends of MH2 and ML2, and the circuits adopt a double-sided layout structure when layout is implemented.

The connection relationship of the circuit is as follows: a first pulse width signal PWH output terminal of the controller U1 is connected to an input terminal of the first gate driving circuit H, a second pulse width signal PWL output terminal of the controller U1 is connected to an input terminal of the second gate driving circuit L, a third pulse width signal PWH1 output terminal of the controller U1 is connected to an input terminal of the third gate driving circuit H1, a fourth pulse width signal PWL1 output terminal of the controller U1 is connected to an input terminal of the fourth gate driving circuit L1, a fifth pulse width signal PWH2 output terminal of the controller U1 is connected to an input terminal of the fifth gate driving circuit H2, and a sixth pulse width signal PWL2 output terminal of the controller U1 is connected to an input terminal of the sixth gate driving circuit L2; the output end of the first gate drive circuit H is connected to the left end of a current-limiting resistor RH, the right end of the current-limiting resistor RH is connected to the gate end of a GaN power switch MH, the output end of the second gate drive circuit L is connected to the left end of a current-limiting resistor RL, the right end of the current-limiting resistor RL is connected to the gate end of a GaN power switch ML, the output end of the third gate drive circuit H1 is connected to the left end of a current-limiting resistor RH1, the right end of a current-limiting resistor RH1 is connected to the gate end of a GaN power switch MH1, the output end of the fourth gate drive circuit L1 is connected to the left end of a current-limiting resistor RL1, the right end of a current-limiting resistor RL1 is connected to the gate end of a GaN power switch ML1, the output end of the fifth gate drive circuit H2 is connected to the left end of a current-limiting resistor RH2, the right end of a current-limiting resistor RH2 is connected to the gate end of an MH2, the output end of. The source end of a GaN power switch MH is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH is a half-bridge output HB, the half-bridge output HB is connected to the drain end of a GaN power switch ML and the left end of an inductor Lc1, and the source end of the GaN power switch ML is connected to the lower ends of an input low-voltage bus Vgnd and a capacitor C1; the source end of a GaN power switch MH1 is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH1 is a half-bridge output HB1, the half-bridge output HB1 is connected to the drain end of the GaN power switch ML1 and the left end of an inductor Lc2, and the source end of the GaN power switch ML1 is connected to the lower ends of the input low-voltage bus Vgnd and a capacitor C2; the source end of a GaN power switch MH2 is connected to an input high-voltage bus Vbus, the drain end of the GaN power switch MH2 is a half-bridge output HB2, the half-bridge output HB2 is connected to the drain end of the GaN power switch ML2 and the left end of an inductor Lc3, and the source end of the GaN power switch ML2 is connected to the lower ends of the input low-voltage bus Vgnd and the capacitor C3. The right end of the inductor Lc1 is connected to the upper end of the capacitor C1, the first input port of the detection circuit U2, the upper end of the output capacitor C4, the lower end of the output capacitor C6 and the first-phase output high-voltage bus UO; the right end of the inductor Lc2 is connected to the upper end of the capacitor C2, the second input port of the detection circuit U2, the lower end of the output capacitor C4, the upper end of the output capacitor C5 and the second-phase output high-voltage bus Vo; the right end of the inductor Lc3 is connected to the upper end of the capacitor C3, the third input port of the detection circuit U2, the lower end of the output capacitor C5, the upper end of the output capacitor C6 and the third-phase output high-voltage bus Wo. The voltage detection signal f1, the current detection signal f2 and the temperature detection signal f3 output by the detection circuit U2 are respectively connected to three input ends of a feedback circuit U3; the first output fb1, the second output fb2 and the third output fb3 of the feedback circuit U3 are connected to three input terminals of the controller U1, respectively. The feedback circuit U3 processes the voltage detection signal, the current detection signal, and the temperature detection signal into feedback signals fb1, fb2, fb3, respectively, and outputs the feedback signals to the controller U1.

In practical applications of the circuit shown in fig. 1, the first gate driving circuit H and the second gate driving circuit L may be implemented by using a half-bridge driving circuit, so that the gate driving circuits may be combined into one. Meanwhile, the output current of the existing GaN device can not reach the current of a silicon-based device, and in order to realize the large-current output capability, the GaN power switch provided by the invention usually adopts a plurality of small-current switch tubes which are connected in parallel to realize large-current output. In order to realize the optimal switching frequency, the GaN power switch adopts an HEMT device in an LGA packaging mode, and the influence of parasitic parameters is reduced to the maximum extent. The controller U1 may be implemented by an analog linear circuit or a DSP, and the layout area and layout mode of the controller may be different according to different controller types. All gate drive circuits of the invention can complete related functions by adopting the existing enhanced GaN HEMT drive chip; the detection circuit U2 can be realized by adopting a temperature detection circuit, a current detection circuit and a voltage detection circuit which are commonly used by the existing switching power supply; the feedback circuit U3 adopts an optical coupler device to transmit signals, and then the signals are processed by a voltage integrating circuit to realize the feedback.

The corresponding working waveforms of the three-phase full-bridge inverter circuit shown in fig. 1 are shown in fig. 2, and the upper and lower switching tubes of each bridge arm are alternately conducted by 180. So that the current flowing through each phase load is continuous. The PWH, PWH1 and PWH2 voltages are rectangular waves, the amplitude is Vcc, and the phase difference among the voltages is 120 degrees; the phase voltage is 6 step waves, the amplitude is +/-2 Vcc/3, the width of each step is 60, and the phase difference between the voltages is 120 degrees. In the current-mode inverter, an inductor L is used as an energy storage element, and when L is large, the input current IL is approximately constant because the current in L cannot be suddenly changed. The time sequences of the driving signals of the power switch tubes sequentially differ by 60 degrees, the power switch tubes are respectively conducted by 120 degrees in sequence, and thus, only two power switch tubes are conducted at any time. In the case of resistive load, the current flowing through each power switching tube has a width of 120 ° and a height of IL, and the waveforms of the load currents Iu, Iv, and Iw are trapezoidal waves with steep front and rear edges. When the resistive load is Y (star) connected, waveforms of the phase current and the current of the 120 ° conduction current type three-phase full-bridge inverter circuit are shown in fig. 2. The waveforms of the load phase currents Iu, Iv, and Iw are rectangular waves having a width of 120 ° and a height IL.

FIG. 3 is a layout diagram of a double-sided layout of the present invention, which includes a first GaN half-bridge layout region 21, a second GaN half-bridge layout region 22, a third GaN half-bridge layout region 23, a detection circuit U2 layout region, an output capacitor C4 layout region, an output capacitor C5 layout region, an output capacitor C6 layout region, and a low voltage power supply region 24; the first GaN half-bridge layout region 21, the second GaN half-bridge layout region 22, the third GaN half-bridge layout region 23, the detection circuit U2 layout region, the output capacitor C4 layout region, the output capacitor C5 layout region and the output capacitor C6 layout region are distributed on the front side, and the low-voltage power supply region 24 is distributed on the back side; all the 6-way PWM pulse width signals between the front and back sides, as well as the voltage detection signal f1, the current detection signal f2, and the temperature detection signal f3, are connected through vias. The first GaN half-bridge layout area 21, the second GaN half-bridge layout area 22 and the third GaN half-bridge layout area 23 adopt the same layout mode of GaN half-bridge layout areas.

The first GaN half-bridge layout area 21 comprises a first grid drive circuit H layout area, a second grid drive circuit L layout area, a current-limiting resistor RH layout area, a current-limiting resistor RL layout area, a GaN power switch MH layout area, a GaN power switch ML layout area, a first radiator layout area, a half-bridge output HB layout area, an inductor Lc1 layout area, a capacitor C1 layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the first radiator layout area is distributed in the half-bridge output HB layout area.

The second GaN half-bridge layout area 22 internally comprises a third gate drive circuit H1 layout area, a fourth gate drive circuit L1 layout area, a current-limiting resistor RH1 layout area, a current-limiting resistor RL1 layout area, a GaN power switch MH1 layout area, a GaN power switch ML1 layout area, a second radiator layout area, a half-bridge output HB1 layout area, an inductor Lc2 layout area, a capacitor C2 layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the second radiator layout area is distributed in the half-bridge output HB1 layout area.

The third GaN half-bridge layout area 23 internally comprises a fifth gate drive circuit H2 layout area, a sixth gate drive circuit L2 layout area, a current-limiting resistor RH2 layout area, a current-limiting resistor RL2 layout area, a GaN power switch MH2 layout area, a GaN power switch ML2 layout area, a third radiator layout area, a half-bridge output HB2 layout area, an inductor Lc3 layout area, a capacitor C3 layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the third radiator layout area is distributed in the half-bridge output HB2 layout area.

The output capacitor C4 layout area is bridged between the first GaN half-bridge layout area 21 and the second GaN half-bridge layout area 22, the output capacitor C5 layout area is bridged between the second GaN half-bridge layout area 22 and the third GaN half-bridge layout area 23, and the output capacitor C6 layout area is bridged between the first GaN half-bridge layout area 21 and the third GaN half-bridge layout area 23.

The low-voltage power supply area 24 internally comprises a controller U1 version area, a feedback circuit U3 version area and a low-voltage ground wire version area 24-1.

Fig. 4 is a detailed layout diagram of the GaN half-bridge layout region according to the present invention, the layout structure of the three GaN half-bridge layout regions is the same, and the reference numeral of the first GaN half-bridge layout region 21 is used as an example for description.

The GaN power switch MH and the GaN power switch ML are realized by connecting 2 low-current HEMT devices in parallel, namely MH is formed by connecting an HEMT device MH11 and an HEMT device MH12 in parallel, and ML is formed by connecting an HEMT device ML11 and an HEMT device ML12 in parallel. The input high-voltage bus Vbus layout area located inside the GaN half-bridge layout area is of a C-shaped half-surrounding structure, and taking the inside of the first GaN half-bridge layout area 21 as an example, a through hole P _ PWH layout area, a first gate drive circuit H layout area, a current-limiting resistor RH layout area, a HEMT device MH11 layout area and a HEMT device MH12 layout area are distributed in the space surrounded by the C-shaped half-surrounding structure. The HEMT device MH11 layout area and the left side of HEMT device MH 12's layout area, the gate end position is towards the right-hand member PH of current-limiting resistor RH promptly, the metal wire of the right-hand member PH of current-limiting resistor RH to the gate end of HEMT device MH11 and the metal wire length of the right-hand member PH of current-limiting resistor RH to the gate end of HEMT device MH12 must strictly equal to the length of two metal wires all must be less than 5mm, the contained angle between the while must be less than 120 degrees. Two ends of the C-shaped semi-surrounding structure of the input high-voltage bus Vbus layout area adopt right-angled triangle structures, and the hypotenuses of the 2 right-angled triangles are opposite and are respectively connected with a source electrode of an HEMT device MH11 layout area and a source electrode of an HEMT device MH12 layout area. The input high-voltage bus Vbus layout area is completely covered by a metal layer and comprises 2 through hole layout areas P _ H1 and P _ H2. The drain electrode of HEMT device MH11 version region and HEMT device MH12 version region sandwich the upper left corner of half-bridge output HB version region, and its shape is an isosceles triangle with its vertex angle towards left and is an acute angle, and there is a through hole version region P _ T1 inside the isosceles triangle.

The input high-voltage ground wire Vgnd layout area also adopts a C-shaped semi-surrounding structure, and a second through hole P _ PWL layout area, a second gate drive circuit L layout area, a current-limiting resistance RL layout area, a HEMT device ML11 layout area and a HEMT device ML12 layout area are distributed in the surrounding space. The HEMT device ML11 layout area and the left side of the HEMT device ML12 layout area, namely the grid end position faces the right end PL of the current limiting resistor RL, the lengths of a metal wire from the right end PL of the current limiting resistor RL to the grid end of the HEMT device ML11 and a metal wire from the right end PL of the current limiting resistor RL to the grid end of the HEMT device ML12 must be strictly equal, the lengths of the two metal wires must be smaller than 5mm, and the included angle between the two metal wires must be smaller than 120 degrees. The input high-voltage ground wire Vgnd layout area adopts a C-shaped semi-surrounding structure, two end parts of the input high-voltage ground wire Vgnd area adopt right-angled triangle structures, and the hypotenuses of the 2 right-angled triangles are opposite and are respectively connected with a source electrode of the HEMT device ML11 layout area and a source electrode of the HEMT device ML12 layout area. The input high-voltage ground wire Vgnd layout area is completely covered by a metal layer and comprises 2 through hole layout areas P _ L1 and P _ L2. The left lower corner of the half-bridge output HB layout area is clamped between the drain electrode of the HEMT device ML11 layout area and the drain electrode of the HEMT device ML12 layout area, the shape of the HEMT device ML11 layout area is an isosceles triangle with the vertex angle facing to the left and an acute angle, and a through hole layout area P _ T2 is arranged inside the isosceles triangle. The right side of the half-bridge output HB layout area contains a via layout area P _ T3 for connecting to the transformer layout area.

In the embodiment of the present invention, the detailed layout diagram of the GaN half-bridge layout area shown in fig. 4 includes 2 gate driving circuit layout areas, 2 current limiting resistor layout areas, 4 GaN power switch layout areas, 1 heat sink 1 layout area, 1 half-bridge output HB layout area, an input high voltage bus Vbus layout area, and an input high voltage ground Vgnd layout area. In practical applications, if a half-bridge driver is used, only 1 gate driver layout area is needed in fig. 4. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, 6 GaN power switch layout areas are needed in fig. 4; if a single GaN power switch is formed by connecting 4 low current GaN power switches in parallel, 8 GaN power switch layout areas are needed in fig. 4.

Further, the layout mode shown in fig. 4 of the present invention is adopted to layout a full-bridge GaN power module (i.e., GaN half-bridge circuit is changed into GaN full-bridge circuit), and each GaN full-bridge circuit needs 4 gate driving circuit layout areas, 4 current limiting resistor layout areas, 8 GaN power switch layout areas, 2 heat sink 1 layout areas, 2 half-bridge output HB layout areas, an input high-voltage bus Vbus layout area, and an input high-voltage ground Vgnd layout area. In practical application, if a full-bridge driver is adopted, only 1 gate driving circuit layout area is needed in fig. 4; if a half-bridge driver is used, only 2 gate driver layout areas are needed in fig. 4. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, 12 GaN power switch layout areas are needed in fig. 4; if a single GaN power switch is formed by connecting 4 low current GaN power switches in parallel, 16 GaN power switch layout areas are needed in fig. 4.

Further, the layout of the three-phase full-bridge GaN power module needs 6 gate drive circuit layout areas, 6 current-limiting resistance layout areas, 12 GaN power switch layout areas, 3 radiator 1 layout areas, 3 half-bridge output HB layout areas, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area. In practical application, if a three-phase full-bridge driver is adopted, the three-phase full-bridge GaN power module only needs 1 gate drive circuit layout area; if a half-bridge driver is adopted, the three-phase full-bridge GaN power module only needs 3 grid driving circuit layout areas. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, the three-phase full-bridge GaN power module needs 18 GaN power switch layout areas; if a single GaN power switch is formed by connecting 4 low-current GaN power switches in parallel, the three-phase full-bridge GaN power module needs 24 GaN power switch layout areas.

The number of the gate driving circuits, the current limiting resistors and the GaN power switching tubes adopted in the output voltage region is equal to the number of the gate driving circuits, the current limiting resistors and the GaN power switching tubes adopted in the input high voltage region in fig. 4. Therefore, when the full-bridge GaN power module is adopted, the output voltage region needs 4 gate drive circuit layout regions, 4 current-limiting resistance layout regions, 8 GaN power switch layout regions, an input high-voltage bus Vbus layout region and an input high-voltage ground wire Vgnd layout region. In practical application, if a full-bridge driver is adopted, only 1 gate driving circuit layout area is needed in fig. 4; if a half-bridge driver is used, only 2 gate driver layout areas are needed in fig. 4. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, 12 GaN power switch layout areas are needed in fig. 4; if a single GaN power switch is formed by connecting 4 low-current GaN power switches in parallel, 16 GaN power switch layout areas are needed in fig. 4

When the three-phase full-bridge GaN power module is adopted, the output voltage area needs 6 gate drive circuit layout areas, 6 current-limiting resistance layout areas, 12 GaN power switch layout areas, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area. In practical application, if a three-phase full-bridge driver is adopted, the three-phase full-bridge GaN power module only needs 1 gate drive circuit layout area; if a half-bridge driver is adopted, the three-phase full-bridge GaN power module only needs 3 grid driving circuit layout areas. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, the three-phase full-bridge GaN power module needs 18 GaN power switch layout areas; if a single GaN power switch is formed by connecting 4 low-current GaN power switches in parallel, the three-phase full-bridge GaN power module needs 24 GaN power switch layout areas.

Fig. 5 is a practical layout diagram of a GaN half-bridge layout area implemented by the present invention, and the device layout is performed completely according to the layout mode shown in fig. 4, and is identified and explained by the reference number in the first GaN half-bridge layout area 21. The source electrode of the HEMT device ML11 version region and the HEMT device ML12 version region is connected with the Vgnd in a right-angled triangle hypotenuse contact mode, so that the current trend can be adapted. According to the HEMT device packaged by the LGA, the source end and the drain end of the HEMT device are of a multi-interdigital parallel structure, the main current of Vgnd is gathered and circulated on the left sides of the ML11 layout area and the ML2 layout area of the HEMT device, so that the current gathered near the left side part of the ML11 layout area of the HEMT device is larger than the current gathered near the right side part of the ML11 layout area of the HEMT device, the HEMT device is connected in a right-angled triangle bevel edge mode, the left side part of the ML11 layout area of the HEMT device is divided into the bottom of the bevel edge, and the right side part of the ML1 layout area of the HEMT device. The drain electrodes of the ML1 version area and the ML2 version area of the HEMT device are connected with the half-bridge output HB by adopting a right-angled triangle hypotenuse contact mode in the opposite direction. The first radiator adopts a circular columnar structure, and the layout area of the first radiator is distributed in the half-bridge output HB layout area. The lengths of the metal line from the right end PL of the current limiting resistor RL to the gate end of the HEMT device ML11 and the metal line from the right end PL of the current limiting resistor RL to the gate end of the HEMT device ML12 must be strictly equal. The lengths of the metal line from the right end PH of the current-limiting resistor RH to the gate terminal of the HEMT device MH11 and the metal line from the right end PH of the current-limiting resistor RH to the gate terminal of the HEMT device MH12 must be strictly equal. In each metal through hole region in the figure, the position of a specific through hole and the number of the through holes can be designed in a differentiated mode according to different power levels and requirements. The gray areas in the figure are all metal layer filling areas. The thick black lines are used to aid understanding of the applied region segmentation lines.

Fig. 6 is a diagram showing a practical layout of a low voltage power supply region 24 implemented by the present invention, which includes a controller U1 layout region, a feedback circuit U3 layout region, and a low voltage ground layout region 24-1. The signals PWL, PWH, PWL1, PWH1, PWL2, PWH2, f1, f2, and f3 are connected through vias. The PWL and PWH signals are low voltage pulse width signals output by the controller U1 to the gate driver, so the PWL and PWH signal wiring must be specially noted, first, the length, width and thickness of the two metal wires responsible for transmitting the PWL and PWH signal wires must be strictly equal; secondly, two metal wires need to adopt a parallel wiring mode, and the vertical distance between the two metal wires is not more than 2 mm; furthermore, the area through which the two metal lines run must be protected by isolation by the low-voltage ground metal area. The two metal wires which are responsible for transmitting the two PWL1 and PWH1 signals adopt the same layout mode as the two metal wires which transmit the PWL and PWH signals; the two metal wires responsible for transmitting the two signal wires PWL2 and PWH2 are laid in the same manner as the two metal wires transmitting the PWL and PWH signals. The gray areas in fig. 6 are also all metal layer fill areas. The thick black lines are used to aid understanding of the applied region segmentation lines.

Fig. 7 is a test waveform of a high-efficiency GaN three-phase inverter module for a new energy power generation system implemented by the present invention. It can be seen that the delay from the gate terminal PH signal of the GaN power switch to the output signal is 30ns, and the rise setup time of the PH signal is only 10ns, at this time, the rising and falling waveform functions of the half-bridge output signal HB are completely correct, the GaN power module realized by the layout mode of the present invention has correct functions, and the technical scheme of the present invention is feasible.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. New forms of energy power generation is high efficiency GaN three-phase inverter module for system, characterized by includes: a controller (U1), a first GaN half-bridge circuit (1), a second GaN half-bridge circuit (2), a third GaN half-bridge circuit (3), a detection circuit (U2), and a feedback circuit (U3); the first GaN half-bridge circuit (1) comprises a first grid drive circuit (H), a second grid drive circuit (L), a GaN power switch MH, a GaN power switch ML, a current-limiting resistor RH connected between the first grid drive circuit (H) and the GaN power switch MH, and a current-limiting resistor RL connected between the second grid drive circuit (L) and the GaN power switch ML; the second GaN half-bridge circuit (2) comprises a third gate drive circuit (H1), a fourth gate drive circuit (L1), a GaN power switch MH1 and a GaN power switch ML1, a current-limiting resistor RH1 connected between the third gate drive circuit (H1) and the GaN power switch MH1, and a current-limiting resistor RL1 connected between the fourth gate drive circuit (L1) and the GaN power switch ML 1; the third GaN half-bridge circuit (3) comprises a fifth gate drive circuit (H2), a sixth gate drive circuit (L2), a GaN power switch MH2 and a GaN power switch ML2, a current-limiting resistor RH2 connected between the fifth gate drive circuit (H2) and the GaN power switch MH2, and a current-limiting resistor RL2 connected between the sixth gate drive circuit (L2) and the GaN power switch ML 2;

the connection relationship of the circuit is as follows: a first pulse width signal PWH output terminal of the controller (U1) is connected to an input terminal of the first gate driving circuit (H), a second pulse width signal PWL output terminal of the controller (U1) is connected to an input terminal of the second gate driving circuit (L), a third pulse width signal PWH1 output terminal of the controller (U1) is connected to an input terminal of the third gate driving circuit (H1), a fourth pulse width signal PWL1 output terminal of the controller (U1) is connected to an input terminal of the fourth gate driving circuit (L1), a fifth pulse width signal PWH2 output terminal of the controller (U1) is connected to an input terminal of the fifth gate driving circuit (H2), and a sixth pulse width signal PWL2 output terminal of the controller (U1) is connected to an input terminal of the sixth gate driving circuit (L2);

the right end of the inductor Lc1 is connected to the upper end of the capacitor C1, a first input port of the detection circuit (U2), the upper end of the output capacitor C4, the lower end of the output capacitor C6 and the first-phase output high-voltage bus UO; the right end of the inductor Lc2 is connected to the upper end of the capacitor C2, a second input port of the detection circuit (U2), the lower end of the output capacitor C4, the upper end of the output capacitor C5 and the second-phase output high-voltage bus Vo; the right end of the inductor Lc3 is connected to the upper end of the capacitor C3, the third input port of the detection circuit (U2), the lower end of the output capacitor C5, the upper end of the output capacitor C6 and the third-phase output high-voltage bus Wo; the voltage detection signal, the current detection signal and the temperature detection signal which are output by the detection circuit (U2) and are applied to the three-phase inverter module are respectively connected to the input end of the feedback circuit (U3); the feedback circuit (U3) respectively processes the voltage detection signal, the current detection signal and the temperature detection signal into feedback signals and outputs the feedback signals to the controller (U1);

the circuit adopts two-sided layout structure when the territory is realized, two-sided layout structure includes: the GaN-based LED comprises a first GaN half-bridge layout region (21), a second GaN half-bridge layout region (22), a third GaN half-bridge layout region (23), a detection circuit (U2) layout region, an output capacitor C4 layout region, an output capacitor C5 layout region, an output capacitor C6 layout region and a low-voltage power supply region (24), wherein the first GaN half-bridge layout region, the second GaN half-bridge layout region and the third GaN half-bridge layout region are distributed on the front side; all PWM pulse width signals and all detection signals between the front side and the back side are connected with signals through holes;

the first GaN half-bridge layout area (21), the second GaN half-bridge layout area (22) and the third GaN half-bridge layout area (23) adopt the same layout mode of the GaN half-bridge layout areas, namely, the interior of the GaN half-bridge layout area comprises a gate drive circuit layout area, a current limiting resistor layout area, a GaN power switch layout area, a radiator layout area, a half-bridge output layout area, an inductance layout area, a capacitance layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the radiator layout areas are distributed in the half-bridge output layout area;

an output capacitor C4 layout area is bridged between the first GaN half-bridge layout area (21) and the second GaN half-bridge layout area (22), an output capacitor C5 layout area is bridged between the second GaN half-bridge layout area (22) and the third GaN half-bridge layout area (23), and an output capacitor C6 layout area is bridged between the first GaN half-bridge layout area (21) and the third GaN half-bridge layout area (23);

the low-voltage power supply area (24) internally comprises a controller (U1) layout area, a feedback circuit (U3) layout area and a low-voltage ground wire layout area;

all the GaN power switches adopt a plurality of low-current GaN power switches which are connected in parallel to realize high-current output; and all adopt HEMT devices of LGA packaging form;

the input high-voltage bus Vbus layout area and the input high-voltage ground wire Vgnd layout area both comprise C-type semi-surrounding structures, and the space surrounded by each C-type semi-surrounding structure is distributed with: the HEMT device comprises a through hole layout area, a gate drive circuit layout area, a current limiting resistor layout area and an HEMT device layout area;

the space surrounded by the C-shaped semi-surrounding structure of the input high-voltage bus Vbus layout area in the first GaN half-bridge layout area (21) is distributed with: a through hole P _ PWH layout area, a first gate drive circuit H layout area, a current limiting resistor RH layout area, a HEMT device MH11 layout area and a HEMT device MH12 layout area; the left side of the HEMT device MH11 layout area and the left side of the HEMT device MH12 layout area face the right end of the current-limiting resistor RH;

the space surrounded by the C-shaped semi-surrounding structure of the input high-voltage ground wire Vgnd layout area in the first GaN half-bridge layout area (21) is distributed with: the HEMT device comprises a through hole P _ PWL layout area, a second gate drive circuit L layout area, a current limiting resistor RL layout area, a HEMT device ML11 layout area and a HEMT device ML12 layout area; the left side of the layout area of the HEMT device ML11 and the left side of the layout area of the HEMT device ML12 face the right end of the current limiting resistor RL;

and the input high-voltage bus Vbus layout area and the input high-voltage ground wire Vgnd layout area in the second GaN half-bridge layout area (22) and the third GaN half-bridge layout area (23) both adopt the same C-shaped semi-surrounding structure as that of the first GaN half-bridge layout area (21).

2. The high-efficiency GaN three-phase inverter module for a new energy power generation system according to claim 1, wherein: the lengths of a metal wire from the right end of the current-limiting resistor RH to the grid end of the HEMT device MH11 and a metal wire from the right end of the current-limiting resistor RH to the grid end of the HEMT device MH12 are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees; the lengths of a metal wire from the right end of the current-limiting resistor RL to the grid end of the HEMT device ML11 and a metal wire from the right end of the current-limiting resistor RL to the grid end of the HEMT device ML12 are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees.

3. The high-efficiency GaN three-phase inverter module for a new energy power generation system according to claim 1, wherein: the two metal wires responsible for transmitting the first and second pulse width signals PWH and PWL, the two metal wires responsible for transmitting the third and fourth pulse width signals PWH1 and PWL1, and the two metal wires responsible for transmitting the fifth and sixth pulse width signals PWH2 and PWL2 have the following requirements: