CN110401365B

CN110401365B - GaN bridgeless PFC power module for high-power charger

Info

Publication number: CN110401365B
Application number: CN201910739167.2A
Authority: CN
Inventors: 周德金
Original assignee: Wuxi Innosys Technology Co Ltd
Current assignee: Wuxi InnoSys Technology Co., Ltd
Priority date: 2019-08-12
Filing date: 2019-08-12
Publication date: 2020-12-01
Anticipated expiration: 2039-08-12
Also published as: CN110401365A

Abstract

The invention relates to a GaN bridgeless PFC power supply module, comprising: the high-power LED driving circuit comprises an EMI filter circuit, a rectifying capacitor C2, an inductor L1, an inductor L2, a first GaN half-bridge circuit, a second GaN half-bridge circuit, a MOS (metal oxide semiconductor) tube MP, a MOS tube Mn, a third gate driving circuit, an output capacitor C1, an output detection circuit, an output feedback circuit, an input detection circuit, an input feedback circuit and a PFC controller. The circuit adopts two-sided layout structure when actual territory is laid out, includes: an input high voltage area positioned on the front surface, an input high voltage bus Vac area, an output voltage area and a low voltage power supply area positioned on the back surface. The invention realizes larger power output by adopting a staggered parallel technology on the basis of the existing bridgeless boost APFC technology; a novel GaN high-speed switching device is adopted for switching conversion, so that higher power density is realized; the layout optimization is carried out on the GaN device, the staggered parallel signals and the high-voltage bus by adopting a double-sided layout structure, the reliability is improved, and the high-voltage bus-bar-type GaN-based high-power charger system can be widely applied to various high-power charger systems.

Description

GaN bridgeless PFC power module for high-power charger

Technical Field

The invention relates to a GaN bridgeless PFC power supply module for a high-power charger, which is used for a high-power charger system and belongs to the field of power electronics.

Background

In the 21 st century, under the traction of emerging industries such as smart grid, mobile communication and new energy automobile, power electronic application systems require further improvement of system efficiency, miniaturization and added functions, and particularly require trade-offs between circuit application size, quality, power and efficiency, such as server power management, battery charger and micro-inverter of solar electric field. The above applications require power electronics systems to be efficient in design>95% of the total power, and also has high power density (>500W/in³I.e. 30.5W/cm³) High specific power (10 kW/lb, 22kW/kg) and high total load point(s) ((>1000W). With the emergence and application popularization of super junction MOSFETs and Insulated Gate Bipolar Transistors (IGBTs), the device performance gradually approaches the limit of silicon materials, the rule that the power density is increased by 1 time every four years tends to saturate (moore's law in the field of power electronics), and the development of silicon-based power semiconductor devices with power densities of only single digit is difficult due to the reasons mentioned above.

In recent years, third-generation semiconductor power devices represented by gallium nitride (GaN) have significantly better performance than first-generation and second-generation semiconductor materials such as Si, Ge, GaAs, and the like in the microelectronic field of high power, high temperature, high frequency, and radiation resistance and the short-wavelength photoelectron field due to high forbidden bandwidth, high breakdown electric field intensity, and high electron saturation velocity. GaN power devices have superior on-state characteristics and superior switching characteristics compared to Si devices, and thus attract attention of the industry in a short time, and researchers engaged in application research have also conducted a lot of research works to apply them to low-voltage and low-power supply devices such as POL, DC/DC, and the like. Research shows that the switching frequency can be greatly improved by replacing a Si device with a GaN device, and good efficiency indexes are kept. Certainly, GaN devices will be more and more commonly used in low voltage, low power applications, and greatly contribute to the performance improvement of power supply devices in these fields in terms of power density, efficiency, and the like.

The current design of new energy automobiles and electric vehicles power battery charger systems faces increasingly serious challenges, and higher charging efficiency and higher charging power are required. With the increasingly strict requirements of the whole vehicle system on the miniaturization and the power density of the power supply module, how to provide higher and higher output power under the condition of unchanged space, and the system has ultrahigh-speed transient response and optimal cost performance, and is a comprehensive bottleneck problem of the design of the charger power supply. The technical requirements of the high-performance vehicle-mounted charger are as follows: high power density, high efficiency, high power factor and low harmonic, electrical isolation, overvoltage, overcurrent, short circuit protection, etc. In order to meet the requirements, a typical vehicle-mounted charger mainly adopts a two-stage topology in terms of circuit topology, a front-stage non-isolated AC-DC converter is used for power factor correction and outputs stable direct-current bus voltage, and a rear-stage isolated DC-DC converter is used for realizing electrical isolation between a power grid input side and a battery output side and outputting voltage and current required by a charging instruction. The charging command is usually given by the battery management system of the battery pack and is sent to the charger in a specific communication manner.

The currently used power factor correction techniques are mainly two, active correction and passive correction. The passive correction network is composed of passive devices such as a capacitor, an inductor and a power diode, and the higher harmonic is reduced by improving the rectification conduction angle to improve the power factor. The passive method has the advantages of simple control, low cost and high reliability, but has large volume and is difficult to obtain high power factor. The active power factor correction can obtain very high power factor, has small volume and is widely applied to the switching power supply. The most important research focus of the power factor correction technology is the research of novel circuit topology, and compared with boost topology, the boost topology has multiple advantages: the inductor is close to the input end, the input current has small pulsation and small EMI, the input current is easy to control, the reliability under the short circuit of the load is high, and the like, so the inductor is most widely applied in the industry. The typical boost APFC structure needs to add a diode rectifier bridge in front of the converter, and the switching tube works in a hard switching state, so that 2 problems exist in medium-high power application occasions: (1) the low-voltage working condition under the requirement of wide input voltage, the input current is large, and the loss of a rectifier bridge is large; (2) under the high-frequency working condition, the switching loss is large, and the EMI is serious. The improved technology for the above problems includes: bridgeless PFC technology, interleaved parallel technology and soft switching technology.

A basic bridgeless boost APFC converter, also called a dual boost APFC converter, is shown in fig. 1. When the input voltage is in a positive half cycle, L1-M1-D1 and M2 are involved in working to form one boost circuit, and when the input voltage is in a negative half cycle, L1-M2-D2 and M1 are involved in working to form the other boost circuit. Compared with a traditional boost APFC circuit, the bridgeless circuit omits two diodes, and the input current only flows through 1 diode and two MOS tubes, so that the conduction loss is reduced. However, the circuit shown in fig. 1 has difficulty in achieving high power output, and further improvement and optimization are required for the purpose. In order to realize larger power output, the staggered parallel technology is a feasible measure, but the power mismatch between staggered parallel phases must be limited; in order to realize higher power density, the switching conversion by adopting a novel high-speed switching device is a main approach.

The characteristics of the GaN device enable the grid drive charge (Qg) of the GaN device to be very small, the junction capacitance to be very small, and the switching speed to be much faster than that of the Si device. The advantage brought by the increase of the switching frequency is the increase of the power density, so that the development of a novel PFC power supply module by adopting a GaN device is a good technical approach. However, the power density is increased by increasing the switching frequency, and two bottleneck problems need to be faced: firstly, the current change of a switch branch circuit in the switching process of a GaN device is very rapid, the di/dt is very high, and because parasitic inductance inevitably exists in a power loop, when the current changes rapidly, very high peak overvoltage can be generated at two ends of the switch device. If the voltage is light, the malfunction of the circuit and the EMI exceeding standard are caused, and if the voltage is heavy, the breakdown and the damage of the device are caused. The very high switching speed of GaN devices results in parasitic oscillations and overvoltage phenomena during their switching process that are much more pronounced than Si devices. GaN devices are more sensitive to parasitic inductance in the circuit due to faster switching speeds. If the wiring is not optimized enough and the parasitic inductance is large, the normal operation of the circuit can be directly influenced. Secondly, as the power density of the GaN power module is improved, the heat dissipation requirement of the power device is stricter. The reason is that the module volume is reduced, and the choice and placement of the heat sink structure is more sensitive to the performance impact of the module than conventional power modules.

In summary, for the application requirements of charging new energy vehicles, the existing bridgeless boost APFC technology has the defects of low efficiency, insufficient power level and insufficient power density. On the basis of the existing bridgeless boost APFC technology, the invention adopts the staggered parallel technology to realize larger power output; a novel GaN high-speed switching device is adopted for switching conversion, so that higher power density is realized; and a double-sided layout structure is adopted to perform layout optimization on the GaN device, the staggered parallel signals and the high-voltage bus, so that the reliability is improved.

Disclosure of Invention

Aiming at the application challenge faced when a GaN power device is adopted for power integration, the GaN bridgeless PFC power module adopts the GaN power device to be applied to a high-power charger, and provides an optimized design in the aspects of a grid driving circuit, device layout, heat dissipation and the like.

According to the technical scheme provided by the invention, the GaN bridgeless PFC power supply module for the high-power charger comprises: the power supply comprises an EMI filter circuit, a rectifying capacitor C2, an inductor L1, an inductor L2, a first GaN half-bridge circuit, a second GaN half-bridge circuit, an MOS (metal oxide semiconductor) tube MP, an MOS tube Mn, a third gate drive circuit, an output capacitor C1, an output detection circuit, an output feedback circuit, an input detection circuit, an input feedback circuit and a PFC controller;

the input high-voltage alternating current bus AC is connected to the input end of the EMI filter circuit; the high-voltage output end Vac of the EMI filter circuit is connected to the upper end of the rectifying capacitor C2, the first input end of the input detection circuit, the left end of the inductor L1, and the left end of the inductor L2; a low-voltage output end Vacgnd of the EMI filter circuit is connected to a second input end of the input detection circuit, a source end of the MOS tube MP and a source end of the MOS tube Mn; the right end VH of the inductor L1 is connected to the high voltage input of the first GaN half bridge circuit and the low voltage input of the second GaN half bridge circuit; the right end VL of the inductor L2 is connected to the low voltage input of the first GaN half bridge circuit and the high voltage input of the second GaN half bridge circuit; the output ends of a first pulse width signal PWH1 and a second pulse width signal PWL1 of the PFC controller are respectively connected to the high-side and low-side input ends of the first GaN half-bridge circuit, the output ends of a third pulse width signal PWH2 and a fourth pulse width signal PWL2 of the PFC controller are respectively connected to the high-side and low-side input ends of the second GaN half-bridge circuit, and the output ends of a fifth pulse width signal PWH3 and a sixth pulse width signal PWL3 of the PFC controller are respectively connected to the high-side and low-side input ends of the third gate drive circuit; the half-bridge output end of the first GaN half-bridge circuit is connected to the output high-voltage bus end Vout +, the drain end of the MOS tube MP, the second input port of the output detection circuit and the upper end of the output capacitor C1; the half-bridge output end of the second GaN half-bridge circuit is connected to the output low-voltage bus end Vout-, the drain end of the MOS tube Mn, the first input port of the output detection circuit and the lower end of the output capacitor C1; an output voltage detection signal output end, an output current detection signal output end and a temperature detection signal output end of the output detection circuit are respectively connected to an input end of the output feedback circuit; the output voltage feedback signal, the output current feedback signal and the temperature feedback signal which are obtained through the processing of the output feedback circuit are respectively connected to the input end of the PFC controller; an input voltage detection signal output end and an input current detection signal output end of the input detection circuit are respectively connected to an input end of the input feedback circuit, and an input voltage feedback signal and an input current feedback signal which are obtained through processing of the input feedback circuit are respectively connected to an input end of the PFC controller.

Specifically, the first GaN half-bridge circuit and the second GaN half-bridge circuit use the same GaN half-bridge circuit, and the GaN half-bridge circuit includes: the power supply comprises a first gate driving circuit, a second gate driving circuit, a first GaN power switch, a second GaN power switch, a first current limiting resistor and a second current limiting resistor; the high-side input end of the GaN half-bridge circuit is connected to the input end of the first gate drive circuit; the low-side input end of the GaN half-bridge circuit is connected to the input end of the second gate drive circuit; the output end of the first gate driving circuit is connected to the left end of the first current-limiting resistor, the right end of the first current-limiting resistor is connected to the gate end of the first GaN power switch, the output end of the second gate driving circuit is connected to the left end of the second current-limiting resistor, and the right end of the second current-limiting resistor is connected to the gate end of the second GaN power switch; the source end of the first GaN power switch, namely the high-voltage input end of the GaN half-bridge circuit, is connected to the input high-voltage bus Vbus; the drain terminal of the first GaN power switch is a half-bridge output HB, and the half-bridge output HB is connected to the drain terminal of the second GaN power switch; the source terminal of the second GaN power switch, i.e., the low voltage input terminal of the GaN half bridge circuit, is connected to the input low voltage bus Vgnd.

Specifically, the first GaN power switch and the second GaN power switch are connected in parallel by adopting a plurality of low-current GaN power switches to realize high-current output, and are both HEMT devices in an LGA packaging form.

Specifically, the circuit adopts two-sided layout structure when actual territory overall arrangement, includes: an input high-voltage area, an input high-voltage bus Vac area, an output voltage area and a low-voltage power supply area; the input high-voltage area, the input high-voltage bus Vac area and the output voltage area are distributed on the front surface, the low-voltage power supply area is distributed on the back surface, and all PWM pulse width signals between the front surface and the back surface, input voltage detection signals, input current detection signals, output voltage detection signals, output current detection signals and temperature detection signals are connected through holes;

the input high-pressure region includes therein: the circuit comprises an EMI filter circuit layout area, a rectifier capacitor C2 layout area, an input detection circuit layout area, an input high-voltage alternating current bus AC layout area and an input high-voltage ground wire layout area;

the output voltage section includes therein: the circuit comprises a first GaN half-bridge circuit layout area, a first radiator layout area, a second GaN half-bridge circuit layout area, a second radiator layout area, an inductor L1 layout area, an inductor L2 layout area, a third gate drive circuit layout area, a MOS (metal oxide semiconductor) tube Mp layout area, a MOS tube Mn layout area, a third radiator layout area, an output capacitor C1 layout area, an output high-voltage bus Vout + layout area, an output low-voltage bus Vout-layout area, a VH layout area, a VL layout area and an output detection circuit layout area; the first radiator layout area is arranged in the first GaN half-bridge circuit layout area, and the second radiator layout area is arranged in the second GaN half-bridge circuit layout area;

the input high-voltage bus Vac area is bridged between the input high-voltage area and the output voltage area, and the left side of the input high-voltage bus Vac area is superposed with the right side of the EMI filter circuit layout area; the right side of an input high-voltage bus Vac area is coincided with the left side of an inductor L1 layout area and the left side of an inductor L2 layout area in an output voltage area;

the low-voltage power supply area internally comprises a PFC controller layout area, an input feedback circuit layout area, an output feedback circuit layout area and a low-voltage ground wire layout area.

Specifically, first GaN half-bridge circuit layout district and second GaN half-bridge circuit layout district adopt the GaN half-bridge layout district of the same structure, and this GaN half-bridge layout district includes: the HEMT device comprises a first gate drive circuit H layout area, a second gate drive circuit L layout area, a first current-limiting resistance layout area, a second current-limiting resistance layout area, a first through hole layout area, a second through hole layout area, a third through hole layout area, a first HEMT device layout area, a second HEMT device layout area, a third HEMT device layout area, a fourth HEMT device layout area, a first radiator layout area, a half-bridge output HB layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area; the first HEMT device and the second HEMT device are connected in parallel to form a first GaN power switch, and the third HEMT device and the fourth HEMT device are connected in parallel to form a second GaN power switch; the first radiator layout area is distributed in the half-bridge output HB layout area.

Specifically, the input high-voltage bus Vbus layout area adopts a C-type half-surrounding structure, and a space surrounded by the C-type half-surrounding structure is distributed with: the HEMT device comprises a first through hole layout area, a first gate drive circuit H layout area, a first current limiting resistor layout area, a first HEMT device layout area and a second HEMT device layout area; the left side of the first HEMT device layout area and the left side of the second HEMT device layout area face the right end of the first current-limiting resistor;

two end parts of the input high-voltage bus Vbus layout region C-shaped semi-surrounding structure are both in a right-angled triangle structure, and the hypotenuses of the 2 right-angled triangles are opposite and are respectively connected with the source electrodes of the first HEMT device layout region and the second HEMT device layout region; the drain electrodes of the first HEMT device layout area and the second HEMT device layout area sandwich the upper left corner of the half-bridge output HB layout area, and the upper left corner is in the shape of an isosceles triangle with a vertex angle facing left and an acute angle;

the input high-voltage ground wire Vgnd layout area adopts the same C-shaped semi-surrounding structure, and a second through hole layout area, a second gate drive circuit L layout area, a second current-limiting resistance layout area, a third HEMT device layout area and a fourth HEMT device layout area are distributed in the surrounded space; the left side of the layout area of the third HEMT device and the left side of the layout area of the fourth HEMT device face the right end of the second current-limiting resistor;

two end parts of the input high-voltage ground wire Vgnd layout area C-type semi-surrounding structure are of right-angled triangle structures, and the hypotenuses of the 2 right-angled triangles are opposite and are respectively connected with the source electrodes of the third HEMT device layout area and the fourth HEMT device layout area; the lower left corner of the half-bridge output HB layout area is clamped between the drain electrodes of the third HEMT device layout area and the fourth HEMT device layout area, and the lower left corner is in the shape of an isosceles triangle with an acute angle towards the left.

Specifically, the length of a metal wire from the right end of the first current limiting resistor to the gate end of the first HEMT device is strictly equal to the length of a metal wire from the right end of the first current limiting resistor to the gate end of the second HEMT device, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees; and the lengths of a metal wire from the right end of the second current-limiting resistor to the grid end of the third HEMT device and a metal wire from the right end of the second current-limiting resistor to the grid end of the fourth HEMT device are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees.

Specifically, the two metal wires responsible for transmitting the first pulse width signal PWH1 and the second pulse width signal PWL1, the two metal wires responsible for transmitting the third pulse width signal PWH2 and the fourth pulse width signal PWL2, and the two metal wires responsible for transmitting the fifth pulse width signal PWH3 and the sixth pulse width signal PWL3 have the following requirements:

the length, width and thickness of the first and second metal wires must be strictly equal;

secondly, two metal wires need to adopt a parallel wiring mode, and the vertical distance between the two metal wires is not more than 2 mm;

and thirdly, the area passed by the layout of the two metal wires must be isolated and protected by a low-voltage ground wire.

The invention has the advantages that: the GaN bridgeless PFC power supply module for the high-power charger provided by the invention adopts a staggered parallel technology to realize larger power output on the basis of the existing bridgeless boost PFC technology; a novel GaN high-speed switching device is adopted for switching conversion, so that higher power density is realized; the layout optimization is carried out on the GaN device, the staggered parallel signals and the high-voltage bus by adopting a double-sided layout structure, the reliability is improved, and the high-voltage bus-bar-type GaN-based high-power charger system can be widely applied to various high-power charger systems.

Drawings

Fig. 1 is a diagram of a conventional PFC circuit without a bridge.

Fig. 2 is a circuit configuration diagram of the present invention.

FIG. 3 is a schematic diagram of a GaN half-bridge circuit according to the present invention.

FIG. 4 is a double-sided layout of the power module of the present invention.

FIG. 5 is a detailed layout of the GaN half-bridge layout area of the present invention.

FIG. 6 is a diagram of the actual layout of a GaN half-bridge layout area implemented by the present invention.

Fig. 7 is a diagram showing an actual layout of a controller and an output feedback section in a low voltage power supply area realized by the present invention.

FIG. 8 is a test waveform using an embodiment of the present invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings and examples.

Fig. 2 is a circuit structure diagram of a GaN bridgeless PFC power supply module for a high-power charger according to the present invention, which includes an EMI filter circuit U6, a rectifier capacitor C2, an inductor L1, an inductor L2, a first GaN half bridge circuit U7, a second GaN half bridge circuit U8, a MOS transistor MP, a MOS transistor Mn, a third gate drive circuit, an output capacitor C1, an output detection circuit U3, an output feedback circuit U2, an input detection circuit U5, an input feedback circuit U4, and a PFC controller U1.

The circuit connection relationship is as follows: the input high-voltage alternating current bus AC is connected to the input end of the EMI filter circuit U6; a high-voltage output end Vac of the EMI filter circuit U6 is connected to the upper end of the rectifying capacitor C2, the first input end of the input detection circuit U5, the left end of the inductor L1, and the left end of the inductor L2; a low-voltage output end Vacgnd of the EMI filter circuit U6 is connected to a second input end of the input detection circuit U5, a source end of the MOS tube MP and a source end of the MOS tube Mn; the right terminal VH of inductor L1 is connected to the high side input of the first GaN half bridge circuit U7 and the low side input of the second GaN half bridge circuit U8; the right terminal VL of inductor L2 is connected to the low side input terminal of first GaN half bridge U7 and the high side input terminal of second GaN half bridge U8; first and second pulse width signal PWH1 and PWL1 output terminals of the PFC controller U1 are respectively connected to high-side H and low-side L input terminals of the first GaN half bridge circuit U7, third and fourth pulse width signal PWH2 and PWL2 output terminals of the PFC controller U1 are respectively connected to high-side and low-side input terminals of the second GaN half bridge circuit U8, and fifth and sixth pulse width signal PWH3 and PWL3 output terminals of the PFC controller U1 are respectively connected to high-side and low-side input terminals of the third gate drive circuit; the half-bridge output end of the first GaN half-bridge circuit U7 is connected to the output high-voltage bus end Vout +, the drain end of the MOS transistor MP, the second input port of the output detection circuit U3 and the upper end of the output capacitor C1; the half-bridge output end of the second GaN half-bridge circuit U8 is connected to the output low-voltage bus terminal Vout-, the drain terminal of the MOS transistor Mn, the first input port of the output detection circuit U3 and the lower end of the output capacitor C1. An output voltage detection signal f1 output end, an output current detection signal f2 output end and a temperature detection signal f3 output end of the output detection circuit U3 are respectively connected to a first input end, a second input end and a third input end of an output feedback circuit U2; the output voltage feedback signal fb1, the output current feedback signal fb2 and the temperature feedback signal fb3 which are processed by the output feedback circuit U2 are respectively connected to a first input end, a second input end and a third input end of the PFC controller U1; an output end of an input voltage detection signal ff1 and an output end of an input current detection signal ff2 of the input detection circuit U5 are respectively connected to a first input end and a second input end of the input feedback circuit U4, and an input voltage feedback signal ffb1 and an input current feedback signal ffb2 which are obtained by processing of the input feedback circuit U4 are respectively connected to a fourth input end and a fifth input end of the PFC controller U1.

The circuit adopts a double-sided layout structure when in actual layout.

The improvement of the bridgeless PFC power supply module circuit structure provided by the invention on the basis of the existing bridgeless boost APFC technology in figure 1 is mainly 2 points: (1) and a staggered parallel technology is adopted to realize larger power output. In the figure, an inductor L1, a first GaN half-bridge circuit U7 and a MOS tube Mp form a boost APFC branch; inductor L2, second GaN half bridge U8 and MOS transistor Mn form another boost APFC branch. To increase the output power, the power switches of the conventional bridgeless boost APFC are replaced by GaN half-bridge circuits. (2) And a novel GaN high-speed switching device is adopted for switching conversion, so that higher power density is realized. By adopting the GaN device packaged by the LGA, the switching frequency of the PFC module can easily exceed 500KHz, the volume is greatly reduced, and the power density is improved. In addition, the invention also adopts a double-sided layout structure to carry out layout optimization on the GaN device, the staggered parallel signals and the high-voltage bus, thereby improving the reliability. The mode of operation of the circuit of fig. 2 is similar to that of the substantially bridgeless PFC of fig. 1 and will not be described again.

The first GaN half-bridge circuit U7 and the second GaN half-bridge circuit U8 used in the present invention are the same GaN half-bridge circuit, and the circuit structure diagram is shown in fig. 3. The GaN half-bridge circuit includes: the power switch MH of the first gate driving circuit H, the power switch MH of the second gate driving circuit L, GaN, the GaN power switch ML, the current limiting resistor RH and the current limiting resistor RL. The high-side input terminal of the GaN half-bridge circuit, i.e., the pulse width signal PWH (corresponding to PWH1, PWH2 of fig. 2) is connected to the input terminal of the first gate driving circuit (H); the input terminal at the low side of the GaN half-bridge circuit, namely a pulse width signal PWL (corresponding to PWL1, PWL2 of fig. 2) is connected to the input terminal of the second gate driving circuit L; the output end of the first gate drive circuit H is connected to the left end of a current-limiting resistor RH, the right end of the current-limiting resistor RH is connected to the gate end of a GaN power switch MH, the output end of the second gate drive circuit L is connected to the left end of a current-limiting resistor RL, and the right end of the current-limiting resistor RL is connected to the gate end of the GaN power switch ML; the source end of the GaN power switch MH, namely the high-voltage input end of the GaN half-bridge circuit, is connected to an input high-voltage bus Vbus; the drain terminal of the GaN power switch MH is a half-bridge output HB, and the half-bridge output HB is connected to the drain terminal of the GaN power switch ML; the source terminal of the GaN power switch ML, i.e., the low voltage input terminal of the GaN half bridge circuit, is connected to the input low voltage bus Vgnd.

In the circuit configuration of fig. 2, among 3 sets of pulse width signals output by the PFC controller U1, PWH1 and PWL1 are first set of complementary pulse signals, PWH2 and PWL2 are second set of complementary pulse signals, and PWH3 and PWL3 are third set of complementary pulse signals. The first and second sets of complementary pulse signals are high-frequency signals with frequency exceeding 500KHz and are used for driving the high-speed GaN switching device; the third group of complementary pulse signals are low-speed pulse signals with the frequency equal to the power frequency signals and are used for driving the MOS tube MP and the MOS tube Mn.

In practical applications of the GaN half-bridge circuit shown in fig. 3, the first gate driving circuit H and the second gate driving circuit L can be implemented by using one half-bridge driving circuit, so that the gate driving circuits can be combined into one. Meanwhile, the output current of the existing GaN device cannot reach the current of a silicon-based device, and in order to realize the large-current output capacity, the GaN power switch provided by the invention realizes large-current output by connecting a plurality of small-current switch tubes in parallel. In order to realize the optimal switching frequency, the GaN power switch MH and the GaN power switch ML both adopt HEMT devices in an LGA packaging mode, and the influence of parasitic parameters is reduced to the maximum extent.

The PFC controller U1 may be implemented by an analog linear circuit or a DSP, and the layout area and the layout mode of the PFC controller may be different according to different controller types. The first pulse width signal PWH1 and the third pulse width signal PWH2 output by the PFC controller may be the same signal, and the second pulse width signal PWL1 and the fourth pulse width signal PWL2 output by the PFC controller may also be the same signal.

The gate driving circuit can complete related functions by adopting the existing enhanced GaNHEMT driving chip; the input detection circuit U5 and the output detection circuit U3 can be realized by adopting a temperature detection circuit, a current detection circuit and a voltage detection circuit which are commonly used by the existing switching power supply; the input feedback circuit U4 and the output feedback circuit U2 adopt optical coupling devices for signal transmission and then are processed by a voltage integrating circuit.

Fig. 4 is a structural diagram of a double-sided layout adopted by the present invention, which includes an input high voltage area 31, an input high voltage bus Vac area 32, an output voltage area 33, and a low voltage power supply area 34. The input high-voltage area 31, the input high-voltage bus Vac area 32 and the output voltage area 33 are distributed on the front side of the power module, the low-voltage power supply area 34 is distributed on the back side, and a first pulse width signal PWH1, a second pulse width signal PWL1, a third pulse width signal PWH2, a fourth pulse width signal PWL2, a fifth pulse width signal PWH3, a sixth pulse width signal PWL3, an input voltage detection signal ff1, an input current detection signal ff2, an output voltage detection signal f1, an output current detection signal f2 and an output temperature detection signal f3 between the front side and the back side are connected through holes.

The input high-voltage area 31 internally comprises an EMI filter circuit U6 layout area, a rectifier capacitor C2 layout area, an input detection circuit U5 layout area, an input high-voltage alternating current bus AC layout area and an input high-voltage ground wire layout area.

The output voltage region 33 internally comprises a first GaN half-bridge U7 layout region, a first radiator layout region, a second GaN half-bridge U8 layout region, a second radiator layout region, an inductor L1 layout region, an inductor L2 layout region, a third gate drive circuit layout region, a MOS (metal oxide semiconductor) tube MP layout region, a MOS tube Mn layout region, a third radiator layout region, an output capacitor C1 layout region, an output high-voltage bus Vout + layout region, an output low-voltage bus Vout-layout region, a VH layout region, a VL layout region and a detection circuit layout region; the first heat sink layout area is inside the first GaN half-bridge U7 layout area, and the second heat sink layout area is inside the second GaN half-bridge U8 layout area.

The input high-voltage bus Vac area 32 is bridged between the input high-voltage area 31 and the output voltage area 33, and the left side of the input high-voltage bus Vac area 32 is superposed with the right side of an EMI filter circuit U6 version area; the right side of the input high-voltage bus Vac area 32 is simultaneously superposed with the left side of an inductor L1 layout area and an inductor L2 layout area in the output voltage area 33.

The low-voltage power supply area 34 internally comprises a PFC controller U1 layout area, an input feedback circuit U4 layout area, an output feedback circuit U2 layout area and a low-voltage ground wire layout area.

The first GaN half-bridge U7 layout area and the second GaN half-bridge U8 layout area adopt the same GaN half-bridge layout area. FIG. 5 is a detailed layout of the GaN half-bridge layout area. The GaN power switch MH and the GaN power switch ML are realized by connecting 2 low-current HEMT devices in parallel, namely the GaN power switch MH is formed by connecting a first HEMT device MH1 and a second HEMT device MH2 in parallel, and the GaN power switch ML is formed by connecting a third HEMT device ML1 and a fourth HEMT device ML2 in parallel. The GaN half-bridge layout area internally comprises a first gate drive circuit H layout area, a second gate drive circuit L layout area, a first current-limiting resistor RH layout area, a second current-limiting resistor RL layout area, a first through hole P _ PWH layout area, a second through hole P _ PWL layout area, a third through hole P _ T3 layout area, a first HEMT device MH1 layout area, a second HEMT device MH2 layout area, a third HEMT device ML1 layout area, a fourth HEMT device ML2 layout area, a first radiator layout area, a half-bridge output HB layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area, and the first radiator layout area is distributed inside the half-bridge output HB layout area.

The input high-voltage bus Vbus layout area adopts a C-shaped semi-surrounding structure, and a first through hole P _ PWH layout area, a first gate drive circuit H layout area, a current-limiting resistor RH layout area, a first HEMT device MH1 layout area and a second HEMT device MH2 layout area are distributed in a surrounding space. The left side in first HEMT device MH1 version region and second HEMT device MH 2's version region, the grid end position is towards the right-hand member PH of current-limiting resistor RH promptly, the right-hand member PH of current-limiting resistor RH reaches the metal wire of first HEMT device MH1 grid end and the right-hand member PH of current-limiting resistor RH reaches the metal wire length of second HEMT device MH2 grid end must strictly equal to the length of two metal wires all must be less than 5mm, the contained angle between the while must be less than 120 degrees. Two ends of the input high-voltage bus Vbus layout area adopting a C-shaped semi-surrounding structure all adopt right-angled triangle structures, and the hypotenuses of the 2 right-angled triangles are opposite and are respectively connected with the source electrodes of a first HEMT device MH1 layout area and a second HEMT device MH2 layout area. The input high-voltage bus Vbus layout area is completely covered by a metal layer and comprises 2 through hole layout areas P _ H1 and P _ H2. The upper left corner of the half-bridge output HB layout area is arranged between the drain electrodes of the first HEMT device MH1 layout area and the second HEMT device MH2 layout area, the shape of the upper left corner is an isosceles triangle with the vertex angle facing to the left and being an acute angle, and a through hole layout area P _ T1 is arranged inside the isosceles triangle.

The input high-voltage ground wire Vgnd layout area adopts the same C-shaped semi-surrounding structure, and a second through hole P _ PWL layout area, a second gate drive circuit L layout area, a second current-limiting resistor RL layout area, a third HEMT device ML1 layout area and a fourth HEMT device ML2 layout area are distributed in the surrounding space. The gate end of the left side of the layout area of the third HEMT device ML1 and the left side of the layout area of the fourth HEMT device ML2, namely the gate end position, faces to the right end PL of the second current limiting resistor RL, the lengths of a metal wire from the right end PL of the second current limiting resistor RL to the gate end of the third HEMT device ML1 and a metal wire from the right end PL of the second current limiting resistor RL to the gate end of the fourth HEMT device ML2 must be strictly equal, the lengths of the two metal wires must be smaller than 5mm, and the included angle between the two metal wires must be smaller than 120 degrees. Two ends of the input high-voltage ground wire Vgnd layout area which adopts a C-shaped semi-surrounding structure both adopt right-angled triangle structures, and the hypotenuses of the 2 right-angled triangles are opposite and respectively connected with the source electrodes of the third HEMT device ML1 layout area and the fourth HEMT device ML2 layout area. The input high-voltage ground wire Vgnd layout area is completely covered by a metal layer and comprises 2 through hole layout areas P _ L1 and P _ L2. The left lower corner of the half-bridge output HB layout area is arranged between the drain electrodes of the layout area of the third HEMT device ML1 and the layout area of the fourth HEMT device ML2, the shape of the left lower corner is an isosceles triangle with the top angle towards the left and an acute angle, and a through hole layout area P _ T2 is arranged inside the isosceles triangle.

In the embodiment of the present invention, the detailed layout diagram of the input high voltage region 31 shown in fig. 5 includes 2 gate driving circuit layout regions, 2 current limiting resistor layout regions, 4 GaN power switch layout regions, 1 first heat sink layout region, 1 half-bridge output HB layout region, an input high voltage bus Vbus layout region, and an input high voltage ground Vgnd layout region. In practical applications, if a half-bridge driver is used, only 1 gate driver layout area is needed in fig. 5. If a single GaN power switch is formed by connecting 3 low-current GaN power switches in parallel, 6 GaN power switch layout areas are needed in fig. 5; if a single GaN power switch is formed by connecting 4 low current GaN power switches in parallel, 8 GaN power switch layout areas are needed in fig. 5.

FIG. 6 is a diagram of the actual layout of a GaN half-bridge layout area implemented by the present invention. The source electrode of the region of the third HEMT device ML1 version and the source electrode of the region of the fourth HEMT device ML2 version are connected with Vgnd in a right-angled triangle hypotenuse contact mode, so that the current trend can be adapted. According to the HEMT device packaged by the LGA, the source end and the drain end of the HEMT device adopt a multi-interdigital parallel structure, and the main current of Vgnd is gathered and circulated on the left sides of the ML1 layout area of the third HEMT device and the ML2 layout area of the fourth HEMT device, so that the current gathered near the left side part of the ML1 layout area of the third HEMT device is larger than the current gathered near the right side part of the ML1 layout area of the third HEMT device, the connection is performed by adopting a right-angled triangle hypotenuse mode, the left side part near the ML1 layout area of the third HEMT device is the bottom of the hypotenuse, and the right side part near the ML1 layout area of the third HEMT device is the top. The drain electrodes of the layout region of the third HEMT device ML1 and the layout region of the fourth HEMT device ML2 are connected with the half-bridge output HB by adopting a right-angled triangle hypotenuse contact mode in the opposite direction. The first radiator adopts a circular columnar structure, and the layout area of the first radiator is distributed in the half-bridge output HB layout area. The lengths of the metal line from the right end PL of the second current-limiting resistor RL to the gate end of the third HEMT device ML1 and the metal line from the right end PL of the second current-limiting resistor RL to the gate end of the fourth sub HEMT device ML2 must be strictly equal. The lengths of a metal wire from the right end PH of the current-limiting resistor RH to the gate end of the first HEMT device MH1 and a metal wire from the right end PH of the current-limiting resistor RH to the gate end of the second HEMT device MH2 must be strictly equal. In each metal through hole region in the figure, the position of a specific through hole and the number of the through holes can be designed in a differentiated mode according to different power levels and requirements. The gray areas in the figure are all metal layer filling areas. The thick black lines are used to aid understanding of the applied region segmentation lines.

The specific layout of the third gate driving circuit layout area, the MOS transistor MP layout area, the MOS transistor Mn layout area, the third radiator layout area, the VH layout area, the VL layout area, the output high voltage bus Vout + layout area, and the output low voltage bus Vout-layout area inside the output voltage area 33 according to the present invention can be implemented by using a layout similar to that of fig. 4. The VH and VL layout areas respectively adopt a C-shaped surrounding structure similar to that of the above, and respectively surround an MOS (metal oxide semiconductor) transistor MP layout area and an MOS transistor Mn layout area; the right sides of the C-shaped surrounding structures of the VH layout area and the VL layout area are an output high-voltage bus Vout + layout area and an output low-voltage bus Vout-layout area respectively; an output capacitor C1 layout area is arranged between the output high-voltage bus Vout + layout area and the output low-voltage bus Vout-layout area; in addition, the detection circuit layout area may be disposed on the right side of the output capacitor C1 layout area. In the invention, a half-bridge output HB layout area in a GaN half-bridge 1 layout area is connected with the left side of the VH layout area, and a half-bridge output HB layout area in a GaN half-bridge 2 layout area is connected with the left side of the VL layout area.

Fig. 7 is a diagram showing the actual layout of the controller and the output feedback section in the low voltage power supply section 34 implemented by the present invention, including a PFC controller U1 layout section, an output feedback circuit U2 layout section, and a low voltage ground layout section 34-1. The signals PWL2, PWH2, f1, f2, and f3 are connected through vias. The PWL2 and PWH2 signals are low-voltage pulse width signals output by the PFC controller U1 to the gate driver, so the PWL2 and PWH2 signal wiring must be specially noted, and the two metal wires responsible for transmitting the PWL2 and PWH2 signals must be strictly equal in length, width and thickness; secondly, two metal wires need to adopt a parallel wiring mode, and the vertical distance between the two metal wires is not more than 2 mm; furthermore, the area through which the two metal lines run must be protected by isolation by the low-voltage ground metal area. The layout area of the input feedback circuit U4 in the invention is realized by adopting a layout mode similar to that of the layout area of the output feedback circuit U2 in the invention shown in FIG. 6, and in addition, the requirements of metal wires responsible for transmitting signals of PWL1 and PWH1 are the same as those of PWL2 and PWH2, and the requirements of metal wires responsible for transmitting signals of PWL3 and PWH3 are the same as those of PWL2 and PWH 2. The gray areas in fig. 6 are also all metal layer fill areas. The thick black lines are used to aid understanding of the applied region segmentation lines.

Fig. 8 is a test waveform of a GaN bridgeless PFC power module for a high-power charger implemented in an embodiment of the present invention. It can be seen that the period of the PL and PH signal waveforms of the gate terminal of the GaN power switch is 1us, the corresponding operating frequency is 1MHz, the rising and falling waveform functions are completely correct, the GaN power module functions correctly by adopting the layout method of the present invention, and the technical scheme of the present invention is feasible.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A GaN does not have bridge PFC power module for high-power machine that charges, characterized by includes: the circuit comprises an EMI filter circuit (U6), a rectifying capacitor C2, an inductor L1, an inductor L2, a first GaN half-bridge circuit (U7), a second GaN half-bridge circuit (U8), a MOS (metal oxide semiconductor) transistor MP, a MOS transistor Mn, a third gate drive circuit, an output capacitor C1, an output detection circuit (U3), an output feedback circuit (U2), an input detection circuit (U5), an input feedback circuit (U4) and a PFC controller (U1);

the input high voltage AC bus is connected to the input end of the EMI filter circuit (U6); a high-voltage output end Vac of the EMI filter circuit (U6) is connected to the upper end of the rectifying capacitor C2, a first input end of the input detection circuit (U5), the left end of the inductor L1 and the left end of the inductor L2; a low-voltage output end Vacgnd of the EMI filter circuit (U6) is connected to a second input end of the input detection circuit (U5), a source end of the MOS tube MP and a source end of the MOS tube Mn; the right end VH of the inductor L1 is connected to the high voltage input of the first GaN half bridge circuit (U7) and the low voltage input of the second GaN half bridge circuit (U8); the right end VL of the inductor L2 is connected to the low voltage input of the first GaN half bridge circuit (U7) and the high voltage input of the second GaN half bridge circuit (U8); first and second pulse width signal PWH1 and PWL1 output terminals of a PFC controller (U1) are respectively connected to high-side and low-side input terminals of a first GaN half-bridge circuit (U7), third and fourth pulse width signal PWH2 and PWL2 output terminals of the PFC controller (U1) are respectively connected to high-side and low-side input terminals of a second GaN half-bridge circuit (U8), and fifth and sixth pulse width signal PWH3 and PWL3 output terminals of the PFC controller (U1) are respectively connected to high-side and low-side input terminals of a third gate drive circuit; the half-bridge output end of the first GaN half-bridge circuit (U7) is connected to the output high-voltage bus end Vout +, the drain end of the MOS transistor MP, the second input port of the output detection circuit (U3) and the upper end of the output capacitor C1; the half-bridge output end of the second GaN half-bridge circuit (U8) is connected to the output low-voltage bus end Vout-, the drain end of the MOS tube Mn, the first input port of the output detection circuit (U3) and the lower end of the output capacitor C1; an output voltage detection signal output end, an output current detection signal output end and a temperature detection signal output end of the output detection circuit (U3) are respectively connected to an input end of the output feedback circuit (U2); an output voltage feedback signal, an output current feedback signal and a temperature feedback signal which are obtained by processing of the output feedback circuit (U2) are respectively connected to the input end of the PFC controller (U1); an input voltage detection signal output end and an input current detection signal output end of the input detection circuit (U5) are respectively connected to an input end of the input feedback circuit (U4), and an input voltage feedback signal and an input current feedback signal which are obtained by processing of the input feedback circuit (U4) are respectively connected to an input end of the PFC controller (U1);

the first GaN half-bridge circuit (U7) and the second GaN half-bridge circuit (U8) employ the same GaN half-bridge circuit, which includes: the power supply circuit comprises a first gate driving circuit (H), a second gate driving circuit (L), a first GaN power switch, a second GaN power switch, a first current limiting resistor and a second current limiting resistor; the high-side input end of the GaN half-bridge circuit is connected to the input end of the first gate drive circuit (H); the low-side input end of the GaN half-bridge circuit is connected to the input end of the second gate drive circuit (L); the output end of the first gate drive circuit (H) is connected to the left end of the first current-limiting resistor, the right end of the first current-limiting resistor is connected to the gate end of the first GaN power switch, the output end of the second gate drive circuit (L) is connected to the left end of the second current-limiting resistor, and the right end of the second current-limiting resistor is connected to the gate end of the second GaN power switch; the source end of the first GaN power switch, namely the high-voltage input end of the GaN half-bridge circuit, is connected to the input high-voltage bus Vbus; the drain terminal of the first GaN power switch is a half-bridge output HB, and the half-bridge output HB is connected to the drain terminal of the second GaN power switch; the source end of the second GaN power switch, namely the low-voltage input end of the GaN half-bridge circuit, is connected to the input low-voltage bus Vgnd;

the first GaN power switch and the second GaN power switch are connected in parallel by adopting a plurality of low-current GaN power switches to realize high-current output, and are both HEMT devices in an LGA packaging form;

the circuit adopts two-sided layout structure when actual territory is laid out, includes: an input high voltage area (31), an input high voltage bus Vac area (32), an output voltage area (33) and a low voltage power supply area (34); the input high-voltage area (31), the input high-voltage bus Vac area (32) and the output voltage area (33) are distributed on the front surface, the low-voltage power supply area (34) is distributed on the back surface, and all PWM pulse width signals between the front surface and the back surface, input voltage detection signals, input current detection signals, output voltage detection signals, output current detection signals and temperature detection signals are connected through holes;

the input high-pressure region (31) includes therein: an EMI filter circuit (U6) layout area, a rectifier capacitor C2 layout area, an input detection circuit (U5) layout area, an input high-voltage alternating current bus AC layout area and an input high-voltage ground wire layout area;

the output voltage section (33) internally comprises: a first GaN half-bridge circuit (U7) layout area, a first radiator layout area, a second GaN half-bridge circuit (U8) layout area, a second radiator layout area, an inductor L1 layout area, an inductor L2 layout area, a third gate drive circuit layout area, a MOS transistor Mp layout area, a MOS transistor Mn layout area, a third radiator layout area, an output capacitor C1 layout area, an output high-voltage bus Vout + layout area, an output low-voltage bus Vout-layout area, a VH layout area, a VL layout area and an output detection circuit (U3) layout area; the first radiator layout area is arranged in a first GaN half-bridge circuit (U7) layout area, and the second radiator layout area is arranged in a second GaN half-bridge circuit (U8) layout area;

the input high-voltage bus Vac area (32) is bridged between the input high-voltage area (31) and the output voltage area (33), and the left side of the input high-voltage bus Vac area is superposed with the right side of the version area of the EMI filter circuit (U6); the right side of an input high-voltage bus Vac area is coincided with the left side of an inductor L1 layout area and the left side of an inductor L2 layout area in an output voltage area;

the low-voltage power supply area (34) internally comprises a PFC controller (U1) layout area, an input feedback circuit (U4) layout area, an output feedback circuit (U2) layout area and a low-voltage ground line layout area (34-1).

2. The GaN bridgeless PFC power module for the high power charger according to claim 1, wherein the first GaN half bridge circuit (U7) layout area and the second GaN half bridge circuit (U8) layout area adopt GaN half bridge layout areas with the same structure, and the GaN half bridge layout areas include: the HEMT device comprises a first gate drive circuit H layout area, a second gate drive circuit L layout area, a first current-limiting resistance layout area, a second current-limiting resistance layout area, a first through hole layout area, a second through hole layout area, a third through hole layout area, a first HEMT device layout area, a second HEMT device layout area, a third HEMT device layout area, a fourth HEMT device layout area, a first radiator layout area, a half-bridge output HB layout area, an input high-voltage bus Vbus layout area and an input high-voltage ground wire Vgnd layout area; the first HEMT device and the second HEMT device are connected in parallel to form a first GaN power switch, and the third HEMT device and the fourth HEMT device are connected in parallel to form a second GaN power switch; the first radiator layout area is distributed in the half-bridge output HB layout area.

3. The GaN bridgeless PFC power supply module for the high-power charger according to claim 2, characterized in that the input high-voltage bus Vbus layout area adopts a C-type semi-surrounding structure, and the space surrounded by the area is distributed with: the HEMT device comprises a first through hole layout area, a first gate drive circuit H layout area, a first current limiting resistor layout area, a first HEMT device layout area and a second HEMT device layout area; the left side of the first HEMT device layout area and the left side of the second HEMT device layout area face the right end of the first current-limiting resistor;

4. The GaN bridgeless PFC power supply module for the high-power charger according to claim 3, wherein the length of a metal wire from the right end of the first current-limiting resistor to the gate end of the first HEMT device is strictly equal to the length of a metal wire from the right end of the first current-limiting resistor to the gate end of the second HEMT device, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees; and the lengths of a metal wire from the right end of the second current-limiting resistor to the grid end of the third HEMT device and a metal wire from the right end of the second current-limiting resistor to the grid end of the fourth HEMT device are strictly equal, the lengths of the two metal wires are both less than 5mm, and the included angle between the two metal wires is less than 120 degrees.

5. The GaN bridgeless PFC power module for a high power charger according to claim 1, wherein the two wires responsible for transmitting the first and second pulse width signals PWH1 and PWL1, the three wires responsible for transmitting the third and fourth pulse width signals PWH2 and PWL2, and the two wires responsible for transmitting the fifth and sixth pulse width signals PWH3 and PWL3 have the following requirements: