CN109921667B

CN109921667B - Virtual CPS-PWM control method of cascade multilevel digital power amplifier with asymmetric structure

Info

Publication number: CN109921667B
Application number: CN201910212185.5A
Authority: CN
Inventors: 罗安; 郭鹏; 岳雨霏; 徐千鸣; 纪勇; 胡家瑜
Original assignee: Hunan University
Current assignee: Hunan University
Priority date: 2019-03-20
Filing date: 2019-03-20
Publication date: 2021-02-09
Anticipated expiration: 2039-03-20
Also published as: CN109921667A

Abstract

The invention discloses a virtual CPS-PWM control method of a cascade multilevel digital power amplifier with an asymmetric structure, wherein cascade multilevel of the asymmetric structure isThe level digital power amplifier comprises N cascaded full-bridge power units, a constant direct current voltage source is connected in parallel to the direct current side of each full-bridge power unit, the alternating current output of each full-bridge power unit is connected with a load, and the direct current side voltage of the first (N-1) power units in the N cascaded full-bridge power units is set to be U_dcThe voltage on the DC side of the Nth power unit is set to be U_dc/3. The invention greatly increases the level number of the output voltage of the cascade multi-level digital power amplifier, improves the output harmonic characteristic of the digital power amplifier and improves the fidelity.

Description

Virtual CPS-PWM control method of cascade multilevel digital power amplifier with asymmetric structure

Technical Field

The invention relates to the field of digital power amplifier control, in particular to a virtual CPS-PWM control method of a cascade multilevel digital power amplifier with an asymmetric structure.

Background

At sea, national defense sentinels are important barriers for maintaining national security, and China clearly points out that the bottleneck technology for breaking through a three-dimensional monitoring system of an ocean space and information transmission equipment is important, wherein a high-power electroacoustic transducer system is taken as a main research direction, and the core of the electroacoustic transducer system is a digital power amplifier. With the great improvement of the voltage grade and the power grade of the power electronic equipment, the cascaded multi-level digital power amplifier applied to high-voltage and high-power occasions receives wide attention of the industry and the academia, and develops rapidly at home and abroad. The cascaded multi-level digital power amplifier is more suitable for high-power application occasions, has the advantages of high modularization, easiness in expansion, high redundancy and low output harmonic distortion rate, each power unit has an independent direct-current voltage source, the capacitor voltage of each power unit does not need to be balanced and controlled, the direct series connection of switching devices is avoided by the design scheme of the series connection of the multi-power units, the contradiction between the grade of each power device and the grade of a high-voltage power grid system is solved, and the application development of the digital power amplifier in a high-voltage high-power electroacoustic transducer system is promoted. The most important performance of the digital power amplifier is the output harmonic characteristic, the fidelity of the digital power amplifier can be improved by improving the harmonic characteristic, and the magnitude of the output harmonic distortion rate is directly influenced by increasing the number of output levels. The direct factor influencing the output voltage level number is the modulation technology of a digital power amplifier, at present, level approximation modulation (NLM) and carrier phase shift pulse width modulation (CPS-PWM) are widely applied in the field of manufacturing of cascaded multi-level digital power amplifier equipment, the level approximation modulation (NLM) is used for approximately modulating sine waves by utilizing step waves, and the carrier phase shift pulse width modulation (CPS-PWM) is used for realizing the reproduction of sine waves by comparing sine modulation signals and a plurality of carrier signals and superposing pulse signals. Therefore, on the premise of not increasing the number of cascaded power units, if the number of output levels can be further increased on the basis of CPS-PWM modulation, the method has important engineering reference significance for developing the cascaded multi-level digital power amplifier.

Disclosure of Invention

The invention aims to provide a virtual CPS-PWM control method of a cascade multilevel digital power amplifier with an asymmetric structure, which increases the level number of output voltage and reduces harmonic distortion rate by increasing the output level number under the condition of keeping the number of cascade power units unchanged.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a virtual CPS-PWM control method for cascade multilevel digital power amplifier with asymmetric structure includes N cascade full bridge power units, each power unit has a DC side connected in parallel with a constant DC voltage source, the AC output of each power unit is connected with load, and the DC side voltage of the first (N-1) power units in the cascade N power units is set as U_dcThe voltage on the DC side of the Nth power unit is set to be U_dcA/3; the method comprises the following steps:

1) normalizing the output voltage, and collecting the output voltage of each power unit as u in the first (N-1) cascaded power units_ciWith { +1, -1, 0}, the range of the cascade output voltage is denoted u_cN-1∈[-(N-1)，(N-1)]，u_cN-1The voltage value corresponding to each level of (1); the set of the output voltages of the Nth power unit is u_cN＝{+1/3，-1/3，0}，u_cN1/3 for each level; the total output voltage of the cascaded multi-level digital power amplifier with the asymmetric structure can be expressed as: u. of_o＝u_cN-1+u_cN；

2) The cascade output voltage u of the first (N-1) power units_cN-1And the Nth power unit output voltage u_cNThe voltage value of each level is unified to 1/3, the output level number of the cascade multi-level digital power amplifier with the asymmetrical structure is 6N-3, and the level variation range is [ - (3N-2), (3N-2)]Calculating to obtain the number of cascade power units required under a corresponding traditional carrier phase-shift pulse width modulation mode (CPS-PWM) to be 3N-2, equivalently regarding the cascade multilevel digital power amplifier with an asymmetric structure as being formed by cascading 3N-2 virtual full-bridge power units, wherein the direct-current side voltage value of each virtual power unit is 1/3;

3) respectively comparing the modulation signal with 3N-2 carrier signals to obtain output switch signals of 3N-2 virtual power units by adopting 3N-2 carrier generators with phase shift angles of pi/(3N-2) in sequence, and superposing the output switch signals to obtain output voltage u containing 6N-3 levels_oThe value range is u_o∈[-(3N-2)/3，(3N-2)/3]；

4) According to the relation u between the output voltage of the power amplifier and the output voltage of the first (N-1) power units and the output voltage of the Nth power unit_o＝u_cN-1+u_cNIn u_cNSelecting a suitable output voltage value from the set of u_cN-1Is an integer according to the voltage value u at that time_cN-1And u_cNThe first (N-1) power units and the Nth power unit are matchedAnd setting a switch signal.

The invention sets N full-bridge sub-module cascades, and sets the direct-current side voltage of the front (N-1) sub-module as U_dcThe voltage on the DC side of the Nth sub-module is set to be U_dcDesigning a cascaded multi-level digital power amplifier with an asymmetric direct-current side voltage structure; the output voltage value of the asymmetric structure is equivalently obtained by utilizing the modulation principle of the traditional CPS-PWM, and U is converted into the output voltage value of the asymmetric structure through reasonably configuring the switching signals of the sub-modules_dcThe voltage value of/3 is superposed on the output voltage of the front (N-1) sub-module, so that the output voltage generates more levels, and the number of output levels is increased.

The voltage class of the switching device of the nth power cell is 1/3 of the voltage class of the switching device of the first (N-1) power cell.

Multilevel output voltage u_o＝(N-1)u_r+u_r/3＝(N-2/3)u_r(ii) a Wherein u is_rIs a modulated signal.

Output voltage u of 6N-3 level_oThe calculation formula of (2) is as follows:

u_o∈[-(3N-2)/3，(3N-2)/3]；H_ioutput switching signals of the virtual full-bridge power unit; n' is the number of virtual full bridge power cells.

The specific implementation process for configuring the switching signals for the first (N-1) power units and the nth power unit includes: according to the output voltage u_oThe output voltage of the Nth power unit is in the set u_cNThe values are respectively selected from { +1/3, -1/3, 0} to obtain the guarantee u_cN-1＝u_o-u_cNUnique u corresponding to integer_cNValue, if and only if u_cNWhen +1/3, u_cN-1＝u_o-u_cNIs an integer, the number of output levels of the first (N-1) power units is u_cN-11, of the first (N-1) power cells, u is configured_cN-1The switching signal of each power unit is +1 or-1, and the rest (N-1- | u) is configured_cN-1|) the switching signal of the power unit is 0, and the switching signal of the nth power unit is 1.

Compared with the prior art, the invention has the beneficial effects that: according to the invention, through setting different direct-current side voltage values of the power units, CPS-PWM modulation control is carried out by using the virtual power units on the premise of output level equivalence, so that the level number of the output voltage of the cascaded multi-level digital power amplifier is greatly increased on the premise of not increasing the number of the cascaded power units, the output harmonic characteristic of the digital power amplifier is improved, and the fidelity is improved.

Drawings

Fig. 1 is a block diagram of a cascaded multi-level digital power amplifier for use in an asymmetric architecture of the present invention.

Fig. 2 is a schematic diagram of a full bridge power unit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a virtual CPS-PWM modulation scheme in accordance with one embodiment of the present invention.

Fig. 4 is an asymmetric level superposition scheme according to an embodiment of the present invention.

Detailed Description

Fig. 1 is a block diagram of a cascaded multi-level digital power amplifier in an asymmetric configuration. In the figure, the digital power amplifier is formed by cascading N full-bridge power units from 1# -N #, the output supplies power to a load, and each full-bridge power unit is provided with T₁～T₄The power switching device comprises four groups of power switching devices, and each group of power switching devices comprises an IGBT and an anti-parallel diode. The DC side capacitor voltage of the 1# to (N-1) # full bridge power unit is U_dcThe DC side capacitor voltage of the Nth # full-bridge power unit is U_dc/3。L_fThe output filter inductor is used for filtering out higher harmonic components and ensuring that the cascaded multi-level digital power amplifier has better sinusoidal characteristic.

The method comprises the following steps:

1) for convenient calculation, the direct current side voltages of the N sub-modules are all divided by U_dcThen the dc-side voltage of the first (N-1) sub-module can be normalized to 1, and the dc-side voltage of the nth sub-module can be normalized to 1/3; the output switching signals of the full-bridge sub-modules are +1, -1 and 0, respectively, so that in the first (N-1) sub-modules each oneSet of output voltages u of the submodules_ciAnd the value range u of the total output voltage after the cascade connection of the front (N-1) sub-modules_cN-1And a set u of nth sub-module output voltages_cNCan be expressed as

2) Suppose the modulation signal is u_r∈[-1，1]The modulation signal is expanded to the level grade of the number of the cascade modules, and the output voltage value u can be calculated_oIs shown as

u_o＝(N-1)u_r+u_r/3＝(N-2/3)u_r

Converting the modulated signal into a multi-level voltage u according to the condition that each level voltage value is 1/3_oForm (d) found u_oThe number of the levels is 6N-3, and if the number of the cascaded full-bridge sub-modules is N ' and the number of the output voltage levels is 2N ' +1 when the traditional CPS-PWM modulation mode is adopted, the relation between N and N ' should be satisfied if the output voltage reaches 6N-3 levels

N'＝3N-2

On the premise of equivalent output level, N' substantially represents the number of virtual cascaded sub-modules under traditional CPS-PWM modulation when the asymmetric cascaded multi-level digital power amplifier contains N cascaded full-bridge sub-modules, and the dc-side voltage of each virtual sub-module is 1/3.

3) Modulating a cascade structure containing N' virtual full-bridge submodules by adopting a traditional CPS-PWM modulation mode, and modulating a modulation signal u_rRespectively comparing with N 'virtual carriers with phase shift angle pi/N' in sequence to obtain output switch signal H of virtual sub-module_{i(i＝1～N′)}And superposing equivalent output voltage u of the cascade multi-level digital power amplifier with the asymmetric structure_oIs shown as

u_oIs 6N-3 level and has a value range of u_o∈[-(3N-2)/3，(3N-2)/3]。

4) According to kirchhoff's voltage law, u can be obtained_cN-1、u_cNAnd u_oHave the circuit relationship between

u_o＝u_cN-1+u_cN

From step 3) u is obtained_oThe actual voltage value of (1) is an integer or a decimal number, in order to ensure u_cN-1Is an integer, needs to be selected from the set u_cNSelecting a suitable voltage value from { +1/3, -1/3, 0} such that u_cN-1＝u_o-u_cNThe output level conditions of the N full-bridge submodules can be determined, and corresponding driving pulse signals are distributed to realize the multi-level output effect. Suppose the output switch signals of N full-bridge submodules are H_i(i＝1～N)And then:

when u is_cNWhen equal to +1/3, (u) is_o-u_cN) Is an integer Q₁The sum of the output switching signals of the first (N-1) sub-modules is Q₁And the output switching value of the Nth module is +1, namely: h₁+H₂+…+H_N-1＝Q₁，H_N＝+1；

When u is_cNWhen is equal to-1/3, if (u)_o-u_cN) Is an integer Q₂The sum of the output switching signals of the first (N-1) sub-modules is Q₂The output switching value of the Nth module is-1, namely: h₁+H₂+…+H_N-1＝Q₂，H_N＝-1；

When u is_cNWhen equal to 0, if (u)_o-u_cN) Is an integer Q₃The sum of the output switching signals of the first (N-1) sub-modules is Q₃The output switching value of the nth module is 0, that is: h₁+H₂+…+H_N-1＝Q₃，H_N＝0。

The switching signal of each full-bridge submodule can be obtained through the steps.

Fig. 2 is a working schematic diagram of a full-bridge power unit. Take the ith # full bridge power unit as an example, H_iIndicating power cell output switching signals，L_iAnd R_iRespectively representing the switching signals of the left and right bridge arms in each power unit, the output switching signal can be represented as

When L is_i＝0，R_iWhen 1, H_i＝L_i-R_i＝-1；

When L is_i＝1，R_i1 or L_i＝0，R_iWhen equal to 0, H_i＝L_i-R_i＝0；

When L is_i＝1，R_iWhen equal to 0, H_i＝L_i-R_i＝+1。

Fig. 3 is a schematic diagram of virtual CPS-PWM modulation. Firstly, according to the number N of cascaded power units of the cascaded multi-level digital power amplifier with the asymmetric structure, the output voltage amplitude of the structure is obtained and expressed as:

since the voltage value corresponding to each level is 1/3, the total output level number is 6N-3, and when the traditional CPS-PWM modulation mode is adopted, the number N' of the virtual cascaded full-bridge power units corresponding to the level number can be calculated as

Modulating signal u according to the modulation principle of the traditional CPS-PWM_rRespectively and N' virtual carriers u with sequential phase shift angle pi/N_{cj(j＝1～N′)}And comparing, wherein the specific comparison process comprises the following steps: u. of_rAnd carrier u_cjComparing to obtain a switching signal L of a left bridge arm of the power unit_j，-u_rAnd carrier u_cjComparing to obtain a switching signal R of a right bridge arm of the power unit_jFinally, the output switch signals H of N' virtual power units are obtained_{j(j＝1～N′)}And superposing equivalent output voltage u of the cascade multi-level digital power amplifier with the asymmetric structure_oIs shown as

u_oIs 6N-3 level, and has a value range of u as shown in the waveform of the multi-level voltage in FIG. 3_o∈[-(3N-2)/3，(3N-2)/3]。

Fig. 4 is an asymmetric level superposition schematic. The first (N-1) cascaded power cells may generate a number of levels up to 2(N-1) +1, each level corresponding to a normalized voltage value of 1, as shown by the black step voltage waveform in FIG. 3. In order to superimpose the balanced number of levels, it is necessary to equally divide the level of each voltage value 1 into 1/3 voltage value levels on the basis of the output voltages of the first (N-1) cascaded power cells, and as shown by the black dotted line in fig. 3, the output voltage of the N # power cell is superimposed on the output voltages of the first (N-1) cascaded power cells, the number of output levels can be increased to 6N-3.

Claims

1. A virtual CPS-PWM control method for cascade multilevel digital power amplifier with asymmetric structure includes N cascade full bridge power units, each power unit has a DC side connected in parallel with a constant DC voltage source, the AC output of each power unit is connected with load, and the DC side voltage of the first (N-1) power units in the cascade N power units is set as U_dcThe voltage on the DC side of the Nth power unit is set to be U_dcA/3; the method is characterized by comprising the following steps:

2) The cascade output voltage u of the first (N-1) power units_cN-1And the Nth power unit output voltage u_cNThe voltage value of each level is unified to 1/3, the output level number of the cascade multi-level digital power amplifier with the asymmetrical structure is 6N-3, and the level variation range is [ - (3N-2), (3N-2)]Calculating to obtain the number of cascade power units required under the corresponding traditional carrier phase-shift pulse width modulation mode to be 3N-2, equivalently regarding the cascade multilevel digital power amplifier with an asymmetric structure as being formed by cascading 3N-2 virtual full-bridge power units, wherein the direct-current side voltage value of each virtual power unit is 1/3;

4) According to the relation u between the output voltage of the power amplifier and the output voltage of the first (N-1) power units and the output voltage of the Nth power unit_o＝u_cN-1+u_cNIn u_cNSelecting a suitable output voltage value from the set of u_cN-1Is an integer according to the voltage value u at that time_cN-1And u_cNConfiguring switching signals for the first (N-1) power units and the Nth power unit;

2. The virtual CPS-PWM control method for cascaded multi-level digital power amplifiers with an asymmetric structure as claimed in claim 1, wherein the withstand voltage level of the switching device of the nth power unit is 1/3 of the withstand voltage level of the switching device of the previous (N-1) power unit.

3. The virtual CPS-PWM control method for cascaded multilevel digital power amplifiers with asymmetric structure as claimed in claim 1, characterized in that the multilevel output voltage u is_o＝(N-1)u_r+u_r/3＝(N-2/3)u_r(ii) a Wherein u is_rIs a modulated signal.

4. The virtual CPS-PWM control method for cascaded multilevel digital power amplifiers with asymmetric structure as claimed in claim 1, characterized in that the output voltage u of 6N-3 level_oThe calculation formula of (2) is as follows: