CN109617440B - SVPWM-based three-level inverter direct-current side midpoint voltage balancing method - Google Patents

SVPWM-based three-level inverter direct-current side midpoint voltage balancing method Download PDF

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CN109617440B
CN109617440B CN201811516424.8A CN201811516424A CN109617440B CN 109617440 B CN109617440 B CN 109617440B CN 201811516424 A CN201811516424 A CN 201811516424A CN 109617440 B CN109617440 B CN 109617440B
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midpoint
small vector
action time
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CN109617440A (en
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施必剑
胥飞
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Shanghai Dianji University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation

Abstract

The invention provides a three-level inverter direct-current side midpoint voltage balancing method based on SVPWM, which is characterized in that control vectors influencing three-level midpoint voltage balancing are controlled by adopting a corresponding method, virtual vectors are adopted for controlling middle vectors, and large vectors which do not influence the middle point voltage are used for synthesizing the middle vectors; the control of the small vector adopts PI to control the synthetic action time of the small vector; the two control methods are combined, and closed-loop feedback control is performed after the medium vector and the small vector are improved, so that the dynamic balance of the three-level midpoint voltage is improved, and the requirement on system stability is met; an additional auxiliary circuit is not needed, the loss of the converter is reduced, the stability of voltage balance of the direct current side of the three-level inverter is improved, and the control method is simple.

Description

SVPWM-based three-level inverter direct-current side midpoint voltage balancing method
Technical Field
The invention relates to a method for balancing midpoint voltage on a direct current side of a three-level inverter, in particular to a method for balancing midpoint voltage on the direct current side of the three-level inverter based on SVPWM.
Background
In order to achieve neutral point voltage balance on the direct current side of the three-level inverter, an auxiliary circuit is added to achieve neutral point voltage balance in the traditional method, but the whole circuit and a control algorithm become more complex after the circuit is improved; the traditional method for controlling the acting time of the synthetic vector voltage easily causes the vector synthetic acting time to be too short, the switch is frequently switched, the surge voltage is generated, and the peak current is generated. Therefore, there is a need for an improved method to overcome the above-mentioned drawbacks.
Disclosure of Invention
The invention aims to provide a three-level inverter direct-current side midpoint voltage balancing method based on SVPWM (space vector pulse width modulation), so as to solve the problem of level midpoint voltage unbalance, improve the dynamic stability of equipment and ensure the normal operation of electrical equipment such as a motor and the like.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a three-level inverter direct-current side midpoint voltage balancing method based on SVPWM comprises the following steps:
firstly, a space voltage vector area is divided, the space voltage vector area is divided into six large vector areas according to the conduction sequence of a switching tube of a diode clamping three-level inverter, each large vector area is divided into four small vector areas, and the large vector areas are composed of 27 vectors in total; the three-level inverter formed by diode clamping comprises 12 switching tubes, wherein each phase circuit comprises 4 switching tubesThe switching tube obtains that each phase of switching tube has U through analyzing the conduction sequence of each phase of switching tubedc/2、0、-Udc/2 three voltage states, so there are 3 in the three-phase circuit327 switching states are distributed at certain positions, and then small areas are divided;
respectively listing the influence of a zero vector, a positive small vector, a negative small vector and a middle vector on the midpoint voltage of the three levels, wherein when the input vector is a zero vector PPP, the load side is connected with a point P and is not connected with a midpoint m, so that the midpoint voltage is not influenced; when a positive small vector POO is input, the end a of the load is connected with a point P, the two ends b and c of the load are connected with a midpoint m, and the electric voltage generated by the voltage at the direct current side is unbalanced; when a negative small vector ONN is input, the load side is communicated with the positive small vector, but the current iz flows out of the midpoint m, so that the voltage of the capacitor C2 is reduced, the voltage of C1 is increased, C2< C1 is met, and the midpoint voltage is unbalanced; when a middle vector PON is input, the load side is respectively connected with a point P, a midpoint m and a point N, at the moment, both current flowing into the midpoint and current flowing out of the midpoint exist, finally, a zero vector and a large vector are obtained, no influence is caused on the midpoint voltage, and the middle vector and the small vector have influence on the balance of the middle vector and the small vector;
in order to balance the midpoint voltage, the medium vector and the small vector need to be improved, the control action time of the positive small vector and the control action time of the negative small vector are changed aiming at the unbalance generated by the small vector, the action time of the positive small vector is equal to the action time of the negative small vector as much as possible, the positive small vector and the negative small vector are mutually offset, the midpoint voltage is balanced, therefore, a midpoint adjusting factor rho is introduced, and V is redistributed1p、V1nThe action time of (2):
Figure GDA0002899812640000021
the comparison points of the SVPWM are substituted with the following results:
Figure GDA0002899812640000031
e is midpoint voltage offset;
when V isc1＝Vc2When 0, ρ is 0; when V isc1＞Vc2Time, rho<0; when V isc1＜Vc2Time, rho>0; the offset correction is carried out by utilizing a PI regulator:
Figure GDA0002899812640000032
ρ∈[-1 1]wherein Δ U (t) is Uc1And Uc2A difference of (d);
continuously adjusting the size of the adjusting factor rho through closed-loop control to balance the midpoint voltage; for the adjustment of the medium vector, a virtual vector method is adopted, namely the medium vector is synthesized by adjacent large vectors according to a triangle rule, and the medium vector
Figure GDA0002899812640000033
Is formed by large vectors
Figure GDA0002899812640000034
And
Figure GDA0002899812640000035
synthetic, is defined as
Figure GDA0002899812640000036
Original vector
Figure GDA0002899812640000037
Showing the switching states of the three-phase bridge arms,
Figure GDA0002899812640000038
representing new vector synthesized by PPN and PNN, drawing circuit diagram according to the three switch vectors, analyzing inflow and outflow midpoint current to obtain Ia+Ib+IcAnd (5) 0, so that the action time of the vector in the whole virtual has no influence on the center.
After the middle vector and the small vector are subjected to a series of improvements and closed-loop feedback control, the dynamic balance of the three-level midpoint voltage is more stable, and the anti-interference performance is stronger.
The invention has the advantages that:
controlling control vectors influencing neutral point voltage balance of three levels by adopting a corresponding method, controlling the neutral vectors by adopting virtual vectors, and synthesizing the neutral vectors by using large vectors which have no influence on the neutral point voltage; the control of the small vector adopts PI to control the synthetic action time of the small vector; the two control methods are combined, and closed-loop feedback control is performed after the medium vector and the small vector are improved, so that the dynamic balance of the three-level midpoint voltage is improved, and the requirement on system stability is met; an additional auxiliary circuit is not needed, the loss of the converter is reduced, the stability of voltage balance of the direct current side of the three-level inverter is improved, and the control method is simple.
Drawings
FIG. 1 is a schematic diagram of a three-level inverter space vector;
FIG. 2 is a voltage vector decomposition diagram for sector I;
FIG. 3 is a schematic illustration of the effect of different vectors on a midpoint;
fig. 4 is a schematic diagram of the control of the midpoint voltage of the capacitor.
Detailed Description
In order to make the technical means, the original characteristics, the achieved purposes and the effects of the invention easy to understand, the invention is further described with reference to the figures and the specific embodiments.
The invention provides a three-level inverter direct-current side midpoint voltage balancing method based on SVPWM, which comprises the following steps:
firstly, a space voltage vector area is divided, the space voltage vector area is divided into six large vector areas according to the conduction sequence of a switching tube of a diode clamping three-level inverter, each large vector area is divided into four small vector areas, and the large vector areas are composed of 27 vectors in total; referring to fig. 1, the three-level inverter formed by diode clamping comprises 12 switching tubes, wherein each phase circuit comprises 4 switching tubes, and each phase switching tube has a U value obtained by analyzing the conduction sequence of each phase switching tubedc/2、0、-Udc/2 three voltage states, so there are 3 in the three-phase circuit327 switching states, then distributing the different states in a certain positionSetting up, and dividing small areas as shown in fig. 2;
as shown in fig. 3, the influence of the zero vector, the positive small vector, the negative small vector and the middle vector on the midpoint voltage of the three levels is listed respectively, and when the input vector is the zero vector PPP, the load side is connected with the point P and is not connected with the midpoint m, so that the midpoint voltage is not influenced; when a positive small vector POO is input, the end a of the load is connected with a point P, the two ends b and c of the load are connected with a midpoint m, and the electric voltage generated by the voltage at the direct current side is unbalanced; when a negative small vector ONN is input, the load side is communicated with the positive small vector, but the current iz flows out of the midpoint m, so that the voltage of the capacitor C2 is reduced, the voltage of C1 is increased, C2< C1 is met, and the midpoint voltage is unbalanced; when a middle vector PON is input, the load side is respectively connected with a point P, a midpoint m and a point N, at the moment, both current flowing into the midpoint and current flowing out of the midpoint exist, finally, a zero vector and a large vector are obtained, no influence is caused on the midpoint voltage, and the middle vector and the small vector have influence on the balance of the middle vector and the small vector;
as shown in FIG. 4, in order to balance the midpoint voltage, it is necessary to improve the middle vector and the small vector, and for the unbalance generated by the small vector, the control action time of the positive and negative small vectors is changed, and the action time of the positive small vector and the action time of the negative small vector are made equal as much as possible and are mutually offset, so as to balance the midpoint voltage, and for this purpose, a midpoint adjusting factor ρ is introduced, and V is redistributed1p、V1nThe action time of (2):
Figure GDA0002899812640000051
the comparison points of the SVPWM are substituted with the following results:
Figure GDA0002899812640000061
e is midpoint voltage offset;
when V isc1＝Vc2When 0, ρ is 0; when V isc1＞Vc2Time, rho<0; when V isc1＜Vc2Time, rho>0; the offset correction is carried out by utilizing a PI regulator:
Figure GDA0002899812640000062
ρ∈[-1 1]wherein Δ U (t) is Uc1And Uc2A difference of (d);
continuously adjusting the magnitude of the adjustment factor ρ by the closed-loop control in fig. 4 to balance the midpoint voltage; for the adjustment of the medium vector, a virtual vector method is adopted, i.e. the medium vector is synthesized by adjacent large vectors according to a triangle rule, as shown in FIG. 2, the medium vector
Figure GDA0002899812640000063
Is formed by large vectors
Figure GDA0002899812640000064
And
Figure GDA0002899812640000065
synthetic, is defined as
Figure GDA0002899812640000066
Original vector
Figure GDA0002899812640000067
Showing the switching states of the three-phase bridge arms,
Figure GDA0002899812640000068
representing new vector synthesized by PPN and PNN, drawing circuit diagram according to the three switch vectors, analyzing inflow and outflow midpoint current to obtain Ia+Ib+IcAnd (5) 0, so that the action time of the vector in the whole virtual has no influence on the center.
Wherein, UdcThe voltages of the upper and lower arm capacitors c1 and c2 in FIG. 3, i.e. DC voltage, V1pIs a positive small vector, V1nIs a negative small vector, t1pFor positive small vector action time after introduction of the regulating factor, t1nFor negative small vector action time after introduction of regulatory factor, Uc1Is the voltage of the capacitor c1 in FIG. 3, i.e. the upper arm capacitor voltage, Uc2Is the voltage of the capacitor c2 in FIG. 3, i.e. the lower arm capacitor voltage，taonIs a small vector action time of phase A, t'aonIs the A-phase small vector action time t 'after introducing the regulating factor'bonIs the B-phase small vector action time t 'after the introduction of the regulating factor'conFor small vector action time of C phase after introduction of a regulating factor, tauiIs the time constant of the PI regulator, t1For positive small vector action time before introduction of the adjustment factor, t2For the time of action of the negative small vector before introduction of the regulating factor, KpIs the proportional adjustment coefficient of the PI regulator.
The above embodiments are merely illustrative of the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the content of the present invention and implement the present invention, and not to limit the scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be covered by the scope of the present invention.

Claims (1)

1. The SVPWM-based neutral point voltage balancing method on the direct current side of the three-level inverter is characterized by comprising the following steps of:
firstly, a space voltage vector area is divided, the space voltage vector area is divided into six large vector areas according to the conduction sequence of a switching tube of a diode clamping three-level inverter, each large vector area is divided into four small vector areas, and the large vector areas are composed of 27 vectors in total; the three-level inverter formed by the clamping of the diodes comprises 12 switching tubes, wherein each phase circuit comprises 4 switching tubes, and the condition that each phase switching tube has U is obtained by analyzing the conduction sequence of each phase switching tubedc/2、0、-Udc/2 three voltage states, so there are 3 in the three-phase circuit327 switching states are distributed at certain positions, and then small areas are divided;
respectively listing the influence of a zero vector, a positive small vector, a negative small vector and a middle vector on the midpoint voltage of the three levels, wherein when the input vector is a zero vector PPP, the load side is connected with a point P and is not connected with a midpoint m, so that the midpoint voltage is not influenced; when a positive small vector POO is input, the end a of the load is connected with a point P, the two ends b and c of the load are connected with a midpoint m, and the electric voltage generated by the voltage at the direct current side is unbalanced; when a negative small vector ONN is input, the load side is communicated with the positive small vector, but the current iz flows out of the midpoint m, so that the voltage of the capacitor C2 is reduced, the voltage of C1 is increased, C2< C1 is met, and the midpoint voltage is unbalanced; when a middle vector PON is input, the load side is respectively connected with a point P, a midpoint m and a point N, at the moment, both current flowing into the midpoint and current flowing out of the midpoint exist, finally, a zero vector and a large vector are obtained, no influence is caused on the midpoint voltage, and the middle vector and the small vector have influence on the balance of the middle vector and the small vector;
in order to balance the midpoint voltage, the medium vector and the small vector need to be improved, the control action time of the positive small vector and the control action time of the negative small vector are changed aiming at the unbalance generated by the small vector, the action time of the positive small vector is equal to the action time of the negative small vector as much as possible, the positive small vector and the negative small vector are mutually offset, the midpoint voltage is balanced, therefore, a midpoint adjusting factor rho is introduced, and V is redistributed1p、V1nThe action time of (2):
Figure FDA0002899812630000021
the comparison points of the SVPWM are substituted with the following results:
Figure FDA0002899812630000022
e is midpoint voltage offset;
when V isc1＝Vc2When 0, ρ is 0; when V isc1＞Vc2Time, rho<0; when V isc1＜Vc2Time, rho>0；
The offset correction is carried out by utilizing a PI regulator:
Figure FDA0002899812630000023
wherein Δ U (t) is Uc1And Uc2A difference of (d);
continuously adjusting the size of the adjusting factor rho through closed-loop control to balance the midpoint voltage; for the middle vectorThe quantity is adjusted by adopting a virtual vector method, namely, a medium vector is synthesized by adjacent large vectors according to a triangle rule
Figure FDA0002899812630000024
Is formed by large vectors
Figure FDA0002899812630000025
And
Figure FDA0002899812630000026
synthetic, is defined as
Figure FDA0002899812630000027
Original vector
Figure FDA0002899812630000028
Showing the switching states of the three-phase bridge arms,
Figure FDA0002899812630000029
representing new vector synthesized by PPN and PNN, drawing circuit diagram according to the three switch vectors, analyzing inflow and outflow midpoint current to obtain Ia+Ib+IcThe vector action time in the whole virtual has no influence on the center point;
wherein, UdcIs the voltage of upper and lower arm capacitors c1 and c2, i.e. DC voltage, V1pIs a positive small vector, V1nIs a negative small vector, t1pFor positive small vector action time after introduction of the regulating factor, t1nFor negative small vector action time after introduction of regulatory factor, Uc1Is the voltage of the capacitor c1, i.e. the upper arm capacitor voltage, Uc2Is the voltage of the capacitor c2, i.e. the lower arm capacitor voltage, taonIs a small vector action time of phase A, t'aonIs the A-phase small vector action time t 'after introducing the regulating factor'bonIs the B-phase small vector action time t 'after the introduction of the regulating factor'conFor small vector action time of C phase after introduction of a regulating factor, tauiIs the time constant of the PI regulator, t1For positive small vector action time before introduction of the adjustment factor, t2For the time of action of the negative small vector before introduction of the regulating factor, KpIs the proportional adjustment coefficient of the PI regulator.
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