CN109962480B - Control system, method and application of static var generator without phase-locked loop - Google Patents

Control system, method and application of static var generator without phase-locked loop Download PDF

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CN109962480B
CN109962480B CN201910266588.8A CN201910266588A CN109962480B CN 109962480 B CN109962480 B CN 109962480B CN 201910266588 A CN201910266588 A CN 201910266588A CN 109962480 B CN109962480 B CN 109962480B
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static var
var generator
phase
neutral point
locked loop
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CN109962480A (en
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张承慧
姜英
李晓艳
邢相洋
耿华
胡顺全
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Tsinghua University
Shandong University
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Shandong University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/10—Flexible AC transmission systems [FACTS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

Abstract

The utility model provides a static var generator non-phase-locked loop control system, method and application, under an alpha beta static coordinate system, the voltage of a power grid and a signal delayed by 90 degrees are utilized to obtain a reference value of the output current of a neutral point clamped three-level static var generator, the positive and negative sequence separation and the phase-locked loop algorithm are avoided, and the voltage outer ring of the neutral point clamped three-level static var generator is controlled by a PI (proportional integral) to realize the control of the voltage stability of a direct current side; the current inner loop of the neutral point clamped three-level static var generator is controlled by utilizing the E-PR, tracking control of the current of the inner loop is realized, the acting time of the redundant small vector is adjusted through proportional control, and balance control of the neutral point potential of the neutral point clamped three-level static var generator is realized.

Description

Control system, method and application of static var generator without phase-locked loop
Technical Field
The disclosure relates to a control system, a control method and application of a static var generator without a phase-locked loop.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The Neutral Point Clamped (NPC) three-level converter has the advantages of low requirement on withstand voltage of devices, less harmonic waves of output waveforms, low switching frequency, high conversion efficiency and the like, and is suitable for occasions of medium-high voltage input.
However, in the power grid transmission, reactive power not only causes extra power loss in the transmission line and the distribution transformer, but also causes large voltage deviation or flicker at the end of voltage, resulting in unstable voltage of the power grid. Therefore, reasonable reactive compensation of the power grid is a key measure for reducing power loss, stabilizing the voltage of the power grid and improving the power quality of the power grid. The Static Var Generator (SVG) can rapidly change the magnitude and direction of the reactive power, has faster regulation speed and wider regulation range, and can continuously regulate the reactive power. The NPC three-level SVG can effectively suppress fluctuation and flicker of the grid voltage and reduce voltage deviation due to its specific structural advantages, thereby enhancing the stability of the grid voltage, and has been widely applied to the power transmission and distribution side (such as transformer substation, wind farm, etc.) and the power utilization side (such as metallurgy, petrochemical industry, mine, electrified railway, etc.) of the grid.
When a power grid is unbalanced, the output current of the NPC three-level SVG based on the traditional balance algorithm is distorted, and reactive power generates double frequency pulsation. This results in increased system losses and reduced system performance. When the power grid is unbalanced, the positive and negative sequence components are respectively controlled in the positive and negative sequence rotating coordinate system by a common positive and negative sequence separation-based method. The method needs complex calculation such as positive and negative sequence separation, phase-locked loop and the like, which increases the complexity of system control, increases control delay and reduces the control performance of the system.
Disclosure of Invention
The disclosure can eliminate the fluctuation of reactive power when a power grid is unbalanced, realize the sine of SVG output current, and reduce the Total Harmonic content (THD) of grid-connected current. Meanwhile, the phase-locked loop technology can be eliminated, the calculated amount caused by the phase-locked loop is greatly reduced, the response speed is obviously improved, and the influence of digital delay on the control performance is reduced.
According to some embodiments, the following technical scheme is adopted in the disclosure:
a static var generator phase-locked loop-free control system for controlling a neutral-point clamped three-level static var generator, configured to:
obtaining a reference value of output current of the neutral point clamped three-level static var generator by utilizing the voltage of a power grid and a signal delayed by 90 degrees thereof under an alpha beta static coordinate system, avoiding positive and negative sequence separation and a phase-locked loop algorithm, and realizing the control of the voltage stability of a direct current side by utilizing a voltage outer ring of a PI controlled neutral point clamped three-level static var generator; the current inner loop of the neutral point clamped three-level static var generator is controlled by utilizing the E-PR, tracking control of the current of the inner loop is realized, the acting time of the redundant small vector is adjusted through proportional control, and balance control of the neutral point potential of the neutral point clamped three-level static var generator is realized.
By way of further limitation, the midpoint clamping type three-level static var generator includes an ac side and a dc side, wherein:
the alternating current side comprises three-phase bridge arms, each phase of bridge arm comprises four power switch tubes connected in series to form a series group, two diodes are connected in series and then connected in parallel with two power switch tubes positioned in the middle of the series group, and the midpoint of the series group at the alternating current side can be connected to an alternating current power supply through a filter;
the direct current side comprises two filter capacitors connected in series, a neutral point is formed between the two filter capacitors, the neutral point is connected with the middle point of the two diodes of the phase, and the middle point of each phase of the series group is connected with a corresponding filter.
By way of further limitation, the neutral point clamped three-level static var generator is connected with a power grid through a reactor.
As a further limitation, the dc side employs a PI controller, the output of which is a reference for active power.
As a further limitation, the direct current side adopts a proportional controller to adjust the action time of the redundant small vector, so as to realize the balance control of the neutral point potential of the neutral point clamping type three-level static var generator.
A static var generator phase-locked loop-free control method comprises the following steps:
obtaining a reference value of output current of the neutral point clamped three-level static var generator by utilizing the voltage of a power grid and a signal delayed by 90 degrees thereof under an alpha beta static coordinate system, avoiding positive and negative sequence separation and a phase-locked loop algorithm, and realizing the control of the voltage stability of a direct current side by utilizing a voltage outer ring of a PI controlled neutral point clamped three-level static var generator; the current inner loop of the neutral point clamped three-level static var generator is controlled by utilizing the E-PR, tracking control of the current of the inner loop is realized, the acting time of the redundant small vector is adjusted through proportional control, and balance control of the neutral point potential of the neutral point clamped three-level static var generator is realized.
As an alternative scheme, under an alpha beta static coordinate system, a reference value of current is calculated by using a power grid voltage, a value delayed by 90 degrees of the power grid voltage and reference values of active power and reactive power according to a principle of eliminating reactive power fluctuation.
By way of further limitation, the grid voltage is delayed by a value of 90 °, and the fractional delay caused by the fixed sampling rate is approximated with a fractional delay filter.
As a further limitation, tracking of the inner loop current is achieved using an E-PR controller.
As a further limitation, a proportional controller is adopted to adjust the action time of the redundant small vectors, and balance control of the midpoint potential is realized.
A computer readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to execute said method for static var generator phase-lock-loop-free control.
A terminal device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the static var generator phase-locked loop-free control method.
Compared with the prior art, the beneficial effect of this disclosure is:
1. under an alpha beta static coordinate system, a reference value of current is obtained by utilizing the voltage and the current of a power grid, the value of 90 degrees of delay of the voltage and the current and the reference values of active power and reactive power, and the reference value of the current has the characteristics of eliminating reactive power fluctuation and ensuring the constant reactive power. In order to obtain a signal delayed by 90 degrees, the fractional delay caused by the fixed sampling rate is approximated by a fractional delay filter, and the response speed of the system is improved.
2. The method does not need a phase-locked loop technology, avoids the difficulty and the error caused by phase locking under the condition of an unbalanced power grid, greatly reduces the calculated amount and improves the control precision.
3. The method does not need positive and negative sequence separation, avoids complex calculation caused by the positive and negative sequence separation, and saves calculation time.
4. The current inner loop adopts an E-PR controller, so that the response speed is improved, and the influence of digital delay on the control performance is reduced.
5. A PI controller is adopted in a direct current side voltage outer ring, so that the stable control of the direct current bus voltage is realized;
6. the neutral point voltage on the direct current side realizes the balance control of the neutral point potential by adjusting the action time of the redundant small vector through a proportional controller.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application.
FIG. 1 is a NPC three-level SVG main circuit topology;
FIG. 2 is an NPC three-level SVG space vector diagram;
FIG. 3 is a NPC three-level SVG control block diagram when a power grid is unbalanced;
FIG. 4 shows an output waveform of the NPC three-level SVG phase-locked loop-free control system when a power grid is unbalanced.
The specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
According to the NPC three-level SVG phase-locked loop-free control system and method based on the power grid unbalance condition, the fluctuation of reactive power when the power grid is unbalanced is eliminated, the sine of the output current of the SVG is realized, and the THD of the grid-connected current is reduced; meanwhile, the phase-locked loop technology and the positive and negative sequence separation of voltage and current are removed, so that the complex calculation caused by the phase-locked loop and the positive and negative sequence separation is avoided, and the error caused by the phase-locked loop is greatly reduced; the current inner loop uses an E-PR controller to reduce the influence of digital delay on the control performance.
The emphasis of this embodiment is:
the system adopts voltage and current double closed loop control, and the whole control is implemented under a two-phase static alpha beta coordinate system. The voltage outer ring controls the voltage at the direct current side, so that the voltage at the direct current side is stable; the current inner ring realizes the tracking control of the current; and the action time of the redundant small vector is adjusted through a proportional controller to realize the balance control of the midpoint potential on the direct current side.
Reference value of voltage outer ring according to DC side voltage
Figure BDA0002017042280000061
And the actual sampled value VdcThe voltage of the DC side is controlled by adopting a Proportional Integral (PI) controller to be stable, and the output of an outer loop is a reference p of active power*。
Sampling value i of current inner ring according to three-phase currentabcObtaining a two-phase current value i through Clark conversionαβWith a two-phase current reference value
Figure BDA0002017042280000062
And performing difference comparison, and realizing tracking control of the inner loop current through an E-PR controller. Compared with the traditional controller, the controller has the advantages of small delay time and better tracking performance.
Current reference
Figure BDA0002017042280000063
The calculation method of (2) is specifically described as: using the mains voltage eαβAnd value e 'delayed by 90 DEG thereof'αβAnd a reference value p of active and reactive power*，q*Calculating a reference for the current in the current inner loop
Figure BDA0002017042280000064
The obtained reference value has the characteristics of eliminating the pulsation of the reactive power and ensuring the constancy of the reactive power. The calculation method does not need positive and negative sequence separation and phase-locked loop technology, and avoids complex calculation, difficult phase locking and no phase locking caused by positive and negative sequence separation when the power grid is unbalancedThe accuracy problem, the calculated amount has been reduced greatly, has saved the calculation time, has improved the precision of control. In order to obtain a signal delayed by 90 degrees, the fractional delay caused by the fixed sampling rate is approximated by a fractional delay filter, and the response speed of the system is improved.
Collect the voltage V of two capacitors at the upper and lower sides of the DC sideC1And VC2And the action time of the redundant small vectors is adjusted through a proportional controller, so that the balance of the midpoint potential is controlled.
Specifically, the present embodiment is based on NPC three-level SVG, and in order to achieve the above purpose, the following technical scheme is adopted:
the object controlled by this embodiment is an NPC three-level SVG system, and fig. 1 shows a main circuit topology of the NPC three-level SVG, which includes the following parts: (1) three-phase network ea，eb，ec(ii) a (2)12 switching tubes Sa1，Sa2，Sa3，Sa4，Sb1，Sb2，Sb3，Sb4，Sc1，Sc2，Sc3，Sc4(ii) a (3)6 diodes Da1，Da2，Db1，Db2，Dc1，Dc2(ii) a (4) DC side capacitor C1，C2. Two filter capacitors connected in series on the direct current side give a neutral point O, two diodes connected in series in each phase of bridge arm are connected between a positive half bridge arm and a negative half bridge arm, the neutral point of each phase of bridge arm is connected to the neutral point O of the capacitor, and each phase of bridge arm can output three level states.
In FIG. 1, the mathematical model for obtaining NPC three-level SVG according to kirchhoff's voltage law is
Figure BDA0002017042280000071
Wherein L and R represent the inductance and equivalent series resistance of the reactor, ea，eb，ecIs a three-phase network voltage ua，ub，ucThe bridge arm output voltage of the NPC three-level SVG is obtained.
Under unbalanced grid conditions, the grid voltage and current may be expressed as
Figure BDA0002017042280000072
Wherein the content of the first and second substances,
Figure BDA0002017042280000073
the positive and negative sequence components of the power grid voltage and the current in the alpha beta static coordinate system are respectively. Under the stationary coordinate system of alpha beta, the coordinate system of alpha beta,
Figure BDA0002017042280000074
available voltage, current and their signals e delayed by 90 degαβ，e'αβ，iαβ，i'αβTo indicate that:
Figure BDA0002017042280000081
the power transmitted by the NPC three-level SVG is obtained according to the expression of voltage and current when the power grid is unbalanced:
Figure BDA0002017042280000082
wherein the content of the first and second substances,
Figure BDA0002017042280000083
Figure BDA0002017042280000084
the control target of the NPC three-level SVG is to eliminate the fluctuation of reactive power when the power grid is unbalanced, ensure the constancy of the reactive power, and realize the sine of the output current of the SVG, the stability of the voltage at the direct current side and the balance of the midpoint potential. When the reactive power fluctuation is zero, p is required to be satisfiedo＝p*，qo＝q*，qs2＝q c20, namely:
Figure BDA0002017042280000091
therefore, the reference value of the current can be expressed as:
Figure BDA0002017042280000092
the current reference value is calculated by utilizing the voltage of a power grid, the value delayed by 90 degrees of the voltage of the power grid and the reference values of active power and reactive power under an alpha beta static coordinate system, and the current reference value has the characteristics of eliminating reactive power fluctuation and ensuring the constancy of the reactive power. The calculation of the reference current does not need positive and negative sequence separation and a phase-locked loop technology, and the calculation amount and the complexity are reduced. In order to obtain a signal delayed by 90 degrees, the fractional delay caused by the fixed sampling rate is approximated by a fractional delay filter, and the response speed of the system is improved.
Fig. 2 is a NPC three-level SVG space voltage vector diagram, and the space voltage vector can be divided into a large vector, a medium vector, a small vector and a zero vector according to the magnitude of the space voltage vector. The large and zero vectors have no effect on the center point potential, while the medium and small vectors have an effect on the center point potential. However, the influence of the medium vector on the midpoint potential is uncertain about the current direction, and the influence of the redundant positive and negative small vectors on the midpoint potential is opposite, so that the balance control of the midpoint potential on the direct current side is realized by adjusting the action time of the redundant small vectors through the proportional controller.
Fig. 3 is a control block diagram of the NPC three-level SVG system. The system adopts voltage and current double closed loop control, and the whole control is implemented under a two-phase static coordinate system, namely an alpha beta static coordinate system.
Reference value of voltage outer ring according to DC side voltage
Figure BDA0002017042280000093
And the actual sampled value VdcThe voltage at the DC side is controlled by PI controller to be stable, and the outer ringReference p with output of active power*。
Sampling value i of current inner ring according to three-phase currentabcObtaining a two-phase current value i through Clark conversionαβWith a two-phase current reference value
Figure BDA0002017042280000101
And performing difference comparison, and realizing tracking control of the inner loop current through an E-PR controller. Compared with the traditional controller, the controller has the advantages of small delay time and better tracking performance.
The conventional PR controller has higher gain at the set resonant frequency, and can realize the suppression of harmonic current. However, the delay time caused by the digital control, sampling and Pulse Width Modulation (PWM) unit can degrade the performance of the conventional PR controller when compensating for higher harmonics. To overcome these problems, the method of the present embodiment proposes an E-PR controller for implementing current control of NPC three-level SVG. A significant advantage over conventional PR controllers is that the delay time can be counteracted by selecting the appropriate controller gain. The transfer function is:
Figure BDA0002017042280000102
collect the voltage V of two capacitors at the upper and lower sides of the DC sideC1And VC2And the action time of the redundant small vectors is adjusted through a proportional controller, so that the balance of the midpoint potential is controlled.
Fig. 4 is an output waveform of the NPC three-level SVG phase-locked loop-free control system when the power grid is unbalanced, which is sequentially power grid voltage, power grid current, active power and reactive power.
A computer-readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to execute the NPC three-level SVG phase-locked loop-free control method provided by the present embodiment.
A terminal device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions which are suitable for being loaded by a processor and executing the NPC three-level SVG phase-locked loop control method provided by the embodiment.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A static var generator does not have phase-locked loop control system, characterized by: for controlling a neutral point clamped three-level static var generator, configured to:
obtaining a reference value of output current of the neutral point clamped three-level static var generator by utilizing the voltage of a power grid and a signal delayed by 90 degrees thereof under an alpha beta static coordinate system, avoiding positive and negative sequence separation and a phase-locked loop algorithm, and realizing the control of the voltage stability of a direct current side by utilizing a voltage outer ring of a PI controlled neutral point clamped three-level static var generator; the current inner loop of the neutral point clamped three-level static var generator is controlled by utilizing the E-PR, tracking control of the current of the inner loop is realized, the acting time of the redundant small vector is adjusted through proportional control, and balance control of the neutral point potential of the neutral point clamped three-level static var generator is realized.
2. The static var generator phase-locked loop-free control system as claimed in claim 1, wherein: the neutral point clamping type three-level static var generator comprises an alternating current side and a direct current side, wherein:
the alternating current side comprises three-phase bridge arms, each phase of bridge arm comprises four power switch tubes connected in series to form a series group, two diodes are connected in series and then connected in parallel with two power switch tubes positioned in the middle of the series group, and the midpoint of the series group at the alternating current side can be connected to an alternating current power supply through a filter;
the direct current side comprises two filter capacitors connected in series, a neutral point is formed between the two filter capacitors, the neutral point is connected with the middle point of the two diodes of the phase, and the middle point of each phase of the series group is connected with a corresponding filter.
3. The static var generator phase-locked loop-free control system as claimed in claim 2, wherein: and the direct current side adopts a PI controller, and the output of the PI controller is the reference of active power.
4. The static var generator phase-locked loop-free control system as claimed in claim 2, wherein: and the direct current side adopts a proportional controller to adjust the action time of the redundant small vector, so that the balance control of the neutral point potential of the neutral point clamping type three-level static var generator is realized.
5. A static var generator phase-locked loop-free control method is characterized by comprising the following steps: obtaining a reference value of output current of the neutral point clamped three-level static var generator by utilizing the voltage of a power grid and a signal delayed by 90 degrees thereof under an alpha beta static coordinate system, avoiding positive and negative sequence separation and a phase-locked loop algorithm, and realizing the control of the voltage stability of a direct current side by utilizing a voltage outer ring of a PI controlled neutral point clamped three-level static var generator; the current inner loop of the neutral point clamped three-level static var generator is controlled by utilizing the E-PR, tracking control of the current of the inner loop is realized, the acting time of the redundant small vector is adjusted through proportional control, and balance control of the neutral point potential of the neutral point clamped three-level static var generator is realized.
6. The method for controlling the static var generator without the phase-locked loop according to claim 5, wherein: and under an alpha beta static coordinate system, calculating to obtain a reference value of current according to the principle of eliminating reactive power fluctuation by utilizing the voltage of the power grid, the value delayed by 90 degrees of the voltage of the power grid and the reference values of active power and reactive power.
7. The method for controlling the static var generator without the phase-locked loop according to claim 5, wherein: the grid voltage is delayed by a value of 90 deg., and the fractional delay caused by the fixed sampling rate is approximated with a fractional delay filter.
8. The method for controlling the static var generator without the phase-locked loop according to claim 5, wherein: tracking the inner loop current by adopting an E-PR controller;
or/and the proportional controller is adopted to adjust the acting time of the redundant small vectors to realize the balance control of the midpoint potential.
9. A computer-readable storage medium having stored thereon a plurality of instructions adapted to be loaded by a processor of a terminal device and to execute the method of any one of claims 5 to 8 for static var generator phase-locked loop-free control.
10. A terminal device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions adapted to be loaded by a processor and to perform the method for static var generator phase-locked loop control as claimed in claims 5-8.
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