CN108365841A - The control system and control method of gated clock - Google Patents
The control system and control method of gated clock Download PDFInfo
- Publication number
- CN108365841A CN108365841A CN201810027309.8A CN201810027309A CN108365841A CN 108365841 A CN108365841 A CN 108365841A CN 201810027309 A CN201810027309 A CN 201810027309A CN 108365841 A CN108365841 A CN 108365841A
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- gated clock
- clock
- signal
- control
- register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of control system of gated clock and control methods, wherein the control system of gated clock includes：Gated clock, the output end of the gated clock are connected with register to be detected；First control circuit, it is connected with the ends TE of the gated clock, the first control circuit is for receiving scan enable signal and first control signal, and the scan enable signal and the first control signal are sent to the ends TE of the gated clock, propagate clock signal to control the gated clock according to the scan enable signal or the first control signal；Gated clock enable signal control module is connected with the enable signal end of the gated clock, the conducting enable signal for providing the gated clock, so that the gated clock is connected when receiving the conducting enable signal.The invention has the advantages that：It can connect whether register breaks down at the capture cycle detections rear of gated clock, improve test coverage.
Description
Technical field
The present invention relates to units test technical fields, and in particular to a kind of control method and control system of gated clock.
Background technology
Clock gating techniques are a kind of simple and effective power consumption control methods, its basic principle is exactly by closing chip
The clock of the function and it that temporarily take less than, to realize the purpose for saving current drain.
Scan testing techniques：Scan testing techniques refer to by the way that common sequential register in integrated circuit to be converted into scanning
Register, and these scan registers are concatenated into scan chain to which circuit testability be significantly greatly increased.This measuring technology is
Test and excitation is realized that test and excitation applies by scan operation input ic using scan chain, passes through sequential register
Sampling come realize test response observation, and will be observed that again by the scan operation of scan chain test response be output to survey
It tries output port and carries out test data comparison analysis.This technology needs input logic controllable, exports logic Observable, all scannings
Register on chain can be tested clock and directly drive.
In the related technology, the ends TE of gated clock logic are surveyed is connected with scanning Enable Pin, and it is effective that the conversion stage fixes output
Digital signal enables the register on scan chain to be tested clock driving；Capture phase fixes nonsignificant digit signal, makes gate
The failure of clocked logic cannot be detected, and coverage rate is caused to decline.
Invention content
The present invention is directed at least solve one of above-mentioned technical problem.
For this purpose, first purpose of the present invention is to propose a kind of control system of gated clock, it can be in gated clock
Capture cycle detection rear connection register whether break down, improve test coverage.
To achieve the goals above, embodiment of the invention discloses that a kind of control system of gated clock, including：First
Control circuit is connected with the ends TE of the gated clock, and the first control circuit is for receiving scan enable signal and first
Signal is controlled, and the scan enable signal and the first control signal are sent to the ends TE of the gated clock, with root
The gated clock, which is controlled, according to the scan enable signal or the first control signal propagates clock signal；Gated clock is enabled
Signal control module is connected with the enable signal end of the gated clock, the enabled letter of the conducting for providing the gated clock
Number, so that the gated clock is connected when receiving the conducting enable signal.
In some embodiments, the first control circuit includes：Scanning signal receiving terminal makes for receiving the scanning
It can signal；First register selectively provides first control signal for providing；Wherein, the scanning signal receiving terminal and
The output end of first register commonly through or door be connected with the ends TE of the gated clock.
In some embodiments, the first control circuit further includes：Clock signal incoming end, for receiving clock letter
Number；Wherein, the scanning signal receiving terminal and the clock signal incoming end commonly through with door and first register
Clock signal input terminal is connected.
In some embodiments, the output end phase of the digital input end of first register and first register
Even.
The control system of gated clock according to the ... of the embodiment of the present invention, by being terminated into control electricity in the TE of gated clock
Road can detect whether rear connection register breaks down in the capture phase of gated clock, improve test coverage.
Second object of the present invention is to propose a kind of control method of gated clock, can be in the capture of gated clock
Whether cycle detection rear connection register breaks down, and improves test coverage.
To achieve the goals above, embodiment of the invention discloses that a kind of control method of gated clock, including it is above-mentioned
The control method of the control system of the gated clock of embodiment, the gated clock includes the following steps：Pass through the first control electricity
Road is set in the logical value of the first register described in the conversion stage；According to the logical value control of the first register described in the conversion stage
It makes the gated clock and propagates clock signal in capture phase.
The control method of gated clock according to the ... of the embodiment of the present invention, by being terminated into control electricity in the TE of gated clock
Road can detect whether rear connection register breaks down in the capture phase of gated clock, improve test coverage.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obviously, or practice through the invention is recognized.
Description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination following accompanying drawings to embodiment
Obviously and it is readily appreciated that, wherein：
Fig. 1 is the structure diagram of the control system of the gated clock of one embodiment of the invention；
Fig. 2 is the circuit diagram of the gated clock part of one embodiment of the invention；
Fig. 3 is the flow chart of the control method of the gated clock of one embodiment of the invention.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that, in addition, term " first ", " second " are used for description purposes only, and
It should not be understood as indicating or implying relative importance.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
Can also be electrical connection to be mechanical connection；It can be directly connected, can also indirectly connected through an intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
With reference to following description and drawings, it will be clear that these and other aspects of the embodiment of the present invention.In these descriptions
In attached drawing, some particular implementations in the embodiment of the present invention are specifically disclosed, to indicate to implement the implementation of the present invention
Some modes of the principle of example, but it is to be understood that the scope of embodiments of the invention is not limited.On the contrary, the present invention
Embodiment includes all changes, modification and the equivalent fallen within the scope of the spirit and intension of attached claims.
The present invention is described below in conjunction with attached drawing.
Fig. 1 is the structure diagram of the control system of the gated clock of one embodiment of the invention.As shown in Figure 1, of the invention
The control system of the gated clock of embodiment, including：Gated clock 100, first control circuit 200 and gated clock enable signal
Control module 300.
Wherein, the output end of gated clock 200 is connected with register to be detected.First control circuit 200 and gated clock
100 ends TE are connected.First control circuit is for receiving scan enable signal and first control signal, and by scan enable signal
The ends TE of gated clock 100 are sent to first control signal, to control door according to scan enable signal or first control signal
It controls clock 100 and propagates clock signal.The enable signal end phase of gated clock enable signal control module 300 and gated clock 100
Even, the conducting enable signal for providing gated clock 100, so that gated clock 100 is connected when receiving conducting enable signal.
Fig. 2 is the circuit diagram of the gated clock part of one embodiment of the invention.As shown in Fig. 2, the first control electricity
Road includes：Scanning signal receiving terminal scan_enable and the first register FF0.Gated clock enable signal control module 300 is wrapped
Include the second register FF1 and corresponding control logic.Wherein, scanning signal receiving terminal scan_enable makes for receiving scanning
It can signal.First register FF0 selectively provides first control signal for providing.Scanning signal receiving terminal scan_
The output end Q of enable and the first register FF0 commonly through or door be connected with the ends TE of gated clock 100.It is posted by first
Storage FF0 controls the logical value of FF0/Q in the conversion stage, to make the ends TE of gated clock become controllable, so as to control
System controls gated clock when capture phase and propagates clock signal, ensures the register FF2 to be detected of gated clock driving
Failure can be detected, and then improves test coverage.
In one embodiment of the invention, first control circuit 200 further includes clock signal incoming end, and clock signal connects
Enter end for receiving clock signal clk.Scanning signal receiving terminal and clock signal incoming end are deposited commonly through with door and first
The clock signal input terminal of device FF0 is connected, it is convenient to omit clock automatic turning.
In one embodiment of the invention, the output end of the digital input end D and the first register of the first register FF0
Q is connected.Since the function of the first register FF0 is used only to the logic state at the ends control TE, detection circuit, therefore number are not needed
Word input terminal D and output end Q are direct-connected.
The control system of gated clock according to the ... of the embodiment of the present invention, by being terminated into control electricity in the TE of gated clock
Road can detect whether rear connection register breaks down in the capture phase of gated clock, improve test coverage.
Fig. 3 is the flow chart of the control method of the gated clock of one embodiment of the invention.As shown in figure 3, the present invention is also
A kind of control method of gated clock is disclosed, the control system of the gated clock of above-described embodiment is provided with, the gated clock
Control method include the following steps：S1：The logic of the first register described in the conversion stage is set in by first control circuit
Value；S2：The gated clock, which is controlled, according to the logical value of the first register described in the conversion stage propagates clock in capture phase
Signal.
The control method of gated clock according to the ... of the embodiment of the present invention, by being terminated into control electricity in the TE of gated clock
Road can detect whether rear connection register breaks down in the capture phase of gated clock, improve test coverage.
It should be noted that the specific implementation mode of the control method of the gated clock of the embodiment of the present invention is real with the present invention
The specific implementation mode for applying the control system of the gated clock of example is similar, is retouched referring specifically to the control system part of gated clock
It states, in order to reduce redundancy, does not repeat.
In addition, the control system of the gated clock of the embodiment of the present invention and other compositions of control method and effect for
All it is known for those skilled in the art, in order to reduce redundancy, does not repeat.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiments or example in can be combined in any suitable manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of being detached from the principle of the present invention and objective a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The range of invention is by claim and its equivalent limits.
Claims (5)
1. a kind of control system of gated clock, which is characterized in that including：
Gated clock, the output end of the gated clock are connected with register to be detected；
First control circuit is connected with the ends TE of the gated clock, and the first control circuit is for receiving the enabled letter of scanning
Number and first control signal, and the scan enable signal and the first control signal are sent to the TE of the gated clock
Clock signal is propagated in end to control the gated clock according to the scan enable signal or the first control signal；
Gated clock enable signal control module is connected with the enable signal end of the gated clock, for providing the gate
The conducting enable signal of clock, so that the gated clock is connected when receiving the conducting enable signal.
2. the control system of gated clock according to claim 1, which is characterized in that the first control circuit includes：
Scanning signal receiving terminal, for receiving the scan enable signal；
First register selectively provides first control signal for providing；
Wherein, the output end of the scanning signal receiving terminal and first register commonly through or door and the gated clock
The ends TE be connected.
3. the control system of gated clock according to claim 2, which is characterized in that the first control circuit also wraps
It includes：
Clock signal incoming end, for receiving clock signal；
Wherein, the scanning signal receiving terminal and the clock signal incoming end commonly through with door and first register
Clock signal input terminal is connected.
4. the control system of gated clock according to claim 3, which is characterized in that the number of first register is defeated
Enter end with the output end of first register to be connected.
5. a kind of control method of gated clock, which is characterized in that including claim 2-4 any one of them gated clocks
The control method of control system, the gated clock includes the following steps：
The logical value of the first register described in the conversion stage is set in by first control circuit；
The gated clock, which is controlled, according to the logical value of the first register described in the conversion stage propagates clock letter in capture phase
Number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027309.8A CN108365841A (en) | 2018-01-11 | 2018-01-11 | The control system and control method of gated clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027309.8A CN108365841A (en) | 2018-01-11 | 2018-01-11 | The control system and control method of gated clock |
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| Publication Number | Publication Date |
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| CN108365841A true CN108365841A (en) | 2018-08-03 |
Family
ID=63010973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810027309.8A Pending CN108365841A (en) | 2018-01-11 | 2018-01-11 | The control system and control method of gated clock |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110346618A (en) * | 2019-07-29 | 2019-10-18 | 天津大学 | A kind of OCC circuit being directed to multi-clock zone at-speed test |
| CN111610435A (en) * | 2020-05-22 | 2020-09-01 | Oppo广东移动通信有限公司 | Control circuit, chip and control method for controlling clock gating unit |
| CN112557887A (en) * | 2020-11-17 | 2021-03-26 | Oppo广东移动通信有限公司 | On-chip clock control device, chip test system and test method |
| CN113467569A (en) * | 2021-06-29 | 2021-10-01 | 展讯通信（上海）有限公司 | Gated clock control system, test method thereof and control chip |
| CN114217211A (en) * | 2021-12-15 | 2022-03-22 | 四川创安微电子有限公司 | Circuit for reducing dynamic test power consumption of scan chain and control method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1139315A (en) * | 1993-06-30 | 1997-01-01 | 哈里公司 | Glitch suppressor circuit and method |
| US6108794A (en) * | 1998-02-24 | 2000-08-22 | Agilent Technologies | Signal comparison system and method for improving data analysis by determining transitions of a data signal with respect to a clock signal |
| CN1702962A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Condition presetting construction based D trigger having scanning test function |
| CN101446842A (en) * | 2008-12-29 | 2009-06-03 | 中国科学院计算技术研究所 | Clock-gating system and operating method thereof |
| CN101686041A (en) * | 2008-09-27 | 2010-03-31 | 深圳市芯海科技有限公司 | Gated clock circuit and gated clock signal generation method |
| WO2012007643A1 (en) * | 2010-07-16 | 2012-01-19 | Aalto University Foundation | Sequential circuit with current mode error detection |
| WO2014043856A1 (en) * | 2012-09-19 | 2014-03-27 | Qualcomm Incoporated | Clock gating circuit for reducing dynamic power |
| CN204131477U (en) * | 2013-07-22 | 2015-01-28 | 北欧半导体公司 | Digital circuits section |
| CN104852712A (en) * | 2015-05-19 | 2015-08-19 | 中国电子科技集团公司第四十七研究所 | Low-power-consumption gated clock circuit structure based on data variation |
| CN105471412A (en) * | 2014-09-29 | 2016-04-06 | 德克萨斯仪器股份有限公司 | Integrated clock gating cell using a low area and a low power latch |
| CN105978539A (en) * | 2016-05-16 | 2016-09-28 | 东南大学 | Quick clock stretching circuit of simplified structure |
| CN107046415A (en) * | 2015-12-14 | 2017-08-15 | 台湾积体电路制造股份有限公司 | Internal clocking door control unit and its operating method |
-
2018
- 2018-01-11 CN CN201810027309.8A patent/CN108365841A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1139315A (en) * | 1993-06-30 | 1997-01-01 | 哈里公司 | Glitch suppressor circuit and method |
| US6108794A (en) * | 1998-02-24 | 2000-08-22 | Agilent Technologies | Signal comparison system and method for improving data analysis by determining transitions of a data signal with respect to a clock signal |
| CN1702962A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Condition presetting construction based D trigger having scanning test function |
| CN101686041A (en) * | 2008-09-27 | 2010-03-31 | 深圳市芯海科技有限公司 | Gated clock circuit and gated clock signal generation method |
| CN101446842A (en) * | 2008-12-29 | 2009-06-03 | 中国科学院计算技术研究所 | Clock-gating system and operating method thereof |
| WO2012007643A1 (en) * | 2010-07-16 | 2012-01-19 | Aalto University Foundation | Sequential circuit with current mode error detection |
| WO2014043856A1 (en) * | 2012-09-19 | 2014-03-27 | Qualcomm Incoporated | Clock gating circuit for reducing dynamic power |
| CN204131477U (en) * | 2013-07-22 | 2015-01-28 | 北欧半导体公司 | Digital circuits section |
| CN105471412A (en) * | 2014-09-29 | 2016-04-06 | 德克萨斯仪器股份有限公司 | Integrated clock gating cell using a low area and a low power latch |
| CN104852712A (en) * | 2015-05-19 | 2015-08-19 | 中国电子科技集团公司第四十七研究所 | Low-power-consumption gated clock circuit structure based on data variation |
| CN107046415A (en) * | 2015-12-14 | 2017-08-15 | 台湾积体电路制造股份有限公司 | Internal clocking door control unit and its operating method |
| CN105978539A (en) * | 2016-05-16 | 2016-09-28 | 东南大学 | Quick clock stretching circuit of simplified structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110346618A (en) * | 2019-07-29 | 2019-10-18 | 天津大学 | A kind of OCC circuit being directed to multi-clock zone at-speed test |
| CN111610435A (en) * | 2020-05-22 | 2020-09-01 | Oppo广东移动通信有限公司 | Control circuit, chip and control method for controlling clock gating unit |
| CN111610435B (en) * | 2020-05-22 | 2022-06-10 | Oppo广东移动通信有限公司 | Control circuit, chip and control method for controlling clock gating unit |
| CN112557887A (en) * | 2020-11-17 | 2021-03-26 | Oppo广东移动通信有限公司 | On-chip clock control device, chip test system and test method |
| CN113467569A (en) * | 2021-06-29 | 2021-10-01 | 展讯通信（上海）有限公司 | Gated clock control system, test method thereof and control chip |
| CN114217211A (en) * | 2021-12-15 | 2022-03-22 | 四川创安微电子有限公司 | Circuit for reducing dynamic test power consumption of scan chain and control method thereof |
| CN114217211B (en) * | 2021-12-15 | 2023-09-01 | 四川创安微电子有限公司 | Circuit for reducing dynamic test power consumption of scan chain and control method thereof |
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