CN101686041A - Gated clock circuit and gated clock signal generation method - Google Patents
Gated clock circuit and gated clock signal generation method Download PDFInfo
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- CN101686041A CN101686041A CN200810216610A CN200810216610A CN101686041A CN 101686041 A CN101686041 A CN 101686041A CN 200810216610 A CN200810216610 A CN 200810216610A CN 200810216610 A CN200810216610 A CN 200810216610A CN 101686041 A CN101686041 A CN 101686041A
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Abstract
The invention belongs to the field of digital circuits and provides a gated clock circuit and a gated clock signal generation method; the gated clock circuit comprises a circuit module for receiving afirst clock signal and outputting a second clock signal which has phase difference with the first clock signal; and an operation module for receiving the second clock signal and an enable signal andoutputting a gated clock signal after logical operation is carried out. By adopting the gated clock circuit provided by the invention, the gated clock signal is output to trigger a register after thelogical operation is carried out to the clock signals and the enable signal by utilizing the simple circuit module and the operation module, so as to lead the register not to use an enable pin (EN); the structure is simple, the occupied chip area of the register is saved and the whole power consumption of the chip is greatly reduced.
Description
Technical field
The invention belongs to the digital circuit field, relate in particular to a kind of door control clock circuit and door controling clock signal production method.
Background technology
In traditional synchronous logic Design of Digital Circuit, as shown in Figure 1, the clock end CK of register is connected directly on the global clock signal CLK_SYS of system, yet, because most registers need all not produce saltus step at the rising edge of each clock, therefore, the high frequency saltus step of clock end CK input signal has caused huge power wastage.
Simultaneously, the register of this structure needs Enable Pin EN, has increased extra enable circuits, has increased the chip area that single register need take.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of can reduce power consumption, saves the door control clock circuit of chip area.
The embodiment of the invention is achieved in that a kind of door control clock circuit, and described door control clock circuit comprises:
Circuit module receives first clock signal, and output and described first clock signal have the second clock signal of phase difference;
Computing module receives described second clock signal and enable signal, carries out exporting door controling clock signal after the logical operation.
Another purpose of the embodiment of the invention is to provide a kind of method that adopts above-mentioned door control clock circuit to produce door controling clock signal, comprises the steps:
Receive first clock signal, output and described first clock signal have the second clock signal of phase difference;
Described second clock signal and enable signal are carried out exporting door controling clock signal after the logical operation.
The door control clock circuit that the embodiment of the invention provides adopts simple circuit module and computing module that clock signal and enable signal are carried out exporting door controling clock signal with trigger register after the logical operation, thereby make register not need Enable Pin EN, simple in structure, saved the chip area that register need take, greatly reduce the overall power of chip.
Description of drawings
Fig. 1 is the circuit diagram of the door control clock circuit that provides of prior art;
Fig. 2 is the circuit diagram of the door control clock circuit that provides of the embodiment of the invention;
Fig. 3 is a signal sequence oscillogram in the door control clock circuit that provides of the embodiment of the invention;
Fig. 4 is the flow chart of the door controling clock signal production method that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The door control clock circuit that the embodiment of the invention provides adopts simple circuit module and computing module that clock signal and enable signal are carried out exporting door controling clock signal after the logical operation; Simple in structure, low in energy consumption.
The door control clock circuit that the embodiment of the invention provides be mainly used in random access memory (RandomAccess Memory, RAM) in, adopt the application scenario of register as main storage means; Specifically be applied in the digital signal processing circuit.
Fig. 2 shows the circuit of the door control clock circuit that the embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention, and details are as follows.
Door control clock circuit 1 comprises: circuit module 11 and computing module 12, and wherein, circuit module 11 receives first clock signal, and the output and first clock signal have the second clock signal of phase difference; Computing module 12 receives second clock signal and enable signal, carries out exporting door controling clock signal after the logical operation; This door controling clock signal is connected to the clock end CK of register 2, as the clock signal of trigger register 2.
In embodiments of the present invention, circuit module 11 can be inverter circuit, also can be a not circuit, can also can produce the circuit module that the appropriate phase difference is arranged with first clock signal for any.As one embodiment of the present of invention, the phase difference of the second clock signal and first clock signal is 180 °.As an alternative embodiment of the invention, first clock signal can be the global clock signal, also can be any clock signal that is used to drive register 2.
In embodiments of the present invention, computing module 12 can be AND circuit, also can be any computing module that can carry out logic and operation.AND circuit 12 carries out second clock signal and enable signal to export door controling clock signal behind the logic and operation.As one embodiment of the present of invention, enable signal is the signal that keeps certain sequential relationship with first rising edge of clock signal or trailing edge signal.
Fig. 3 shows signal sequence oscillogram in the door control clock circuit that the embodiment of the invention provides, and first clock signal is a square-wave signal, and the second clock signal is the square-wave signal anti-phase with first clock signal; Enable signal is triggered by first rising edge of clock signal and changes, ratio first rising edge of clock signal is td late, the enable signal and first clock signal carry out with computing after, obtained door controling clock signal, and the rising edge of door controling clock signal is relevant with the trailing edge of first clock signal.
Fig. 4 shows the flow process of the door controling clock signal production method that the embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention, and details are as follows.
In step S41, receive first clock signal, the output and first clock signal have the second clock signal of phase difference; Wherein, the phase difference of the second clock signal and first clock signal is 180 °.
In step S42, second clock signal and enable signal are carried out exporting door controling clock signal after the logical operation.
As one embodiment of the present of invention, second clock signal and enable signal carry out exporting door controling clock signal behind the logic and operation, and this door controling clock signal is connected to the clock end CK of register, as the clock signal of trigger register 2.Like this, the time that register will about in advance half first clock signal period produces saltus step; Reduced power consumption.Simultaneously, the register that adopts above-mentioned door controling clock signal to trigger does not need Enable Pin, saves chip area.
The door control clock circuit that the embodiment of the invention provides adopts simple circuit module and computing module that clock signal and enable signal are carried out exporting door controling clock signal with trigger register after the logical operation, thereby make register not need Enable Pin EN, simple in structure, saved the chip area that register need take, greatly reduce the overall power of chip.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of door control clock circuit is characterized in that, described door control clock circuit comprises:
Circuit module receives first clock signal, and output and described first clock signal have the second clock signal of phase difference;
Computing module receives described second clock signal and enable signal, carries out exporting door controling clock signal after the logical operation.
2, door control clock circuit as claimed in claim 1 is characterized in that, described circuit module comprises the inverter circuit OR-NOT circuit.
3, door control clock circuit as claimed in claim 1 is characterized in that, the phase difference of described second clock signal and described first clock signal is 180 °.
4, door control clock circuit as claimed in claim 1 is characterized in that, described computing module comprises AND circuit, and described AND circuit carries out described second clock signal and enable signal to export door controling clock signal behind the logic and operation.
5, door control clock circuit as claimed in claim 1 is characterized in that, described first clock signal is the global clock signal.
6, door control clock circuit as claimed in claim 1 is characterized in that, described enable signal and described first clock signal keep sequential relationship.
7, a kind of method that adopts the door control clock circuit generation door controling clock signal of claim 1 is characterized in that described method comprises the steps:
Receive first clock signal, output and described first clock signal have the second clock signal of phase difference;
Described second clock signal and enable signal are carried out exporting door controling clock signal after the logical operation.
8, method as claimed in claim 7 is characterized in that, the phase difference of described second clock signal and described first clock signal is 180 °.
9, method as claimed in claim 7 is characterized in that, described second clock signal and enable signal are carried out exporting door controling clock signal behind the logic and operation.
10, method as claimed in claim 7 is characterized in that, described enable signal and described first clock signal keep sequential relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810216610A CN101686041A (en) | 2008-09-27 | 2008-09-27 | Gated clock circuit and gated clock signal generation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810216610A CN101686041A (en) | 2008-09-27 | 2008-09-27 | Gated clock circuit and gated clock signal generation method |
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| CN101686041A true CN101686041A (en) | 2010-03-31 |
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| CN200810216610A Pending CN101686041A (en) | 2008-09-27 | 2008-09-27 | Gated clock circuit and gated clock signal generation method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819418A (en) * | 2012-07-31 | 2012-12-12 | 中国人民解放军国防科学技术大学 | FIFO data storage method and device of ultrafine particle gated clock |
| WO2014043856A1 (en) * | 2012-09-19 | 2014-03-27 | Qualcomm Incoporated | Clock gating circuit for reducing dynamic power |
| CN104104377A (en) * | 2013-04-01 | 2014-10-15 | 联发科技（新加坡）私人有限公司 | Low power clock gating circuit |
| CN104598160A (en) * | 2013-10-31 | 2015-05-06 | 北京航天长征飞行器研究所 | Method for lowering power consumption of nand flash controller |
| CN108365841A (en) * | 2018-01-11 | 2018-08-03 | 北京国睿中数科技股份有限公司 | The control system and control method of gated clock |
| CN109857190A (en) * | 2019-02-27 | 2019-06-07 | 苏州浪潮智能科技有限公司 | A kind of clock signal processing method, device, equipment and readable storage medium storing program for executing |
| CN111753962A (en) * | 2020-06-24 | 2020-10-09 | 国汽(北京)智能网联汽车研究院有限公司 | Adder, multiplier, convolution layer structure, processor and accelerator |
-
2008
- 2008-09-27 CN CN200810216610A patent/CN101686041A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819418A (en) * | 2012-07-31 | 2012-12-12 | 中国人民解放军国防科学技术大学 | FIFO data storage method and device of ultrafine particle gated clock |
| CN102819418B (en) * | 2012-07-31 | 2015-01-07 | 中国人民解放军国防科学技术大学 | FIFO data storage method and device of ultrafine particle gated clock |
| US9270270B2 (en) | 2012-09-19 | 2016-02-23 | Qualcomm Incorporated | Clock gating circuit for reducing dynamic power |
| WO2014043856A1 (en) * | 2012-09-19 | 2014-03-27 | Qualcomm Incoporated | Clock gating circuit for reducing dynamic power |
| CN104104377B (en) * | 2013-04-01 | 2017-12-12 | 联发科技（新加坡）私人有限公司 | Clock gating circuit |
| CN104104377A (en) * | 2013-04-01 | 2014-10-15 | 联发科技（新加坡）私人有限公司 | Low power clock gating circuit |
| CN107911104A (en) * | 2013-04-01 | 2018-04-13 | 联发科技（新加坡）私人有限公司 | Clock gating circuit |
| CN107911104B (en) * | 2013-04-01 | 2021-08-10 | 联发科技（新加坡）私人有限公司 | Clock gating circuit |
| CN104598160A (en) * | 2013-10-31 | 2015-05-06 | 北京航天长征飞行器研究所 | Method for lowering power consumption of nand flash controller |
| CN108365841A (en) * | 2018-01-11 | 2018-08-03 | 北京国睿中数科技股份有限公司 | The control system and control method of gated clock |
| CN109857190A (en) * | 2019-02-27 | 2019-06-07 | 苏州浪潮智能科技有限公司 | A kind of clock signal processing method, device, equipment and readable storage medium storing program for executing |
| CN111753962A (en) * | 2020-06-24 | 2020-10-09 | 国汽(北京)智能网联汽车研究院有限公司 | Adder, multiplier, convolution layer structure, processor and accelerator |
| CN111753962B (en) * | 2020-06-24 | 2023-07-11 | 国汽(北京)智能网联汽车研究院有限公司 | Adder, multiplier, convolution layer structure, processor and accelerator |
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Application publication date: 20100331 |