CN107991981B - A kind of service board and electronic equipment - Google Patents
A kind of service board and electronic equipment Download PDFInfo
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- CN107991981B CN107991981B CN201711269548.6A CN201711269548A CN107991981B CN 107991981 B CN107991981 B CN 107991981B CN 201711269548 A CN201711269548 A CN 201711269548A CN 107991981 B CN107991981 B CN 107991981B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor
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Abstract
The embodiment of the present invention provides a kind of service board and electronic equipment, is related to field of electronic device, the power supply power supply stability of main business processing unit circuit can be improved.Electronic equipment includes: that the pre- power domain that powers on includes: pre- to power on power supply, microprocessor, power supply control chip, logic gate device；Main circuit power domain includes: at least one branch power supply, at least one set of main business processing unit circuit, primary processor and complex programmable logic device (CPLD).
Description
Technical field
The embodiment of the present invention is related to field of electronic device more particularly to a kind of service board and electronic equipment.
Background technique
Either modern communications industry device, or the equipment such as server, PC of industry class are calculated, it is required to industry
Processing capacity of being engaged in is stronger and stronger, therefore, undertakes core devices (such as the CPU, ether exchange chip of the processing of these appliance services
Deng) integrated level is commonly several hundred million equivalent transistors.With the sustainable development of circuit of single-chip integrated scale and processing speed,
The power consumption requirements of itself even more rapidly increase, and in order to lower consumption and facilitate heat dissipation, present large scale integrated circuit generallys use more
Kind supply voltage internal zone dividing power supply mode, such as integrated circuit kernel device, Peripheral Interface class device, communication interface class device
The Service Processing Units such as part, common management class device are required to that respective supply voltage is supported to power, therefore, either embedded
CPU calculates class CPU or ether exchange chip, and each model device needs the power supply of multiple voltage value right and wrong
The device technology specification usually seen.
To realize multivoltage value working method, industry design it is almost the same using programmable single chip computer (such as: MCU,
Micro Controller Unit, Chinese: microcontroller) go control service board on various voltages branch power supply open and
It closes, the electric sequential control that powers on/descend of each branch power supply is realized using the code of MCU, with extraordinary using flexible and good
Good technology is portable.
But realize that the periphery MCU makes can control at signal (ON/OFF signal) to branch power supply in specific design
In reason, there are many variations, such as the design having uses CPLD (Complex Programmable Logic Device, complexity
Programmable logic device) device carries out branch power supply and makes to can control the latch of signal keeping, and some designs use the most common mark
Quasi- gate circuit: 74HC273, which carries out branch power supply, keeps the latch that can control signal, or even some designs are directly using MCU's
GPIO (General Purpose Input Output, universal input output) pin, the above design in practical applications
Reliability operation problem can be all faced, under certain situation, entire business can be led to because of the one small loophole (BUG) of MCU
Veneer powers off and the catastrophe failure event that is unable to run.
Summary of the invention
The embodiment of the present invention provides a kind of service board and electronic equipment, and the electricity of main business processing unit circuit can be improved
The stability of source power supply.
In a first aspect, providing a kind of service board, including power domain and main circuit power domain are powered in advance；
The pre- power domain that powers on includes: pre- to power on power supply, microprocessor, power supply control chip, logic gate device；It is described
Main circuit power domain includes: at least one branch power supply, at least one main business processing unit circuit, primary processor and complexity
Programmable logic device (CPLD)；
The pre- power supply that powers on connects the microprocessor, the power supply control chip, the logic gate；It is described micro-
At least one signal output end of processor is connect one by one at least one signal input part of the power supply control chip；It is described
The either signal output end of microprocessor connects the first input end of the logic gate device；The power supply control chip is at least
One signal output end is connected one by one at least one described branch power supply；The power supply control chip either signal output end connects
Connect the second input terminal of the logic gate device；The output end of the logic gate device connects the clock of the power supply control chip
Signal input part；
At least one branch power supply is used to supply at least one main business processing unit circuit, primary processor and CPLD
Electricity；One general-purpose interface of the primary processor connects the third input terminal of the logic gate device, the primary processor
Described in the connection of UART (Universal Asynchronous Receiver/Transmitter, UART Universal Asynchronous Receiver Transmitter) interface
The UART interface of microprocessor；The primary processor is also connected with the CPLD；Described in the general-purpose interface connection of the CPLD
4th input terminal of logic gate device；
Wherein, it is described it is pre- power on power supply, for the microprocessor, the power supply control chip, the logic gate device
Part power supply；
The microprocessor connects the power supply control chip, for controlling the power supply control chip to the main circuit
At least one branch power supply output of power domain opens or closes signal；
The microprocessor is used for the first input end input clock signal to the logic gate；
After the primary processor sends normal operation signal to the microprocessor by UART interface, the microprocessor
It is also used to control the power supply control chip and inputs first control signal to the second input terminal of the logic gate device；
The primary processor is also used to input second control signal to the third input terminal of the logic gate device；
The primary processor is also used to control the CPLD and inputs third control to the 4th input terminal of the logic gate device
Signal processed；
The logic gate device be used for according to the first control signal, second control signal, third control signal and
The clock signal generates locking signal, and exports to the clock signal input terminal of the power supply control chip, the power supply control
Coremaking piece locks the state of current each signal output end output signal according to the locking signal.
In the above scheme, the structure based on above-mentioned service board, due to passing through UART interface to micro- place when primary processor
After managing device transmission normal operation signal, the second input terminal that microprocessor can control power supply control chip to logic gate device is defeated
Enter first control signal；Primary processor can input second control signal to the third input terminal of logic gate device；Primary processor
CPLD can also be controlled to the 4th input terminal of logic gate device input third control signal；It logic gate device can be according to first
It controls signal, second control signal, third control signal and clock signal and generates locking signal, and export to power supply and control core
The clock signal of piece, power supply control chip lock the state of current each signal output end output signal according to locking signal, from
And after service board operates normally, so that each branch power supply is to corresponding device not by the device for powering on power domain in advance
(for example, microprocessor) influences, so that the stability of the power supply power supply of main business processing unit circuit can be improved.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be in embodiment or description of the prior art
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the invention
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of structure chart of service board provided in an embodiment of the present invention；
Fig. 2 be another embodiment of the present invention provides a kind of service board structure chart.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Shown in referring to Fig.1, the structure for the service board that the electronic equipment that the embodiment of the present invention provides is included is carried out
It is described in detail, which includes: including powering on power domain C1 and main circuit power domain C2 in advance.
Powering on power domain C1 in advance includes: pre- to power on power supply 11, microprocessor 12, power supply control chip 13, logic gate device
14；Main circuit power domain C2 includes: at least one branch power supply 21 (21-1,21-2 ... 21-n), at least one main business
Manage element circuit 22 (22-1,22-2 ... 22-n), primary processor 23 and complex programmable logic device (CPLD) 24.Wherein,
Power in advance the main power source of at least one branch power supply 21 connection in power supply 11 and main circuit power domain parallel to logic gate device and
The power supply control chip is powered.Wherein, powering on power supply 11 and at least one branch power supply 21 in advance may include direct current and turns
DC power supply DC/DC, illustratively ,+12V power supply power supply can be used by powering on power supply 11 and at least one branch power supply 21 in advance,
The DC/DC in power supply 11 is powered in advance, and the voltage of main power source is converted to the electricity for meeting the device voltage requirement for powering on power domain C1 in advance
Pressure is for example
+ 3.3V, the DC/DC in branch power supply 21, which is converted to the voltage of+12V power supply, to be met in the C2 of main circuit power domain
The voltage that the voltage of the circuits such as each main business processing unit circuit, primary processor, CPLD requires, including main circuit power domain C2
Used in+3.3V main power source: VCCmain-3V3.
Power supply 11 is powered in advance connects microprocessor 12, power supply control chip 13, logic gate 14；Microprocessor 12 is extremely
A few signal output end is connect one by one at least one signal input part of power supply control chip 13；Any of microprocessor 12
The first input end in1 of signal output end connection logic gate device 14；At least one signal output end of power supply control chip 13
It is connected one by one at least one branch power supply 21；13 either signal output end of power supply control chip connects the of logic gate device 14
Two input terminal in2；The clock signal input terminal of the output end out connection power supply control chip 13 of logic gate device 14.
At least one branch power supply 21 is used for at least one main business processing unit 22, primary processor 23 and CPLD24
Power supply；Third the input terminal in3, the UART of primary processor 23 of the general-purpose interface connection logic gate device 14 of primary processor 23
The UART interface of interface connection microprocessor 12；Primary processor 23 is also connected with CPLD24；A general-purpose interface of CPLD24 connects
4th input terminal in4 of logic gate device 14.It should be noted that at least one main business processing unit 22, primary processor 23
And CPLD24 may be univoltage value or multivoltage value power supply device, therefore at least one main business processing unit 22, main place
Managing device 23 and CPLD24 can be powered by one or more voltage values provided at least one branch power supply 21.
Wherein, power supply 11 is powered in advance, for powering to microprocessor 12, power supply control chip 13, logic gate device 14；It is micro-
Processor 12 connects power supply control chip 13, for controlling at least one branch of power supply control chip 13 to main circuit power domain
The output of power supply 21 opens or closes signal.
Microprocessor 12 is used for the first input end in1 input clock signal to logic gate 14.
After primary processor 23 sends normal operation signal to microprocessor 12 by UART interface, microprocessor 12 is also used to
It controls power supply control chip 13 and inputs first control signal to the second input terminal in2 of logic gate device 14.
Primary processor 23 is also used to input second control signal to the third input terminal in3 of logic gate device 14.
Primary processor 23 is also used to control CPLD24 to the 4th input terminal in4 of logic gate device 14 input third control letter
Number.
Logic gate device 14 is used to be believed according to first control signal, second control signal, third control signal and clock
Number generate locking signal, and export to power supply control chip 13 clock signal input terminal, power supply control chip 13 is according to locking
The state of the current each signal output end output signal of semaphore lock.
In the above scheme, the structure based on above-mentioned service board, due to passing through UART interface to micro- place when primary processor
After managing device transmission normal operation signal, the second input terminal that microprocessor can control power supply control chip to logic gate device is defeated
Enter first control signal；Primary processor can input second control signal to the third input terminal of logic gate device；Primary processor
CPLD can also be controlled to the 4th input terminal of logic gate device input third control signal；It logic gate device can be according to first
It controls signal, second control signal, third control signal and clock signal and generates locking signal, and export to power supply and control core
The clock signal of piece, power supply control chip lock the state of current each signal output end output signal according to locking signal, from
And after service board operates normally, so that each branch power supply is to corresponding device not by the device for powering on power domain in advance
(for example, microprocessor) influences, so that the stability of the power supply power supply of main business processing unit circuit can be improved.
In 23 failure of primary processor, primary processor 23 is also used to input to the third input terminal in3 of logic gate device 14
5th control signal；Primary processor 23 is also used to control CPLD24 to the 4th input terminal in4 of logic gate device 14 input the 6th
Control signal.
Logic gate device 14 is used to be believed according to the clock that the 5th control signal, the 6th control signal export microprocessor 12
Number output to power supply control chip 14 clock signal input terminal, power supply control chip 14 is according to the clock signal, in Wei Chu
Manage the state that each signal output end is adjusted under the control of device 12.
It such as needs to actively close power supply, then microprocessor 12 sends power supply closing to primary processor 23 by UART interface and refers to
Show；Primary processor 23 is sent to microprocessor 12 by UART interface and closes response；Primary processor 23 is also used to be closed according to power supply
Instruction is closed to the 7th control signal of the third input terminal in3 of logic gate device 14 input；Primary processor 23 is also used to control
CPLD24 controls signal to the 4th input terminal in4 of logic gate device 14 input the 8th；Microprocessor 12 is also used to according to closing
Response control power supply control chip 13 controls signal to the second input terminal in2 of logic gate device 14 input the 9th；Logic gate device
Part 14 is used to be believed according to the clock that the 7th control signal, the 8th control signal and the 9th control signal export microprocessor 12
Number output to power supply control chip 13 clock signal input terminal, power supply control chip 13 is according to clock signal, in microprocessor
The state of each signal output end output signal is adjusted under 12 control, to control the power supply control chip to described at least one
A branch power supply exports shutdown signal.
Referring to shown in Fig. 2, logic gate 14 includes: and door module 141 and/or door module 142；Wherein, with door module
141 include first and door G3 and second and door G4, and first connect the second defeated of logic gate device 14 with the first input end of door G3
Enter and hold in2, first connect the third input terminal in3 of logic gate device 14 with the second input terminal of door G3；Second and the of door G4
One input terminal connects the second input terminal in2 of logic gate device 14, and second connect logic gate device with the second input terminal of door G4
14 the 4th input terminal in4 or door module 142 includes first or door G1 and second or door G2, wherein the first of first or door G1
The second input terminal that input terminal connects the first input end in1, first or door G1 of logic gate device 14 connects second or door G2's
Output end, the output end out of the output end connection logic gate device 14 of first or door G1；The first input end of second or door G2 connects
Connect the output end of first Yu door G3, the output end of the second input terminal connection second and door G4 of second or door G2.
Shown in referring to Fig.1, power supply 11 is powered in advance, microprocessor 12, power supply control chip 13 and logic gate device 14 are adopted
It is powered with such as under type: the first end of the power interface connection first switch transistor Q1 of power supply control chip 13, first switch
The second end connection of transistor Q1 powers on power supply 11 in advance, and the control terminal of first switch transistor Q1 is grounded by first resistor R1
GND；The reseting interface of power supply control chip 13 passes through the first end of second resistance R2 connection first switch transistor Q1, power supply control
The reseting interface of coremaking piece 13 is grounded by capacitor C1；The first end of second switch transistor Q2 connects first switch transistor Q1
First end, the control terminal of second switch transistor Q2 is grounded by 3rd resistor R3, the second end of second switch transistor Q2
Connect the main power source of at least one branch power supply connection in main circuit power domain.The power interface connection first of logic gate device 14
The first end of switching transistor Q1.
In a kind of example, power supply control chip 13 can be used using 74HC273 latch or door module 142
74HC32 or door, 74HC32 or door include G1 and G2, use 74HC08 and door with door module 141,74HC08 and door include G3 and
G4, microprocessor 12 can use PNP triode using CPU, Q1 and Q2 using MCU, primary processor 23, then to above-mentioned electricity
The connection relationship of each device is described as follows in sub- equipment:
The power interface VDD of 74HC273 latch, 74HC32 or door, 74HC08 and door be connected to simultaneously a safety+
3.3V power supply: on Vgood, wherein the VCCpre-3V3 for powering on power domain C1 in advance is connected to Vgood by PNP triode Q1, electricity
Resistance R1 provides enough saturation conduction base current drivings for Q1.Wherein, it with the output end of door G3 and G4, is connected respectively to or door
Two input terminals of G2.Or the output end of door G2, it is connected to or another input terminal of door G1.Master in the C2 of main circuit power domain
Power supply VCCmain-3V3 is connected to Vgood by PNP triode Q2, and resistance R3 provides enough saturation conduction base stage electricity for Q2
Stream driving.
The signal output end Q [6:0] of 74HC273 latch is connected respectively to 7 branch power supplys in the C2 of main circuit power domain
(such as: ON/OFF enable end DC/DC), the output of Xiang Zhilu power supply open or close signal (On/off) for controlling brancher electricity
It opens and powers on interval time in a predetermined sequence in source.The signal output end Q7 of 74HC273 latch, for exporting LOCK letter
Number (i.e. first control signal), is connected to an input terminal of 74HC08 Yu door G3 and G4, for 74HC273 latch clock
The clock signal of signal input part (CLOCK) from lock control.Resistance R2 and capacitor C1 are connected in series on Vgood power supply, resistance R2
The reseting interface (Clear) of 74HC273 latch is connected between capacitor C1, provides electrification reset letter for 74HC273 latch
Number.Signal output end GPIO [7:0] pin (totally 8 pin 8*GIPO) of MCU, is connected respectively to the letter of 74HC273 latch
Number input terminal D [7:0] pin makes to can control signal and generates LOCK latch signal for transmitting branch electric power on/off.
The GPIO8 pin of MCU is connected to an input pin of 74HC32 or door G1, and the output of G1 is connected to 74HC273
The clock signal input terminal CLOCK of latch, the latch control for D [7:0] input information.The UART interface of MCU, passes through
UART-BUS bus is connected in " main circuit power domain C2 " in the UART interface of CPU, for the two intercommunication, transmitting
Necessary control information.
A general-purpose interface (such as GPIO pin) of CPU in the C2 of main circuit power domain be connected to door G3 another
Input terminal can issue control signal, such as: second control signal CPU-ctl, the 4th resistance R4 that one end is grounded GND connect
It is connected to the GPIO pin of CPU, so that CPU-ctl signal is defaulted as low level.CPLD in " main circuit power domain C2 " is used
One general-purpose interface (such as GPIO pin) is connected to another input terminal with door G4, can issue control signal, such as:
Third controls signal CPLD-ctl, and the 5th resistance R5 of one end ground connection GND is connected in the GPIO pin of CPLD, makes the signal
CPLD-ctl is defaulted as low level.It is connected with cbus communication bus between CPU and CPLD, is passed for information necessary between two devices
It passs.It is total that cbus communication bus can be the most common SPI (Serial Peripheral Interface, serial type Peripheral Interface)
Line, LPC (Low Pin Count, low pin count communication interface) bus, Local_Bus (local communications bus) bus etc..
Based on the connection relationship of above-mentioned electronic equipment, to the workflow for the electronic equipment that the embodiment of the present invention provides
It is described as follows:
Process one: the procedure declaration that main circuit power domain C2 is powered on for the first time is as follows :+12V the voltage stabilization that main power source provides
After normal, power on the start-up operation of power supply 11 in advance, convert out VCCpre-3V3 power supply be initially supplied it is pre- power on it is each in power domain C1
A device.And each branch power supply 21 (21-1,21-2 ... 21-n) in the C2 of main circuit power domain is although be also connected to main electricity
Source, but since the enabled control terminal of branch power supply 21 is in invalid state, it is completely in closed state, so that main circuit
Each circuit of power domain C2 is all temporarily in electroless state.After MCU12 obtains VCCpre-3V3 power supply power supply, start starting fortune
Row.
Meanwhile VCCpre-3V3 power supply by Q1 generate Vgood power supply, also start to 74HC273 latch, 74HC32 or
Door, 74HC08 and door are powered.The resistance R2 being connected on Vgood power supply charges to capacitor C1, and when C1 meets predetermined voltage,
Reset operation is carried out to 74HC273 latch by Clear pin, after powering on 74HC273 latch, output Q [7:0]=
0, it is completely in stable low level state.When the Q7 of 74HC273 latch output is 0, i.e. signal LOCK=0, then compeling
Make output all 0 (unrelated with the level value of CPU-ctl signal and CPLD-ctl signal) with door G3 and G4 or door G2's is defeated
It is out also 0, be equivalent to the GPIO8 output signal of MCU: the clock signal that GPIO-CLK is directly connected to 74HC273 latch is defeated
Enter end (CLOCK).
After MCU start completion, GPIO [8:0] will be all configured to signal output end, the UART controller initialization of MCU
For state can be used directly.In next step will according to set strategy, control main circuit power domain C2 each branch power supply 21 (21-1,
21-2 ... 21-n) unlatching, it is assumed that the opening sequence of each branch power supply is 1/2/3/4/5/6/7, and each branch power supply is opened
It is divided into 10 milliseconds between opening, specific as follows:
The GPIO-CLK signal that GPIO8 is arranged in S1, MCU exports high level 1, and keeps.
S2, MCU are arranged GPIO0 and export high level 1, and keep.
The GPIO-CLK signal that GPIO8 is arranged in S3, MCU exports low level 0, after 10 milliseconds of delay, then setting GPIO8's
GPIO-CLK signal exports high level 1, and keeps；At this point, the branch power supply 22-1 of main circuit power domain C2 works on power.
Then, MCU is delayed 10 milliseconds, starts the unlatching control of next branch power supply 22-2, is directed to GPIO1/ respectively
GPIO2/GPIO3/GPIO4/GPIO5/GPIO6 repeats step S1-S3, in this way will be branch power supply 22-2 to branch electricity
Source 22-7 is successively opened, and main circuit power domain C2 is made to enter regular traffic starting state.MCU controls each on the C2 of main circuit power domain
After branch power supply electrifying, other monitor tasks, while the confirmation message of waiting for CPU loopback " normal operation " are started to process.
Process two: CPU starts to start in the C2 of main circuit power domain, and controls other circuits in power domain C2 while carrying out
Starting.After CPU start completion, its general-purpose interface GPIO2 pin will be initialized as exporting, and export high level 1, i.e., at this time
CPU-ctl signal is high level 1.Also by the cbus communication bus by being connected with CPLD, general CPLD connects CPU simultaneously
Mouth GPIO3 is set as output high level 1, i.e., CPLD-ctl signal is high level 1 at this time.Later, CPU is total by UART-BUS
Line sends normal operation signal to MCU.
After MCU receives the normal operation signal of CPU transmission, it will be considered that each circuit unit in the C2 of main circuit power domain is
Through completely normal, MCU is performed the following operations at this time:
S1, MCU are arranged GPIO7 and export high level 1, and keep.
The GPIO-CLK signal that GPIO8 is arranged in S2, MCU exports low level 0, is delayed 10 milliseconds, the GPIO- of GPIO8 is arranged
CLK signal exports high level 1, and keeps；At this point, the Q7 output of 74HC273 latch will become high level 1, i.e. signal LOCK
=1.
In this way with all high level 1 of all input signals of door G3 and G4 so that their output signal: G3SIG and
G4SIG also by all high level 1, thus or door G2 output signal: G2SIG becomes high level 1.When signal G2SIG becomes
When high level 1 or the output of door G1 by it is constant be high level 1, make the CLOCK of 74HC273 latch no longer by the GPIO8 of MCU
Output signal control, no matter MCU occurs which type of catastrophe failure (including restarting, chaotic operation, power down etc.) will not at this time
Any influence is generated to the branch power unit in the C2 of main circuit power domain, makes the main business processing unit of main circuit power domain C2
Remain normal operation.
Process three: when CPU breaks down, the hardware watchdog circuit for CPU configuration will carry out hardware reset behaviour to CPU
Make, while also CPU-ctl signal and CPLD-ctl signal can all be resetted output low level 0, at this time signal G3SIG=
G4SIG=G2SIG=0, is equivalent to the GPIO8 output signal of MCU: GPIO-CLK be directly connected to 74HC273 latch when
Clock signal input part (CLOCK), a MCU occur can control the time window of 74HC273 latch.When CPU restarts
After the completion, output high level 1 all will be arranged in CPU-ctl signal and CPLD-ctl signal again, as described in process two, this
When signal G3SIG=G4SIG=G2SIG=1, the time window of MCU control 74HC273 latch is closed, and MCU will not be to master
Branch power unit in the C2 of circuit power domain generates any influence, makes the main business processing unit of main circuit power domain C2 always
It keeps operating normally.
Process four: when MCU and CPU is all worked normally, the institute in the C2 of main circuit power domain is actively closed if necessary
There is branch power supply, treatment process is as follows:
S1, MCU issue power supply to CPU by UART-BUS and close instruction, after CPU receives power supply closing instruction,
All setting exports low level 0 for CPU-ctl signal and CPLD-ctl signal, is then replied by UART-BUS and closes response extremely
MCU, at this point, G3SIG=G4SIG=G2SIG=0, MCU retrieve the control of 74HC273 latch.
The Q7 output of 74HC273 latch is set as 0 by S2, MCU, i.e. holding signal LOCK=0.
S3, MCU carry out according to this various branch power supplys in the C2 of main circuit power domain according to set lower electric order requirements
Shutoff operation.
After the various branch power supply shutoff operations in the C2 of main circuit power domain are fully completed, MCU enters low power consumpting state
Operation.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of service board, which is characterized in that including powering on power domain and main circuit power domain in advance；
The pre- power domain that powers on includes: pre- to power on power supply, microprocessor, power supply control chip, logic gate device；The main electricity
Road power domain includes: that at least one branch power supply, at least one main business processing unit circuit, primary processor and complexity can be compiled
Journey logic device (CPLD)；
The pre- power supply that powers on connects the microprocessor, the power supply control chip, the logic gate device；The micro process
At least one signal output end of device is connect one by one at least one signal input part of the power supply control chip；Micro- place
The either signal output end of reason device connects the first input end of the logic gate device；At least one of the power supply control chip
Signal output end is connected one by one at least one described branch power supply；The power supply control chip either signal output end connects institute
State the second input terminal of logic gate device；The output end of the logic gate device connects the clock signal of the power supply control chip
Input terminal；
At least one branch power supply is used to power at least one main business processing unit circuit, primary processor and CPLD；Institute
A general-purpose interface for stating primary processor connects the third input terminal of the logic gate device, the UART interface of the primary processor
Connect the UART interface of the microprocessor；The primary processor is also connected with the CPLD；A general-purpose interface of the CPLD
Connect the 4th input terminal of the logic gate device；
Wherein, it is described it is pre- power on power supply, for the microprocessor, the power supply control chip, the logic gate device supply
Electricity；
The microprocessor connects the power supply control chip, for controlling the power supply control chip to the main circuit power
At least one branch power supply output in domain opens or closes signal；
The microprocessor is used for the first input end input clock signal to the logic gate device；
After the primary processor sends normal operation signal to the microprocessor by UART interface, the microprocessor is also used
First control signal is inputted to the second input terminal of the logic gate device in controlling the power supply control chip；The main process task
Device is also used to input second control signal to the third input terminal of the logic gate device；
The primary processor is also used to control the CPLD to the 4th input terminal of logic gate device input third control letter
Number；
The logic gate device is used for according to the first control signal, second control signal, third control signal and described
Clock signal generates locking signal, and exports to the clock signal input terminal of the power supply control chip, and the power supply controls core
Piece locks the state of current each signal output end output signal according to the locking signal；
Wherein, the logic gate device includes and door module and/or door module；It is described to include first and door and second with door module
With door, described or door module includes first or door and second or door.
2. service board according to claim 1, which is characterized in that
When the primary processor failure, the primary processor is also used to input the 5th to the third input terminal of the logic gate device
Control signal；
The primary processor is also used to control the CPLD to the 6th control letter of the 4th input terminal of logic gate device input
Number；
The logic gate device is used for the institute for exporting the microprocessor according to the 5th control signal, the 6th control signal
It states clock signal to export to the clock signal input terminal of the power supply control chip, the power supply control chip is according to the clock
Signal adjusts the state of each signal output end under the control of the microprocessor.
3. service board according to claim 1, which is characterized in that
The microprocessor sends power supply to the primary processor by UART interface and closes instruction；The primary processor passes through
UART interface sends to microprocessor and closes response；
The primary processor is also used to close instruction according to power supply to the 7th control of the third input terminal of logic gate device input
Signal processed；
The primary processor is also used to control the CPLD to the 8th control letter of the 4th input terminal of logic gate device input
Number；
The microprocessor is also used to the power supply control chip according to the closing response control to the logic gate device
The 9th control signal of second input terminal input；
The logic gate device is used for will according to the 7th control signal, the 8th control signal and the 9th control signal
The clock signal of the microprocessor output is exported to the clock signal input terminal of the power supply control chip, the power supply
Chip is controlled according to the clock signal, the shape of each signal output end output signal is adjusted under the control of the microprocessor
State exports shutdown signal to control the power supply control chip at least one branch power supply in the main circuit power domain.
4. service board according to claim 1, which is characterized in that
Described first connect the second input terminal of the logic gate device with the first input end of door, and described first and the second of door
Input terminal connects the third input terminal of the logic gate device；Described second connect the logic gate device with the first input end of door
Second input terminal of part, described second connect the 4th input terminal of the logic gate device with the second input terminal of door；
Described first or the first input end of door connect the first input end of the logic gate device, described first or door second
Input terminal connects the output end of described second or door, described first or the output end of door connect the output of the logic gate device
End；Described second or the first input end of door connect the output end of described first Yu door, described second or door the second input terminal
Connect the output end of described second Yu door.
5. service board according to claim 1, which is characterized in that described pre- to power on power supply and the main circuit power domain
At least one branch power supply connection main power source the logic gate device and the power supply control chip are powered parallel.
6. service board according to claim 5, which is characterized in that the power interface of power supply control chip connection the
The first end of one switching transistor, the first switch transistor second end connection it is described it is pre- power on power supply, described first opens
The control terminal for closing transistor is grounded by first resistor；
The reseting interface of the power supply control chip connects the first end of the first switch transistor by second resistance, described
The reseting interface of power supply control chip passes through capacity earth；
The first end of second switch transistor connects the first end of the first switch transistor, the second switch transistor
Control terminal is grounded by 3rd resistor, and the second end of the second switch transistor connects at least the one of the main circuit power domain
The main power source of a branch power supply connection.
7. service board according to claim 6, which is characterized in that described in the power interface connection of the logic gate device
The first end of first switch transistor.
8. service board according to claim 1, which is characterized in that the general-purpose interface of the primary processor passes through the 4th electricity
Resistance ground connection.
9. service board according to claim 1, which is characterized in that the general-purpose interface of the general-purpose interface of the CPLD passes through
5th resistance eutral grounding.
10. a kind of electronic equipment, which is characterized in that including such as described in any item service boards of claim 1-9.
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| CN201711269548.6A CN107991981B (en) | 2017-12-05 | 2017-12-05 | A kind of service board and electronic equipment |
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| CN201711269548.6A CN107991981B (en) | 2017-12-05 | 2017-12-05 | A kind of service board and electronic equipment |
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| CN107991981B true CN107991981B (en) | 2019-09-20 |
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| CN111782429B (en) * | 2020-06-12 | 2023-08-29 | 上海橙群微电子有限公司 | Watchdog timer, control method thereof and electronic equipment |
| CN112925380B (en) * | 2021-02-04 | 2022-04-29 | 烽火通信科技股份有限公司 | Complex communication equipment control method, device, equipment and storage medium |
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| CN107991981A (en) | 2018-05-04 |
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Address after: 610041 nine Xing Xing Road 16, hi tech Zone, Sichuan, Chengdu Patentee after: MAIPU COMMUNICATION TECHNOLOGY Co.,Ltd. Address before: 610041, 17 floor, maple building, 1 building, 288 Tianfu street, Chengdu, Sichuan. Patentee before: MAIPU COMMUNICATION TECHNOLOGY Co.,Ltd. |