CN107302317A - The carrier wave implementation method of three-phase five-level inverter drain current suppressing - Google Patents

The carrier wave implementation method of three-phase five-level inverter drain current suppressing Download PDF

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CN107302317A
CN107302317A CN201710444049.XA CN201710444049A CN107302317A CN 107302317 A CN107302317 A CN 107302317A CN 201710444049 A CN201710444049 A CN 201710444049A CN 107302317 A CN107302317 A CN 107302317A
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phase
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CN107302317B (en
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王付胜
郑德佑
李祯
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Hefei University of Technology
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Hefei University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current

Abstract

The invention discloses a kind of carrier wave implementation method of three-phase five-level inverter drain current suppressing.Sampling three-phase raw modulation ripple, according to its position, calculates middle zero-sequence component and excessive zero-sequence component, according to middle zero-sequence component and the size of excessive zero-sequence component, determines the zero-sequence component of superposition needed for three-phase raw modulation ripple.Three-phase raw modulation ripple is added with zero-sequence component and obtains modulating wave in the middle of three-phase.Division zero-sequence component is calculated by modulating wave in the middle of three-phase and zero-sequence component.Three-phase amendment modulating wave and three-phase division modulating wave are obtained by modulating wave in the middle of three-phase and division zero-sequence component.Finally three-phase amendment modulating wave and three-phase division modulating wave are compared with Three Phase Carrier Based, generation PWM ripple control five-electrical level inverters.The present invention can realize that common-mode voltage is low, and striding capacitance voltage pulsation is small, the advantages of leakage current is small；Due to being realized using carrier wave, realize that simply, it is convenient to control, it is easy to be generalized in Practical Project.

Description

The carrier wave implementation method of three-phase five-level inverter drain current suppressing
Technical field
The present invention relates to field of photovoltaic technology, the carrier wave of more particularly to a kind of three-phase five-level inverter drain current suppressing is real Existing method.
Background technology
Solar energy is as a kind of regenerative resource, with widely distributed, sustainable, free of contamination advantage.Photovoltaic generation skill Art is effectively to utilize one of Basic Ways of solar energy resources.At present, the various photovoltaic power generation technologies including grid-connected The support energetically of national governments is received.
In photovoltaic generating system, five-electrical level inverter has lower open for conventional three-level inverter Close loss and current ripples.There is lower Current harmonic distortion rate in the case of filter element identical.
Leakage current is always multi-electrical level inverter research and the emphasis and difficult point in design process, because photovoltaic array is present Direct-to-ground capacitance, high frequency common mode voltage is acted in parasitic capacitance, the resonance circuit of wave filter, electric network impedance and parasitic capacitance composition Impedance very little, therefore the common mode current of high frequency, i.e. leakage current will be produced in not shielding system loop.The presence of leakage current will drop Security, the reliability of low system, easily cause electric shock and fire.And up to the present, rarely have patent and document to propose that this is asked The effective workaround of topic.
The size of leakage current and common-mode voltage amplitude and change frequency are closely related, and amplitude is bigger, and change frequency is higher, leakage Electric current is bigger, conversely, leakage current is smaller.
Five traditional level modulation strategies are using space vector modulation (SVPWM), it is necessary to first carry out area to three dimensional vector diagram Domain is divided, then calculates the action time of basic vector, will finally distribute to corresponding vector state action time, and process is complicated, Project Realization difficulty is big.
Document " A Novel SVPWM Algorithm for Five-Level Active Neutral-Neutral- point-Clamped Converter”,Zhan Liu,Yu Wang,Guojun Tan,Member IEEE,Hao Li,and Yunfeng Zhang,《IEEE Transactions on Power Electronics》,2016,31(5)3859-3866 (" a kind of research of the new SVPWM control algolithms based on active neutral point clamp five-electrical level inverter ",《IEEE journals-electric power electricity Sub- periodical》, the 5th phase page 3859~3866 of volume 31 in 2016) and give the SVPWM algorithms of simplification a kind of, although greatly reduce Amount of calculation, but still excessively cumbersome, have it is certain realize difficulty, while the common-mode voltage amplitude of the modulation strategy is larger, reach To total DC bus-bar voltage 1/6, change frequency is 6 times in a carrier cycle；On the other hand, leakage current is not also provided in text Suppress the specific control program balanced with striding capacitance；
Document " Capacitor Voltage Balancing of a Five-Level ANPC Converter UsingPhase-Shifted PWM ", Kui Wang, Member, IEEE, Lie Xu, Member, IEEE, Zedong Zheng, Member,IEEE,and Yongdong Li,Member,IEEE《IEEE Transactions on PowerElectronics》, 2015,30 (3), 1147-1156 (" the five level ANPC electric capacity based on phase-shifting carrier wave modulator approach Voltage balancing control ",《IEEE journals-power electronics periodical》, the 3rd phase page 1147~1156 of volume 30 in 2015) and propose one The control method of the striding capacitance balance of voltage based on phase-shifting carrier wave is planted, the balance control of striding capacitance voltage is effectively realized System, but common-mode voltage amplitude is identical with SVPWM, reaches the 1/6 of total DC bus-bar voltage, and change frequency is 6 times, is not also had in text Provide the specific control program of drain current suppressing；
Document " A novel SVPWM scheme for common-mode voltage reduction in five- Level active NPC inverters ", Quoc Anh Le, Member, IEEE, and Dong-Choon Lee, Member,IEEE,《2015 9th International Conference on Power Electronics and ECCE Asia(ICPE-ECCE Asia)》, 2015,281-287 (" it is new that a kind of five-level active clamp powder inverter common-mode voltage suppresses Type SVPWM modulation strategies ",《9th ICPE-ECCE Asia international conference in 2015》, 2015 281-287 pages) propose one Plant common-mode voltage and suppress modulation strategy, suppression common mode voltage magnitude is the 1/12 of total DC bus-bar voltage, and change frequency is 4 times, But still have the specific control program that drain current suppressing is not provided in certain optimization space, and text yet；
To sum up, existing five-electrical level inverter control still has following problem：
1) existing modulation algorithm common-mode voltage amplitude and change frequency are larger, and amplitude maximum is the 1/6 of DC bus-bar voltage, And change frequency is to the maximum 6 times；
2) striding capacitance voltage balancing control difficulty is big；
3) analysis and effectively control are not carried out to system leakage current, and modulation strategy is realized using vector method, is calculated Complexity, is difficult Project Realization.
The content of the invention
The problem of present invention is the common-mode voltage, the striding capacitance balance of voltage and leakage current for solving five-electrical level inverter, carries A kind of carrier wave implementation method of drain current suppressing is gone out, the modulator approach that can be laminated by carrier wave is so that inverter is in whole line The amplitude of common-mode voltage is reduced to the 1/12 of total DC bus-bar voltage in sex work area, change frequency is reduced to 2 times, realizes and fly Controlled across the balance of electric capacity, while ensureing the reduction of system leakage current, method is simple, it is easy to engineer applied.
The object of the present invention is achieved like this.The invention provides a kind of three-phase five-level inverter drain current suppressing Carrier wave implementation method.
Per circuitry phase, topology is identical and is following structure for three-phase five-level inverter involved by this carrier wave implementation method：Directly It is V to flow bus total voltagedc, DC side be provided with two series connection electric capacity C1With electric capacity C2, electric capacity C1Positive pole connection inverter input Positive pole, electric capacity C1Negative pole and electric capacity C2Positive pole tie point is defined as inverter midpoint；Inverter includes 8 switching tubes per circuitry phase, That is switching tube Ski, i=1,2,3......8, k=a, b, c, wherein k represent the three-phase circuit of inverter, i.e. a phases, b phases, c phases； Switching tube Sk1, switching tube Sk5, switching tube Sk7, switching tube Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Emitter stage Connecting valve pipe Sk5Colelctor electrode, switching tube Sk5Emitter stage connecting valve pipe Sk7Colelctor electrode, switching tube Sk7Emitter stage connecting valve pipe Sk8Colelctor electrode, switching tube Sk8Emitter stage connecting valve pipe Sk6Colelctor electrode, switching tube Sk6Emitter stage connecting valve pipe Sk4Colelctor electrode； Switching tube Sk1Colelctor electrode connection electric capacity C1Positive pole, switching tube Sk4Emitter stage connection electric capacity C2Negative pole, switching tube Sk7Colelctor electrode is with opening Close pipe Sk8Launch interpolar striding capacitance C in parallelf, electric capacity CfPositive pole and switching tube Sk7Colelctor electrode is connected, switching tube Sk1Emitter stage with Paralleling switch pipe S between inverter midpointk2, switching tube Sk1Emitter stage and switching tube Sk2Colelctor electrode be connected, switching tube Sk4Colelctor electrode The paralleling switch pipe S between inverter midpointk3, switching tube Sk3Emitter stage and switching tube Sk4Colelctor electrode is connected, switching tube Sk2Emitter stage With switching tube Sk3Colelctor electrode is all connected with inverter midpoint；
This carrier wave implementation method includes the sampling to three-phase raw modulation ripple, comprises the following steps：
Step 1, sampling three-phase raw modulation ripple Va、Vb、Vc, and according to three-phase raw modulation ripple Va、Vb、VcPosition, meter Zero-sequence component V in the middle of calculating01With excessive zero-sequence component V02, it is final to determine three-phase raw modulation ripple Va、Vb、VcThe zero sequence of required superposition Component V0；
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤- 0.66)||(Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va ≤-0.33&&Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc)
Region two：Region beyond region one,
Wherein, VmaxFor three-phase raw modulation ripple Va、Vb、VcIn maximum, VminFor three-phase raw modulation ripple Va、Vb、Vc In minimum value, VmidFor three-phase raw modulation ripple Va、Vb、VcIn median , ＆＆ represent and computing, | | represent or computing；
Step 2, superposition zero-sequence component V0Obtain modulating wave V in the middle of three-phasea *、Vb *、Vc *；
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0；
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion；
Region one：If V0=V01,
△ V=Vmax1+Vmin1,
If V0=V02,
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In maximum, Vmin1For modulating wave V in the middle of three-phasea *、 Vb *、Vc *In minimum value, Vmid1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In median；
Step 4, superposition division zero-sequence component △ V obtain three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Step 5, by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" with carrier wave ratio compared with, Generate PWM ripples control inverter；Specifically include following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, and its definition is as follows with scope：
The Tri of carrier wave onek1, scope for [- 1, -0.5)；The Tri of carrier wave twok2, scope for [- 0.5,0)；The Tri of carrier wave threek3, scope For [0,0.5)；The Tri of carrier wave fourk4, scope [0.5,1]；The Tri of carrier wave fivek5, scope for [- 1, -0.5)；The Tri of carrier wave sixk6, scope For [- 0.5,0)；K=a, b, c；
Wherein, Trik1、Trik2、Trik5、Trik6Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase phase Poor 180 °；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second Individual carrier cycle is defined as T2；1 represents that switching tube is open-minded, and 0 represents switching tube shut-off；
3) by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vk", k =a, b, c；
4) by Vk'、Vk" be compared with carrier wave, and generate following pwm signal control inverter：
As 0.5≤VkDuring '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkDuring "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk=0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk=0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik6When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik6When, PWMFLk=0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik5When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik5When, PWMFLk=0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ represent with or computing；
Work as VkDuring ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3All the time For 0, Sk2, Sk4It is always 1；
As 0.5≤VkDuring '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5 It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
Relative to prior art, beneficial effects of the present invention are as follows：
1st, the common-mode voltage amplitude for effectively inhibiting five-electrical level inverter is the 1/12 of DC bus-bar voltage, and change frequency For 2 times, the reliability of system is improved；
2nd, the balance control of striding capacitance voltage is realized；
3rd, using multi-carrier modulation scheme, realize simple, it is easy to engineer applied and the leakage current for reducing system.
Brief description of the drawings：
Fig. 1 is the carrier wave implementation method schematic flow sheet of drain current suppressing proposed by the present invention.
Fig. 2 is the single-phase topological diagram of five-electrical level inverter involved in the present invention.
Fig. 3 is three-phase middle tone of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Ripple V processedk *Oscillogram.Wherein, 3a is modulating wave oscillogram in the middle of A phases, and 3b is modulating wave oscillogram in the middle of B phases, and 3c is in the middle of C phases Modulating wave oscillogram.
Fig. 4 is that three-phase amendment of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 is adjusted Ripple V processedk' and three-phase division modulating wave Vk" oscillogram, wherein, 4a is that A phases correct modulating wave and division modulating wave oscillogram, thereon Figure is that A phases correct modulating wave oscillogram, and figure below is that A phases divide modulating wave oscillogram；4b is that B phases correct modulating wave and division is modulated Ripple oscillogram, figure is that B phases correct modulating wave oscillogram thereon, and figure below is that B phases divide modulating wave oscillogram；4c is that C phases correct tune Ripple processed and division modulating wave oscillogram, figure is that C phases correct modulating wave oscillogram thereon, and figure below is that C phases divide modulating wave oscillogram.
Fig. 5 is striding capacitance electricity of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Pressure figure.
Embodiment
Three-phase five-level inverter involved in the present invention is identical per circuitry phase topology, and its single-phase topological diagram is as shown in Figure 2. Dc bus total voltage is Vdc, DC side be provided with two series connection electric capacity C1With electric capacity C2, electric capacity C1Positive pole connection inverter is defeated Enter positive pole, electric capacity C1Negative pole and electric capacity C2Positive pole tie point is defined as inverter midpoint；Opened in the every circuitry phase of inverter comprising 8 Guan Guan, i.e. switching tube Ski, i=1,2,3......8, k=a, b, c, wherein k represent the three-phase circuit of inverter, i.e. a phases, b phases, C phases；Switching tube Sk1, switching tube Sk5, switching tube Sk7, switching tube Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Hair Emitter-base bandgap grading connecting valve pipe Sk5Colelctor electrode, switching tube Sk5Emitter stage connecting valve pipe Sk7Colelctor electrode, switching tube Sk7Emitter stage connection is opened Close pipe Sk8Colelctor electrode, switching tube Sk8Emitter stage connecting valve pipe Sk6Colelctor electrode, switching tube Sk6Emitter stage connecting valve pipe Sk4Collection Electrode；Switching tube Sk1Colelctor electrode connection electric capacity C1Positive pole, switching tube Sk4Emitter stage connection electric capacity C2Negative pole, switching tube Sk7Colelctor electrode With switching tube Sk8Launch interpolar striding capacitance C in parallelf, electric capacity CfPositive pole and switching tube Sk7Colelctor electrode is connected, switching tube Sk1Transmitting Paralleling switch pipe S between pole and inverter midpointk2, switching tube Sk1Emitter stage and switching tube Sk2Colelctor electrode be connected, switching tube Sk4Collection Paralleling switch pipe S between electrode and inverter midpointk3, switching tube Sk3Emitter stage and switching tube Sk4Colelctor electrode is connected, switching tube Sk2Hair Emitter-base bandgap grading and switching tube Sk3Colelctor electrode is all connected with inverter midpoint.
The flow chart of this carrier wave implementation method such as Fig. 1.Implementation method includes the sampling to three-phase raw modulation ripple, its feature It is to comprise the following steps：
Step 1, sampling three-phase raw modulation ripple Va、Vb、Vc, and according to three-phase raw modulation ripple Va、Vb、VcPosition, meter Zero-sequence component V in the middle of calculating01With excessive zero-sequence component V02, it is final to determine three-phase raw modulation ripple Va、Vb、VcThe zero sequence of required superposition Component V0。
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤- 0.66)||(Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va ≤-0.33&&Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc),
Region two：Region beyond region one,
Wherein, VmaxFor three-phase raw modulation ripple Va、Vb、VcIn maximum, VminFor three-phase raw modulation ripple Va、Vb、Vc In minimum value, VmidFor three-phase raw modulation ripple Va、Vb、VcIn median , ＆＆ represent and computing, | | represent or computing.
Step 2, superposition zero-sequence component V0Obtain modulating wave V in the middle of three-phasea *、Vb *、Vc *。
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0
Modulating wave V in the middle of three-phase when modulation degree is 0.8k *Waveform is as shown in Figure 3.Wherein, 3a is modulating wave ripple in the middle of A phases Shape figure, 3b is modulating wave oscillogram in the middle of B phases, and 3c is modulating wave oscillogram in the middle of C phases.
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion.
Region one：If V0=V01,
△ V=Vmax1+Vmin1
If V0=V02
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In maximum, Vmin1For modulating wave V in the middle of three-phasea *、 Vb *、Vc *In minimum value, Vmid1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In median.
Step 4, superposition division zero-sequence component △ V obtain three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Three-phase amendment modulating wave V when modulation degree is 0.8k' and three-phase division modulating wave Vk" waveform is as shown in Figure 4.Wherein, 4a is that A phases correct modulating wave and division modulating wave oscillogram, and figure is that A phases correct modulating wave oscillogram thereon, and figure below is that A phases divide Modulating wave oscillogram；4b is that B phases correct modulating wave and division modulating wave oscillogram, and figure is that B phases correct modulating wave oscillogram thereon, Figure below is that B phases divide modulating wave oscillogram；4c is that C phases correct modulating wave and division modulating wave oscillogram, and figure is that C phases are corrected thereon Modulating wave oscillogram, figure below is that C phases divide modulating wave oscillogram.
Step 5, by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" with carrier wave ratio compared with, Generate PWM ripples control inverter；Specifically include following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, and its definition is as follows with scope：
The Tri of carrier wave onek1, scope for [- 1, -0.5)；The Tri of carrier wave twok2, scope for [- 0.5,0)；The Tri of carrier wave threek3, scope For [0,0.5)；The Tri of carrier wave fourk4, scope [0.5,1]；The Tri of carrier wave fivek5, scope for [- 1, -0.5)；The Tri of carrier wave sixk6, scope For [- 0.5,0)；K=a, b, c；
Wherein, Trik1、Trik2、Trik5、Trik6Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase phase Poor 180 °；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second Individual carrier cycle is defined as T2；1 represents that switching tube is open-minded, and 0 represents switching tube shut-off；
2) by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vk", k =a, b, c；
3) by Vk'、Vk" be compared with carrier wave, and generate following PWM ripples control inverter：
As 0.5≤VkDuring '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkDuring "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk=0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk=0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik6When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik6When, PWMFLk=0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik5When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik5When, PWMFLk=0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ represent with or computing.
Work as VkDuring ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3All the time For 0, Sk2, Sk4It is always 1；
As 0.5≤VkDuring '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5 It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
The MATLAB/Sinmulink simulation models of three-phase five-level inverter have been built according to algorithm proposed by the present invention, Emulation uses passive inverter, circuit parameter：Load R=10 Ω, L=1.5mH, switching frequency fc=10kHz, DC voltage Vdc= 200V, dc-link capacitance Cdc1=Cdc2=2000uF, striding capacitance Cf=1500uF, frequency of modulated wave fr=50Hz.
In MATLAB/Sinmulink, write S-Function and realize algorithm proposed by the present invention, pass through system .m texts The operation of part is verified to the carrier wave implementation method of drain current suppressing proposed by the present invention, it is found that first, in modulation Spend for 0.8 when, phase-shifting carrier wave method and SVPWM common-mode voltage amplitudes areAnd amplitude changes 6 times in a carrier cycle, altogether Mode voltage suppress modulation common-mode voltage amplitude beAmplitude changes 4 times, and the common-mode voltage amplitude for method of withdrawing deposit herein ForAmplitude only changes 2 times；Second, the implementation method of the invention that carries is with the obvious advantage in terms of drain current suppressing, stream peak of leaking electricity Peak value is only 80mA.
Fig. 5 is striding capacitance electricity of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Pressure figure, fluctuation peak-to-peak value is the 2.5% of 1.2V, only average value.

Claims (1)

1. a kind of carrier wave implementation method of three-phase five-level inverter drain current suppressing, the three-phase involved by this carrier wave implementation method Per circuitry phase, topology is identical and is following structure for five-electrical level inverter：Dc bus total voltage is Vdc, DC side is provided with two The electric capacity C of series connection1With electric capacity C2, electric capacity C1Positive pole connection inverter input positive pole, electric capacity C1Negative pole and electric capacity C2Positive pole tie point It is defined as inverter midpoint；Inverter includes 8 switching tubes, i.e. switching tube S per circuitry phaseki, i=1,2,3......8, k=a, B, c, wherein k represent the three-phase circuit of inverter, i.e. a phases, b phases, c phases；Switching tube Sk1, switching tube Sk5, switching tube Sk7, switch Pipe Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Emitter stage connecting valve pipe Sk5Colelctor electrode, switching tube Sk5Transmitting Pole connecting valve pipe Sk7Colelctor electrode, switching tube Sk7Emitter stage connecting valve pipe Sk8Colelctor electrode, switching tube Sk8Emitter stage connecting valve Pipe Sk6Colelctor electrode, switching tube Sk6Emitter stage connecting valve pipe Sk4Colelctor electrode；Switching tube Sk1Colelctor electrode connection electric capacity C1Positive pole, is opened Close pipe Sk4Emitter stage connection electric capacity C2Negative pole, switching tube Sk7Colelctor electrode and switching tube Sk8Launch interpolar striding capacitance C in parallelf, electricity Hold CfPositive pole and switching tube Sk7Colelctor electrode is connected, switching tube Sk1Paralleling switch pipe S between emitter stage and inverter midpointk2, switching tube Sk1Emitter stage and switching tube Sk2Colelctor electrode be connected, switching tube Sk4Paralleling switch pipe S between colelctor electrode and inverter midpointk3, switch Pipe Sk3Emitter stage and switching tube Sk4Colelctor electrode is connected, switching tube Sk2Emitter stage and switching tube Sk3Colelctor electrode all with inverter midpoint It is connected；
This carrier wave implementation method includes the sampling to three-phase raw modulation ripple, it is characterised in that comprise the following steps：
Step 1, sampling three-phase raw modulation ripple Va、Vb、Vc, and according to three-phase raw modulation ripple Va、Vb、VcPosition, in calculating Between zero-sequence component V01With excessive zero-sequence component V02, it is final to determine three-phase raw modulation ripple Va、Vb、VcThe zero-sequence component of required superposition V0；
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤-0.66)|| (Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va≤-0.33&& Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc),
<mrow> <msub> <mi>V</mi> <mn>01</mn> </msub> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mn>0.5</mn> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> </mrow> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> </mrow> </msub> <mo>&amp;GreaterEqual;</mo> <mn>0</mn> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>-</mo> <mn>0.5</mn> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> </mrow> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> </mrow> </msub> <mo>&lt;</mo> <mn>0</mn> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> </mrow>
<mrow> <msub> <mi>V</mi> <mn>02</mn> </msub> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mn>1</mn> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>a</mi> <mi>x</mi> </mrow> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mo>|</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>a</mi> <mi>x</mi> </mrow> </msub> <mo>|</mo> <mo>&amp;GreaterEqual;</mo> <mo>|</mo> <msub> <mi>V</mi> <mi>min</mi> </msub> <mo>|</mo> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>-</mo> <mn>1</mn> <mo>-</mo> <msub> <mi>V</mi> <mi>min</mi> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mo>|</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>a</mi> <mi>x</mi> </mrow> </msub> <mo>|</mo> <mo>&lt;</mo> <mo>|</mo> <msub> <mi>V</mi> <mi>min</mi> </msub> <mo>|</mo> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> </mrow>
<mrow> <msub> <mi>V</mi> <mn>0</mn> </msub> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <msub> <mi>V</mi> <mn>01</mn> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mo>|</mo> <msub> <mi>V</mi> <mn>01</mn> </msub> <mo>|</mo> <mo>&amp;GreaterEqual;</mo> <mo>|</mo> <msub> <mi>V</mi> <mn>02</mn> </msub> <mo>|</mo> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <msub> <mi>V</mi> <mn>02</mn> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mo>|</mo> <msub> <mi>V</mi> <mn>01</mn> </msub> <mo>|</mo> <mo>&lt;</mo> <mo>|</mo> <msub> <mi>V</mi> <mn>02</mn> </msub> <mo>|</mo> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> </mrow>
Region two：Region beyond region one,
<mrow> <msub> <mi>V</mi> <mn>0</mn> </msub> <mo>=</mo> <mo>-</mo> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> <mrow> <mo>(</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>a</mi> <mi>x</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>min</mi> </msub> <mo>)</mo> </mrow> </mrow>
Wherein, VmaxFor three-phase raw modulation ripple Va、Vb、VcIn maximum, VminFor three-phase raw modulation ripple Va、Vb、VcIn Minimum value, VmidFor three-phase raw modulation ripple Va、Vb、VcIn median , ＆＆ represent and computing, | | represent or computing；
Step 2, superposition zero-sequence component V0Obtain modulating wave V in the middle of three-phasea *、Vb *、Vc *,
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0；
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion,
Region one：If V0=V01,
△ V=Vmax1+Vmin1,
If V0=V02,
<mrow> <mi>&amp;Delta;</mi> <mi>V</mi> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mn>0.5</mn> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> <mn>1</mn> </mrow> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> <mn>1</mn> </mrow> </msub> <mo>&amp;GreaterEqual;</mo> <mn>0</mn> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>-</mo> <mn>0.5</mn> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> <mn>1</mn> </mrow> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>V</mi> <mrow> <mi>m</mi> <mi>i</mi> <mi>d</mi> <mn>1</mn> </mrow> </msub> <mo>&lt;</mo> <mn>0</mn> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> </mrow>
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In maximum, Vmin1For modulating wave V in the middle of three-phasea *、Vb *、Vc * In minimum value, Vmid1For modulating wave V in the middle of three-phasea *、Vb *、Vc *In median；
Step 4, superposition division zero-sequence component △ V obtain three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、 Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb"=0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb"=0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Step 5, by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" with carrier wave ratio compared with, generation PWM ripples control inverter；Specifically include following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, and its definition is as follows with scope：
The Tri of carrier wave onek1, scope for [- 1, -0.5)；The Tri of carrier wave twok2, scope for [- 0.5,0)；The Tri of carrier wave threek3, scope is [0,0.5)；The Tri of carrier wave fourk4, scope [0.5,1]；The Tri of carrier wave fivek5, scope for [- 1, -0.5)；The Tri of carrier wave sixk6, scope is [-0.5,0)；K=a, b, c；
Wherein, Trik1、Trik2、Trik5、Trik6Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase is differed 180°；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second carrier wave Period definition is T2；1 represents that switching tube is open-minded, and 0 represents switching tube shut-off；
3) by three-phase amendment modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vk", k=a, b,c；
4) by Vk'、Vk" be compared with carrier wave, and generate following pwm signal control inverter：
As 0.5≤VkDuring '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkDuring "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk =0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk= 0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik6When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik6When, PWMFLk =0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik5When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik5When, PWMFLk =0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ represent with or computing；
Work as VkDuring ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3It is always 0, Sk2, Sk4It is always 1；
As 0.5≤VkDuring '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7Begin It is 1, S eventuallyk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5All the time For 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7Begin It is 1, S eventuallyk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5Begin It is 0, S eventuallyk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
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