CN106787891B - Five-level inverter - Google Patents
Five-level inverter Download PDFInfo
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- CN106787891B CN106787891B CN201710128511.5A CN201710128511A CN106787891B CN 106787891 B CN106787891 B CN 106787891B CN 201710128511 A CN201710128511 A CN 201710128511A CN 106787891 B CN106787891 B CN 106787891B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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Abstract
The application discloses a five-level inverter, which comprises a three-level direct current converter and a polarity conversion circuit. The three-level direct current converter comprises a direct current source, a first capacitance switching tube, a second capacitance switching tube, a first capacitance, a second capacitance, a first level selection switching tube, a second level selection switching tube, a third level selection switching tube, a first diode and a second diode. The input end of the polarity conversion circuit is connected with the three-level direct current converter, and the output end of the polarity conversion circuit is connected with the power grid in parallel or connected with the load circuit in parallel. The maximum level in the five levels output by the five-level inverter is twice the level of a direct current source, and the utilization rate of the direct current source is very high; the three-level direct current converter can output stable levels with the same size as a direct current source, and solves the problems of unbalanced neutral point potential and lower accuracy of the output level of the five-level inverter caused by directly utilizing the charged and discharged capacitor to provide the output level in the prior art.
Description
Technical Field
The application relates to the technical field of power electronics, in particular to a five-level inverter.
Background
The multi-level inverter is power generation equipment for converting a direct-current power supply into an alternating-current power supply, and has wide application prospect in high-power application places such as photovoltaic power generation, wind power generation, new energy combined power generation and the like because the multi-level inverter can provide good large voltage and large current.
The currently widely used multilevel inverter comprises a five-level inverter, referring to fig. 1, which is a schematic diagram of a five-level inverter in the prior art, as shown in fig. 1, the existing five-level inverter is usually a neutral point clamped five-level inverter, a direct current source Vdc is connected in series with capacitors C1 and C2 with the same capacity, voltages on the capacitors C1 and C2 are Vdc/2, and a node O point between the capacitors C1 and C2 is used as a reference zero potential, namely neutral point clamping. The switching tubes T3 and T4 are connected in series, and the switching tubes T5 and T6 are connected in series and then connected to the node O respectively. The switching tubes T1, T2, T7 and T8 form an H bridge with a voltage polarity conversion function, and when other switching tubes are turned off, the switching tubes T1 and T8 are turned on or the switching tubes T2 and T7 are turned on, the output level of the inverter output to the power Grid is Vdc or-Vdc respectively. When the switching transistors T3-T6 are conducted, the absolute value of the output level of the inverter is the level of the capacitor C2, namely Vdc/2. When the H bridge is short-circuited, namely other switching tubes are turned off, the switching tubes T2 and T8 are turned on, or the switching tubes T1 and T7 are turned on, the output level of the inverter is 0.
As can be seen from the structure of the five-level inverter and the working principle thereof, when the switching transistors T3-T6 are turned on, the capacitor C2 discharges, thereby providing an inverter output level of Vdc/2, and under other on conditions, the capacitor C2 charges, and the dc source provides the inverter output level, or the H-bridge is shorted, and the inverter output level is 0. Because the capacitor C2 can generate voltage change in the charging and discharging processes, the voltage of the capacitor C2 is difficult to stably maintain at the Vdc/2 potential during discharging, and the accuracy of the output level of the existing five-level inverter is lower.
Disclosure of Invention
The application provides a five-level inverter to solve the problem that current five-level inverter output level accuracy is low.
The application provides a five-level inverter, this five-level inverter includes: a three-level DC converter and a polarity conversion circuit connected with the three-level DC converter in parallel, wherein,
the three-level direct current converter comprises a direct current source, a first capacitance switching tube and a second capacitance switching tube which are sequentially connected in series;
one end of the first capacitance switch tube, which is close to the direct current source, is connected with the positive electrode of a first diode, the negative electrode of the first diode is connected with one end of a first capacitor, and the other end of the first capacitor is connected with one end of the first capacitance switch tube, which is connected with the second capacitance switch tube;
one end of the second capacitance switch tube, which is close to the direct current source, is connected with the cathode of the second diode, the anode of the second diode is connected with one end of the second capacitor, and the other end of the second capacitor is connected with one end of the second capacitance switch tube, which is connected with the first capacitance switch tube;
if the first capacitance switch tube is conducted, the second capacitance switch tube is turned off, and if the second capacitance switch tube is conducted, the first capacitance switch tube is turned off, and the conduction time of the first capacitance switch tube and the conduction time of the second capacitance switch tube are respectively a first preset conduction time and a second preset conduction time;
one end of a first level selection switch tube is connected with the cathode of the first diode, and the other end of the first level selection switch tube is connected with the anode input end of the polarity conversion circuit;
one end of a second level selection switch tube is connected with one end of the first capacitance switch tube, which is connected with the second capacitance switch tube, and the other end of the second level selection switch tube is connected with an anode input end of the polarity conversion circuit;
one end of a third level selection switch is connected with an anode input end in the polarity conversion circuit, and the other end of the third level selection switch is respectively connected with an anode of the second diode and a cathode input end in the polarity conversion circuit;
the output end of the polarity conversion circuit is used for being connected with a power grid in parallel or connected with a load circuit in parallel.
Preferably, the first preset conduction time and the second preset conduction time are the same.
Preferably, the polarity conversion circuit comprises a first bridge arm switch tube, a second bridge arm switch tube, a third bridge arm switch tube and a fourth bridge arm switch tube, wherein the positive electrode input end of the polarity conversion circuit is respectively connected with one ends of the first bridge arm switch tube and the third bridge arm switch tube, the other ends of the first bridge arm switch tube and the third bridge arm switch tube are respectively connected with one ends of the second bridge arm switch tube and the fourth bridge arm switch tube, the other ends of the second bridge arm switch tube and the fourth bridge arm switch tube are respectively connected with the negative electrode input end of the polarity conversion circuit, one port of the output end of the polarity conversion circuit is arranged between the first bridge arm switch tube and the second bridge arm switch tube, and the other port of the output end of the polarity conversion circuit is arranged between the third bridge arm switch tube and the fourth bridge arm switch tube.
Preferably, if the first bridge arm switching tube is turned on, the fourth bridge arm switching tube is turned on, and the second and third bridge arm switching tubes are turned off;
and if the second bridge arm switching tube is conducted, the third bridge arm switching tube is conducted, and the first bridge arm switching tube and the fourth bridge arm switching tube are turned off.
Preferably, the first capacitive switch tube and the second capacitive switch tube comprise fully controlled thyristors.
Preferably, if the first level selection switch tube is turned on, the second level selection switch tube and the third level selection switch tube are turned off;
if the second level selection switch tube is turned on, the first level selection switch tube and the third level selection switch tube are turned off;
and if the third level selection switch tube is turned on, the second level selection switch tube and the first level selection switch tube are turned off.
Preferably, the second capacitor is turned on and the first capacitor is turned off according to the difference that the first capacitor voltage is larger than the second capacitor voltage is larger than a preset threshold, and the first capacitor is turned on and the second capacitor is turned off according to the difference that the first capacitor voltage is smaller than the second capacitor voltage is smaller than the preset threshold.
Preferably, the control signal modulation mode of the five-level inverter includes carrier laminated modulation, and the modulated wave of the carrier laminated modulation includes a sine wave.
Preferably, the carrier stack modulated carrier comprises a first carrier, a second carrier, a third carrier, and a fourth carrier, wherein,
the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave all comprise triangular waves, and the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave have the same amplitude, the same frequency and the same phase;
the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave are vertically stacked in the same coordinate system, and the minimum value of one carrier wave is the maximum value of the other carrier wave in two adjacent carrier waves;
the maximum value of the modulation wave is smaller than the maximum value of the first carrier wave, and the minimum value of the modulation wave is smaller than the minimum value of the fourth carrier wave.
The beneficial effects of the five-level inverter that this application provided include:
the five-level inverter comprises a three-level direct current converter and a polarity conversion circuit. The three-level direct current converter comprises a direct current source, a first capacitance switching tube, a second capacitance switching tube, a first capacitance, a second capacitance, a first level selection switching tube, a second level selection switching tube, a third level selection switching tube, a first diode and a second diode. The first capacitor and the second capacitor can respectively output the same level as the direct current source in size by controlling the conduction of the first capacitor switch tube and the second capacitor switch tube, the three-level direct current converter can respectively output the same level as the direct current source in size, the level twice as large as the direct current source in size and the zero level by utilizing the first level selection switch tube, the second level selection switch tube and the third level selection switch tube, and the polarity conversion circuit can be utilized to realize the conversion of the polarity of the output level of the three-level direct current converter, so that the five-level inverter provided by the application can output five levels. The maximum level in the five levels output by the five-level inverter is twice the level of a direct current source, and the utilization rate of the direct current source is very high; the three-level direct-current converter can output stable levels which are the same as the direct-current source in size by controlling the conduction of the first capacitance switching tube and the second capacitance switching tube, and the problem that the accuracy of the output level of the five-level inverter is lower due to the fact that the output level is provided by directly utilizing the charged and discharged capacitors in the prior art is solved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of a five-level inverter in the prior art;
fig. 2 is a schematic structural diagram of a five-level inverter according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a neutral-point potential balance control structure according to an embodiment of the present disclosure;
fig. 4 is an equivalent circuit schematic diagram of a five-level inverter according to an embodiment of the present disclosure;
fig. 5 is a schematic carrier stacked modulation diagram of a five-level inverter according to an embodiment of the present disclosure;
fig. 6 is a truth table of output of a level selection switch tube and a comparator in a five-level inverter according to an embodiment of the present application.
Detailed Description
Referring to fig. 2, a schematic structural diagram of a five-level inverter according to an embodiment of the present application is provided. As shown in fig. 2, the five-level inverter provided in the embodiment of the present application includes a three-level dc converter and a polarity conversion circuit connected in parallel with the three-level dc converter, where the three-level dc converter includes a dc source and a first capacitive switching tube Q connected in series in sequence 1 And a second capacitance switch tube Q 2 。
Specifically, a first capacitive switch tube Q 1 One end of the medium direct current source is connected with the first diode T 1 Is connected with the positive electrode of the first diode T 1 And the negative electrode of (C) and the first capacitor C 1 Is connected with one end of a first capacitor C 1 The other end of (2) is connected with a first capacitance switch tube Q 1 The middle is connected with a second capacitance switch tube Q 2 Is connected to one end of the connecting rod.
Second capacitance switch tube Q 2 One end of the capacitor close to the direct current source is connected with a second diode T 2 Is connected with the negative pole of the second diode T 2 Positive electrode of (C) and second capacitor C 2 Is connected with one end of a second capacitor C 2 And the other end of the second capacitance switch tube Q 2 Is connected with a first capacitance switch tube Q 1 Is connected to one end of the connecting rod.
First level selection switch tube S 2 One end of (a) is connected with the first diode T 2 The other end of the circuit is connected with the positive electrode input end of the polarity conversion circuit. Second level selection switch tube S 1 One end of (1) is connected with a first capacitance switch tube Q 1 The middle is connected with a second capacitance switch tube Q 1 One end of the power supply is connected with the other end of the power supply, and the other end of the power supply is connected with the input end of the positive electrode in the polarity conversion circuit. Third level selection switch S 0 One end of the first diode is connected with the positive electrode input end of the polarity conversion circuit, and the other end is respectively connected with the second diode T 2 The positive electrode of the (a) is connected with the negative electrode input end of the polarity conversion circuit. The output end of the polarity conversion circuit is used for being connected with the power grid in parallel or connected with the load circuit in parallel.
The polarity conversion circuit comprises a first bridge arm switch tube H 1 Second bridge arm switch tube H 2 Third bridge arm switch tube H 3 And a fourth bridge arm switch tube H 4 The positive input end of the polarity conversion circuit is respectively connected with the first bridge arm switch tube H 1 Third bridge arm switch tube H 3 Is connected with one end of a first bridge arm switch tube H 1 Third bridge arm switch tube H 3 The other end of (a) is respectively connected with a second bridge arm switch tube H 2 Fourth bridge arm switching tube H 4 One end of the second bridge arm switch tube H is connected with 2 Fourth bridge arm switching tube H 4 The other end of the first bridge arm switch tube is connected with the negative electrode input end of the polarity conversion circuit, and one port of the output end of the polarity conversion circuit is arranged on the first bridge arm switch tube H 1 Second bridge arm switch tube H 2 Another port is arranged at the third bridge arm switch tube H 3 Fourth bridge arm switching tube H 4 Between them.
In the embodiment of the present application, the first capacitor C 1 And a second capacitor C 2 Selecting capacitors with equal capacitance values, and switching the first capacitor to the transistor Q 1 Second capacitance switch tube Q 2 First level selection switch tube S 2 Second level selection switch tube S 1 Third level selection switch tube S 0 First bridge arm switching tube H 1 Second bridge arm switch tube H 2 Third bridge arm switch tube H 3 And a fourth bridge arm switch tube H 4 The fully controlled thyristors can be selected, and can be specifically a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, electric field effect transistor) or an IGBT (Insulated Gate Bipolar Transistor ).
In the five-level inverter provided in the embodiment of the present application, the voltage of the dc source is V in First capacitor C 1 The voltage value of (2) is V c1 Second capacitor C 2 The voltage value of (2) is V c2 . If the first capacitance is a switch tube Q 1 On, the second capacitance switch tube Q 2 Turn off if the second capacitance switch tube Q 2 On, the first capacitance switch tube Q 1 Turn off, i.e. the first capacitive switch Q 1 And a second capacitance switch tube Q 2 Alternately conducting, when the first capacitance switch tube Q 1 When conducting, the second capacitor C 2 Charging is performed when the second capacitance switch tube Q 2 When conducting, the first capacitor C 1 Charging is performed. First capacitance switch tube Q 1 The conduction time of the capacitor is a first preset conduction time, a second capacitor switch tube Q 2 The conduction time of the capacitor is the second preset conduction time, and the first preset conduction time is the same as the second preset conduction time, namely the first capacitor switch tube Q 1 And a second capacitance switch tube Q 2 The on duty ratio is 0.5, then V c1 ＝V c2 ＝V in Thereby realizing the first capacitance C 1 And a second capacitor C 2 And the midpoint potential is balanced, so that the accuracy of the output level is improved.
Further, when the first capacitance switch tube Q 1 And a second capacitance switch tube Q 2 When the on-duty ratios are all 0.5, the firstCapacitor C 1 And a second capacitor C 2 Is liable to have a certain difference due to the first capacitance voltage V c1 And a second capacitance switch tube Q 2 Positive correlation of the on-time of the second capacitor voltage V c2 And a first capacitance switch tube Q 1 By acquiring and comparing the first capacitor voltage V in real time c1 And a second capacitance voltage V c2 The comparison result is used for correcting the distribution ratio of the first preset conduction time and the second preset conduction time in the next period, so that the balance of the midpoint potential can be further improved. Referring to fig. 3, a schematic diagram of a neutral-point potential balance control structure is provided in an embodiment of the present application. As shown in fig. 3, by setting the first capacitance voltage V c1 And a second capacitance voltage V c2 A preset threshold h of the difference Deltaepsilon, if the first capacitance voltage V c1 And a second capacitance voltage V c2 If the difference delta epsilon exceeds the preset threshold h, locking the duty ratio with the falling value of 0.5, and using a hysteresis comparator to switch the first capacitance switch tube Q 1 And a second capacitance switch tube Q 2 The trigger signal of (1) is specifically that the second capacitance switch tube Q is turned on according to the difference delta epsilon of the first capacitance voltage larger than the second capacitance voltage larger than the preset threshold h and the hysteresis comparator output being 1 2 Turning off the first capacitance switching tube Q 1 Realizing a first capacitance C 1 Multiple discharge, second capacitor C 2 Multiple charges according to the first capacitance voltage V c1 Less than the second capacitance voltage V c2 The difference delta epsilon of the voltage difference is smaller than a preset threshold h, the output of the hysteresis comparator is 1, and the first capacitance switching tube Q is conducted 1 Turning off the second capacitance switch Q 2 Realizing a first capacitance C 1 Multiple charging, second capacitor C 2 And multiple discharges are carried out to gradually reach voltage balance. After the hysteresis comparator is used for adjusting, if the first capacitor voltage V c1 And a second capacitance voltage V c2 If the difference delta epsilon is smaller than the preset threshold h, locking the hysteresis comparator, and reusing the trigger signal with the duty ratio of 0.5 for the first capacitance switch tube Q 1 And a second capacitance switch tube Q 2 And controlling.
The five-level inverter provided by the application has 12 working modes in total, when V c1 ＝V c2 At the time, a first capacitor C 1 A second capacitor C 2 The equivalent is a direct-current voltage source, 12 working modes are simplified to 6, and referring to fig. 4, an equivalent circuit schematic diagram of the five-level inverter is provided in the embodiment of the application. As shown in fig. 4, a first level selection switch tube S 2 Second level selection switch tube S 1 And a third level selection switch tube S 0 Are not turned on at the same time. If the first level selects the switching tube S 2 On, the second level selection switch tube S 1 And a third level selection switch tube S 0 Turn-off, output level V of three-level DC converter h ＝V c1 +V c2 ＝2V in . If the second level selects the switch tube S 1 On, the first level selection switch tube S 2 And a third level selection switch tube S 0 Turn-off, output level V of three-level DC converter h ＝V c2 =vin. If the third level selects the switch tube S 0 On, the second level selection switch tube S 1 And a first level selection switch tube S 2 Turn-off, output level V of three-level DC converter h ＝0。
Further, in the polarity conversion circuit, if the first bridge arm switch tube H 1 On, the fourth bridge arm switch tube H 4 Conduction, second bridge arm switch tube H 2 Third bridge arm switch tube H 3 Turning off, wherein the output polarity of the polarity conversion circuit is positive; if the second bridge arm switch tube H 2 On, the third bridge arm switch tube H 3 Conduction is carried out, and the first bridge arm switch tube H 1 Fourth bridge arm switching tube H 4 At this time, the output polarity of the polarity conversion circuit is negative.
Defining a first level selection switch tube S 2 Second level selection switch tube S 1 And a third level selection switch tube S 0 Is a switching function S of i As shown in formula (1):
the same applies to obtain a first bridge arm switch tube H 1 Second bridge arm switch tube H 2 Third bridge arm switch tube H 3 And a fourth bridge arm switch tube H 4 Is a switching function H of j As defined in formula (2):
ignoring the five-level inverter output current i o In combination with the formulas (1), (2) and the above, the 6 operation modes of the five-level inverter can be unified as a logic expression (3):
|U|＝V h ＝i(S i ＝1,i＝0,1,2) (3)
if consider the output current i of the five-level inverter o The direction, then 6 working modes can be unified into logical expression (4):
in summary, the first capacitive switch tube Q 1 Second capacitance switch tube Q 2 The first capacitor voltage V is determined by the on-time of the first preset on-time and the second preset on-time c1 And a second capacitance voltage V c2 Switching function S i Determining the output level V of a three-level DC converter h Switching function H j The frequency and initial phase of the five-level inverter output waveform are controlled. In the implementation of the application, a first capacitance switch tube Q 1 Second capacitance switch tube Q 2 And a switching function S i Switching function H j Separately and independently controlled, switch function S i And a switching function H j The frequency and phase of (a) need to be synchronized.
In the embodiment of the application, the modulation of the inverter is the process of generating the inverter control signal PWM wave. Switching function S i And a switching function H j The modulation mode of the control signal PWM wave of (1) comprises carrier laminated modulation, the carrier laminated modulation wave comprises sine wave, the carrier comprises a first carrier,A second carrier, a third carrier, and a fourth carrier. Referring to fig. 5, a carrier stack modulation schematic diagram of a five-level inverter is provided in an embodiment of the present application. As shown in fig. 5, the first carrier, the second carrier, the third carrier, and the fourth carrier have the same amplitude, the same frequency, and the same phase. The first carrier, the second carrier, the third carrier and the fourth carrier are stacked up and down in the same coordinate system, and the minimum value of one carrier is the maximum value of the other carrier in two adjacent carriers. The maximum value of the modulation wave is smaller than the maximum value of the first carrier wave, and the minimum value of the modulation wave is smaller than the minimum value of the fourth carrier wave.
Specifically, the first carrier, the second carrier, the third carrier and the fourth carrier divide the coordinate plane into 5 areas, compare the modulated waves with the first carrier, the second carrier, the third carrier and the fourth carrier respectively, and sequentially correspond to five levels of the output level U from bottom to top: -2, -1, 0, +1, +2. By combining (1) and (4), the switching function S under carrier laminated modulation can be obtained i And a switching function H j Is a waveform of (a).
The comparator output for generating PWM waves when the modulation wave is larger than the carrier wave is defined as 1, and the waveform in FIG. 5 can be converted into a switching function S i The logic relationship between the outputs of the four PWM comparators (carriers) Mi (i=1, 2,3, 4) is shown in fig. 6, which is a truth table of the level selection switching tube and the comparator output in the five-level inverter provided in the embodiment of the present application.
The switch function S can be obtained by using the Calo diagram simplification i The modulation of the five-level inverter can be realized by the logic relation with the output of the PWM comparator, as shown in the formula (7):
the on-off signals of the three level selection switch tubes are generated by carrier wave lamination, three levels of 0, +1 and +2 are generated, then the on-off signals with the same frequency as the carrier wave are input to the H bridge, the H bridge is utilized to adjust the positive and negative of the signals, and five levels can be obtained: -2, -1, 0, +1, +2. When the carrier wave lamination modulation is applied to the five-level inverter for simulation, the alternating voltage waveform generated by inversion is stable, and the harmonic distortion rate is low.
As can be seen from the above embodiments, in the five-level inverter provided by the present application, the maximum level of the output five levels is twice the level of the direct current source, and the utilization rate of the direct current source is very high; the three-level direct-current converter can output stable levels which are the same as the direct-current source in size by controlling the conduction of the first capacitance switching tube and the second capacitance switching tube, the problem that the five-level inverter is low in output level accuracy due to the fact that the output level is provided by directly utilizing the charged and discharged capacitor in the prior art is solved, and the balance of the midpoint potential is high.
The embodiments of the present invention described above do not limit the scope of the present invention.
Claims (9)
1. A five-level inverter is characterized by comprising a three-level direct current converter and a polarity conversion circuit connected with the three-level direct current converter in parallel, wherein,
the three-level direct current converter comprises a direct current source, a first capacitance switching tube and a second capacitance switching tube which are sequentially connected in series;
one end of the first capacitance switch tube, which is close to the direct current source, is connected with the positive electrode of a first diode, the negative electrode of the first diode is connected with one end of a first capacitor, and the other end of the first capacitor is connected with one end of the first capacitance switch tube, which is connected with the second capacitance switch tube;
one end of the second capacitance switch tube, which is close to the direct current source, is connected with the cathode of the second diode, the anode of the second diode is connected with one end of the second capacitor, and the other end of the second capacitor is connected with one end of the second capacitance switch tube, which is connected with the first capacitance switch tube;
if the first capacitance switch tube is conducted, the second capacitance switch tube is turned off, and if the second capacitance switch tube is conducted, the first capacitance switch tube is turned off, and the conduction time of the first capacitance switch tube and the conduction time of the second capacitance switch tube are respectively a first preset conduction time and a second preset conduction time;
one end of a first level selection switch tube is connected with the cathode of the first diode, and the other end of the first level selection switch tube is connected with the anode input end of the polarity conversion circuit;
one end of a second level selection switch tube is connected with one end of the first capacitance switch tube, which is connected with the second capacitance switch tube, and the other end of the second level selection switch tube is connected with an anode input end of the polarity conversion circuit;
one end of a third level selection switch is connected with an anode input end in the polarity conversion circuit, and the other end of the third level selection switch is respectively connected with an anode of the second diode and a cathode input end in the polarity conversion circuit;
the output end of the polarity conversion circuit is used for being connected with a power grid in parallel or connected with a load circuit in parallel.
2. The five-level inverter of claim 1, wherein the first preset on-time and the second preset on-time are the same.
3. The five-level inverter of claim 1, wherein the polarity conversion circuit comprises a first bridge arm switch tube, a second bridge arm switch tube, a third bridge arm switch tube and a fourth bridge arm switch tube, wherein an anode input end in the polarity conversion circuit is respectively connected with one ends of the first bridge arm switch tube and the third bridge arm switch tube, the other ends of the first bridge arm switch tube and the third bridge arm switch tube are respectively connected with one ends of the second bridge arm switch tube and the fourth bridge arm switch tube, the other ends of the second bridge arm switch tube and the fourth bridge arm switch tube are respectively connected with a cathode input end in the polarity conversion circuit, and one port of an output end in the polarity conversion circuit is arranged between the first bridge arm switch tube and the second bridge arm switch tube, and the other port is arranged between the third bridge arm switch tube and the fourth bridge arm switch tube.
4. The five-level inverter of claim 3,
if the first bridge arm switching tube is conducted, the fourth bridge arm switching tube is conducted, and the second bridge arm switching tube and the third bridge arm switching tube are turned off;
and if the second bridge arm switching tube is conducted, the third bridge arm switching tube is conducted, and the first bridge arm switching tube and the fourth bridge arm switching tube are turned off.
5. The five-level inverter of claim 1, wherein the first capacitive switching tube and the second capacitive switching tube comprise fully controlled thyristors.
6. The five-level inverter of claim 1,
if the first level selection switch tube is turned on, the second level selection switch tube and the third level selection switch tube are turned off;
if the second level selection switch tube is turned on, the first level selection switch tube and the third level selection switch tube are turned off;
and if the third level selection switch tube is turned on, the second level selection switch tube and the first level selection switch tube are turned off.
7. The five-level inverter of claim 1, wherein the second capacitor is turned on and the first capacitor is turned off according to a difference between the first capacitor voltage and the second capacitor voltage being greater than a preset threshold, and the first capacitor is turned on and the second capacitor is turned off according to a difference between the first capacitor voltage and the second capacitor voltage being greater than a preset threshold.
8. The five-level inverter of claim 1, wherein the control signal modulation scheme of the five-level inverter comprises carrier stack modulation, the modulated wave of the carrier stack modulation comprising a sine wave.
9. The five-level inverter of claim 8, wherein the carrier stack modulated carrier comprises a first carrier, a second carrier, a third carrier, and a fourth carrier, wherein,
the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave all comprise triangular waves, and the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave have the same amplitude, the same frequency and the same phase;
the first carrier wave, the second carrier wave, the third carrier wave and the fourth carrier wave are vertically stacked in the same coordinate system, and the minimum value of one carrier wave is the maximum value of the other carrier wave in two adjacent carrier waves;
the maximum value of the modulation wave is smaller than the maximum value of the first carrier wave, and the minimum value of the modulation wave is larger than the minimum value of the fourth carrier wave.
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