CN105262356B - A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage - Google Patents
A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage Download PDFInfo
- Publication number
- CN105262356B CN105262356B CN201510621195.6A CN201510621195A CN105262356B CN 105262356 B CN105262356 B CN 105262356B CN 201510621195 A CN201510621195 A CN 201510621195A CN 105262356 B CN105262356 B CN 105262356B
- Authority
- CN
- China
- Prior art keywords
- signal
- comparator
- drive signal
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Inverter Devices (AREA)
Abstract
The invention discloses a kind of five Level Full Bridges combining inverter input capacitance from method for equalizing voltage, belong to convertor controls technical field.This method changes the amplitude of modulation wave signal or triangle carrier signal, realizes pressing naturally for input capacitance voltage according to the change of five Level Full Bridge combining inverter modulation ratios.It is beneficial in that：Only need the total input voltage of sampling that pressing naturally for derided capacitors can be achieved, save one group of capacitance voltage sample circuit, control circuit cost is low；The control loop that capacitance voltage is pressed is eliminated, control program is simplified.This method is applied to a variety of five Level Full Bridges combining inverters topology, is had broad application prospects in new energy grid-connected power field.
Description
Technical field
The present invention relates to a kind of five Level Full Bridges combining inverter input capacitance from method for equalizing voltage, belong to Technics of Power Electronic Conversion
Device control technology field.
Background technology
As energy crisis and problem of environmental pollution are increasingly serious, the generation of electricity by new energy skill such as solar energy, wind energy, fuel cell
Art turns into the focus that countries in the world are paid close attention to and studied.Grid-connected power generation system is connected according to whether with public electric wire net, is divided into grid-connected
Operation and independent operating two ways, wherein, it is that most common mode, and combining inverter are applied in generation of electricity by new energy to be incorporated into the power networks
As the critical component in new energy grid connection system, its reliability, efficiency and power density are improved significant.
Dual buck inverter has the advantages that reliability is high, separate diode afterflow, but its filter inductance half period
Work, therefore power density is relatively low.Multilevel converter can reduce the voltage ladder of switching tube and filter inductance, therefore in same inductance
Under conditions of current ripples and power, relative to three Level Full Bridge combining inverters, five Level Full Bridge combining inverters can be by
Inductance volume reduces half.But, because input side is connected using derided capacitors, therefore in the range of certain modulation ratio, input
Derided capacitors voltage can voltage un-balance.
With reference to the input capacitance method for equalizing voltage of traditional single phase half-bridge three-level inverter, as shown in figure 1, five Level Full Bridges are simultaneously
The mode that net inverter can be biased according to the voltage difference adjustment current reference signal of input derided capacitors realizes capacitor voltage equalizing, but
This method needs two input capacitance voltages of sampling simultaneously, increases circuit cost, control program and modulator approach are all more multiple
It is miscellaneous, need improvement badly.
The content of the invention
To solve the deficiencies in the prior art, it is an object of the invention to provide a kind of input of five Level Full Bridges combining inverter
Electric capacity is from method for equalizing voltage.
In order to realize above-mentioned target, the present invention is adopted the following technical scheme that：
As the specific embodiment of the present invention, five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage, institute
The full-bridge grid-connected inverter used includes dc source Udc, input derided capacitors, five Level Full Bridge inverter circuits, first output filter
Ripple inductance Lf1, the second output inductor Lf2With output filter capacitor Cf, the control circuit part bag of the full-bridge grid-connected inverter
Control circuit and modulation circuit are included, the control circuit includes current sensor, the first subtracter and inductive current adjuster, institute
Modulation circuit is stated including first comparator, the second comparator, the 3rd comparator, the 4th comparator, the 5th comparator, the 6th to compare
Device, the first drive circuit, the second drive circuit, the 3rd drive circuit, the 4th drive circuit, the 5th drive circuit, the 6th driving
Circuit, the second subtracter, the 3rd subtracter, the first multiplier, the second multiplier and a phase inverter；
The five Level Full Bridges combining inverter input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current iLObtain inductor current feedback signal iLf, inductor current feedback signal iLf
It is connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal i of the first subtracterLr, first subtracts
The output end of musical instruments used in a Buddhist or Taoist mass obtains modulated signal u by inductive current adjustere, modulated signal ueIt is just defeated with the second subtracter respectively
Enter the input connection of end, an input of the first multiplier, the in-phase end of the 5th comparator and phase inverter, phase inverter output
End-uePositive input terminal, an input of the second multiplier, the in-phase end of the 6th comparator respectively with the 3rd subtracter connects
Connect；
DC bias signal ubIt is connected with the negative input end of the second subtracter, the output end connection first of the second subtracter is compared
Compared with the in-phase end of device, the end of oppisite phase connection triangle carrier signal u of first comparatorst, the output of first comparator is by the first drive
Dynamic circuit obtains first switch pipe drive signal ugs1；
DC bias signal ubIt is connected with the negative input end of the 3rd subtracter, the output end connection second of the 3rd subtracter is compared
Compared with the in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the second comparatorst, the output of the second comparator is by the second drive
Dynamic circuit obtains second switch pipe drive signal ugs2；
Another input connection scaling signal k of first multiplier, the output end connection the 3rd of the first multiplier is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the 3rd comparatorst, the output of the 3rd comparator is by the 3rd driving
Circuit obtains the 3rd switching tube drive signal ugs3；
Another input connection scaling signal k of second multiplier, the output end connection the 4th of the second multiplier is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the 4th comparatorst, the output of the 4th comparator is by the 4th driving
Circuit obtains the 4th switching tube drive signal ugs4；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th by the 5th drive circuit
Switching tube drive signal ugs5；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th by the 6th drive circuit
Switching tube drive signal ugs6。
Preferably, foregoing DC bias signal ubAmplitude be equal to triangle carrier signal ustPeak value；When five Level Full Bridges
When the modulation ratio of combining inverter is more than 0.55, the scaling signal k=1, when the modulation ratio of five Level Full Bridge combining inverters
During less than 0.55, the scaling signal k values>0 and<1.
As the present invention another specific embodiment, five Level Full Bridge combining inverter input capacitances from method for equalizing voltage,
The full-bridge grid-connected inverter used includes dc source Udc, input derided capacitors, five Level Full Bridge inverter circuits, first output
Filter inductance Lf1, the second output inductor Lf2With output filter capacitor Cf, the control circuit part of the full-bridge grid-connected inverter
Including control circuit and modulation circuit, the control circuit includes current sensor, the first subtracter and inductive current adjuster,
The modulation circuit includes first comparator, the second comparator, the 3rd comparator, the 4th comparator, the 5th comparator, the 6th ratio
Driven compared with device, the first drive circuit, the second drive circuit, the 3rd drive circuit, the 4th drive circuit, the 5th drive circuit, the 6th
Dynamic circuit, first adder, second adder, the first multiplier, the second multiplier and a phase inverter；
The five Level Full Bridges combining inverter input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current iLObtain inductor current feedback signal iLf, inductor current feedback signal iLf
It is connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal i of the first subtracterLr, first subtracts
The output end of musical instruments used in a Buddhist or Taoist mass obtains modulated signal u by inductive current adjustere, modulated signal ueRespectively with the same phase of first comparator
The input connection at end, the in-phase end of the 3rd comparator, the in-phase end of the 5th comparator and phase inverter, inverter output-ue
In-phase end, the in-phase end of the 4th comparator, the in-phase end of the 6th comparator respectively with the second comparator is connected；
Triangle carrier signal ustAn input respectively with first adder, an input of the first multiplier,
The input connection of the input, second adder of paired multiplier；
DC bias signal ubIt is connected with another input of first adder, the output end of first adder connection the
The end of oppisite phase of one comparator, the output of first comparator obtains first switch pipe drive signal u by the first drive circuitgs1；
DC bias signal ubIt is connected with another input of second adder, the output end of second adder connection the
The end of oppisite phase of two comparators, the output of the second comparator obtains second switch pipe drive signal u by the second drive circuitgs2；
Another input connection scaling signal k of first multiplier, the output end connection the 3rd of the first multiplier is compared
The end of oppisite phase of device, the output of the 3rd comparator obtains the 3rd switching tube drive signal u by the 3rd drive circuitgs3；
Another input connection scaling signal k of second multiplier, the output end connection the 4th of the second multiplier is compared
The end of oppisite phase of device, the output of the 4th comparator obtains the 4th switching tube drive signal u by the 4th drive circuitgs4；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th by the 5th drive circuit
Switching tube drive signal ugs5；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th by the 6th drive circuit
Switching tube drive signal ugs6。
Preferably, foregoing DC bias signal ubAmplitude be equal to triangle carrier signal ustPeak value；When five Level Full Bridges
When the modulation ratio of combining inverter is more than 0.55, the scaling signal k=1, when the modulation ratio of five Level Full Bridge combining inverters
During less than 0.55, the scaling signal k values>1 and<2.
Further, when the modulation ratio of five Level Full Bridge combining inverters is more than 0.55, line voltage ugPositive half cycle and
More than dc source UdcVoltage magnitude half, first switch pipe drive signal ugs1High frequency mo, the 3rd switching tube drive signal
ugs3Grow tall, line voltage ugNegative half period and absolute value are more than dc source UdcVoltage magnitude half, second switch pipe drive signal
ugs2High frequency mo, the 4th switching tube drive signal ugs4Grow tall；When the modulation ratio of five Level Full Bridge combining inverters is less than 0.55
When, line voltage ugPositive half cycle and more than dc source UdcVoltage magnitude half, first switch pipe drive signal ugs1Opened with the 3rd
Close pipe drive signal ugs3It is high frequency mo, and the 3rd switching tube drive signal ugs3Dutycycle is more than first switch pipe and drives letter
Number ugs1, line voltage ugNegative half period and absolute value are more than dc source UdcVoltage magnitude half, second switch pipe drive signal
ugs2With the 4th switching tube drive signal ugs4It is high frequency mo, and the 4th switching tube drive signal ugs4Dutycycle is more than second
Switching tube drive signal ugs2。
The present invention is advantageous in that the present invention's only needs total input voltage i.e. achievable point of sampling from method for equalizing voltage
Pressing naturally for voltage capacitance, saves one group of capacitance voltage sample circuit, can effectively control circuit cost；Meanwhile, eliminate
The control loop that capacitance voltage is pressed, so that control program is simplified, moreover, should be simple from method for equalizing voltage modulator approach, it is easy to
DSP is realized.
Brief description of the drawings
Fig. 1 is traditional pressure equalizing control method；
Fig. 2 is a kind of electricity of five Level Full Bridges combining inverter input capacitance of the invention from the embodiment 1 of method for equalizing voltage
Line structure schematic diagram；
Fig. 3 (a) and Fig. 3 (b) are the driving principle oscillograms of embodiment 1；
Fig. 4 is a kind of electricity of five Level Full Bridges combining inverter input capacitance of the invention from the embodiment 2 of method for equalizing voltage
Line structure schematic diagram；
Fig. 5 (a) and Fig. 5 (b) are the driving principle oscillograms of embodiment 2；
Fig. 6 (a), Fig. 6 (b) and Fig. 6 (c) apply to three kind of five Level Full Bridge combining inverter circuit topology of the present invention
Embodiment；
Fig. 7 is a kind of simulation result figure of five Level Full Bridges combining inverter input capacitance of the invention from method for equalizing voltage.
Embodiment
Make specific introduce to the present invention below in conjunction with the drawings and specific embodiments.
Embodiment 1
Referring to Fig. 2, the five Level Full Bridge combining inverter input capacitances of the present embodiment are from method for equalizing voltage, the full-bridge used
Combining inverter includes dc source Udc, input derided capacitors 1, five Level Full Bridge inverter circuits 2, the first output inductor
Lf1, the second output inductor Lf2With output filter capacitor Cf, the control circuit part of the full-bridge grid-connected inverter is including controlling
Circuit 3 and modulation circuit 4, wherein control circuit 3 specifically includes current sensor, the first subtracter and inductive current adjuster,
Modulation circuit 4 compares including first comparator, the second comparator, the 3rd comparator, the 4th comparator, the 5th comparator, the 6th
Device, the first drive circuit, the second drive circuit, the 3rd drive circuit, the 4th drive circuit, the 5th drive circuit, the 6th driving
Circuit, the second subtracter, the 3rd subtracter, the first multiplier, the second multiplier and a phase inverter.
The five Level Full Bridges combining inverter input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current iLObtain inductor current feedback signal iLf, inductor current feedback signal iLf
It is connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal i of the first subtracterLr, first subtracts
The output end of musical instruments used in a Buddhist or Taoist mass obtains modulated signal u by inductive current adjustere, modulated signal ueIt is just defeated with the second subtracter respectively
Enter the input connection of end, an input of the first multiplier, the in-phase end of the 5th comparator and phase inverter, phase inverter output
End-uePositive input terminal, an input of the second multiplier, the in-phase end of the 6th comparator respectively with the 3rd subtracter connects
Connect；
DC bias signal ubIt is connected with the negative input end of the second subtracter, the output end connection first of the second subtracter is compared
Compared with the in-phase end of device, the end of oppisite phase connection triangle carrier signal u of first comparatorst, the output of first comparator is by the first drive
Dynamic circuit obtains first switch pipe drive signal ugs1；
DC bias signal ubIt is connected with the negative input end of the 3rd subtracter, the output end connection second of the 3rd subtracter is compared
Compared with the in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the second comparatorst, the output of the second comparator is by the second drive
Dynamic circuit obtains second switch pipe drive signal ugs2；
Another input connection scaling signal k of first multiplier, the output end connection the 3rd of the first multiplier is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the 3rd comparatorst, the output of the 3rd comparator is by the 3rd driving
Circuit obtains the 3rd switching tube drive signal ugs3；
Another input connection scaling signal k of second multiplier, the output end connection the 4th of the second multiplier is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal u of the 4th comparatorst, the output of the 4th comparator is by the 4th driving
Circuit obtains the 4th switching tube drive signal ugs4；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th by the 5th drive circuit
Switching tube drive signal ugs5；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th by the 6th drive circuit
Switching tube drive signal ugs6。
Fig. 3 is the driving principle oscillogram of embodiment 1, in figure, ugs1To ugs6Represent the first to the 6th power switch tube S1
~S6Drive signal, ustRepresent triangle carrier signal, ueRepresent modulation wave signal, ubDC offset voltage is represented, equal to triangle
Carrier peak value, k represents proportionality coefficient.
When the modulation ratio of five Level Full Bridge combining inverters is more than 0.55, driving principle waveform such as Fig. 3 of embodiment 1
(a) shown in, proportionality coefficient k values are 1.
The positive half cycle of line voltage, line voltage ugMore than dc source UdcDuring the half of voltage magnitude, the first power switch
Pipe S1By Unipolar SPWM mode high frequency mo, modulation wave signal ue-ubAmplitude is more than carrier signal ustHigh electricity is exported during amplitude
It is flat, on the contrary output low level；3rd power switch tube S3With the 5th power switch tube S5It is long logical, other power switch tube drives letters
Number it is low level.
The positive half cycle of line voltage, line voltage ugLess than dc source UdcDuring the half of voltage magnitude, the 3rd power switch
Pipe S3By Unipolar SPWM mode high frequency mo, modulation wave signal kueAmplitude is more than carrier signal ustHigh level is exported during amplitude,
Otherwise output low level；5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
Line voltage negative half period, line voltage ugAbsolute value be more than dc source UdcDuring the half of voltage magnitude, second
Power switch tube S2By Unipolar SPWM mode high frequency mo, modulation wave signal-(ue-ub) amplitude be more than carrier signal ustAmplitude
When export high level, otherwise output low level；4th power switch tube S4With the 6th power switch tube S6Long logical, other power are opened
It is low level to close pipe drive signal.
Line voltage negative half period, line voltage ugAbsolute value be less than dc source UdcDuring the half of voltage magnitude, the 4th
Power switch tube S4By Unipolar SPWM mode high frequency mo, modulation wave signal-kueAmplitude is more than carrier signal ustIt is defeated during amplitude
Go out high level, on the contrary output low level；6th power switch tube S6Long logical, other driving signal of power switching tube are low electricity
It is flat.
When the modulation ratio of five Level Full Bridge combining inverters is less than 0.55, driving principle waveform such as Fig. 3 (b) of embodiment 1
Shown, proportionality coefficient k values are>0 and<1.
The positive half cycle of line voltage, line voltage ugMore than dc source UdcDuring the half of voltage magnitude, the first power switch
Pipe S1By Unipolar SPWM mode high frequency mo, modulation wave signal ue-ubAmplitude is more than carrier signal ustHigh electricity is exported during amplitude
It is flat, on the contrary output low level；3rd power switch tube S3By Unipolar SPWM mode high frequency mo, modulation wave signal kueAmplitude is big
In carrier signal ustHigh level is exported during amplitude, on the contrary output low level；3rd power switch tube S3Dutycycle be more than first
Power switch tube S1Dutycycle.5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
The positive half cycle of line voltage, line voltage ugLess than dc source UdcDuring the half of voltage magnitude, the 3rd power switch
Pipe S3By Unipolar SPWM mode high frequency mo, modulation wave signal kueAmplitude is more than carrier signal ustHigh level is exported during amplitude,
Otherwise output low level；5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
Line voltage negative half period, line voltage ugAbsolute value be more than dc source UdcDuring the half of voltage magnitude, second
Power switch tube S2By Unipolar SPWM mode high frequency mo, modulation wave signal-(ue-ub) amplitude be more than carrier signal ustAmplitude
When export high level, otherwise output low level；4th power switch tube S4By Unipolar SPWM mode high frequency mo, modulating wave letter
Number-kueAmplitude is more than carrier signal ustHigh level is exported during amplitude, on the contrary output low level；4th power switch tube S4Account for
Sky is than being more than the second power switch tube S2Dutycycle.6th power switch tube S6Long logical, other driving signal of power switching tube are equal
For low level.
Line voltage negative half period, line voltage ugAbsolute value be less than dc source UdcDuring the half of voltage magnitude, the 4th
Power switch tube S4By Unipolar SPWM mode high frequency mo, modulation wave signal-kueAmplitude is more than carrier signal ustIt is defeated during amplitude
Go out high level, on the contrary output low level；6th power switch tube S6Long logical, other driving signal of power switching tube are low electricity
It is flat.
Embodiment 2
Referring to Fig. 4, the five Level Full Bridge combining inverter input capacitances of the present embodiment are from method for equalizing voltage, full-bridge grid-connected inversion
Device includes dc source Udc, input derided capacitors 1, five Level Full Bridge inverter circuits 2, the first output inductor Lf1, it is second defeated
Go out filter inductance Lf2With output filter capacitor Cf, the control circuit part of the full-bridge grid-connected inverter is including controlling circuit 3 and adjusting
Circuit 4 processed, wherein, control circuit 3 includes current sensor, the first subtracter and inductive current adjuster, and modulation circuit 4 includes
First comparator, the second comparator, the 3rd comparator, the 4th comparator, the 5th comparator, the 6th comparator, the first driving electricity
Road, the second drive circuit, the 3rd drive circuit, the 4th drive circuit, the 5th drive circuit, the 6th drive circuit, the first addition
Device, second adder, the first multiplier, the second multiplier and a phase inverter.
The five Level Full Bridges combining inverter input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current iLObtain inductor current feedback signal iLf, inductor current feedback signal iLf
It is connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal i of the first subtracterLr, first subtracts
The output end of musical instruments used in a Buddhist or Taoist mass obtains modulated signal u by inductive current adjustere, modulated signal ueRespectively with the same phase of first comparator
The input connection at end, the in-phase end of the 3rd comparator, the in-phase end of the 5th comparator and phase inverter, inverter output-ue
In-phase end, the in-phase end of the 4th comparator, the in-phase end of the 6th comparator respectively with the second comparator is connected；
Triangle carrier signal ustAn input respectively with first adder, an input of the first multiplier,
The input connection of the input, second adder of paired multiplier；
DC bias signal ubIt is connected with another input of first adder, the output end of first adder connection the
The end of oppisite phase of one comparator, the output of first comparator obtains first switch pipe drive signal u by the first drive circuitgs1；
DC bias signal ubIt is connected with another input of second adder, the output end of second adder connection the
The end of oppisite phase of two comparators, the output of the second comparator obtains second switch pipe drive signal u by the second drive circuitgs2；
Another input connection scaling signal k of first multiplier, the output end connection the 3rd of the first multiplier is compared
The end of oppisite phase of device, the output of the 3rd comparator obtains the 3rd switching tube drive signal u by the 3rd drive circuitgs3；
Another input connection scaling signal k of second multiplier, the output end connection the 4th of the second multiplier is compared
The end of oppisite phase of device, the output of the 4th comparator obtains the 4th switching tube drive signal u by the 4th drive circuitgs4；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th by the 5th drive circuit
Switching tube drive signal ugs5；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th by the 6th drive circuit
Switching tube drive signal ugs6。
Fig. 5 is the driving principle oscillogram of embodiment 2, in figure, ugs1To ugs6Represent the first to the 6th power switch tube S1
~S6Drive signal, ustRepresent triangle carrier signal, ueRepresent modulation wave signal, ubDC offset voltage is represented, equal to triangle
Carrier peak value, k represents proportionality coefficient.
When the modulation ratio of five Level Full Bridge combining inverters is more than 0.55, driving principle waveform such as Fig. 5 (a) of embodiment 2
Shown, proportionality coefficient k values are 1.
The positive half cycle of line voltage, line voltage ugMore than dc source UdcDuring the half of voltage magnitude, the first power switch
Pipe S1By Unipolar SPWM mode high frequency mo, modulation wave signal ueAmplitude is more than carrier signal (ust+ub) amplitude when the high electricity of output
It is flat, on the contrary output low level；3rd power switch tube S3With the 5th power switch tube S5It is long logical, other power switch tube drives letters
Number it is low level.
The positive half cycle of line voltage, line voltage ugLess than dc source UdcDuring the half of voltage magnitude, the 3rd power switch
Pipe S3By Unipolar SPWM mode high frequency mo, modulation wave signal ueAmplitude is more than carrier signal kustHigh level is exported during amplitude,
Otherwise output low level；5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
Line voltage negative half period, line voltage ugAbsolute value be more than dc source UdcDuring the half of voltage magnitude, second
Power switch tube S2By Unipolar SPWM mode high frequency mo, modulation wave signal-ueAmplitude is more than carrier signal-(ust+ub) amplitude
When export high level, otherwise output low level；4th power switch tube S4With the 6th power switch tube S6Long logical, other power are opened
It is low level to close pipe drive signal.
Line voltage negative half period, line voltage ugAbsolute value be less than dc source UdcDuring the half of voltage magnitude, the 4th
Power switch tube S4By Unipolar SPWM mode high frequency mo, modulation wave signal-ueAmplitude is more than carrier signal kustIt is defeated during amplitude
Go out high level, on the contrary output low level；6th power switch tube S6Long logical, other driving signal of power switching tube are low electricity
It is flat.
When the modulation ratio of five Level Full Bridge combining inverters is less than 0.55, driving principle waveform such as Fig. 5 (b) of embodiment 2
Shown, proportionality coefficient k values are>1 and<2.
The positive half cycle of line voltage, line voltage ugMore than dc source UdcDuring the half of voltage magnitude, the first power switch
Pipe S1By Unipolar SPWM mode high frequency mo, modulation wave signal ueAmplitude is more than carrier signal (ust+ub) amplitude when the high electricity of output
It is flat, on the contrary output low level；3rd power switch tube S3By Unipolar SPWM mode high frequency mo, modulation wave signal ueAmplitude is big
In carrier signal kustHigh level is exported during amplitude, on the contrary output low level.3rd power switch tube S3Dutycycle be more than first
Power switch tube S1Dutycycle；5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
The positive half cycle of line voltage, line voltage ugLess than dc source UdcDuring the half of voltage magnitude, the 3rd power switch
Pipe S3By Unipolar SPWM mode high frequency mo, modulation wave signal ueAmplitude is more than carrier signal kustHigh level is exported during amplitude,
Otherwise output low level；5th power switch tube S5Long logical, other driving signal of power switching tube are low level.
Line voltage negative half period, line voltage ugAbsolute value be more than dc source UdcDuring the half of voltage magnitude, second
Power switch tube S2By Unipolar SPWM mode high frequency mo, modulation wave signal-ueAmplitude is more than carrier signal (ust+ub) amplitude
When export high level, otherwise output low level.4th power switch tube S4By Unipolar SPWM mode high frequency mo, modulating wave letter
Number-ueAmplitude is more than carrier signal kustHigh level is exported during amplitude, on the contrary output low level；4th power switch tube S4Account for
Sky is than being more than the second power switch tube S2Dutycycle.6th power switch tube S6Long logical, other driving signal of power switching tube are equal
For low level.
Line voltage negative half period, line voltage ugAbsolute value be less than dc source UdcDuring the half of voltage magnitude, the 4th
Power switch tube S4By Unipolar SPWM mode high frequency mo, modulation wave signal-ueAmplitude is more than carrier signal kustIt is defeated during amplitude
Go out high level, on the contrary output low level；6th power switch tube S6Long logical, other driving signal of power switching tube are low electricity
It is flat.
In specific implementation, five Level Full Bridge inverters have various topological structures, and Fig. 6 gives three kind of five Level Full Bridge
Inverter topology.Wherein：Fig. 6 (a) is the Level Full Bridge inverter of neutral-point-clamped bridge-type five；Fig. 6 (b) is that Diode series are double
The Level Full Bridge inverter of buck five；Fig. 6 (c) is the switching tube series connection Level Full Bridge inverter of dual-buck five.
Fig. 7 is simulation waveform of the five Level Full Bridge combining inverter input capacitances from method for equalizing voltage shown in Fig. 2.Wherein, VC1
Represent input capacitance C respectively with VC2dc1And Cdc2Voltage, I (L1) and I (L2) represent inductance L respectivelyf1And Lf2Electric current.Electricity
Net voltage ugVirtual value be 220V, dc source UdcVoltage in 0.2s by 540V mutation value 600V, modulation ratio correspondence by
0.576 is changed into 0.518, and proportionality coefficient k is changed into 0.5 in 0.6s from 1.It can be seen from figure 7 that due between 0.2s~0.6s,
Modulation ratio is less than 0.518, and proportionality coefficient k is 1, therefore voltage un-balance occurs in input capacitance voltage；After 0.6s, proportionality coefficient k is
0.5, the difference of input capacitance voltage gradually levels off to zero, realizes the automatic equalization of input capacitance voltage, demonstrates the present invention
Five Level Full Bridge combining inverter input capacitances from the correctness of method for equalizing voltage.
The basic principles, principal features and advantages of the present invention have been shown and described above.The technical staff of the industry should
Understand, the invention is not limited in any way for above-described embodiment, it is all to be obtained by the way of equivalent substitution or equivalent transformation
Technical scheme, all falls within protection scope of the present invention.
Claims (6)
1. a kind of five Level Full Bridges combining inverter input capacitance includes dc source from method for equalizing voltage, the full-bridge grid-connected inverter
(Udc), input derided capacitors (1), five Level Full Bridge inverter circuits (2), two output inductor (Lf1、Lf2) and output filtering
Electric capacity (Cf), the control circuit part of the full-bridge grid-connected inverter includes control circuit (3) and modulation circuit (4), the control
Circuit (3) includes current sensor, subtracter and inductive current adjuster, and the modulation circuit (4) includes six comparators, six
Individual drive circuit, two subtracters, two multipliers, a phase inverters, it is characterised in that：The five Level Full Bridges combining inverter
Input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current (iL) obtain inductor current feedback signal (iLf), inductor current feedback signal
(iLf) be connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal (i of the first subtracterLr),
The output end of first subtracter obtains modulated signal (u by inductive current adjustere), modulated signal (ue) subtract respectively with second
The positive input terminal of musical instruments used in a Buddhist or Taoist mass, an input of the first multiplier, the input connection of the in-phase end of the 5th comparator and phase inverter,
Inverter output (- ue) positive input terminal, an input, the 6th comparator of the second multiplier respectively with the 3rd subtracter
In-phase end connection；
DC bias signal (ub) be connected with the negative input end of the second subtracter, the output end connection first of the second subtracter is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal (u of first comparatorst), the output of first comparator is driven by first
Dynamic circuit obtains first switch pipe drive signal (ugs1)；
DC bias signal (ub) be connected with the negative input end of the 3rd subtracter, the output end connection second of the 3rd subtracter is compared
The in-phase end of device, the end of oppisite phase connection triangle carrier signal (u of the second comparatorst), the output of the second comparator is driven by second
Dynamic circuit obtains second switch pipe drive signal (ugs2)；
Another input connection scaling signal (k) of first multiplier, the output end of the first multiplier connects the 3rd comparator
In-phase end, the end of oppisite phase connection triangle carrier signal (u of the 3rd comparatorst), the output of the 3rd comparator is by the 3rd driving
Circuit obtains the 3rd switching tube drive signal (ugs3)；
Another input connection scaling signal (k) of second multiplier, the output end of the second multiplier connects the 4th comparator
In-phase end, the end of oppisite phase connection triangle carrier signal (u of the 4th comparatorst), the output of the 4th comparator is by the 4th driving
Circuit obtains the 4th switching tube drive signal (ugs4)；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th switch by the 5th drive circuit
Pipe drive signal (ugs5)；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th switch by the 6th drive circuit
Pipe drive signal (ugs6)。
2. five Level Full Bridges combining inverter input capacitance according to claim 1 is from method for equalizing voltage, it is characterised in that：Institute
State DC bias signal (ub) amplitude be equal to triangle carrier signal (ust) peak value；
When the modulation ratio of five Level Full Bridge combining inverters is more than 0.55, scaling signal (k) value is equal to 1, when five electricity
When the modulation ratio for putting down full-bridge grid-connected inverter is less than 0.55, scaling signal (k) value>0 and<1.
3. five Level Full Bridges combining inverter input capacitance according to claim 1 is from method for equalizing voltage, it is characterised in that：
The modulation ratio of five Level Full Bridge combining inverters is more than 0.55, line voltage (ug) positive half cycle and more than dc source (Udc)
During voltage magnitude half, first switch pipe drive signal (ugs1) with Unipolar SPWM mode high frequency mo, the driving of the 3rd switching tube
Signal (ugs3) it is high level, line voltage (ug) negative half period and absolute value be more than dc source (Udc) voltage magnitude half, second
Switching tube drive signal (ugs2) with Unipolar SPWM mode high frequency mo, the 4th switching tube drive signal (ugs4) it is high level；
The modulation ratio of five Level Full Bridge combining inverters is less than 0.55, line voltage (ug) positive half cycle and more than dc source (Udc)
During voltage magnitude half, first switch pipe drive signal (ugs1) and the 3rd switching tube drive signal (ugs3) with Unipolar SPWM side
Formula high frequency mo, and the 3rd switching tube drive signal (ugs3) dutycycle be more than first switch pipe drive signal (ugs1), power network electricity
Press (ug) negative half period and absolute value be more than dc source (Udc) voltage magnitude half, second switch pipe drive signal (ugs2) and the
Four switching tube drive signal (ugs4) with Unipolar SPWM mode high frequency mo, and the 4th switching tube drive signal (ugs4) duty
Than more than second switch pipe drive signal (ugs2)。
4. a kind of five Level Full Bridges combining inverter input capacitance includes dc source from method for equalizing voltage, the full-bridge grid-connected inverter
(Udc), input derided capacitors (1), five Level Full Bridge inverter circuits (2), two output inductor (Lf1、Lf2) and output filtering
Electric capacity (Cf), the control circuit part of the full-bridge grid-connected inverter includes control circuit (3) and modulation circuit (4), the control
Circuit (3) includes current sensor, subtracter and inductive current adjuster, and the modulation circuit (4) includes six comparators, six
Individual drive circuit, two adders, two multipliers, a phase inverters, it is characterised in that：The five Level Full Bridges combining inverter
Input capacitance includes following content from method for equalizing voltage：
Using current sensor sampling inductive current (iL) obtain inductor current feedback signal (iLf), inductor current feedback signal
(iLf) be connected with the negative input end of the first subtracter, the positive input terminal connection inductive current reference signal (i of the first subtracterLr),
The output end of first subtracter obtains modulated signal (u by inductive current adjustere), modulated signal (ue) compare respectively with first
The input connection of in-phase end, the in-phase end of the 3rd comparator, the in-phase end of the 5th comparator and phase inverter compared with device, phase inverter
Output end (- ue) in-phase end respectively with the second comparator, the in-phase end of the 4th comparator, the in-phase end of the 6th comparator connect
Connect；
Triangle carrier signal (ust) input respectively with first adder, input, second of the first multiplier
The input connection of the input, second adder of multiplier；
DC bias signal (ub) be connected with another input of first adder, the output end connection first of first adder
The end of oppisite phase of comparator, the output of first comparator obtains first switch pipe drive signal (u by the first drive circuitgs1)；
DC bias signal (ub) be connected with another input of second adder, the output end connection second of second adder
The end of oppisite phase of comparator, the output of the second comparator obtains second switch pipe drive signal (u by the second drive circuitgs2)；
Another input connection scaling signal (k) of first multiplier, the output end of the first multiplier connects the 3rd comparator
End of oppisite phase, the output of the 3rd comparator obtains the 3rd switching tube drive signal (u by the 3rd drive circuitgs3)；
Another input connection scaling signal (k) of second multiplier, the output end of the second multiplier connects the 4th comparator
End of oppisite phase, the output of the 4th comparator obtains the 4th switching tube drive signal (u by the 4th drive circuitgs4)；
The end of oppisite phase connection reference ground of 5th comparator, the output of the 5th comparator obtains the 5th switch by the 5th drive circuit
Pipe drive signal (ugs5)；
The end of oppisite phase connection reference ground of 6th comparator, the output of the 6th comparator obtains the 6th switch by the 6th drive circuit
Pipe drive signal (ugs6)。
5. five Level Full Bridges combining inverter input capacitance according to claim 4 is from method for equalizing voltage, it is characterised in that：Institute
State DC bias signal (ub) amplitude be equal to triangle carrier signal (ust) peak value；
When the modulation ratio of five Level Full Bridge combining inverters is more than 0.55, scaling signal (k) value is equal to 1, when five electricity
When the modulation ratio for putting down full-bridge grid-connected inverter is less than 0.55, scaling signal (k) value>1 and<2.
6. five Level Full Bridges combining inverter input capacitance according to claim 4 is from method for equalizing voltage, it is characterised in that：
The modulation ratio of five Level Full Bridge combining inverters is more than 0.55, line voltage (ug) positive half cycle and more than dc source (Udc)
During voltage magnitude half, first switch pipe drive signal (ugs1) with Unipolar SPWM mode high frequency mo, the driving of the 3rd switching tube
Signal (ugs3) it is high level, line voltage (ug) negative half period and absolute value be more than dc source (Udc) voltage magnitude half, second
Switching tube drive signal (ugs2) with Unipolar SPWM mode high frequency mo, the 4th switching tube drive signal (ugs4) it is high level；
The modulation ratio of five Level Full Bridge combining inverters is less than 0.55, line voltage (ug) positive half cycle and more than dc source (Udc)
During voltage magnitude half, first switch pipe drive signal (ugs1) and the 3rd switching tube drive signal (ugs3) with Unipolar SPWM side
Formula high frequency mo, and the 3rd switching tube drive signal (ugs3) dutycycle be more than first switch pipe drive signal (ugs1), power network electricity
Press (ug) negative half period and absolute value be more than dc source (Udc) voltage magnitude half, second switch pipe drive signal (ugs2) and the
Four switching tube drive signal (ugs4) with Unipolar SPWM mode high frequency mo, and the 4th switching tube drive signal (ugs4) duty
Than more than second switch pipe drive signal (ugs2)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510621195.6A CN105262356B (en) | 2015-09-25 | 2015-09-25 | A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510621195.6A CN105262356B (en) | 2015-09-25 | 2015-09-25 | A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105262356A CN105262356A (en) | 2016-01-20 |
| CN105262356B true CN105262356B (en) | 2017-09-15 |
Family
ID=55101902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510621195.6A Active CN105262356B (en) | 2015-09-25 | 2015-09-25 | A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105262356B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106451533B (en) * | 2016-09-09 | 2019-05-03 | 河海大学 | Quasi-single-stage transless gird-connected inverter and its control circuit |
| CN107070275A (en) * | 2017-03-24 | 2017-08-18 | 江苏固德威电源科技股份有限公司 | The low common mode leakage current single-phase photovoltaic grid-connected inverter of five level and photovoltaic parallel in system |
| CN108282103A (en) * | 2018-02-11 | 2018-07-13 | 许继电气股份有限公司 | A kind of five-electrical level inverter |
| CN110011560B (en) * | 2019-04-24 | 2020-04-21 | 河海大学 | Double-buck full-bridge grid-connected inverter with circulating current eliminating capability and control circuit thereof |
| CN112636581B (en) * | 2020-12-16 | 2021-12-07 | 河海大学 | Soft switch control circuit of totem-pole PFC rectifier |
| CN113206601B (en) * | 2021-04-12 | 2022-06-14 | 三峡大学 | Direct current charger based on single-phase II type three-level pseudo totem pole |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005117896A (en) * | 2004-12-14 | 2005-04-28 | Hitachi Ltd | Three-level power converter |
| CN1967997A (en) * | 2006-10-20 | 2007-05-23 | 南京航空航天大学 | Five-level double step-down full bridge inverter |
| CN101902142A (en) * | 2010-07-26 | 2010-12-01 | 南京航空航天大学 | Diode clamping five-level dual buck half-bridge inverter |
| CN102223101A (en) * | 2011-06-21 | 2011-10-19 | 盐城工学院 | Control method for dual-bucking full-bridge grid-connected inverter |
| CN102427304A (en) * | 2011-10-17 | 2012-04-25 | 阳光电源股份有限公司 | Single-phase half-bridge five-level inverter and application circuit thereof |
-
2015
- 2015-09-25 CN CN201510621195.6A patent/CN105262356B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005117896A (en) * | 2004-12-14 | 2005-04-28 | Hitachi Ltd | Three-level power converter |
| CN1967997A (en) * | 2006-10-20 | 2007-05-23 | 南京航空航天大学 | Five-level double step-down full bridge inverter |
| CN101902142A (en) * | 2010-07-26 | 2010-12-01 | 南京航空航天大学 | Diode clamping five-level dual buck half-bridge inverter |
| CN102223101A (en) * | 2011-06-21 | 2011-10-19 | 盐城工学院 | Control method for dual-bucking full-bridge grid-connected inverter |
| CN102427304A (en) * | 2011-10-17 | 2012-04-25 | 阳光电源股份有限公司 | Single-phase half-bridge five-level inverter and application circuit thereof |
Non-Patent Citations (1)
| Title |
|---|
| 一种五电平双降压式并网逆变器;夏玲芳，等;《电力电子技术》;20121130;第46卷(第11期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105262356A (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105262356B (en) | A kind of five Level Full Bridge combining inverter input capacitances are from method for equalizing voltage | |
| CN104796030B (en) | Single-phase photovoltaic off-grid inverter and its soft switching control method based on quasi- Z-source inverter | |
| CN103001511B (en) | Voltage converter and operating method thereof | |
| CN105978388B (en) | One kind can inhibit leakage current single-phase buck-boost type photovoltaic DC-to-AC converter and its control method | |
| CN104638971B (en) | A kind of photovoltaic combining inverter and its control method | |
| CN105162350A (en) | High-efficiency wide-load-range three-phase micro-inverter and control method thereof | |
| CN105186912B (en) | A kind of non-isolated full-bridge grid-connected inverter of two-stage type | |
| CN104871421A (en) | Single-pole switch power source | |
| CN105281361B (en) | A kind of five-level double step-down combining inverter | |
| CN107196491B (en) | A kind of double buck gird-connected inverter half period current distortion inhibition system and method | |
| CN104767365B (en) | T-shaped three level DC/AC converters DC voltage ripple compensation system and method | |
| CN110620377A (en) | Three-port DC-DC converter applied to efficient energy transmission of photovoltaic power generation system and control method thereof | |
| CN103532417A (en) | Control method of topology variable grid-connected inverter | |
| CN108616224A (en) | A kind of single-phase seven electrical level inverter of booster type | |
| CN103618336B (en) | The output digital modulation circuit of rectifier type High Frequency Link combining inverter and control system | |
| CN104883046A (en) | High-power factor critical continuous mode buck-boost power factor correction converter | |
| CN109756138A (en) | A kind of control circuit of five Level Full Bridges inverter | |
| CN102025161B (en) | Five-level dual-buck parallel active power filter (APF) and dual-frequency half-wave control method thereof | |
| CN106452144B (en) | A kind of buck-boost type three-level inverter based on Zeta | |
| CN105262361A (en) | Two-stage non-isolation photovoltaic grid-connected inverter and control method thereof | |
| CN202435291U (en) | PFC (Power Factor Correction) boost circuit with adjustable carrier wave amplitude | |
| CN107124105B (en) | Improve the control system and method for isolated form three-level PFC converter PF | |
| CN203151389U (en) | Control circuit of three-phase high power factor rectifier | |
| CN214205365U (en) | Non-isolated current type grid-connected inverter without overlapping time | |
| CN115833562A (en) | Open-loop PFC (Power factor correction) control method based on totem-pole bidirectional AC/DC (alternating Current/direct Current) converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |