CN103401507B - Square-wave pulse drive waveforms modulation circuit - Google Patents
Square-wave pulse drive waveforms modulation circuit Download PDFInfo
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Abstract
The invention provides a kind of square-wave pulse drive waveforms modulation circuit, comprising: basic square wave source, the square wave driving pulse CLK that output frequency is adjustable, duty ratio is adjustable; D type flip flop, is modulated into two antipodal square-wave pulses of polarity, is respectively AU-1 and BU-1 by square wave driving pulse CLK; Middle modulation module, is modulated into AU-2 and BU-2 respectively by AU-1 and BU-1; Control module, is modulated into AD and BD respectively by AU-1 and BU-1; Final modulation module, is modulated into the 3rd control waveform AU under the control of BD by AU-2; Under the control of AD, BU-2 is modulated into the 4th control waveform BU.Because circuit of the present invention is primarily of logic gates and RC element composition, once parameter is determined, just reliablely and stablely one group of basic square wave source can be modulated into the drive waveforms of power device on four groups of H bridge brachium pontis, antijamming capability is stronger; And only need control one group of basic square wave source, the parameters of H bridge square-wave pulse can be regulated neatly, be conducive to realizing modularized design.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to a kind of bipolar pulse modulation circuit, particularly relate to a kind of square-wave pulse drive waveforms modulation circuit.
Background technology
As shown in Figure 1, H-bridge circuit is made up of Au, Ad, Bu, Bd tetra-groups of power devices, and out1, out2 are output.H-bridge circuit can be used for producing ambipolar square-wave pulse, needs the action of the collaborative switch controlling four groups of power devices respectively, needs four groups of drive waveforms altogether; Four groups of drive waveforms control and determine frequency (cycle), duty ratio, the positive-negative polarity WFS (△ t) that H-bridge circuit exports square-wave pulse.The ambipolar square-wave pulse that existing H-bridge circuit exports as shown in Figure 2, comprises two opposite polarity square wave t1 and t2 in one-period T, due to circuit and device, also there is an of short duration interval △ t between t1 and t2; In strict bipolar square wave pulse, t1=t2, duty ratio=t1/T=t2/T; Also under having certain situation, t1 ≠ t2, duty ratio=t1/(t1+ △ t+t2) or t2/(t1+ △ t+t2), this means, when T is constant, t1 reduces or increases, and t2 will increase thereupon or reduce; In H-bridge circuit, Au and Ad correspondence generates the square wave of t1 section, Bu and Bd correspondence generates the square wave of t2 section.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of square-wave pulse drive waveforms modulation circuit, controls complicated, inflexible problem for the driving pulse solving H-bridge circuit in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of square-wave pulse drive waveforms modulation circuit.
A kind of square-wave pulse drive waveforms modulation circuit, comprising: basic square wave source, the square wave driving pulse CLK that output frequency is adjustable, duty ratio is adjustable; D type flip flop, is connected with described basic square wave source, and described square wave driving pulse CLK is modulated into two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1; Middle modulation module, is connected with described d type flip flop, described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively; Control module, is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively; Final modulation module, is connected with described control module respectively with described middle modulation module, under the control of described second control waveform BD, described third party's wave impulse AU-2 is modulated into the 3rd control waveform AU; Under the control of described first control waveform AD, described 4th square-wave pulse BU-2 is modulated into the 4th control waveform BU.
Preferably, described middle modulation module is NOR gate combination, and described NOR gate combination is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively; The high level of described third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 does not overlap.
Preferably, described NOR gate combination comprises NOR gate U2A in parallel and NOR gate U2B, an input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source, and the output of NOR gate U2A exports third party's wave impulse AU-2; An input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, and the output of NOR gate U2B exports the 4th square-wave pulse BU-2.
Preferably, described control module is first to combine with door, and described first to combine with door and be connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively; Described first with door combine in be provided with delay circuit with an input of door; Described first control waveform AD has predetermined forward position time delay relative to first party wave impulse AU-1; Described second control waveform BD has predetermined forward position time delay relative to second party wave impulse BU-1.
Preferably, described first to combine with door and comprises NAND gate U3A in parallel and NAND gate U3B, and NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; An input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C are all connected with the output of NAND gate U3A, and the output of NAND gate U3C exports the first control waveform AD; An input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D are all connected with the output of NAND gate U3B, and the output of NAND gate U3D exports the second control waveform BD.
Preferably, described final modulation module is second to combine with door, described second combines to combine with described NOR gate to combine with door with described first with door and is connected respectively, logical operation and time delay are carried out to described third party's wave impulse AU-2 and the second control waveform BD, the 4th square-wave pulse BU-2 and the first control waveform AD, produce the 3rd control waveform AU and the 4th control waveform BU, the safety that the forward position of described 3rd control waveform AU results from after the second control waveform BD forward position the soonest opens interval; The safety that the forward position of described 4th control waveform BU results from after the first control waveform AD forward position the soonest opens interval.
Preferably, described second to combine with door and comprises NAND gate U4A in parallel and NAND gate U4B, and NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; An input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C are all connected with the output of NAND gate U4A, and the output of NAND gate U4C exports the 3rd control waveform AU; An input of NAND gate U4B is connected with the 4th square-wave pulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D are all connected with the output of NAND gate U4B, and the output of NAND gate U4D exports the 4th control waveform BU.
Preferably, described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D be trigger input with Si Mite and gate device.
Preferably, described delay circuit is RC integrator.
As mentioned above, square-wave pulse drive waveforms modulation circuit of the present invention, has following beneficial effect:
Because circuit of the present invention is primarily of logic gates and RC element composition, once parameter is determined, just reliablely and stablely one group of basic square wave source can be modulated into the drive waveforms of power device on four groups of H bridge brachium pontis, antijamming capability is stronger; And only need control one group of basic square wave source, the parameters of H bridge square-wave pulse can be regulated neatly, be conducive to realizing modularized design.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing H-bridge circuit.
Fig. 2 is the waveform schematic diagram of existing bipolar square wave pulse.
Fig. 3 is the structured flowchart of square-wave pulse drive waveforms modulation circuit of the present invention.
Fig. 4 is the structural representation of a kind of embodiment of square-wave pulse drive waveforms modulation circuit of the present invention.
Fig. 5 a is the basic CLK pulse of square wave source output of the present invention and the sequential relationship schematic diagram of AU-1 pulse.
Fig. 5 b is the basic CLK pulse of square wave source output of the present invention and the sequential relationship schematic diagram of BU-1 pulse.
Fig. 6 is the pulse sequence relation schematic diagram of AU-1 and BU-1 of the present invention.
Fig. 7 a is the basic CLK pulse of square wave source output of the present invention and the sequential relationship schematic diagram of AU-2 pulse.
Fig. 7 b is the basic CLK pulse of square wave source output of the present invention and the sequential relationship schematic diagram of BU-2 pulse.
Fig. 8 is the pulse sequence relation schematic diagram of AU-2 and BU-2 of the present invention.
Fig. 9 a is the pulse sequence relation schematic diagram of AU-1 and AD of the present invention.
Fig. 9 b is the pulse sequence relation schematic diagram of BU-1 and BD of the present invention.
Figure 10 is the pulse sequence relation schematic diagram of AU and BD of the present invention.
Figure 11 is the result pulse sequence schematic diagram four groups of control waveforms AU, BU, AD, BD being applied to the H-bridge circuit in Fig. 1.
Element numbers explanation
100 basic square wave source
200D trigger
300 middle modulation modules
400 control modules
500 final modulation modules
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Below in conjunction with embodiment and accompanying drawing, the present invention is described in detail.
Embodiment
The present embodiment provides a kind of square-wave pulse drive waveforms modulation circuit, as shown in Figure 3, comprising: basic square wave source 100, d type flip flop 200, middle modulation module 300, control module 400 and final modulation module 500.Square-wave pulse drive waveforms modulation circuit of the present invention can produce four groups for driving the drive waveforms of power device on four brachium pontis in H bridge respectively, and these four groups of waveforms can be labeled as AU, BU, AD, BD respectively; When in the present invention, the drive waveforms of setting power device is high level, power device is open-minded.
The square wave driving pulse CLK that described basic square wave source 100 output frequency is adjustable, duty ratio is adjustable.Further, represent basic square wave source with V2 in illustrated Fig. 4, the output waveform of this basic square wave source represents with CLK, and CLK is frequency-adjustable, duty ratio is adjustable, and the waveform that wave period in odevity week and duty ratio can control respectively.
Described d type flip flop 200 is connected with described basic square wave source 100, and described square wave driving pulse CLK is modulated into two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1.CLK is modulated into antipodal square-wave pulse AU-1 and BU-1 of polarity by described d type flip flop 200, and square-wave pulse AU-1 and BU-1 exists as intermediate state signal in the present invention.D type flip flop in the present invention can adopt 74LS74 chip to realize, but is not limited to 74LS74 chip.
Described middle modulation module 300 is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively.Further, described middle modulation module 300 comprises NOR gate combination, described NOR gate combination is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively; The high level of described third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 does not overlap.Specific address, as shown in Figure 4, described NOR gate combination comprises NOR gate U2A in parallel and NOR gate U2B, an input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source 100, and the output of NOR gate U2A exports third party's wave impulse AU-2; An input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, and the output of NOR gate U2B exports the 4th square-wave pulse BU-2.NOR gate U2A in the present invention and U2B can adopt 74LS02 chip to realize, but is not limited to 74LS02 chip.
As shown in Figure 4, CLK, AU-1 and BU-1 are modulated into the second intermediate state signal AU-2 and BU-2 by NOR gate U2A, U2B, through the process of the logical circuit that NOR gate U2A, U2B are formed, the high level of AU-2 and BU-2 will not overlap, and provides enough switching times can to the driving of rear end power device.
Described control module 400 is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively.Further, described control module 400 comprises first with door and combines, and described first to combine with door and be connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively; Described first with door combine in be provided with delay circuit with an input of door; Described first control waveform AD has predetermined forward position time delay relative to first party wave impulse AU-1; Described second control waveform BD has predetermined forward position time delay relative to second party wave impulse BU-1.
Particularly, as shown in Figure 4, described first to combine with door and comprises NAND gate U3A in parallel and NAND gate U3B, and NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; An input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C are all connected with the output of NAND gate U3A, and the output of NAND gate U3C exports the first control waveform AD; An input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D are all connected with the output of NAND gate U3B, and the output of NAND gate U3D exports the second control waveform BD.NAND gate U3A in the present invention, U3B, U3C and U3D can adopt 74LS132 chip to realize, but are not limited to 74LS132 chip.An input of NAND gate have employed RC integrating circuit as input, and for producing certain time delay to the forward position of AU-1 and BU-1, time delay size depends on RC value.
Described final modulation module 500 is connected with described control module 400 respectively with described middle modulation module 300, under the control of described first control waveform AD, described third party's wave impulse AU-2 is modulated into the 3rd control waveform AU; Under the control of described second control waveform BD, described 4th square-wave pulse BU-2 is modulated into the 4th control waveform BU.Further, described final modulation module 500 comprises second and combines with door, described second combines to combine with described NOR gate to combine with door with described first with door and is connected respectively, logical operation and time delay are carried out to described third party's wave impulse AU-2 and the second control waveform BD, the 4th square-wave pulse BU-2 and the first control waveform AD, produces the 3rd control waveform AU and the 4th control waveform BU; The safety that the forward position of described 3rd control waveform AU results from after the second control waveform BD forward position the soonest opens interval; The safety that the forward position of described 4th control waveform BU results from after the first control waveform AD forward position the soonest opens interval.Particularly, as shown in Figure 4, described second to combine with door and comprises NAND gate U4A in parallel and NAND gate U4B, and NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; An input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C are all connected with the output of NAND gate U4A, and the output of NAND gate U4C exports the 3rd control waveform AU; An input of NAND gate U4B is connected with the 4th square-wave pulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D are all connected with the output of NAND gate U4B, and the output of NAND gate U4D exports the 4th control waveform BU.U4A, U4B, U4C and U4D in the present invention can adopt 74LS132 chip to realize, but are not limited to 74LS132 chip.The input of U4A and U4B have employed RC integration (time delay) circuit as input, and for producing certain time delay to the forward position of AU and BU, time delay size depends on RC value.
Further, described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D be trigger input with Si Mite and gate device.
Further, delay circuit of the present invention (or claim integrating circuit) includes but not limited to RC integrator, also can have logical device or the circuit of delay function for other.
The present invention is mainly through basic square wave source, d type flip flop-NOR gate-RC integrator combination, d type flip flop-combine with door-RC integrator, combines with door-RC integrator, produces AU, BU, AD, BD tetra-groups for driving the drive waveforms of power device on four brachium pontis in H bridge respectively.
By basic square wave source of the present invention and d type flip flop, make the odd-times cycle of CLK and the forward position of even-times cycle can be respectively used to the forward position of triggered D flip flop generation AU-1 and BU-1, determine the duty ratio of AU-1 and BU-1 wave period respectively in the odd-times cycle of CLK and even-times week.The sequential relationship of CLK pulse and AU-1 and BU-1 as shown in figure 5a and 5b.The sequential relationship of AU-1 and BU-1 as shown in Figure 6.Or contrary, the odd-times cycle of CLK and the forward position of even-times cycle are respectively used to trigger the forward position producing BU-1 and AU-1, determine the duty ratio of BU-1 and AU-1 wave period respectively in the odd-times cycle of CLK and even-times week.
By the middle modulation module in circuit of the present invention, make the odd-times cycle of CLK and even-times cycle produce the high level of AU-2 and the high level of BU-2 respectively, the duty ratio of CLK determines the duty ratio of AU-2 and BU-2; When the duty ratio of the odd-times cycle of control CLK respectively and even-times cycle, just can control AU-2 and BU-2 independently duty ratio respectively; The sequential relationship of CLK pulse and AU-2 and BU-2 as illustrated in figs. 7 a and 7b.The sequential relationship of AU-2 and BU-2 as shown in Figure 8.Or contrary, make the odd-times cycle of CLK and even-times cycle produce the high level of BU-2 and the high level of AU-2 respectively, the duty ratio of CLK determines the duty ratio of BU-2 and AU-2; When the duty ratio of the odd-times cycle of control CLK respectively and even-times cycle, just can control BU-2 and AU-2 independently duty ratio respectively.
By the control module in circuit of the present invention, make the integrator be made up of R1, C1 produce time delay to AU-1 forward position, generate final control waveform AD; Also make the integrator be made up of R2, C2 produce time delay to BU-1 forward position, generate final control waveform BD; Wherein, the pulse sequence relation of AU-1 and AD, BU-1 and BD respectively as shown in figures 9 a and 9b.
By the final modulation module in circuit of the present invention, logical operation and time delay are carried out to AU-2 and BD, BU-2 and AD, produce final control waveform AU and BU.And having following effect: the forward position safety resulted from the soonest after BD forward position of AU opens interval, and this is opened safely interval and is determined by the RC value of R3, C3; Equally, the forward position safety resulted from the soonest after AD forward position of BU opens interval, and this is opened safely interval and is determined by the RC value of R4, C4; The sequential relationship of AU and BD as shown in Figure 10.
The function that square-wave pulse drive waveforms modulation circuit of the present invention realizes is: achieve the frequency adjustment to four groups of control waveforms AU, BU, AD, BD by the frequency of regulating and controlling CLK; By the duty ratio of regulating and controlling CLK waveform, achieve the adjustment of the duty ratio to AU and BU; By wave period in regulating and controlling CLK odd even secondary week, achieve the adjustment of the duty ratio to AD, BD.
Above-mentioned four groups of control waveforms AU, BU, AD, BD are applied to the H-bridge circuit in Fig. 1, result as shown in figure 11:
By the frequency of regulating and controlling CLK, realize adjustment H bridge being exported to square-wave pulse cycle T;
By the duty ratio of the odd-times cycle of regulating and controlling CLK, achieve adjustment H bridge being exported to square-wave pulse parametric t 1;
By the duty ratio of the even-times cycle of regulating and controlling CLK, achieve adjustment H bridge being exported to square-wave pulse parametric t 2;
Interval △ t of short duration between t1 and t2 determines by two aspect factors: the RC value of R3 and C3, R4 and C4, the value of parametric t 1 or t2; When △ t is less, determine its size by RC value, RC value ensure that the safety of power device opens interval for preset parameter; When △ t is larger, determine its size by t1 and t2 value, t1 and t2 value is by the Duty ratio control of CLK.
As can be seen from Figure 10, the odd even of CLK time wave period in week, duty ratio are different, and corresponding H bridge exports t1, t2 parameter of square-wave pulse, and namely cycle of square-wave pulse and duty ratio also can have corresponding change thereupon.Such as, the 1st cycle of CLK determines the t1_1 in first pulse high level, and the 2nd cycle of CLK determines the t2_1 in first pulses low, the like; Short time between t1 and t2 every △ t, by the Duty ratio control of CLK, as the △ t1 ~ △ t4 in figure.
Because circuit of the present invention is primarily of logic gates and RC element composition, once parameter is determined, reliablely and stablely one group of basic square wave source will be modulated into the drive waveforms of power device on four groups of H bridge brachium pontis, antijamming capability is stronger; And only need control one group of basic square wave source, the parameters of H bridge square-wave pulse can be regulated neatly, be conducive to realizing modularized design.
The schematic diagram that this specification institute accompanying drawings illustrates, device model, timing waveform, content all only in order to coordinate specification to disclose, understand for person skilled in the art scholar and read, and be not used to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the modification of any structure, the change of proportionate relationship, the adjustment of size, RC value parameter changes, the device type alternation of signs, logic state circulation conversion, logic state integral transformation, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents obtains in the scope that can contain, logic state circulation conversion refers to the way but not making logic state generation change by increasing logical operation device in critical path, such as, two NAND gate are serially connected and are equal to one and door, it is constant that two not gates are serially connected in logic state in same path.Due to the difference of witness mark, contrary logical relation may be obtained, can not as the enforceable qualifications of restriction the present invention.Simultaneously, quote in this specification as " on ", D score, "left", "right", " centre " and " one " etc. term, also only for ease of understanding of describing, and be not used to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
In sum, the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a square-wave pulse drive waveforms modulation circuit, is characterized in that, described square-wave pulse drive waveforms modulation circuit comprises:
Basic square wave source, the square wave driving pulse CLK that output frequency is adjustable, duty ratio is adjustable;
D type flip flop, is connected with described basic square wave source, and described square wave driving pulse CLK is modulated into two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1;
Middle modulation module, is connected with described d type flip flop, described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively;
Control module, is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively;
Final modulation module, is connected with described control module respectively with described middle modulation module, under the control of described second control waveform BD, described third party's wave impulse AU-2 is modulated into the 3rd control waveform AU; Under the control of described first control waveform AD, described 4th square-wave pulse BU-2 is modulated into the 4th control waveform BU.
2. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: described middle modulation module is NOR gate combination, described NOR gate combination is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 respectively; The high level of described third party's wave impulse AU-2 and the 4th square-wave pulse BU-2 does not overlap.
3. square-wave pulse drive waveforms modulation circuit according to claim 2, it is characterized in that: described NOR gate combination comprises NOR gate U2A in parallel and NOR gate U2B, an input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source, and the output of NOR gate U2A exports third party's wave impulse AU-2; An input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, and the output of NOR gate U2B exports the 4th square-wave pulse BU-2.
4. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: described control module is first to combine with door, described first to combine with door and is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 is modulated into the first control waveform AD and the second control waveform BD respectively; Described first with door combine in be provided with delay circuit with an input of door; Described first control waveform AD has predetermined forward position time delay relative to first party wave impulse AU-1; Described second control waveform BD has predetermined forward position time delay relative to second party wave impulse BU-1.
5. square-wave pulse drive waveforms modulation circuit according to claim 4, it is characterized in that: described first to combine with door and comprise NAND gate U3A in parallel and NAND gate U3B, NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; An input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C are all connected with the output of NAND gate U3A, and the output of NAND gate U3C exports the first control waveform AD; An input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D are all connected with the output of NAND gate U3B, and the output of NAND gate U3D exports the second control waveform BD.
6. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: described final modulation module is second to combine with door, described second to combine with door and is connected respectively with described control module with described middle modulation module, logical operation and time delay are carried out to described third party's wave impulse AU-2 and the second control waveform BD, the 4th square-wave pulse BU-2 and the first control waveform AD, produce the 3rd control waveform AU and the 4th control waveform BU, the safety that the forward position of described 3rd control waveform AU results from after the second control waveform BD forward position the soonest opens interval; The safety that the forward position of described 4th control waveform BU results from after the first control waveform AD forward position the soonest opens interval.
7. square-wave pulse drive waveforms modulation circuit according to claim 6, it is characterized in that: described second to combine with door and comprise NAND gate U4A in parallel and NAND gate U4B, NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; An input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C are all connected with the output of NAND gate U4A, and the output of NAND gate U4C exports the 3rd control waveform AU; An input of NAND gate U4B is connected with the 4th square-wave pulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D are all connected with the output of NAND gate U4B, and the output of NAND gate U4D exports the 4th control waveform BU.
8. the square-wave pulse drive waveforms modulation circuit according to claim 5 or 7, is characterized in that: described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D be trigger input with Si Mite and gate device.
9. the square-wave pulse drive waveforms modulation circuit according to claim 4,5 or 7, is characterized in that: described delay circuit is RC integrator.
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| CN104753501A (en) * | 2013-12-30 | 2015-07-01 | 上海普锐马电子有限公司 | Circuit for completing synchronous square-wave output in programmable mode |
| CN104865506B (en) * | 2015-05-20 | 2017-11-14 | 王运国 | A kind of insulation detection device of DC electrical system |
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