CN103401507A - Square-wave pulse driving waveform modulation circuit - Google Patents
Square-wave pulse driving waveform modulation circuit Download PDFInfo
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Abstract
The invention provides a square-wave pulse driving waveform modulation circuit. The waveform modulation circuit comprises a basic square-wave source, a D trigger, an intermediate modulation module, a control module and a final modulation module, wherein the basic square-wave source is used for outputting a square-wave driving pulse CLK with adjustable frequency and duty cycle; the D trigger is used for modulating the square-wave driving pulse CLK into two square-wave pulses with completely opposite polarities, namely AU-1 and BU-1; the intermediate modulation module is used for modulating AU-1 and BU-1 into AU-2 and BU-2 respectively; the control module is used for modulating AU-1 and BU-1 into AD and BD respectively; the final modulation module is used for modulating AU-2 into a third control waveform AU under the control of SD and modulating BU-2 into a fourth control waveform BU under the control of AD. As the square-wave pulse driving waveform modulation circuit mainly comprises a logic gate circuit and RC elements, once parameters are determined, a group of basic square-wave sources can be stably and reliably modulated into driving waveforms of power devices on four groups of H-bridge arms, and accordingly, stronger anti-interference ability is achieved; all parameters of the H-bridge square-wave pulse can be flexibly adjusted so long as one group of basic square-wave sources are controlled, so that the realization of modular design is facilitated.
Description
Technical field
The invention belongs to the electronic circuit technology field, relate to a kind of bipolar pulse modulation circuit, particularly relate to a kind of square-wave pulse drive waveforms modulation circuit.
Background technology
As shown in Figure 1, the H bridge circuit is comprised of Au, Ad, Bu, tetra-groups of power devices of Bd, and out1, out2 are output.The H bridge circuit can be used for producing ambipolar square-wave pulse, need to control respectively the action of the collaborative switch of four groups of power devices, needs altogether four groups of drive waveforms; Frequency (cycle), duty ratio, the positive-negative polarity WFS (△ t) of H bridge circuit output square-wave pulse controlled and determined to four groups of drive waveforms.The ambipolar square-wave pulse of existing H bridge circuit output as shown in Figure 2, comprises two opposite polarity square wave t1 and t2 in one-period T, due to circuit and device, between t1 and t2, also exist an of short duration interval △ t; In strict bipolar square wave pulse, t1=t2, duty ratio=t1/T=t2/T; T1 ≠ t2, duty ratio=t1/(t1+ △ t+t2 are also arranged under certain situation) or t2/(t1+ △ t+t2), this means, when T was constant, t1 reduced or increases, and t2 will increase thereupon or reduce; In the H bridge circuit, the corresponding square wave that generates the t1 section of Au and Ad, the corresponding square wave that generates the t2 section of Bu and Bd.
Summary of the invention
The shortcoming of prior art, the object of the present invention is to provide a kind of square-wave pulse drive waveforms modulation circuit in view of the above, for the driving pulse that solves prior art H bridge circuit, controls complicated, inflexible problem.
Reach for achieving the above object other relevant purposes, the invention provides a kind of square-wave pulse drive waveforms modulation circuit.
A kind of square-wave pulse drive waveforms modulation circuit comprises: basic square wave source, the square wave driving pulse CLK that output frequency is adjustable, duty ratio is adjustable; D type flip flop, be connected with described basic square wave source, and described square wave driving pulse CLK is modulated into to two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1; Middle modulation module, be connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2; Control module, be connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD; Final modulation module, be connected respectively with described control module with described middle modulation module, under the control of described the second control waveform BD, described third party's wave impulse AU-2 is modulated into to the 3rd control waveform AU; Under the control of described the first control waveform AD, described cubic wave impulse BU-2 is modulated into to the 4th control waveform BU.
Preferably, described middle modulation module is the NOR gate combination, and described NOR gate combination is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2; The high level of described third party's wave impulse AU-2 and cubic wave impulse BU-2 does not overlap.
Preferably, described NOR gate combination comprises NOR gate U2A and NOR gate U2B in parallel, the input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source, the output output third party wave impulse AU-2 of NOR gate U2A; The input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, the cubic wave impulse BU-2 of output output of NOR gate U2B.
Preferably, described control module be first with door combination, described first is connected with described d type flip flop with the door combination, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD; Described first with door combination in an input with door be provided with delay circuit; Described the first control waveform AD has predetermined forward position time delay with respect to first party wave impulse AU-1; Described the second control waveform BD has predetermined forward position time delay with respect to second party wave impulse BU-1.
Preferably, described first comprises NAND gate U3A in parallel and NAND gate U3B with the door combination, and NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; The input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C all are connected with the output of NAND gate U3A, output output the first control waveform AD of NAND gate U3C; The input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D all are connected with the output of NAND gate U3B, output output the second control waveform BD of NAND gate U3D.
Preferably, described final modulation module be second with door combination, described second is connected respectively with the door combination with described first with described NOR gate combination with the door combination, described third party's wave impulse AU-2 and the second control waveform BD, cubic wave impulse BU-2 and the first control waveform AD are carried out to logical operation and time delay, produce the 3rd control waveform AU and the 4th control waveform BU, the safety that the forward position of described the 3rd control waveform AU results from after the second control waveform BD forward position is the soonest opened interval; The safety that the forward position of described the 4th control waveform BU results from after the first control waveform AD forward position is the soonest opened interval.
Preferably, described second comprises NAND gate U4A in parallel and NAND gate U4B with the door combination, and NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; The input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C all are connected with the output of NAND gate U4A, output output the 3rd control waveform AU of NAND gate U4C; The input of NAND gate U4B is connected with the cubic wave impulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D all are connected with the output of NAND gate U4B, output output the 4th control waveform BU of NAND gate U4D.
Preferably, described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D be with Si Mite, trigger input and gate device.
Preferably, described delay circuit is the RC integrator.
As mentioned above, square-wave pulse drive waveforms modulation circuit of the present invention has following beneficial effect:
Because main circuit of the present invention will be comprised of logic gates and RC element, in case parameter is determined, just can reliablely and stablely one group of basic square wave source be modulated into to the drive waveforms of power device on four groups of H bridge brachium pontis, antijamming capability is stronger; And only needing to control one group of basic square wave source, the parameters that can regulate neatly H bridge square-wave pulse, be conducive to realize modularized design.
The accompanying drawing explanation
Fig. 1 is the structural representation of existing H bridge circuit.
Fig. 2 is the waveform schematic diagram of existing bipolar square wave pulse.
Fig. 3 is the structured flowchart of square-wave pulse drive waveforms modulation circuit of the present invention.
Fig. 4 is the structural representation of a kind of embodiment of square-wave pulse drive waveforms modulation circuit of the present invention.
Fig. 5 a is the CLK pulse of basic square wave source output of the present invention and the sequential relationship schematic diagram of AU-1 pulse.
Fig. 5 b is the CLK pulse of basic square wave source output of the present invention and the sequential relationship schematic diagram of BU-1 pulse.
Fig. 6 is that the pulse sequence of AU-1 of the present invention and BU-1 concerns schematic diagram.
Fig. 7 a is the CLK pulse of basic square wave source output of the present invention and the sequential relationship schematic diagram of AU-2 pulse.
Fig. 7 b is the CLK pulse of basic square wave source output of the present invention and the sequential relationship schematic diagram of BU-2 pulse.
Fig. 8 is that the pulse sequence of AU-2 of the present invention and BU-2 concerns schematic diagram.
Fig. 9 a is that the pulse sequence of AU-1 of the present invention and AD concerns schematic diagram.
Fig. 9 b is that the pulse sequence of BU-1 of the present invention and BD concerns schematic diagram.
Figure 10 is that the pulse sequence of AU of the present invention and BD concerns schematic diagram.
Figure 11 is for being applied to four groups of control waveform AU, BU, AD, BD in the schematic diagram of pulse sequence as a result of the H bridge circuit in Fig. 1.
The element numbers explanation
100 basic square wave source
200 d type flip flops
Modulation module in the middle of 300
400 control modules
500 final modulation modules
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic only show with the present invention in relevant assembly but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The present invention is described in detail below in conjunction with embodiment and accompanying drawing.
Embodiment
The present embodiment provides a kind of square-wave pulse drive waveforms modulation circuit, as shown in Figure 3, comprising: basic square wave source 100, d type flip flop 200, middle modulation module 300, control module 400 and final modulation module 500.Square-wave pulse drive waveforms modulation circuit of the present invention can produce four groups for driving respectively the drive waveforms of power device on four brachium pontis of H bridge, and these four groups of waveforms can be labeled as respectively AU, BU, AD, BD; When in the present invention, the drive waveforms of setting power device was high level, power device was open-minded.
The square wave driving pulse CLK that described basic square wave source 100 output frequencies are adjustable, duty ratio is adjustable.Further, in Fig. 4 shown in the present, with V2, represent basic square wave source, the output waveform of this basic square wave source represents with CLK, and CLK is that frequency is adjustable, duty ratio is adjustable, and the waveform that can control respectively of the cycle of odevity cycle and duty ratio.
Described d type flip flop 200 is connected with described basic square wave source 100, and described square wave driving pulse CLK is modulated into to two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1.Described d type flip flop 200 is modulated into the antipodal square-wave pulse AU-1 of polarity and BU-1 by CLK, and square-wave pulse AU-1 and BU-1 exist as the intermediate state signal in the present invention.D type flip flop in the present invention can adopt the 74LS74 chip to realize, but is not limited to the 74LS74 chip.
In the middle of described, modulation module 300 is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2.Further, in the middle of described, modulation module 300 comprises the NOR gate combination, described NOR gate combination is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2; The high level of described third party's wave impulse AU-2 and cubic wave impulse BU-2 does not overlap.Specific address, as shown in Figure 4, described NOR gate combination comprises NOR gate U2A and NOR gate U2B in parallel, the input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source 100, the output output third party wave impulse AU-2 of NOR gate U2A; The input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, the cubic wave impulse BU-2 of output output of NOR gate U2B.NOR gate U2A in the present invention and U2B can adopt the 74LS02 chip to realize, but are not limited to the 74LS02 chip.
As shown in Figure 4, NOR gate U2A, U2B are modulated into the second intermediate state signal AU-2 and BU-2 by CLK, AU-1 and BU-1, the processing of the logical circuit that process NOR gate U2A, U2B form, the high level of AU-2 and BU-2 will not overlap, and is provided enough switching times can for the driving of rear end power device.
Described control module 400 is connected with described d type flip flop 200, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD.Further, described control module 400 comprises that first makes up with door, and described first is connected with described d type flip flop 200 with the door combination, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD; Described first with door combination in an input with door be provided with delay circuit; Described the first control waveform AD has predetermined forward position time delay with respect to first party wave impulse AU-1; Described the second control waveform BD has predetermined forward position time delay with respect to second party wave impulse BU-1.
Particularly, as shown in Figure 4, described first comprises NAND gate U3A in parallel and NAND gate U3B with the door combination, and NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; The input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C all are connected with the output of NAND gate U3A, output output the first control waveform AD of NAND gate U3C; The input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D all are connected with the output of NAND gate U3B, output output the second control waveform BD of NAND gate U3D.NAND gate U3A in the present invention, U3B, U3C and U3D can adopt the 74LS132 chip to realize, but are not limited to the 74LS132 chip.An input of NAND gate has adopted the RC integrating circuit as input, for the forward position to AU-1 and BU-1, produces certain time delay, and the time delay size depends on the RC value.
Described final modulation module 500 is connected respectively with described control module 400 with described middle modulation module 300, under the control of described the first control waveform AD, described third party's wave impulse AU-2 is modulated into to the 3rd control waveform AU; Under the control of described the second control waveform BD, described cubic wave impulse BU-2 is modulated into to the 4th control waveform BU.Further, described final modulation module 500 comprises that second makes up with door, described second is connected respectively with the door combination with described first with described NOR gate combination with the door combination, described third party's wave impulse AU-2 and the second control waveform BD, cubic wave impulse BU-2 and the first control waveform AD are carried out to logical operation and time delay, produce the 3rd control waveform AU and the 4th control waveform BU; The safety that the forward position of described the 3rd control waveform AU results from after the second control waveform BD forward position is the soonest opened interval; The safety that the forward position of described the 4th control waveform BU results from after the first control waveform AD forward position is the soonest opened interval.Particularly, as shown in Figure 4, described second comprises NAND gate U4A in parallel and NAND gate U4B with the door combination, and NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; The input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C all are connected with the output of NAND gate U4A, output output the 3rd control waveform AU of NAND gate U4C; The input of NAND gate U4B is connected with the cubic wave impulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D all are connected with the output of NAND gate U4B, output output the 4th control waveform BU of NAND gate U4D.U4A in the present invention, U4B, U4C and U4D can adopt the 74LS132 chip to realize, but are not limited to the 74LS132 chip.The input of U4A and U4B has adopted RC integration (time delay) circuit as input, for the forward position to AU and BU, produces certain time delay, and the time delay size depends on the RC value.
Further, described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D be with Si Mite, trigger input and gate device.
Further, delay circuit of the present invention (or claiming integrating circuit) includes but not limited to also can have for other logical device or the circuit of delay function by the RC integrator.
The present invention is mainly by basic square wave source, d type flip flop-NOR gate-RC integrator combination, d type flip flop-with door-RC integrator combination, with door-RC integrator combination, produce tetra-groups of AU, BU, AD, BD for driving respectively the drive waveforms of power device on four brachium pontis of H bridge.
By basic square wave source of the present invention and d type flip flop, make the odd number time cycle of CLK and the forward position of even number time cycle can be respectively used to trigger the forward position that d type flip flop produces AU-1 and BU-1, the cycle of the odd number of CLK time cycle and even number time cycle has determined respectively the duty ratio of AU-1 and BU-1.The sequential relationship of CLK pulse and AU-1 and BU-1 is as shown in Fig. 5 a and 5b.The sequential relationship of AU-1 and BU-1 as shown in Figure 6.Perhaps opposite, the forward position of the odd number of CLK time cycle and even number time cycle is respectively used to the forward position of triggering for generating BU-1 and AU-1, and the cycle of the odd number of CLK time cycle and even number time cycle has determined respectively the duty ratio of BU-1 and AU-1.
By the middle modulation module in circuit of the present invention, make the odd number time cycle of CLK and even number time cycle produce respectively the high level of AU-2 and the high level of BU-2, the duty ratio of CLK has determined the duty ratio of AU-2 and BU-2; When the duty ratio of the odd number of controlling respectively CLK time cycle and even number time cycle, just can control respectively independently duty ratio of AU-2 and BU-2; The sequential relationship of CLK pulse and AU-2 and BU-2 is as shown in Fig. 7 a and 7b.The sequential relationship of AU-2 and BU-2 as shown in Figure 8.Perhaps opposite, make the odd number time cycle of CLK and even number time cycle produce respectively the high level of BU-2 and the high level of AU-2, the duty ratio of CLK has determined the duty ratio of BU-2 and AU-2; When the duty ratio of the odd number of controlling respectively CLK time cycle and even number time cycle, just can control respectively independently duty ratio of BU-2 and AU-2.
By the control module in circuit of the present invention, make the integrator that is formed by R1, C1 produce time delay to the AU-1 forward position, generate final control waveform AD; Also make the integrator that is formed by R2, C2 produce time delay to the BU-1 forward position, generate final control waveform BD; Wherein, the pulse sequence relation of AU-1 and AD, BU-1 and BD is respectively as shown in Fig. 9 a and Fig. 9 b.
By the final modulation module in circuit of the present invention, AU-2 and BD, BU-2 and AD are carried out to logical operation and time delay, produce final control waveform AU and BU.And the safety that the forward position that following effect: AU is arranged results from after the BD forward position the soonest opens interval, and this opens safely the RC value decision of interval by R3, C3; Equally, the safety that the forward position of BU results from after the AD forward position is the soonest opened interval, and this opens safely the RC value decision of interval by R4, C4; The sequential relationship of AU and BD as shown in figure 10.
The function that square-wave pulse drive waveforms modulation circuit of the present invention is realized is: the frequency by regulating and controlling CLK has realized the frequency adjustment to four groups of control waveform AU, BU, AD, BD; By the duty ratio of regulating and controlling CLK waveform, realized the adjusting to the duty ratio of AU and BU; By the cycle of regulating and controlling CLK odd even time cycle, realized the adjusting to the duty ratio of AD, BD.
Above-mentioned four groups of control waveform AU, BU, AD, BD are applied to the H bridge circuit in Fig. 1, result as shown in figure 11:
By the frequency of regulating and controlling CLK, realize the adjusting to H bridge output square-wave pulse cycle T;
The duty ratio of time cycle of the odd number by regulating and controlling CLK, realized the adjusting to H bridge output square-wave pulse parametric t 1;
The duty ratio of time cycle of the even number by regulating and controlling CLK, realized the adjusting to H bridge output square-wave pulse parametric t 2;
Between t1 and t2, of short duration interval △ t is determined by two aspect factors: the RC value of R3 and C3, R4 and C4, the value of parametric t 1 or t2; When △ t hour, by its size of RC value decision, the RC value has been guaranteed the safety of power device for preset parameter and has been opened interval; When △ t is larger, by t1 and t2 value, determine its size, t1 and t2 value are subjected to the Duty ratio control of CLK.
As can be seen from Figure 10, cycle, the duty ratio difference of the odd even of CLK time cycle, t1, the t2 parameter of corresponding H bridge output square-wave pulse, namely the cycle of square-wave pulse and duty ratio also can have corresponding variation thereupon.For example, the 1st cycle of CLK determined the t1_1 in first pulse high level, and the 2nd cycle of CLK determined the t2_1 in first pulses low, the like; Short time between t1 and t2, every △ t, is subjected to the Duty ratio control of CLK, as the t1 of the △ in figure～△ t4.
Because main circuit of the present invention will be comprised of logic gates and RC element, in case parameter is determined, will reliablely and stablely one group of basic square wave source be modulated into to the drive waveforms of power device on four groups of H bridge brachium pontis, antijamming capability is stronger; And only needing to control one group of basic square wave source, the parameters that can regulate neatly H bridge square-wave pulse, be conducive to realize modularized design.
the appended graphic schematic diagram that illustrates of this specification, the device model, timing waveform, equal contents in order to coordinate specification to disclose only, for person skilled in the art scholar, understand and read, not in order to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the modification of any structure, the change of proportionate relationship, the adjustment of size, the RC value parameter changes, the device type alternation of signs, logic state circulation conversion, the logic state integral transformation, do not affecting under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents obtains in the scope that can contain, logic state circulation conversion refers to by in critical path, increasing the logical operation device and does not but make logic state that the way that changes occurs, such as, two NAND gate are serially connected and are equal to one and door, it is constant that two not gates are serially connected in same path logic state.Due to the difference of witness mark, may obtain opposite logical relation, can not be as limiting the enforceable qualifications of the present invention.Simultaneously, in this specification, quote as " on ", D score, " left side ", " right side ", " centre " reach the term of " " etc., also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the present invention.
In sum, the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not be used to limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and know that usually the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (9)
1. a square-wave pulse drive waveforms modulation circuit, is characterized in that, described square-wave pulse drive waveforms modulation circuit comprises:
Basic square wave source, the square wave driving pulse CLK that output frequency is adjustable, duty ratio is adjustable;
D type flip flop, be connected with described basic square wave source, and described square wave driving pulse CLK is modulated into to two antipodal square-wave pulses of polarity, is respectively first party wave impulse AU-1 and second party wave impulse BU-1;
Middle modulation module, be connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2;
Control module, be connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD;
Final modulation module, be connected respectively with described control module with described middle modulation module, under the control of described the second control waveform BD, described third party's wave impulse AU-2 is modulated into to the 3rd control waveform AU; Under the control of described the first control waveform AD, described cubic wave impulse BU-2 is modulated into to the 4th control waveform BU.
2. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: in the middle of described, modulation module is the NOR gate combination, described NOR gate combination is connected with described d type flip flop, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to third party's wave impulse AU-2 and cubic wave impulse BU-2; The high level of described third party's wave impulse AU-2 and cubic wave impulse BU-2 does not overlap.
3. square-wave pulse drive waveforms modulation circuit according to claim 2, it is characterized in that: described NOR gate combination comprises NOR gate U2A and NOR gate U2B in parallel, the input of NOR gate U2A is connected with the first party wave impulse AU-1 output of d type flip flop, another input of NOR gate U2A is connected with the square wave driving pulse CLK output of basic square wave source, the output output third party wave impulse AU-2 of NOR gate U2A; The input of NOR gate U2B is connected with the second party wave impulse BU-1 output of d type flip flop, another input of NOR gate U2B is connected with the square wave driving pulse CLK output of basic square wave source, the cubic wave impulse BU-2 of output output of NOR gate U2B.
4. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: described control module be first with door combination, described first is connected with described d type flip flop with the door combination, and described first party wave impulse AU-1 and second party wave impulse BU-1 are modulated into respectively to the first control waveform AD and the second control waveform BD; Described first with door combination in an input with door be provided with delay circuit; Described the first control waveform AD has predetermined forward position time delay with respect to first party wave impulse AU-1; Described the second control waveform BD has predetermined forward position time delay with respect to second party wave impulse BU-1.
5. square-wave pulse drive waveforms modulation circuit according to claim 4, it is characterized in that: described first comprises NAND gate U3A in parallel and NAND gate U3B with the door combination, NAND gate U3A connects with a NAND gate U3C, and NAND gate U3B connects with a NAND gate U3D; The input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop, and another input of NAND gate U3A is connected with the first party wave impulse AU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3C all are connected with the output of NAND gate U3A, output output the first control waveform AD of NAND gate U3C; The input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop, and another input of NAND gate U3B is connected with the second party wave impulse BU-1 output of described d type flip flop by a delay circuit; Two inputs of NAND gate U3D all are connected with the output of NAND gate U3B, output output the second control waveform BD of NAND gate U3D.
6. square-wave pulse drive waveforms modulation circuit according to claim 1, it is characterized in that: described final modulation module be second with door combination, described second is connected respectively with the door combination with described first with described NOR gate combination with the door combination, to described third party's wave impulse AU-2 and the second control waveform BD, cubic wave impulse BU-2 and the first control waveform AD carry out logical operation and time delay, produce the 3rd control waveform AU and the 4th control waveform BU, the safety that the forward position of described the 3rd control waveform AU results from after the second control waveform BD forward position is the soonest opened interval, the safety that the forward position of described the 4th control waveform BU results from after the first control waveform AD forward position is the soonest opened interval.
7. square-wave pulse drive waveforms modulation circuit according to claim 6, it is characterized in that: described second comprises NAND gate U4A in parallel and NAND gate U4B with the door combination, NAND gate U4A connects with a NAND gate U4C, and NAND gate U4B connects with a NAND gate U4D; The input of NAND gate U4A is connected with third party's wave impulse AU-2 output of described middle modulation module, and another input of NAND gate U4A is connected with the second control waveform BD output of described control module by a delay circuit; Two inputs of NAND gate U4C all are connected with the output of NAND gate U4A, output output the 3rd control waveform AU of NAND gate U4C; The input of NAND gate U4B is connected with the cubic wave impulse BU-2 output of described middle modulation module, and another input of NAND gate U4B is connected with the first control waveform AD output of described control module by a delay circuit; Two inputs of NAND gate U4D all are connected with the output of NAND gate U4B, output output the 4th control waveform BU of NAND gate U4D.
8. according to claim 5 or 7 described square-wave pulse drive waveforms modulation circuits is characterized in that: described NAND gate U3A, NAND gate U3B, NAND gate U3C, NAND gate U3D, NAND gate U4A, NAND gate U4B, NAND gate U4C, inclusive NAND door U4D for Si Mite, trigger input and gate device.
9. according to claim 4,5 or 7 described square-wave pulse drive waveforms modulation circuits, it is characterized in that: described delay circuit is the RC integrator.
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