CN102624271B

CN102624271B - Five-level inverted topology unit and five-level inverter

Info

Publication number: CN102624271B
Application number: CN201210097639.7A
Authority: CN
Inventors: 汪洪亮; 赵为; 张彦虎
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2012-04-01
Filing date: 2012-04-01
Publication date: 2014-07-16
Anticipated expiration: 2032-04-01
Also published as: CN102624271A

Abstract

The invention provides a five-level inverted topology unit. The five-level inverted topology unit comprises six switch tubes and four diodes, wherein the switch tubes are reversely connected in parallel with diodes, and the four diodes are connected in series with the switch tubes. Compared with the prior art which needs to take pressure equalizing measures and employ a larger RC (Resistor-Capacitor) absorption circuit to prevent two ends of part of the diodes from overvoltage so as to result in huge volume, increased cost, higher loss and lower efficiency of an inverter, less semiconductor devices, smaller volume, lower cost, less loss and higher efficiency of the entire inverter are ensured when single-phase and multi-phase applications are realized and a current path is guaranteed.

Description

A kind of five level inverse conversion topology unit and five-electrical level inverters

Technical field

The application relates to electric and electronic technical field, particularly a kind of five level inverse conversion topology unit and five-electrical level inverters.

Background technology

The large capacity occasion of middle pressure, multi-electrical level inverter is widely used, and current five-electrical level inverter is mainly diode-clamped.Below diode-clamped five-level inverter is introduced.

Referring to Fig. 1, this figure is the five-electrical level inverter topological diagram of the diode-clamped that provides in prior art.

Shown in Fig. 1 is the topological structure of half-bridge five-electrical level inverter.Diode is used to each switching tube to carry out voltage clamp.For example, the first diode DB1 is for being positioned at the voltage clamp of switch transistor T 1 lower end the lower end of the first capacitor C 1; The second diode DB2 is for being positioned at the voltage clamp of switch transistor T 5 lower ends the lower end of the first capacitor C 1.Other diodes DB3, DB4, DB5 and DB6 are similar, do not repeat them here.

Because clamping diode need to be blocked many times of level voltages, conventionally need the diode series connection of a plurality of same nominal values, these diodes are together in series and jointly bear the voltage that in Fig. 1, diode DB2 bears.Due to the dispersiveness of diode and the impact of stray parameter, the pressure that the diode that nominal value is identical can bear is difference to some extent also, is together in series like this and may causes the diode two ends overvoltage having.Therefore, need to all press measure and very large RC absorbing circuit, but will cause systems bulky like this, cost increases, and loss is more, and efficiency is lower.

Summary of the invention

The application's technical problem to be solved is to provide a kind of five level inverse conversion topology unit and five-electrical level inverters, and bulky in order to solve in prior art inverter system, cost increases, and loss is more, the technical problem that efficiency is lower.

The application provides a kind of five level inverse conversion topology unit, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of switching tube described in each;

The first direct-flow input end M1 of this topology unit is connected with the second direct-flow input end M2 of this topology unit by diode DA1, switch transistor T A1, switch transistor T 1, switch transistor T 2, switch transistor T B1 and the diode DB1 connecting successively;

The 3rd direct-flow input end M3 of this topology unit is connected with the 4th direct-flow input end M4 of this topology unit with switch transistor T B2 by the switch transistor T A2 connecting successively;

The connecting line of switch transistor T 2 and switch transistor T B1 is connected with the connecting line of switch transistor T 1 with switch transistor T A1 with diode D1 by the diode D2 connecting successively;

The 5th direct-flow input end M5 of this topology unit is connected with the connecting line of diode D1 with diode D2;

The connecting line of switch transistor T A2 and switch transistor T B2 is connected with the first ac output end of this topology unit, and diode D2 and the connecting line of diode D1 and the second ac output end of this topology unit are connected.

The application also provides a kind of five-electrical level inverter, comprises above topology unit, wherein:

The first direct current positive level PV1+ is connected with the first direct-flow input end M1, the second direct current positive level PV2+ is connected with the 3rd direct-flow input end M3, direct current zero level PV0 is connected with the 5th direct-flow input end M5, the first direct current negative level PV1-is connected with the second direct-flow input end M2, and the second direct current negative level PV2-is connected with the 4th direct-flow input end M4;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 is connected with the connecting line of the second direct-flow input end M2 with the first direct current negative level PV1-with capacitor C B 1 by the capacitor C A1 connecting successively;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 is connected with the connecting line of the 4th direct-flow input end M4 with the second direct current negative level PV2-with capacitor C B2 by the capacitor C A2 connecting successively;

The connecting line of capacitor C A1 and capacitor C B 1 is connected and is connected with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2;

The first ac output end of topology unit is connected with the first ac output end of this inverter, and the second ac output end of topology unit is connected with the second ac output end of this inverter.

The application also provides another kind of five level inverse conversion topology unit, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

The first direct-flow input end M1 of this topology unit is connected with the second direct-flow input end M2 of this topology unit by switch transistor T 1, switch transistor T A1, diode DA1, diode DB1, switch transistor T B1 and the switch transistor T 2 of connecting successively;

The 3rd direct-flow input end M3 of this topology unit is connected with the 4th direct-flow input end M4 of this topology unit with switch transistor T B2 by the switch transistor T A2 connecting successively; The connecting line of switch transistor T 2 and switch transistor T B 1 is connected with the connecting line of switch transistor T 1 with switch transistor T A1 with diode D1 by the diode D2 connecting successively; The 5th direct-flow input end M5 of this topology unit is connected with the connecting line of diode D1 with diode D2;

The application also provides another kind of five-electrical level inverter, comprises above topology unit, wherein:

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 is connected with the connecting line of the second direct-flow input end M2 with the first direct current negative level PV1-with capacitor C B1 by the capacitor C A1 connecting successively;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 is connected with the connecting line of the 4th direct-flow input end M4 with the second direct current negative level PV2-with capacitor C B2 by the capacitor C A2 connecting successively; The connecting line of capacitor C A1 and capacitor C B1 is connected and is connected with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2; The first ac output end of topology unit is connected with the first ac output end of this inverter, and the second ac output end of topology unit is connected with the second ac output end of this inverter.

The application also provides a kind of five-electrical level inverter, comprises two above-mentioned topology unit: the first topology unit and the second topology unit, wherein:

The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit and the second topology unit; The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit and the second topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of the first topology unit or the second topology unit is connected with the connecting line of the second direct-flow input end M2 with the first direct current negative level PV1-of the first topology unit or the second topology unit with capacitor C B1 by the capacitor C A1 connecting successively;

The second direct current positive level PV2+ is connected with each the 3rd direct-flow input end M3 of the first topology unit and the second topology unit; The second direct current negative level PV2-is connected with each the 4th direct-flow input end M4 of the first topology unit and the second topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of the first topology unit or the second topology unit is connected with the connecting line of the 4th direct-flow input end M4 with the second direct current negative level PV2-of the first topology unit or the second topology unit with capacitor C B2 by the capacitor C A2 connecting successively;

Direct current zero level PV0 is connected with each the 5th direct-flow input end M5 of the first topology unit and the second topology unit; The connecting line of capacitor C A1 and capacitor C B1 is connected with the connecting line of capacitor C A2 and capacitor C B2 and is connected with the 5th direct-flow input end M5 of the first topology unit or the second topology unit;

The first topology unit is connected with the second ac output end with the first ac output end of this inverter respectively with each first ac output end in the second topology unit.

The application also provides a kind of five-electrical level inverter, comprises three above-mentioned topology unit: the first topology unit, the second topology unit and the 3rd topology unit; The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit, the second topology unit and the 3rd topology unit; The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of the first topology unit, the second topology unit or the 3rd topology unit is connected with the connecting line of the second direct-flow input end M2 with the first direct current negative level PV1-of the first topology unit, the second topology unit or the 3rd topology unit with capacitor C B1 by the capacitor C A1 connecting successively;

The second direct current positive level PV2+ is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit and the 3rd topology unit;

The second direct current negative level PV2-is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit and the 3rd topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of the first topology unit, the second topology unit or the 3rd topology unit is connected with the connecting line of the 4th direct-flow input end M4 with the second direct current negative level PV2-of the first topology unit, the second topology unit or the 3rd topology unit with capacitor C B2 by the capacitor C A2 connecting successively;

Direct current zero level PV0 is connected with each the 5th direct-flow input end M5 of the first topology unit, the second topology unit and the 3rd topology unit;

The connecting line of capacitor C A1 and capacitor C B1 is connected with the connecting line of capacitor C A2 and capacitor C B2 and is connected with the 5th direct-flow input end M5 of the first topology unit, the second topology unit or the 3rd topology unit;

Each first ac output end in the first topology unit, the second topology unit and the 3rd topology unit is connected with the first ac output end, the second ac output end and the 3rd ac output end of this inverter respectively.

The application also provides a kind of five-electrical level inverter, comprises four above-mentioned topology unit: the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of the first topology unit, the second topology unit, the 3rd topology unit or the 4th topology unit is connected with the connecting line of the second direct-flow input end M2 with the first direct current negative level PV1-of the first topology unit, the second topology unit, the 3rd topology unit or the 4th topology unit with capacitor C B1 by the capacitor C A1 connecting successively;

The second direct current positive level PV2+ is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The second direct current negative level PV2-is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of the first topology unit, the second topology unit is connected with the connecting line of the 4th direct-flow input end M4 with the second direct current negative level PV2-of the first topology unit, the second topology unit, the 3rd topology unit or the 4th topology unit with capacitor C B2 by the capacitor C A2 connecting successively;

Direct current zero level PV0 is connected with each the 5th direct-flow input end M5 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of capacitor C A1 and capacitor C B1 is connected with the connecting line of capacitor C A2 and capacitor C B2 and is connected with the 5th direct-flow input end M5 of the first topology unit, the second topology unit, the 3rd topology unit or the 4th topology unit;

Each first ac output end in the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit is connected with the first ac output end, the second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.

From the above, the five level inverse conversion topology unit that the application provides comprise switching tube and four diodes of connecting with switching tube of six reverse parallel connection diodes, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause inverter bulky compared with large RC absorbing circuit, cost increases, the problem that loss is more and efficiency is lower, the five level inverse conversion topology unit that the application provides when realizing single-phase and heterogeneous application when guaranteeing to provide path for electric current, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, loss is simultaneously less, efficiency is higher.

Certainly, arbitrary product of enforcement the application might not need to reach above-described all advantages simultaneously.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiment of the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is diode-clamped five-level inverter topology figure in prior art;

The topological diagram of a kind of five level inverse conversion topology unit embodiment mono-that Fig. 2 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 3 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 4 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 5 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 6 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 7 provides for the application in the first operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 8 provides for the application in the second operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Fig. 9 provides for the application in the 3rd operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Figure 10 provides for the application in the 4th operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Figure 11 provides for the application in the 5th operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Figure 12 provides for the application in the 6th operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Figure 13 provides for the application in the 7th operation mode;

The topological diagram of a kind of five-electrical level inverter embodiment bis-that Figure 14 provides for the application in the 8th operation mode;

The topological diagram of a kind of five level inverse conversion topology unit embodiment tri-that Figure 15 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment tetra-that Figure 16 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment tetra-that Figure 17 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment tetra-that Figure 18 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment tetra-that Figure 19 provides for the application;

The isoboles of a kind of five level inverse conversion topology unit embodiment mono-that Figure 20 provides for the application;

The isoboles of a kind of five level inverse conversion topology unit embodiment tri-that Figure 21 provides for the application;

Figure 22 is the topological diagram of a kind of five-electrical level inverter embodiment five of passing through of the application;

Figure 23 is another topological diagram of a kind of five-electrical level inverter embodiment five of passing through of the application;

Figure 24 is the topological diagram of a kind of five-electrical level inverter embodiment six of passing through of the application;

Figure 25 is another topological diagram of a kind of five-electrical level inverter embodiment six of passing through of the application;

Figure 26 is another topological diagram of a kind of five-electrical level inverter embodiment six of passing through of the application;

Figure 27 is the topological diagram of a kind of five-electrical level inverter embodiment seven of passing through of the application;

Figure 28 is another topological diagram of a kind of five-electrical level inverter embodiment seven of passing through of the application.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Embodiment based in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the application's protection.

With reference to figure 2, it shows the topological diagram of the topology unit embodiment mono-of a kind of five-electrical level inverter that the application provides, and the topology unit of described five-electrical level inverter comprises: switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Wherein, the switching tube of above topology unit can be managed for IGBT, MOSFET manages, IGCT manages or IEGT pipe.Be understandable that, above switching tube also can be selected the switching tube of other types.Can be diode independently with the diode of switching tube reverse parallel connection above, can be also the diode together with switching tube encapsulation and integration.

From the above, in corresponding prior art, need to adopt and all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five-electrical level inverter of the five level inverse conversion topology unit that provide based on the application when realizing single-phase and heterogeneous application when guaranteeing to provide path for electric current, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, loss is simultaneously less, and efficiency is higher.

With reference to figure 3, it shows the topological diagram of a kind of five-electrical level inverter embodiment bis-that the application provides, and based on the embodiment of the present application one, the embodiment of the present application two comprises a topology unit as described in embodiment mono-, wherein:

The connecting line of capacitor C A1 and capacitor C B1 is connected and is connected with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2;

Wherein, as shown in Figure 4, above-mentioned five level can add that two DC/DC booster circuits obtain by two DC power supply PVM and PVN, concrete, two DC power supply PVM and the positive and negative docking of PVN, generate the first direct current positive level PV1+, the first direct current negative level PV1-and direct current zero level PV0, two DC power supply PVM are respectively connected a DC/DC booster circuit with PVN, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

With reference to figure 5, it shows the another kind of structural representation of the embodiment of the present application two, and based on above-mentioned embodiment as shown in Figure 4, the five-electrical level inverter that the application provides also comprises inductance L 501 and capacitor C 501, wherein:

The connecting line of switch transistor T A2 and switch transistor T B2 is connected with the connecting line of diode D2 with diode D1 with capacitor C 501 by the inductance L 501 of connecting successively;

The connecting line of inductance L 501 and capacitor C 501 is connected with the first ac output end of this inverter.

Above-mentioned five level as shown in Figure 4 can also obtain by mode as described in Figure 6, DC power supply PVS produces the first direct current positive level PV1+ and the first direct current negative level PV1-, dividing potential drop effect by capacitor C A1 and capacitor C B1 produces direct current zero level PV0, DC power supply PVS two ends respectively connect a DC/DC booster circuit, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

Have above-mentioned knownly, the application realizes the practical application of the embodiment of the present application two by increasing inductance and electric capacity, reduce the harmonic wave of the output current of the embodiment of the present application two, improves the embodiment of the present application two in the accuracy of carrying out current conversion.

The syndeton class of the syndeton of the five-electrical level inverter shown in Fig. 5 and inductance and electric current formed filtration module and five-electrical level inverter as shown in Figure 6 and inductance and electric current formed filtration module this, at this, no longer set forth.

From the above, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five-electrical level inverter embodiment bis-that the application provides, be the embodiment of the present application one when realizing and guaranteeing to provide path for electric current when single-phase, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, loss is simultaneously less, and efficiency is higher.

Wherein, the five-electrical level inverter embodiment bis-that the application provides, when realizing the conversion of direct current and alternating current, comprises eight operation modes, below in conjunction with accompanying drawing, the eight kinds of operation modes of the five-electrical level inverter embodiment bis-shown in Fig. 5 is carried out to labor.

Wherein, diode DA2 and switch transistor T A2 reverse parallel connection, diode DB2 and switch transistor T B2 reverse parallel connection.Wherein, the operation mode of the embodiment of the present application two forms and can realize by sequencing control.

With reference to figure 7, it shows the topological diagram of the first operation mode of the five-electrical level inverter embodiment bis-that the application provides.The first operation mode: switch transistor T 1 conducting, rest switch pipe all ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

The path of electric current is: D1-T1-L501-VG-D1.

With reference to figure 8, it shows the topological diagram of five-electrical level inverter embodiment 2 second operation modes that the application provides.The second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV1+-DA1-TA1-T1-L501-V _g-PV0.

With reference to figure 9, it shows the topological diagram of five-electrical level inverter embodiment 2 the 3rd operation mode that the application provides.The 3rd operation mode: switch transistor T A2 conducting, rest switch pipe all ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV2+-TA2-L501-V _g-PV0.

Wherein, described the 3rd operation mode can also be: switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends, after the second operation mode finishes, switch transistor T 1 and switch transistor T A1 can select not give closing, now the 3rd operation mode with only have the current path of switch transistor T A2 conducting consistent, the loss in the time of can reducing thus switching tube and operate between conducting and closure.

With reference to Figure 10, it shows the topological diagram of the 4th operation mode of the five-electrical level inverter embodiment bis-that the application provides.The 4th operation mode: switch transistor T 2 conductings, rest switch pipe all ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: T2-D2-V _g-L501-T2.

With reference to Figure 11, it shows the topological diagram of the 5th operation mode of the five-electrical level inverter embodiment bis-that the application provides.The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _g-L501-T2-TB1-DB1-PV1-.

With reference to Figure 12, it shows the topological diagram of the 6th operation mode of the five-electrical level inverter embodiment bis-that the application provides.The 6th operation mode: switch transistor T B2 conducting, rest switch pipe all ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _g-L501-TB2-PV2-.

Wherein, described the 6th operation mode can also be: switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends, after the 5th operation mode finishes, switch transistor T 2 and switch transistor T B1 can select not give closing, now the 6th operation mode with only have the current path of switch transistor T B2 conducting consistent, the loss in the time of can reducing thus switching tube and operate between conducting and closure.

With reference to Figure 13, it shows the topological diagram of five-electrical level inverter embodiment 2 the 7th operation mode that the application provides.The 7th operation mode: switch transistor T 1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch pipe all ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CA2-V _g-L501-DA2-CA2.

With reference to Figure 14, it shows the topological diagram of the 8th operation mode of the five-electrical level inverter embodiment bis-that the application provides.The 8th operation mode: switch transistor T 2 conductings, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch pipe all ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CB2-DB2-L501-V _g-CB2.

In above-mentioned the second operation mode, switch transistor T 1 and switch transistor T A1 bear the first positive level PV1+ jointly; In the 5th operation mode, switch transistor T 2 and switch transistor T B1 bear the first negative level PV1-jointly, and with respect to the situation of single switching transistor in prior art, the voltage stress that switching tube components and parts bear is little, less to the loss of components and parts.

Have above-mentioned knownly, five-electrical level inverter embodiment that the application provides bis-adopts the thinking of five Level Technology matching sine waves, and with respect to prior art, common-mode voltage is little, and ripple loss is lower, and conversion efficiency is higher.

Wherein, eight operation modes of the five level inverse conversion topology unit embodiment mono-that the application provides when realizing the conversion of direct current and alternating current, similar with the operation mode shown in Fig. 7 to Figure 14 in the embodiment of the present application two, do not repeat them here.

With reference to Figure 15, it shows the topological diagram of a kind of five level inverse conversion topology unit embodiment tri-that the application provides, and described five level inverse conversion topology unit comprise: switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

From the above, in corresponding prior art, need to adopt and all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five-electrical level inverter of the five level inverse conversion topology unit embodiment tri-that provide based on the application when realizing single-phase and heterogeneous application when guaranteeing to provide path for electric current, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, loss is simultaneously less, and efficiency is higher.

With reference to Figure 16, it shows the topological diagram of a kind of five-electrical level inverter embodiment tetra-that the application provides, and based on the embodiment of the present application three, the embodiment of the present application four comprises a topology unit as described in embodiment tri-, wherein:

Wherein, as shown in figure 17, above-mentioned five level can add that two DC/DC booster circuits obtain by two DC power supply PVM and PVN, concrete, two DC power supply PVM and the positive and negative docking of PVN, generate the first direct current positive level PV1+, the first direct current negative level PV1-and direct current zero level PV0, two DC power supply PVM are respectively connected a DC/DC booster circuit with PVN, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

Above-mentioned five level can also obtain by mode as described in Figure 19, DC power supply PVS produces the first direct current positive level PV1+ and the first direct current negative level PV1-, dividing potential drop effect by capacitor C A1 and capacitor C B1 produces direct current zero level PV0, DC power supply PVS two ends respectively connect a DC/DC booster circuit, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

With reference to Figure 18, it shows the another kind of structural representation of the embodiment of the present application four, and based on above-described embodiment, the five-electrical level inverter that the application provides also comprises inductance L 1801 and capacitor C 1801, wherein:

The connecting line of switch transistor T A2 and switch transistor T B2 is connected with the connecting line of diode D2 with diode D1 with capacitor C 1801 by the inductance L 1801 of connecting successively;

The connecting line of inductance L 1801 and capacitor C 1801 is connected with the first ac output end of this inverter.

Have above-mentioned knownly, the application realizes the practical application of the embodiment of the present application four by increasing inductance and electric capacity, reduce the harmonic wave of the output current of the embodiment of the present application four, improves the embodiment of the present application four in the accuracy of carrying out current conversion.

The syndeton of the five-electrical level inverter based on as shown in figure 19 and inductance and electric current formed filtration module and the syndeton class in Figure 18 this, at this, no longer set forth.

From the above, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five-electrical level inverter embodiment tetra-that the application provides, be the embodiment of the present application three when realizing and guaranteeing to provide path for electric current when single-phase, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, loss is simultaneously less, and efficiency is higher.

Wherein, the five-electrical level inverter embodiment tetra-that the application provides, when realizing the conversion of direct current and alternating current, comprises eight operation modes, eight kinds of operation modes is carried out to labor below:

The first operation mode: switch transistor T A1 conducting, rest switch pipe all ends; The path of electric current is: D1-TA1-DA1-L1801-VG-D1.

The second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends; Current path is: PV1+-T1-TA1-DA1-L1801-V _g-PV0.

The 3rd operation mode: switch transistor T A2 conducting, rest switch pipe all ends; Current path is: PV2+-TA2-L1801-V _g-PV0.

Wherein, described the 3rd operation mode can also be: switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends, after the second operation mode finishes, switch transistor T 1 and switch transistor T A1 can select not give closing, now the 3rd operation mode with only have the operation mode of switch transistor T A2 conducting consistent, the loss in the time of can reducing thus switching tube and operate between conducting and closure.

The 4th operation mode: switch transistor T B1 conducting, rest switch pipe all ends; Current path is: DB1-TB1-D2-V _g-L1801-DB1.

The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends; Current path is: PV0-V _g-L1801-DB1-TB1-T2-PV1-.

The 6th operation mode: switch transistor T B2 conducting, rest switch pipe all ends; Current path is: PV0-V _g-L1801-TB2-PV2-.

Wherein, described the 6th operation mode can also be: switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends, after the 5th operation mode finishes, switch transistor T 2 and switch transistor T B1 can select not give closing, now the 6th operation mode with only have the operation mode of switch transistor T B2 conducting consistent, the loss in the time of can reducing thus switching tube and operate between conducting and closure.

The 7th operation mode: switch transistor T A1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch pipe all ends; Current path is: CA2-V _g-L1801-DA2-CA2.

The 8th operation mode: switch transistor T B1 conducting, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch pipe all ends; Current path is: CB2-DB2-L1801-V _g-CB2.

Have above-mentioned knownly, five-electrical level inverter embodiment that the application provides tetra-adopts the thinking of five Level Technology matching sine waves, and with respect to prior art, common-mode voltage is little, and ripple loss is lower, and conversion efficiency is higher.Wherein, eight operation modes of the five level inverse conversion topology unit embodiment tri-that the application provides when realizing the conversion of direct current and alternating current, similar with eight operation modes described in the embodiment of the present application four, do not repeat them here.

With reference to Figure 20, it shows five level inverse conversion topology unit embodiment mono-isoboleses that the application provides.In described isoboles, the first ac output end of described five level inverse conversion topology unit embodiment mono-is defined as to the AC exit of topology unit.

With reference to Figure 21, it shows five level inverse conversion topology unit embodiment tri-isoboleses that the application provides.In described isoboles, the first ac output end of described five level inverse conversion topology unit embodiment tri-is defined as to the AC exit of topology unit.

With reference to Figure 22, it shows the topological diagram of a kind of five-electrical level inverter embodiment five that the application provides, based on above-mentioned the embodiment of the present application one or the embodiment of the present application three, the embodiment of the present application five comprises that two as the topology unit of Figure 20 or two topology unit as described in Figure 21: the first topology unit and the second topology unit;

The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit and the second topology unit;

The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit and the second topology unit;

The second direct current positive level PV2+ is connected with each the 3rd direct-flow input end M3 of the first topology unit and the second topology unit;

The second direct current negative level PV2-is connected with each the 4th direct-flow input end M4 of the first topology unit and the second topology unit;

Direct current zero level PV0 is connected with each the 5th direct-flow input end M5 of the first topology unit and the second topology unit;

The connecting line of capacitor C A1 and capacitor C B1 is connected with the connecting line of capacitor C A2 and capacitor C B2 and is connected with the 5th direct-flow input end M5 of the first topology unit or the second topology unit;

The first topology unit is connected with the second ac output end with the first ac output end of this inverter respectively with each AC exit in the second topology unit.

Wherein, with reference to Figure 23, it shows another topological diagram of the embodiment of the present application five, and based on above-mentioned embodiment as described in Figure 22, described five-electrical level inverter also comprises inductance L 2301, inductance L 2302 and capacitor C 2301, wherein:

The AC exit of the first topology unit is connected with the AC exit of the second topology unit by inductance L 2301, capacitor C 2301 and the inductance L 2302 of connecting successively;

The connecting line of inductance L 2301 and capacitor C 2301 is connected with the first ac output end of this inverter, and capacitor C 2301 and the connecting line of inductance L 2302 and the second ac output end of this inverter are connected.

Have above-mentioned known, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, when the five level inverse conversion topology unit that the application provides are guaranteeing to provide path for electric current when realizing two-phase application, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, and loss is simultaneously less, and efficiency is higher.

With reference to Figure 24, it shows the topological diagram of a kind of five-electrical level inverter embodiment six that the application provides, based on above-mentioned the embodiment of the present application one or the embodiment of the present application three, the embodiment of the present application six comprises that three as the topology unit of Figure 20 or three topology unit as described in Figure 21: the first topology unit, the second topology unit and the 3rd topology unit;

The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit, the second topology unit and the 3rd topology unit; The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;

The second direct current positive level PV2+ is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit and the 3rd topology unit; The second direct current negative level PV2-is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit and the 3rd topology unit;

Each AC exit in the first topology unit, the second topology unit and the 3rd topology unit is connected with the first ac output end, the second ac output end and the 3rd ac output end of this inverter respectively.

Wherein, with reference to Figure 25, it shows another topological diagram of the embodiment of the present application six, based on above-mentioned embodiment as described in Figure 24, described five-electrical level inverter also comprises inductance L 2501, inductance L 2502, inductance L 2503, capacitor C 2501, capacitor C 2502 and capacitor C 2503, wherein:

The AC exit of the first topology unit is connected with the AC exit of the second topology unit by inductance L 2501, capacitor C 2501, capacitor C 2502 and the inductance L 2502 of connecting successively;

The AC exit of the 3rd topology unit is connected with the connecting line of capacitor C 2502 with capacitor C 2501 with capacitor C 2503 by the inductance L 2503 of connecting successively;

The connecting line of inductance L 2501 and capacitor C 2501 is connected with the first ac output end of this inverter, the connecting line of capacitor C 2502 and inductance L 2502 is connected with the second ac output end of this inverter, and the connecting line of inductance L 2503 and capacitor C 2503 is connected with the 3rd ac output end of this inverter.

Have above-mentioned known, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five level inverse conversion topology unit that the application provides when realizing three-phase applications when guaranteeing to provide path for electric current, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, and loss is simultaneously less, and efficiency is higher.

It should be noted that, above-mentioned five-electrical level inverter embodiment six is three-phase three-wire system (three brachium pontis) five-electrical level inverter.

With reference to Figure 26, it shows the another kind of topological diagram of the embodiment of the present application six, based on above-mentioned embodiment as described in Figure 25, wherein:

The connecting line of capacitor C 2501, capacitor C 2502 and capacitor C 2503 is connected with direct current zero level PV0.It should be noted that, five-electrical level inverter is as shown in figure 26 three-phase four-wire system (three brachium pontis) five-electrical level inverter.

With reference to Figure 27, it shows the topological diagram of a kind of five-electrical level inverter embodiment seven that the application provides, based on above-mentioned the embodiment of the present application one or the embodiment of the present application three, the embodiment of the present application seven comprises that four as the topology unit of Figure 20 or four topology unit as described in Figure 21: the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;

AC exit in the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit is connected with the first ac output end, the second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.

Wherein, with reference to Figure 28, it shows another topological diagram of the embodiment of the present application seven, based on above-mentioned embodiment as described in Figure 27, described five-electrical level inverter also comprises inductance L 2801, inductance L 2802, inductance L 2803, capacitor C 2801, capacitor C 2802 and capacitor C 2803, wherein:

The AC exit of the second topology unit is connected with the AC exit of the 3rd topology unit by inductance L 2801, capacitor C 2801, capacitor C 2802 and the inductance L 2802 of connecting successively; The AC exit of the 4th topology unit is connected with the connecting line of capacitor C 2802 with capacitor C 2801 with capacitor C 2803 by the inductance L 2803 of connecting successively;

The connecting line of capacitor C 2801, capacitor C 2802 and capacitor C 2803 is connected with the AC exit of the first topology unit; The connecting line of inductance L 2801 and capacitor C 2801 is connected with the first ac output end of this inverter, the connecting line of capacitor C 2802 and inductance L 2802 is connected with the second ac output end of this inverter, and the connecting line of inductance L 2803 and capacitor C 2803 is connected with the 3rd ac output end of this inverter.

Have above-mentioned known, with respect to needing in prior art to adopt, all press measure and prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficiency is lower compared with large RC absorbing circuit, the five level inverse conversion topology unit that the application provides were realizing for four corresponding used times when assurance provides path for electric current, the semiconductor device that guarantees whole inverter is less, small volume, cost is lower, and loss is simultaneously less, and efficiency is higher.It should be noted that, above-mentioned five-electrical level inverter embodiment seven is three-phase four-wire system (four brachium pontis) five-electrical level inverter.

It should be noted that, each embodiment in this specification all adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.

Finally, also it should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.

A kind of five level inverse conversion topology unit and the five-electrical level inverter that above the application are provided are described in detail, applied specific case herein the application's principle and execution mode are set forth, the explanation of above embodiment is just for helping to understand the application's method and core concept thereof; Meanwhile, for one of ordinary skill in the art, the thought according to the application, all will change in specific embodiments and applications, and in sum, this description should not be construed as the restriction to the application.

Claims

1. five level inverse conversion topology unit, is characterized in that, comprise switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1 and diode D2;

The connecting line of switch transistor T A2 and switch transistor T B2 is connected with the first ac output end of this topology unit, and diode D2 and the connecting line of diode D1 and the second ac output end of this topology unit are connected;

Eight operation modes corresponding to this five level inverse conversions topology unit are respectively:

The first operation mode: switch transistor T 1 conducting, rest switch pipe all ends;

The second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends;

The 3rd operation mode: switch transistor T A2 conducting, rest switch pipe all ends; Or switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting, rest switch pipe all ends;

The 4th operation mode: switch transistor T 2 conductings, rest switch pipe all ends;

The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends;

The 6th operation mode: switch transistor T B2 conducting, rest switch pipe all ends; Or switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting, rest switch pipe all ends;

The 7th operation mode: switch transistor T 1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch pipe all ends;

The 8th operation mode: switch transistor T 2 conductings, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch pipe all ends.

2. a five-electrical level inverter, is characterized in that, comprises that one as weighed the topology unit as described in 1, wherein:

3. five level inverse conversion topology unit, is characterized in that, comprise switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

The connecting line of switch transistor T A2 and switch transistor T B2 is connected with the first ac output end of this topology unit, and diode D2 and the connecting line of diode D1 and the second ac output end of this topology unit are connected; Eight operation modes corresponding to this five level inverse conversions topology unit are respectively:

The first operation mode: switch transistor T A1 conducting, rest switch pipe all ends;

The second operation mode: switch transistor T A1 and switch transistor T 1 conducting, rest switch pipe all ends;

The 3rd operation mode: switch transistor T A2 conducting, rest switch pipe all ends; Or switch transistor T A1, switch transistor T 1 and switch transistor T A2 conducting, rest switch pipe all ends;

The 4th operation mode: switch transistor T B1 conducting, rest switch pipe all ends;

The 5th operation mode: switch transistor T B1 and switch transistor T 2 conductings, rest switch pipe all ends;

The 6th operation mode: switch transistor T B2 conducting, rest switch pipe all ends; Or switch transistor T B1, switch transistor T 2 and switch transistor T B2 conducting, rest switch pipe all ends;

The 7th operation mode: switch transistor T A1 conducting, switch transistor T A1 and switch transistor T 1 conducting or switch transistor T A1 and switch transistor T 1 and switch transistor T A2 conducting, rest switch pipe all ends;

The 8th mode: switch transistor T B1 conducting, switch transistor T B1 and switch transistor T 2 conductings or switch transistor T B1 and switch transistor T 2 and switch transistor T B2 conducting, rest switch pipe all ends.

4. a five-electrical level inverter, is characterized in that, comprises that one as weighed the topology unit as described in 3, wherein:

5. a five-electrical level inverter, is characterized in that, comprises that two as weighed topology unit as described in 1 or two as weighed the topology unit as described in 3: the first topology unit and the second topology unit;

6. a five-electrical level inverter, is characterized in that, comprises that three as weighed topology unit as described in 1 or three as weighed the topology unit as described in 3: the first topology unit, the second topology unit and the 3rd topology unit;

The first direct current positive level PV1+ is connected with each first direct-flow input end M1 of the first topology unit, the second topology unit and the 3rd topology unit;

The first direct current negative level PV1-is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;

7. a five-electrical level inverter, is characterized in that, comprises that four as weighed topology unit as described in 1 or four as weighed the topology unit as described in 3: the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;