CN102437192B - N-type silicon-on-insulator transverse double-diffusion field effect transistor - Google Patents
N-type silicon-on-insulator transverse double-diffusion field effect transistor Download PDFInfo
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- CN102437192B CN102437192B CN201110404027.3A CN201110404027A CN102437192B CN 102437192 B CN102437192 B CN 102437192B CN 201110404027 A CN201110404027 A CN 201110404027A CN 102437192 B CN102437192 B CN 102437192B
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Abstract
The invention relates to an N-type silicon-on-insulator transverse double-diffusion field effect transistor, which comprises an N underlay, wherein buried oxygen is arranged on the N-type underlay, an N-type extension layer is arranged on the buried oxygen, an N-type buffering well and a P-type body area are arranged inside the N-type extension layer, an N-type anode area is arranged inside the N-type buffering well, an N-type cathode area and a P-type body contact area are arranged inside the P-type body area, a grid oxidized layer and a field oxidized layer are arranged within a given range on the surface of the N-type extension layer, the upper surface of the grid oxidized layer is provided with a polysilicon grid, and a passivation layer and a metal layer are also arranged within a given range on the surface of the transistor. The N-type silicon-on-insulator transverse double-diffusion field effect transistor is characterized in that: the N-type extension layer is also provided with a P-type well area, the P-type well area and the P-type body area form staircase-shaped P-type doping, the doping concentration of the P-type well area is lower than the doping concentration of the P-type body area, one side of the P-type well area is tangential to the field oxidized layer, and the other side of the P-type well area is pushed against the P-type body area. By adopting the structure, the field density and the collision ionization rate at a beak position can be remarkably reduced, so the output characteristics can be effectively improved.
Description
Technical field
The present invention relates generally to field of high voltage power semiconductor devices, specifically, is a kind of N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, is applicable to plasma flat-plate display device, half-bridge drive circuit and automobile production field etc. and drives chip.
Background technology
Along with improving constantly of people's living standard, electronic product constantly proposes new requirement for aspects such as volume, performance, reliability and costs.Silicon-on-insulator (Silicon On Insulator under these circumstances, SOI) technology has been come out, its unique insulating buried layer is isolated device and substrate completely, alleviated the impact of substrate on device, eliminated the risk of device generation latch-up (latch-up), alleviate to a great extent the ghost effect of silicon device, greatly improved the performance of device and circuit.Therefore the circuit that adopts SOI technique to make has the characteristics such as speed is high, low in energy consumption, high temperature resistant.
Horizontal dual pervasion field effect transistor is because the impact of blemish and various surface states makes the critical electric field of Si lower than in body, and the curvature effect that bring because of planar technique on surface exists peak electric field.These two factors have determined that puncturing of LDMOS class device easily occurs in surface; And a large amount of electron-hole pairs that the existence of surperficial peak electric field produces in the time of can causing avalanche breakdown enter thin gate oxide, thereby affect the reliability of device.So optimizing surface electric field just becomes the key of optimizing this class device.For the LDMOS of SOI, the existence of insulating buried layer brings two problems to the characteristic of device: the one, and oxygen buried layer increases device self-heating effect; The 2nd, owing to being subject to free charge, be the restriction of zero interface Gauss theorem, the voltage bearing in oxygen buried layer is limited.So, utilize the screen effect of electric charge local area field to carry out the high electric field in shielding insulation medium, to break through conventional electric field relation, longitudinal puncture voltage is increased, just become a kind of effective ways of this class high tension apparatus of design.
As everyone knows, the development of electronic technology is that semiconductor power device has been opened up application widely, power semiconductor is also being played the part of more and more important role in daily life, and weigh a kind of quality of power semiconductor, mainly comprise output, the transfer characteristic curve of device, and the degeneration of other the various parameters aspect such as whether.Meanwhile, the output characteristic curve of high tension apparatus, than low-voltage device, more easily departs from the situation of ideal conditions.Therefore, how not changing under the prerequisite of other parameters of device, better optimize output characteristic curve, make the operating state of high tension apparatus more stable, become an important topic of current power semiconductor device research.
The present invention is exactly for the problems referred to above, has proposed a kind of N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor structure.The device of this structure can significantly reduce electric field strength and the impact ionization rate at device beak place, thereby effectively improves output characteristic curve.
Summary of the invention
The invention provides a kind of N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor.
The present invention adopts following technical scheme: a kind of N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, comprise: N-type substrate, on N-type substrate, be provided with and bury oxygen, on oxygen, be provided with N-type epitaxial loayer burying, in the inside of N-type epitaxial loayer, be provided with N-type buffering trap and P type tagma, in N-type buffering trap, be provided with NXing Yang district, in P type tagma, be provided with NXing Yin district and P type body contact zone, on the surface of N-type epitaxial loayer, being provided with gate oxide and one end of field oxide and gate oxide and one end of field oxide offsets, extend and terminate in NXing Yin district in the other end XiangNXing Yin district of described gate oxide, extend and terminate in NXing Yang district in the other end XiangNXing Yang district of described field oxide, on the surface of gate oxide, be provided with the surface that polysilicon gate and polysilicon gate extend to field oxide, at field oxide, P type body contact zone, NXing Yin district, the surface in polysilicon gate HeNXing Yang district is provided with passivation layer, surface, NXing Yang district is connected with the first metal layer, in P type body contact zone, HeNXing Yin district is connected with the second metal level, it is characterized in that, in N-type epitaxial loayer and below gate oxide, be provided with P type well region, P type well region and P type tagma form stepped P type doping, the doping content of described P type well region is lower than P type tagma, and a side and the field oxide of P type well region are tangent, opposite side and P type tagma offset.
Compared with prior art, tool of the present invention has the following advantages:
(1), device of the present invention is also provided with P type well region 15 on N-type epitaxial loayer 3, and P type well region 15 and P type tagma 14 form stepped P type doping (participating in accompanying drawing 2), so just make the radius of curvature at beak place obviously diminish, the electric field strength at this place also obviously reduces (referring to accompanying drawing 3).
(2) when, benefit of the present invention is to reduce the electric field strength at field oxide beak place, can also reduce the impact ionization rate at this place, thereby reduced the risk that device generation hot carrier degradation lost efficacy, also promoted the ability of the reverse-biased stress of device high temperature resistance (HTRB), and then improved the reliability of device, extended the useful life of device.Accompanying drawing 4 shows that the beak place impact ionization rate adopting after device architecture of the present invention obviously reduces.
(3), the output characteristic curve of device of the present invention had obvious improvement than general device, the curve of saturation region drain current becomes smooth, more approaching with theoretical situations.Main cause is that the impact ionization rate at beak place declines, and ion produces also still less, because the impact of colliding the ion pair drain current producing reduces.Accompanying drawing 5 shows and adopted after device architecture of the present invention, the output characteristic curve of device be improved significantly.
(4), device of the present invention adopts high pressure SOI technique, in this technique, high-voltage P-type MOS device used includes the structure of similar P type well region 15; Therefore, manufacture craft of the present invention can with existing CMOS process compatible, can not increase extra reticle and processing step, can not increase cost yet.
(5), device of the present invention can not only improve output characteristic curve effectively, also can not exert an influence to other performance parameters of device.For example, although P type tagma 15 is tangent with field oxide 10, due to the effect that oxide layer surface is inhaled boron and arranged phosphorus, make the variation of threshold voltage of device very little, negligible.Accompanying drawing 6 shows that the threshold voltage variation adopting after device architecture of the present invention is very little.In addition, the reverse breakdown voltage of device can be because not adopting device architecture of the present invention to change yet, and result is with reference to accompanying drawing 7.
Accompanying drawing explanation
Fig. 1 is profile, illustrates the device profile structure of general N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor.
Fig. 2 is profile, illustrates the device profile structure of the N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor after the present invention improves.
Fig. 3 is the comparison diagram that longitudinal electric field located longitudinal electric field and general structure device " beak " and locate by device of the present invention " beak ".Can find out that device of the present invention has obvious reduction in the longitudinal electric field at this place.
Fig. 4 is the comparison diagram of impact ionization rate under impact ionization rate and general structure device operating state under device operating state of the present invention.Can find out that the impact ionization rate that device of the present invention is located at " beak " has obvious reduction.
Fig. 5 is the comparison diagram of device output characteristic curve of the present invention and general device output characteristic curve.The output characteristic curve that can find out device of the present invention is more excellent, and the trend that upwarps of saturation region has significantly and weakens.
Fig. 6 is the comparison diagram of device threshold voltage of the present invention and general device threshold voltage.The threshold voltage difference that can find out both is very little, approximate can ignoring.
Fig. 7 is the reverse breakdown voltage of device of the present invention and the reverse breakdown voltage comparison diagram of general device.Can find out that both almost do not have difference.Complex chart 6 and Fig. 7, i.e. the present invention, when having improved device output characteristic curve, does not almost affect other performance parameters of device.
Embodiment
Below in conjunction with accompanying drawing 2, the present invention is elaborated, a kind of N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, comprise: N-type substrate 1, on N-type substrate 1, be provided with and bury oxygen 2, on oxygen 2, be provided with N-type epitaxial loayer 3 burying, in the inside of N-type epitaxial loayer 3, be provided with N-type buffering trap 4 and P type tagma 14, in N-type buffering trap 4, be provided with NXing Yang district 5, in P type tagma 14, be provided with NXing Yin district 13 and P type body contact zone 12, on the surface of N-type epitaxial loayer 3, be provided with one end of gate oxide 10 and field oxide 8 and gate oxide 10 and one end of field oxide 8 offsets, extend and terminate in NXing Yin district 13 in the other end XiangNXing Yin district 13 of described gate oxide 10, extend and terminate in NXing Yang district 5 in the other end XiangNXing Yang district 5 of described field oxide 8, on the surface of gate oxide 10, be provided with the surface that polysilicon gate 9 and polysilicon gate 9 extend to field oxide 8, at field oxide 8, P type body contact zone 12, NXing Yin district 13, the surface in polysilicon gate 9 HeNXing Yang districts 5 is provided with passivation layer 7, 5 surfaces, NXing Yang district are connected with the first metal layer 6, in 12HeNXing Yin district, P type body contact zone 13, be connected with the second metal level 11, it is characterized in that, in N-type epitaxial loayer 3 and below gate oxide 10, be provided with P type well region 15, P type well region 15 and P type tagma 14 form stepped P type doping, the P type doping content of described P type well region 15 is lower than P type tagma 14, and a side and the field oxide 8 of P type well region 15 are tangent, opposite side and P type tagma 14 offset.
Described structure is made a P type well region 15 that concentration is not high between P type tagma 14 and field oxide 8, can effectively reduce the electric field strength at field oxide 8 beak places.
Described structure is to reduce the electric field strength at field oxide 8 beak places, and the impact ionization rate of corresponding position also can decline, and ion generation rate reduces.
The output characteristic curve of described structure upwarps obviously and weakens, because the impact that ionization by collision produces drain current has obtained very large improvement.
Described structure is compared with general structure, and the parameters such as the threshold voltage of device and reverse breakdown voltage change very little, negligible.
The present invention adopts with the following method and prepares:
The first step, conventional soi layer is made, and wherein epitaxial loayer 3 adopts N-type doping.
Second step, ensuing is the making of horizontal dual pervasion field effect transistor, is included in N-type extension 3 and forms N-type resilient coating 4 by injecting phosphonium ion, B Implanted ion forms P type tagma 14; Then being that boron Implantation forms doped with P type well region 15, is secondly the growth of field oxide 8, gate oxide 10, depositing polysilicon 9 afterwards, and etching forms grid, then makes 5 He Yin districts 13, heavily doped positive district and P type body contact zone 12.Deposit silicon dioxide, depositing metal behind etching electrode contact district.Etching metal extraction electrode, finally carry out Passivation Treatment.
Claims (3)
1. a N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, comprise: N-type substrate (1), on N-type substrate (1), be provided with and bury oxygen (2), on oxygen (2), be provided with N-type epitaxial loayer (3) burying, in the inside of N-type epitaxial loayer (3), be provided with N-type buffering trap (4) and P type tagma (14), in N-type buffering trap (4), be provided with NXing Yang district (5), in P type tagma (14), be provided with NXing Yin district (13) and P type body contact zone (12), on the surface of N-type epitaxial loayer (3), be provided with one end of gate oxide (10) and field oxide (8) and gate oxide (10) and one end of field oxide (8) offsets, extend and terminate in NXing Yin district (13) in the other end XiangNXing Yin district (13) of described gate oxide (10), extend and terminate in NXing Yang district (5) in the other end XiangNXing Yang district (5) of described field oxide (8), on the surface of gate oxide (10), be provided with the surface that polysilicon gate (9) and polysilicon gate (9) extend to field oxide (8), in field oxide (8), P type body contact zone (12), NXing Yin district (13), the surface in polysilicon gate (9) HeNXing Yang district (5) is provided with passivation layer (7), surface, NXing Yang district (5) is connected with the first metal layer (6), in HeNXing Yin district, P type body contact zone (12) (13), be connected with the second metal level (11), it is characterized in that, in N-type epitaxial loayer (3) and in the below of gate oxide (10), be provided with P type well region (15), P type well region (15) and P type tagma (14) form stepped P type doping, the P type doping content of described P type well region (15) is lower than P type tagma (14), and a side of P type well region (15) and field oxide (8) are tangent, opposite side and P type tagma (14) offset.
2. N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, the doping content that it is characterized in that P type well region (15) is 1/10th to 1/5th of P type tagma (14) doping content.
3. N-type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, the junction depth that it is characterized in that P type well region (15) is 1/3rd to 1/2nd of P type tagma (14) junction depth.
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| CN103456784B (en) * | 2012-05-30 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method |
| CN102769038B (en) * | 2012-06-30 | 2014-12-10 | 东南大学 | Latch-up resisting N-type SOI laterally diffused metal oxide semiconductor |
| CN103280460B (en) * | 2013-05-22 | 2016-09-07 | 矽力杰半导体技术(杭州)有限公司 | Inject and form high voltage PMOS transistor and the manufacture method thereof with superposition drift region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5977569A (en) * | 1996-09-24 | 1999-11-02 | Allen-Bradley Company, Llc | Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability |
| CN202394983U (en) * | 2011-12-08 | 2012-08-22 | 东南大学 | N type silicon on insulator transversal double diffusion field effect transistor |
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| US7135751B2 (en) * | 2003-07-25 | 2006-11-14 | Fuji Electric Device Technology Co., Ltd. | High breakdown voltage junction terminating structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977569A (en) * | 1996-09-24 | 1999-11-02 | Allen-Bradley Company, Llc | Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability |
| CN202394983U (en) * | 2011-12-08 | 2012-08-22 | 东南大学 | N type silicon on insulator transversal double diffusion field effect transistor |
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