WO2024029336A1

WO2024029336A1 - Semiconductor device

Info

Publication number: WO2024029336A1
Application number: PCT/JP2023/026441
Authority: WO
Inventors: 和則富士
Original assignee: ローム株式会社
Priority date: 2022-08-02
Filing date: 2023-07-19
Publication date: 2024-02-08

Abstract

This semiconductor device is provided with: a first conductive layer; a first semiconductor element; a second conductive layer; a second semiconductor element; a first terminal; and a sealing resin that covers the first semiconductor element and the second semiconductor element. The first semiconductor element has a first electrode and a second electrode that are located on sides opposite to each other in a first direction. The second semiconductor element 22 has a third electrode and a fourth electrode that are located on sides opposite to each other in the first direction. The first electrode is conductively bonded to the first conductive layer. The fourth electrode is conductively bonded to the second conductive layer. The first terminal is conductively bonded to the second electrode and the third electrode. The polarity of the second electrode and the polarity of the third electrode are different from each other. The first terminal is exposed from the sealing resin.

Description

semiconductor equipment

The present disclosure relates to a semiconductor device.

Conventionally, semiconductor devices equipped with semiconductor elements having a switching function are widely known. The semiconductor device is mainly used for power conversion. Patent Document 1 discloses an example of such a semiconductor device.

In the semiconductor element mounted on the semiconductor device disclosed in Patent Document 1, the source electrode and the drain electrode are located on opposite sides. A top plate electrode is electrically connected to the source electrode. A drain electrode pattern is conductively bonded to the drain electrode. The semiconductor element is sandwiched between a top plate electrode and a drain electrode pattern. By adopting this configuration, it is possible to reduce the parasitic inductance in the semiconductor device while reducing the size of the semiconductor device. However, the area of the source electrode is generally smaller than the area of the drain electrode. Therefore, in this semiconductor device, the amount of heat radiation from the source electrode to the top plate electrode is smaller than the amount of heat radiation from the drain electrode to the drain electrode pattern, and there is a problem that the heat radiation of the semiconductor element is not fully utilized. be.

Japanese Patent Application Publication No. 2013-258387

An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can improve heat dissipation while reducing parasitic inductance.

A semiconductor device provided by a first aspect of the present disclosure includes a first conductive layer, a first electrode and a second electrode located on opposite sides of each other in a first direction, and wherein the first electrode is connected to the first conductive layer. a first semiconductor element conductively bonded to a conductive layer; a second conductive layer spaced apart from the first conductive layer in a direction perpendicular to the first direction; and a second conductive layer located on opposite sides of the first conductive layer. a second semiconductor element having three electrodes and a fourth electrode, the fourth electrode being electrically conductively bonded to the second conductive layer; a first terminal electrically bonding to the second electrode and the third electrode; A sealing resin that covers the first semiconductor element and the second semiconductor element is provided. The polarity of the second electrode and the polarity of the third electrode are different from each other. The first terminal is exposed from the sealing resin.

According to the above configuration, in the semiconductor device, it is possible to improve heat dissipation while reducing parasitic inductance.

Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a bottom view corresponding to FIG. 2, showing the sealing resin transparently. FIG. 4 is a bottom view corresponding to FIG. 3, in which the first terminal is further shown transparently. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a partially enlarged view of FIG. 4, showing the first semiconductor element and its vicinity, and also showing the first semiconductor element transparently. FIG. 10 is a cross-sectional view taken along line XX in FIG. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 is a partially enlarged view of FIG. 4, showing the second semiconductor element and its vicinity. FIG. 13 is a sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a bottom view of the semiconductor device according to the second embodiment of the present disclosure, and is shown through the sealing resin. FIG. 15 is a bottom view corresponding to FIG. 14, in which the first terminal is further shown transparently. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 14. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 14. FIG. 20 is a bottom view of the first semiconductor element included in the semiconductor device shown in FIG. 14. FIG. 21 is a plan view of the first semiconductor element shown in FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20. FIG. 24 is a sectional view taken along line XXIV-XXIV in FIG. 20. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 20. FIG. 26 is a partially enlarged view of FIG. 15, showing the first semiconductor element and its vicinity. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 26. FIG. 28 is a bottom view of the second semiconductor element included in the semiconductor device shown in FIG. 14. FIG. 29 is a plan view of the second semiconductor element shown in FIG. 28. FIG. 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 28. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 28. FIG. 32 is a cross-sectional view taken along the line XXXII-XXXII in FIG. 28. FIG. 33 is a partially enlarged view of FIG. 15, showing the second semiconductor element and its vicinity. FIG. 34 is a sectional view taken along line XXXIV-XXXIV in FIG. 33. FIG. 35 is a bottom view of the semiconductor device according to the third embodiment of the present disclosure, and is shown through the sealing resin. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 35. FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG. 35.

A mode for carrying out the present disclosure will be described based on the accompanying drawings.

First embodiment:
A semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 13. The semiconductor device A10 includes an insulating layer 11, a first conductive layer 12, a second conductive layer 13, a heat dissipation layer 16, a plurality of first semiconductor elements 21, a plurality of second semiconductor elements 22, a plurality of first spacers 31, a plurality of It includes a second spacer 32, a first terminal 41, a second terminal 42, a third terminal 43, and a sealing resin 60. Further, the semiconductor device A10 includes a first gate conductive layer 141, a second gate conductive layer 142, a first detection conductive layer 151, a second detection conductive layer 152, a first gate terminal 441, a second gate terminal 442, a first detection terminal 451 and a second detection terminal 452.

Here, for convenience of understanding, FIG. 3 shows the sealing resin 60 transparently. For convenience of understanding, FIG. 4 shows the first terminal 41 in a more transparent manner than in FIG. For convenience of understanding, FIG. 9 shows the first semiconductor element 21 in a more transparent manner than in FIG. In FIGS. 3 and 4, the outline of the sealing resin 60 that has passed through is shown by an imaginary line (two-dot chain line). In FIG. 4, the outline of the transparent first terminal 41 is shown with imaginary lines. In FIG. 9, the transparent first semiconductor element 21 is shown by an imaginary line. In FIG. 3, the VI-VI line and the VII-VII line are each shown by a dashed-dotted line.

In the description of the semiconductor device A10, for convenience, the normal direction of the first main surface 12A of the first conductive layer 12, which will be described later, will be referred to as a "first direction z." One direction perpendicular to the first direction z is called a "second direction x." A direction perpendicular to both the first direction z and the second direction x is referred to as a "third direction y."

The semiconductor device A10 converts the DC power supply voltage applied to the second terminal 42 and the third terminal 43 into AC power using the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22. The converted AC power is input from the first terminal 41 to a power supply target such as a motor. The semiconductor device A10 constitutes a part of a power conversion circuit such as an inverter.

As shown in FIG. 5 and FIG. It supports the detection conductive layer 152 and the heat dissipation layer 16. The insulating layer 11 is made of a material with relatively high thermal conductivity. Insulating layer 11 is made of ceramics containing aluminum nitride (AlN), for example. The periphery of the insulating layer 11 is sandwiched between the sealing resin 60 in the first direction z. The thickness of the insulating layer 11 is smaller than the thickness of each of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16. Therefore, in the semiconductor device A10, each of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16 is thicker than the insulating layer 11.

The first conductive layer 12 is bonded to one side of the insulating layer 11 in the first direction z, as shown in FIGS. 3, 4, 5, 6, and 8. The first conductive layer 12 has a plurality of first semiconductor elements 21 and a plurality of first spacers 31 mounted thereon. The first conductive layer 12 has a rectangular shape with its long side extending in the third direction y. The first conductive layer 12 is surrounded by the periphery of the insulating layer 11 when viewed in the first direction z. The composition of the first conductive layer 12 includes copper (Cu). The first conductive layer 12 has a first main surface 12A facing in the first direction z. The plurality of first semiconductor elements 21 and the plurality of first spacers 31 face the first main surface 12A.

As shown in FIGS. 3, 4, and 5 to 7, the second conductive layer 13 is located on the same side as the first conductive layer 12 in the first direction z, and is bonded to the insulating layer 11. . The second conductive layer 13 has a plurality of second semiconductor elements 22 mounted thereon. The second conductive layer 13 is separated from the first conductive layer 12 in the second direction x. The second conductive layer 13 has a rectangular shape with its long side extending in the third direction y. The second conductive layer 13 is surrounded by the periphery of the insulating layer 11 when viewed in the first direction z. The composition of the second conductive layer 13 includes copper. The second conductive layer 13 has a second main surface 13A facing the same side as the first main surface 12A of the first conductive layer 12 in the first direction z. The plurality of second semiconductor elements 22 face the second main surface 13A.

As shown in FIGS. 5 to 8, the heat dissipation layer 16 is located on the opposite side of the first conductive layer 12 and the second conductive layer 13 with respect to the insulating layer 11, and is bonded to the insulating layer 11. The heat dissipation layer 16 is exposed from the sealing resin 60. The volume of the heat dissipation layer 16 is larger than the sum of the volumes of the first conductive layer 12 and the second conductive layer 13. As shown in FIG. 1, the heat dissipation layer 16 is surrounded by the periphery of the insulating layer 11 when viewed in the first direction z. When viewed in the first direction z, the heat dissipation layer 16 overlaps the entire first conductive layer 12 and the entire second conductive layer 13 . The area of the heat dissipation layer 16 is larger than the sum of the area of the first conductive layer 12 and the area of the second conductive layer 13 when viewed in the first direction z. The composition of the heat dissipation layer 16 includes copper. When the semiconductor device A10 is used, a heat sink (not shown) is bonded to the heat dissipation layer 16.

The plurality of first semiconductor elements 21 are bonded to the plurality of first spacers 31, as shown in FIGS. 5 and 8. All of the plurality of first semiconductor elements 21 are the same element. The plurality of first semiconductor elements 21 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In addition, the plurality of first semiconductor elements 21 may be field-effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors), or bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). In the description of the semiconductor device A10, the plurality of first semiconductor elements 21 are n-channel type MOSFETs with a vertical structure. The plurality of first semiconductor elements 21 include a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon carbide (SiC). The plurality of first semiconductor elements 21 are arranged along the third direction y.

As shown in FIGS. 10 and 11, the plurality of first semiconductor elements 21 have a first electrode 211, a second electrode 212, and a first gate electrode 213.

As shown in FIGS. 10 and 11, the first electrode 211 faces the first main surface 12A of the first conductive layer 12. A current corresponding to the power converted by the first semiconductor element 21 flows through the first electrode 211 . That is, the first electrode 211 corresponds to the source electrode of the first semiconductor element 21.

As shown in FIGS. 10 and 11, the second electrode 212 is located on the side opposite to the first main surface 12A of the first conductive layer 12 in the first direction z. A current corresponding to the power before being converted by the first semiconductor element 21 flows through the second electrode 212 . That is, the second electrode 212 corresponds to the drain electrode of the first semiconductor element 21.

As shown in FIGS. 10 and 11, the first gate electrode 213 faces the first main surface 12A of the first conductive layer 12. Therefore, the first gate electrode 213 is located on the same side as the first electrode 211 in the first direction z. A gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213 . As shown in FIG. 9, the area of the first gate electrode 213 is smaller than the area of the first electrode 211 when viewed in the first direction z.

The plurality of second semiconductor elements 22 are bonded to the second main surface 13A of the second conductive layer 13, as shown in FIGS. 5 to 7. The plurality of second semiconductor elements 22 are the same elements as the plurality of first semiconductor elements 21. Therefore, the plurality of second semiconductor elements 22 are n-channel type MOSFETs with a vertical structure. The plurality of second semiconductor elements 22 are arranged along the third direction y.

As shown in FIG. 13, the plurality of second semiconductor elements 22 have a third electrode 221, a fourth electrode 222, and a second gate electrode 223.

As shown in FIG. 13, the third electrode 221 is located on the side opposite to the second main surface 13A of the second conductive layer 13 in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 flows through the third electrode 221 . That is, the third electrode 221 corresponds to the source electrode of the second semiconductor element 22.

As shown in FIG. 13, the fourth electrode 222 faces the second main surface 13A of the second conductive layer 13. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the fourth electrode 222 . That is, the fourth electrode 222 corresponds to the drain electrode of the second semiconductor element 22. The fourth electrode 222 is conductively bonded to the second main surface 13A via the conductive bonding layer 29. Thereby, the fourth electrodes 222 of the plurality of second semiconductor elements 22 are electrically connected to the second conductive layer 13. The conductive bonding layer 29 is, for example, solder. In addition, the conductive bonding layer 29 may be a sintered metal containing silver (Ag) or the like.

As shown in FIG. 13, the second gate electrode 223 is located on the side opposite to the second main surface 13A of the second conductive layer 13 in the first direction z. Therefore, the second gate electrode 223 is located on the same side as the third electrode 221 in the first direction z. A gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223 . As shown in FIG. 12, the area of the second gate electrode 223 is smaller than the area of the third electrode 221 when viewed in the first direction z.

In the semiconductor device A10, the plurality of first semiconductor elements 21 constitute part of the upper arm circuit, and the plurality of second semiconductor elements 22 constitute part of the lower arm circuit. Furthermore, in the semiconductor device A10, the configuration of the plurality of first semiconductor elements 21 is equivalent to the configuration when the plurality of second semiconductor elements 22 are reversed around the direction perpendicular to the first direction z. Therefore, the polarity of the first electrode 211 of each of the plurality of first semiconductor elements 21 and the polarity of the fourth electrode 222 of each of the plurality of second semiconductor elements 22 are different from each other. In addition, the second electrode 212 of each of the plurality of first semiconductor elements 21 and the third electrode 221 of each of the plurality of second semiconductor elements 22 are different from each other.

As shown in FIG. 8, the plurality of first spacers 31 are electrically bonded to the first main surface 12A of the first conductive layer 12. As shown in FIGS. 8, 10, and 11, the first electrodes 211 of each of the plurality of first semiconductor elements 21 are individually conductively bonded to the plurality of first spacers 31. Therefore, each of the plurality of first spacers 31 conductively connects the first conductive layer 12 and the first electrode 211 of one of the plurality of first semiconductor elements 21. The first electrode 211 of each of the plurality of first semiconductor elements 21 is individually electrically connected to the plurality of first spacers 31 and is electrically connected to the first conductive layer 12 via any one of the plurality of first spacers 31. ing. The plurality of first spacers 31 are arranged along the third direction y. The plurality of first spacers 31 are located between the first main surface 12A and the plurality of first semiconductor elements 21. As shown in FIGS. 10 and 11, the plurality of first spacers 31 include a first portion 311 and a second portion 312. As shown in FIG. 9, the plurality of first spacers 31 have a rectangular shape when viewed in the first direction z. In addition, the plurality of first spacers 31 may have a circular shape when viewed in the first direction z. The composition of the plurality of first spacers 31 includes copper.

As shown in FIGS. 9 to 11, the first portion 311 has a second surface 311A, a third surface 311B, and a fourth surface 311C. The second surface 311A faces the first main surface 12A of the first conductive layer 12. The second surface 311A is conductively bonded to the first main surface 12A via the conductive bonding layer 29. In addition, the second surface 311A may be conductively bonded to the first main surface 12A by solid-phase diffusion. The third surface 311B faces the opposite side from the second surface 311A in the first direction z. When viewed in the first direction z, the first semiconductor element 21 is surrounded by the periphery of the third surface 311B. The fourth surface 311C faces a direction perpendicular to the first direction z. In the semiconductor device A10, the fourth surface 311C includes a plurality of regions.

As shown in FIGS. 9 to 11, the first portion 311 is provided with a first recess 311D that is recessed from the third surface 311B and the fourth surface 311C. When viewed in the first direction z, the first gate electrode 213 of the first semiconductor element 21 overlaps the first recess 311D.

As shown in FIGS. 10 and 11, the second portion 312 is located between the first portion 311 and the first electrode 211 of the first semiconductor element 21. The second portion 312 is connected to the first portion 311 at a third surface 311B. As shown in FIG. 9, the second portion 312 is surrounded by the periphery of the first semiconductor element 21 when viewed in the first direction z. The second portion 312 is separated from the first gate electrode 213 of the first semiconductor element 21 when viewed in the first direction z.

The dimension t1 of the first part 311 in the first direction z is larger than the dimension t2 of the second part 312 in the thickness direction. The dimension t1 is 3 times or more and 30 times or less of the dimension t2.

As shown in FIGS. 9 to 11, the second portion 312 has a first surface 312A. The first surface 312A faces the first semiconductor element 21. The first surface 312A is separated from the first gate electrode 213 of the first semiconductor element 21 when viewed in the first direction z. When viewed in the first direction z, the first surface 312A is surrounded by the periphery of the second surface 311A of the first portion 311. In the semiconductor device A10, the area of the first surface 312A is smaller than the area of the first electrode 211 of the first semiconductor element 21. The first electrode 211 of each of the plurality of first semiconductor elements 21 is individually conductively bonded to the first surface 312A of each of the plurality of first spacers 31 by solid-phase diffusion. In addition, the first electrode 211 of each of the plurality of first semiconductor elements 21 may be individually conductively bonded to the first surface 312A of each of the plurality of first spacers 31 via the conductive bonding layer 29.

As shown in FIGS. 9 to 11, the second portion 312 is provided with a second recess 312B that is recessed in a direction perpendicular to the first direction z. The second recess 312B penetrates the second portion 312 in the first direction z and is connected to the first recess 311D of the first portion 311. When viewed in the first direction z, the second recess 312B overlaps the first recess 311D and the first gate electrode 213 of the first semiconductor element 21.

The plurality of second spacers 32 are individually conductively bonded to the third electrodes 221 of each of the plurality of second semiconductor elements 22, as shown in FIGS. 7 and 13. The plurality of second spacers 32 are arranged along the third direction y. The plurality of second spacers 32 are located between the plurality of second semiconductor elements 22 and the first terminals 41. As shown in FIG. 12, each of the plurality of second spacers 32 has a rectangular shape when viewed in the first direction z. In addition, each of the plurality of second spacers 32 may have a circular shape when viewed in the first direction z. The area of each of the plurality of second spacers 32 is smaller than the area of the third electrode 221 when viewed in the first direction z. The composition of the plurality of second spacers 32 includes copper. Each of the plurality of second spacers 32 is individually conductively bonded to the third electrode 221 of each of the plurality of second semiconductor elements 22 by solid phase diffusion. Alternatively, each of the plurality of second spacers 32 may be individually conductively bonded to the third electrode 221 of each of the plurality of second semiconductor elements 22 via the conductive bonding layer 29.

As shown in FIGS. 3 to 6, the first gate conductive layer 141 is located on the same side as the first conductive layer 12 in the first direction z, and is bonded to the insulating layer 11. The first gate conductive layer 141 is located on the opposite side of the first conductive layer 12 with respect to the second conductive layer 13 in the second direction x. The first gate conductive layer 141 extends along the third direction y. The composition of the first gate conductive layer 141 includes copper.

As shown in FIG. 9, each of the plurality of first gate wirings 51 is electrically connected to the first gate electrode 213 of any one of the plurality of first semiconductor elements 21 and the first gate conductive layer 141. Thereby, the first gate electrodes 213 of the plurality of first semiconductor elements 21 are electrically connected to the first gate conductive layer 141. The plurality of first gate wirings 51 are metal leads. The composition of the plurality of first gate wirings 51 includes copper. As shown in FIG. 3, the plurality of first gate wirings 51 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 5, the plurality of first gate wirings 51 overlap the heat dissipation layer 16 when viewed in the first direction z.

As shown in FIGS. 3 to 6, the second gate conductive layer 142 is located on the same side as the second conductive layer 13 in the first direction z, and is bonded to the insulating layer 11. The second gate conductive layer 142 is located on the opposite side of the first gate conductive layer 141 with respect to the first conductive layer 12 and the second conductive layer 13 in the second direction x. The second gate conductive layer 142 extends along the third direction y. The composition of the second gate conductive layer 142 includes copper.

As shown in FIG. 12, each of the plurality of second gate wirings 53 is electrically connected to the second gate electrode 223 of any one of the plurality of second semiconductor elements 22 and the second gate conductive layer 142. Thereby, the second gate electrodes 223 of the plurality of second semiconductor elements 22 are electrically connected to the second gate conductive layer 142. The plurality of second gate wirings 53 are wires. The composition of the plurality of second gate wirings 53 includes gold (Au). In addition, the composition of the plurality of second gate wirings 53 may include copper or aluminum. As shown in FIG. 3, the plurality of second gate wirings 53 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 5, the plurality of second gate wirings 53 overlap the heat dissipation layer 16 when viewed in the first direction z.

As shown in FIGS. 3, 4, 5, and 6, the first detection conductive layer 151 is located on the same side as the second conductive layer 13 in the first direction z, and is bonded to the insulating layer 11. . The first detection conductive layer 151 is located next to the first gate conductive layer 141 in the second direction x. The first detection conductive layer 151 extends along the third direction y. The composition of the first detection conductive layer 151 includes copper.

As shown in FIG. 9, each of the plurality of first detection wirings 52 is electrically bonded to the third surface 311B of any one of the plurality of first spacers 31 and the first detection conductive layer 151. Thereby, the first electrodes 211 of the plurality of first semiconductor elements 21 are electrically connected to the first detection conductive layer 151. The plurality of second gate wirings 53 are wires. The composition of the plurality of second gate wirings 53 includes gold. In addition, the composition of the plurality of second gate wirings 53 may include copper or aluminum. As shown in FIG. 3, the plurality of first detection wirings 52 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 6, the plurality of first detection wirings 52 overlap the heat dissipation layer 16 when viewed in the first direction z.

As shown in FIGS. 3, 4, 5, and 6, the second detection conductive layer 152 is located on the same side as the second conductive layer 13 in the first direction z, and is bonded to the insulating layer 11. . The second sensing conductive layer 152 is located next to the second gate conductive layer 142 in the second direction x. The second detection conductive layer 152 extends along the third direction y. The composition of the second detection conductive layer 152 includes copper.

As shown in FIG. 12, each of the plurality of second detection wirings 54 is electrically connected to the third electrode 221 of one of the plurality of second semiconductor elements 22 and the second detection conductive layer 152. Thereby, the third electrodes 221 of the plurality of second semiconductor elements 22 are electrically connected to the second detection conductive layer 152. The plurality of second detection wirings 54 are wires. The composition of the plurality of second detection wirings 54 includes gold. In addition, the composition of the plurality of second detection wirings 54 may include copper or aluminum. As shown in FIG. 3, the plurality of second detection wirings 54 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 6, the plurality of second detection wirings 54 overlap the heat dissipation layer 16 when viewed in the first direction z.

As shown in FIGS. 5 to 8, the first terminal 41 connects the first conductive layer 12 and the second conductive layer with respect to the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 in the first direction z. It is located on the opposite side from 13. The first terminal 41 is conductively bonded to the second electrode 212 of each of the plurality of first semiconductor elements 21 and to the third electrode 221 of each of the plurality of second semiconductor elements 22. The first terminal 41 is exposed from the sealing resin 60. The first terminal 41 is a metal lead made of a material containing copper or a copper alloy. AC power converted by the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 is output from the first terminal 41 .

As shown in FIGS. 5 to 8, the first terminal 41 has a bonding surface 41A and a mounting surface 41B facing oppositely to each other in the first direction z. The bonding surface 41A is conductively bonded to the second electrode 212 of each of the plurality of first semiconductor elements 21 via the conductive bonding layer 29. Further, the bonding surface 41A is electrically bonded to the third electrode 221 of each of the plurality of second semiconductor elements 22 via the conductive bonding layer 29 and the plurality of second spacers 32. The mounting surface 41B faces the opposite side to the bonding surface 41A in the first direction z. The mounting surface 41B is exposed from the sealing resin 60. In the semiconductor device A10, the area of the mounting surface 41B is equal to the area of the bonding surface 41A.

The second terminal 42 is located on one side in the third direction y with the insulating layer 11 as a reference, as shown in FIGS. 2 to 4. As shown in FIG. 8, the second terminal 42 is conductively bonded to the first conductive layer 12. Thereby, the second terminal 42 is electrically connected to the first electrodes 211 of the plurality of first semiconductor elements 21 via the first conductive layer 12 and the plurality of first spacers 31. The second terminal 42 is a metal lead made of a material containing copper or a copper alloy. The second terminal 42 is an N terminal (negative electrode) to which a DC power supply voltage to be subjected to power conversion is applied. The second terminal 42 includes a portion exposed from the sealing resin 60. As shown in FIG. 8, this portion is bent in a gull-wing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

As shown in FIGS. 2 to 4, the third terminal 43 is located on the same side as the second terminal 42 with respect to the insulating layer 11 in the third direction y. The third terminal 43 is separated from the second terminal 42 in the second direction x. As shown in FIG. 7, the third terminal 43 is conductively bonded to the second conductive layer 13. Thereby, the third terminal 43 is electrically connected to the fourth electrode 222 of the plurality of second semiconductor elements 22 via the second conductive layer 13. The third terminal 43 is a metal lead made of a material containing copper or a copper alloy. The third terminal 43 is a P terminal (positive electrode) to which a DC power supply voltage to be subjected to power conversion is applied. The third terminal 43 includes a portion exposed from the sealing resin 60. As shown in FIG. 7, this portion is bent in a gull-wing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

As shown in FIGS. 2 to 4, the first gate terminal 441 is located on the same side as the second terminal 42 with respect to the insulating layer 11 in the third direction y. The first gate terminal 441 is located on the opposite side of the third terminal 43 with respect to the second terminal 42 in the second direction x. The first gate terminal 441 is electrically connected to the first gate conductive layer 141 . Thereby, the first gate terminal 441 is electrically connected to the first gate electrodes 213 of the plurality of first semiconductor elements 21 via the first gate conductive layer 141 and the plurality of first gate wirings 51. The first gate terminal 441 is a metal lead made of a material containing copper or a copper alloy. A gate voltage for driving the plurality of first semiconductor elements 21 is applied to the first gate terminal 441 . The first gate terminal 441 includes a portion exposed from the sealing resin 60. The portion is bent in a gullwing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

As shown in FIGS. 2 to 4, the second gate terminal 442 is located on the same side as the third terminal 43 with respect to the insulating layer 11 in the third direction y. The second gate terminal 442 is located on the opposite side of the second terminal 42 with respect to the third terminal 43 in the second direction x. The second gate terminal 442 is electrically conductively bonded to the second gate conductive layer 142 . Thereby, the second gate terminal 442 is electrically connected to the second gate electrodes 223 of the plurality of second semiconductor elements 22 via the second gate conductive layer 142 and the plurality of second gate wirings 53. The second gate terminal 442 is a metal lead made of a material containing copper or a copper alloy. A gate voltage for driving the plurality of second semiconductor elements 22 is applied to the second gate terminal 442. The second gate terminal 442 includes a portion exposed from the sealing resin 60. The portion is bent in a gullwing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

As shown in FIGS. 2 to 4, the first detection terminal 451 is located on the same side as the second terminal 42 with respect to the insulating layer 11 in the third direction y. The first detection terminal 451 is located on the opposite side of the second terminal 42 with respect to the first gate terminal 441 in the second direction x. The first detection terminal 451 is electrically conductively bonded to the first detection conductive layer 151. Thereby, the first detection terminal 451 is electrically connected to the first electrode 211 of the plurality of first semiconductor elements 21 via the first detection conductive layer 151, the plurality of first detection wirings 52, and the plurality of first spacers 31. are doing. The first detection terminal 451 is a metal lead made of a material containing copper or a copper alloy. A voltage having the same potential as the voltage applied to each of the first electrodes 211 of the plurality of first semiconductor elements 21 is applied to the first detection terminal 451 . The first detection terminal 451 includes a portion exposed from the sealing resin 60. The portion is bent in a gullwing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

As shown in FIGS. 2 to 4, the second detection terminal 452 is located on the same side as the third terminal 43 with respect to the insulating layer 11 in the third direction y. The second detection terminal 452 is located on the opposite side of the third terminal 43 with respect to the second gate terminal 442 in the second direction x. The second detection terminal 452 is conductively bonded to the second detection conductive layer 152. Thereby, the second detection terminal 452 is electrically connected to the third electrodes 221 of the plurality of second semiconductor elements 22 via the second detection conductive layer 152 and the plurality of second detection wirings 54. The second detection terminal 452 is a metal lead made of a material containing copper or a copper alloy. A voltage having the same potential as the voltage applied to each of the third electrodes 221 of the plurality of second semiconductor elements 22 is applied to the second detection terminal 452 . The second detection terminal 452 includes a portion exposed from the sealing resin 60. The portion is bent in a gullwing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

The sealing resin 60 covers the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22, as shown in FIGS. 5 to 8. The sealing resin 60 is an insulator. The sealing resin 60 is made of a material containing, for example, a black epoxy resin. A portion of the sealing resin 60 is sandwiched between the insulating layer 11 and the first terminal 41 in the first direction z.

As shown in FIGS. 1, 2, and 5 to 8, the sealing resin 60 has a top surface 61, a bottom surface 62, two first side surfaces 63, and two second side surfaces 64. The top surface 61 faces the opposite side to the first main surface 12A of the first conductive layer 12 in the first direction z. The heat dissipation layer 16 is exposed from the top surface 61. The bottom surface 62 faces the opposite side from the top surface 61 in the first direction z. The mounting surface 41B of the first terminal 41 is exposed from the bottom surface 62.

As shown in FIGS. 1, 2, 5, and 6, the two first side surfaces 63 are separated from each other in the second direction x, and are connected to the top surface 61 and the bottom surface 62.

As shown in FIGS. 1, 2, 7, and 8, the two second side surfaces 64 are separated from each other in the third direction y, and are connected to the top surface 61 and the bottom surface 62. The second terminal 42 , the third terminal 43 , the first gate terminal 441 , the second gate terminal 442 , the first detection terminal 451 , and the second detection terminal 452 are connected from one of the two second side surfaces 64 . exposed. The first terminal 41 is exposed from the other of the two second side surfaces 64 . When viewed in the first direction z, each of the first terminal 41, the second terminal 42, the third terminal 43, the first gate terminal 441, the second gate terminal 442, the first detection terminal 451, and the second detection terminal 452, It extends in the first direction z from either of the two second side surfaces 64.

Next, the effects of the semiconductor device A10 will be explained.

The semiconductor device A10 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 to which the first terminal 41 is conductively bonded, and a fourth electrode 222 to which the second conductive layer 13 is conductively bonded. The polarity of the second electrode 212 and the polarity of the third electrode 221 are different from each other. The first terminal 41 is exposed from the sealing resin 60. By adopting this configuration, the length of the conductive path from the second electrode 212 to the third electrode 221 is further shortened. Thereby, it is possible to reduce the parasitic inductance of the semiconductor device A10. Furthermore, by adopting this configuration, heat generated from the first semiconductor element 21 and the second semiconductor element 22 is released to the outside via the first terminal 41. Therefore, according to this configuration, in the semiconductor device A10, it is possible to reduce the parasitic inductance of the semiconductor device A10 and improve the heat dissipation of the semiconductor device A10.

The semiconductor device A10 further includes an insulating layer 11 and a heat dissipation layer 16. The heat dissipation layer 16 is located on the opposite side of the first conductive layer 12 and the second conductive layer 13 with respect to the insulating layer 11 . The heat dissipation layer 16 is exposed from the sealing resin 60. By adopting this configuration, the heat generated from the first semiconductor element 21 and the second semiconductor element 22 can be released to the outside not only from the first terminal 41 but also from the heat dissipation layer 16.

The heat dissipation layer 16 is surrounded by the periphery of the insulating layer 11 when viewed in the first direction z. With this configuration, when the insulating layer 11 tries to fall off from the sealing resin 60, the periphery of the insulating layer 11 comes into contact with the sealing resin 60 in the first direction z, so that the insulating layer 11 can be prevented from falling off.

When viewed in the first direction z, the heat dissipation layer 16 overlaps the entire first conductive layer 12 and the entire second conductive layer 13. The area of the heat dissipation layer 16 is larger than the sum of the area of the first conductive layer 12 and the area of the second conductive layer 13 when viewed in the first direction z. By adopting this configuration, the heat conducted from the first conductive layer 12 and the second conductive layer 13 to the heat dissipation layer 16 via the insulating layer 11 is easily diffused in a direction perpendicular to the first direction z. Thereby, the thermal resistance of the heat dissipation layer 16 in the first direction z can be reduced.

The thickness of each of the first conductive layer 12 , the second conductive layer 13 , and the heat dissipation layer 16 is greater than the thickness of the insulating layer 11 . By adopting this configuration, the heat diffusion efficiency in the direction perpendicular to the first direction z is improved in each of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16. Therefore, the heat dissipation of the semiconductor device A10 can be further improved.

In the semiconductor device A10, the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first electrode 211 of the first semiconductor element 21 in the first direction z. The semiconductor device A10 further includes a first spacer 31 that conductively connects the first conductive layer 12 and the first electrode 211. The first spacer 31 has a first surface 312A facing the first electrode 211. The first surface 312A is separated from the first gate electrode 213 when viewed in the first direction z. By adopting this configuration, a short circuit between the first gate electrode 213 and the first gate wiring 51 shown in FIG. 10 and the first spacer 31 can be prevented.

The first spacer 31 has a second surface 311A facing the first conductive layer 12. The area of the second surface 311A is larger than the area of the first surface 312A. When viewed in the first direction z, the first surface 312A is surrounded by the periphery of the second surface 311A. Here, if the first spacer 31 is set as a virtual plane that extends from the periphery of the first surface 312A toward the second surface 311A and has an inclination angle of 45° with respect to the first direction z, the first spacer 31 The heat conducted to is uniformly diffused in the area surrounded by the virtual plane. Therefore, by adopting this configuration, the heat conducted from the first surface 312A to the first spacer 31 is easily diffused uniformly in the first direction z and the direction orthogonal to the first direction z. Thereby, the heat conducted from the first electrode 211 of the first semiconductor element 21 to the first spacer 31 is conducted to the first conductive layer 12 more quickly.

The semiconductor device A10 further includes a second terminal 42 conductively bonded to the first conductive layer 12 and a third terminal 43 conductively bonded to the second conductive layer 13. The second terminal 42 and the third terminal 43 are exposed from the sealing resin 60. Each portion of the second terminal 42 and the third terminal 43 exposed from the sealing resin 60 is bent toward the side where the first terminal 41 is located in the first direction z. By adopting this configuration, it becomes possible to surface-mount the semiconductor device A10 on the wiring board.

Second embodiment:
A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 14 to 34. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted. Here, for convenience of understanding, FIG. 14 shows the sealing resin 60 transparently. For convenience of understanding, FIG. 15 shows the first terminal 41 more clearly than in FIG. 14. In FIGS. 14 and 15, the outline of the sealing resin 60 that has passed through is shown with imaginary lines. In FIG. 15, the outline of the transparent first terminal 41 is shown with imaginary lines. In FIG. 14, the XVIII-XVIII line is indicated by a chain line.

In the semiconductor device A20, the structure of the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 and the fact that the plurality of first spacers 31 and the plurality of second spacers 32 are not provided are different from the semiconductor device A10. This is different from the case of

As shown in FIGS. 20 to 25, each of the plurality of first semiconductor elements 21 includes a first detection electrode 214, a first element body 215, a first rewiring 216, a second rewiring 217, a first resin 218, and It has a covering layer 219. The plurality of first semiconductor elements 21 are resin packages.

The first element body 215 is an element corresponding to any one of the plurality of first semiconductor elements 21 of the semiconductor device A10. The first element body 215 includes a first pad 215A and a first gate pad 215B. As shown in FIG. 27, the first pad 215A and the first gate pad 215B are located on the side facing the first conductive layer 12 in the first direction z. The first pad 215A corresponds to the first electrode 211 of the first semiconductor element 21 of the semiconductor device A10. The first gate pad 215B corresponds to the first gate electrode 213 of the first semiconductor element 21 of the semiconductor device A10. The first element body 215 includes a second electrode 212 .

As shown in FIGS. 22 to 25, the first resin 218 covers a portion of the first element body 215 and at least a portion of each of the first rewiring 216 and the second rewiring 217. The first electrode 211 , the second electrode 212 , the first gate electrode 213 , and the first detection electrode 214 are exposed from the first resin 218 .

As shown in FIGS. 22 to 24, the first electrode 211 is electrically connected to the first pad 215A of the first element body 215, and is in contact with the first pad 215A. As shown in FIG. 21, the first electrode 211 includes a portion that protrudes outward from the second electrode 212 when viewed in the first direction z. When viewed in the first direction z, the area of the first electrode 211 is larger than the area of the first pad 215A.

As shown in FIGS. 20, 22, and 23, the first gate electrode 213 and the first detection electrode 214 are located on the same side as the second electrode 212 in the first direction z. The first detection electrode 214 is separated from the first gate electrode 213 in the third direction y.

As shown in FIGS. 20 to 22, the first rewiring 216 connects the first gate pad 215B of the first element body 215 and the first gate electrode 213. A portion of the first rewiring 216 is covered with a first resin 218.

As shown in FIGS. 20, 21, and 23, the second rewiring 217 connects the first pad 215A of the first element body 215 and the first detection electrode 214. A portion of the second rewiring 217 is covered with the first resin 218. The second rewiring 217 is connected to the first electrode 211.

The first rewiring 216, the second rewiring 217, and the first resin 218 can be formed by, for example, the LDS (Laser Direct Structuring) method disclosed in US Patent Application Publication No. 2010/0019370. In this case, the material of the first resin 218 includes an additive containing a metal element. Each of the first rewiring 216 and the second rewiring 217 includes the metal element.

As shown in FIGS. 21 to 23, the covering layer 219 covers each portion of the first rewiring 216 and the second rewiring 217 exposed from the first resin 218. Covering layer 219 is an insulator. The covering layer 219 is in contact with the first rewiring 216, the second rewiring 217, and the first resin 218. Covering layer 219 is, for example, a solder resist.

As shown in FIG. 27, the bonding surface 41A of the third conductive layer 172 of the first terminal 41 is conductively bonded to the second electrode 212 of each of the plurality of first semiconductor elements 21 via the conductive bonding layer 29. .

As shown in FIGS. 15 and 26, each of the plurality of first detection wirings 52 is electrically connected to the first detection electrode 214 of any one of the plurality of first semiconductor elements 21 and the first detection conductive layer 151. ing. The plurality of first detection wirings 52 are metal leads. The composition of the plurality of first detection wirings 52 includes copper.

As shown in FIGS. 28 to 32, each of the plurality of second semiconductor elements 22 includes a second detection electrode 224, a second element body 225, a third rewiring 226, a fourth rewiring 227, and a second resin 228. have The plurality of second semiconductor elements 22 are resin packages.

The second element main body 225 is an element corresponding to any one of the plurality of second semiconductor elements 22 of the semiconductor device A10. The second element body 225 includes a second pad 225A and a second gate pad 225B. As shown in FIG. 34, the second pad 225A and the second gate pad 225B are located on the opposite side to the side facing the second conductive layer 13 in the first direction z. The second pad 225A corresponds to the third electrode 221 of the second semiconductor element 22 of the semiconductor device A10. The second gate pad 225B corresponds to the second gate electrode 223 of the second semiconductor element 22 of the semiconductor device A10. The first element body 215 includes a fourth electrode 222 .

As shown in FIGS. 30 to 32, the second resin 228 covers a portion of the second element main body 225 and at least a portion of each of the third rewiring 226 and the fourth rewiring 227. A third electrode 221 , a fourth electrode 222 , a second gate electrode 223 , and a second detection electrode 224 are exposed from the second resin 228 .

As shown in FIGS. 30 to 32, the third electrode 221 is electrically connected to the second pad 225A of the second element main body 225, and is in contact with the second pad 225A. As shown in FIG. 28, the third electrode 221 includes a portion that protrudes outward from the fourth electrode 222 when viewed in the first direction z. When viewed in the first direction z, the area of the third electrode 221 is larger than the area of the second pad 225A.

As shown in FIGS. 28, 30, and 31, the second gate electrode 223 and the second detection electrode 224 are located on the same side as the third electrode 221 in the first direction z. The second detection electrode 224 is separated from the second gate electrode 223 in the third direction y.

As shown in FIGS. 28 to 30, the third rewiring 226 connects the second gate pad 225B of the second element main body 225 and the second gate electrode 223. A portion of the third rewiring 226 is covered with a second resin 228.

As shown in FIGS. 28, 29, and 31, the fourth rewiring 227 connects the second pad 225A of the second element main body 225 and the second detection electrode 224. A portion of the fourth rewiring 227 is covered with a second resin 228. The fourth rewiring 227 is connected to the third electrode 221.

The third rewiring 226, fourth rewiring 227, and second resin 228 can be formed by the LDS method described above. In this case, the material of the second resin 228 includes an additive containing a metal element. Each of the third rewiring 226 and the fourth rewiring 227 includes the metal element.

As shown in FIG. 34, the bonding surface 41A of the third conductive layer 172 of the first terminal 41 is conductively bonded to the third electrode 221 of each of the plurality of second semiconductor elements 22 via the conductive bonding layer 29. .

As shown in FIGS. 15 and 33, each of the plurality of second detection wirings 54 is electrically connected to the second detection electrode 224 of any one of the plurality of second semiconductor elements 22 and the second detection conductive layer 152. ing. Each of the plurality of second gate wirings 53 and the plurality of second detection wirings 54 is a metal lead. The composition of each of the plurality of second gate wirings 53 and the plurality of second detection wirings 54 includes copper.

Next, the effects of the semiconductor device A20 will be explained.

The semiconductor device A20 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 to which the first terminal 41 is conductively bonded, and a fourth electrode 222 to which the second conductive layer 13 is conductively bonded. The polarity of the second electrode 212 and the polarity of the third electrode 221 are different from each other. The first terminal 41 is exposed from the sealing resin 60. Therefore, according to this configuration, also in the semiconductor device A20, it is possible to improve the heat dissipation of the semiconductor device A20 while reducing the parasitic inductance of the semiconductor device A20. Further, the semiconductor device A20 has the same configuration as the semiconductor device A10, so that the same effects as the semiconductor device A10 can be achieved.

In the semiconductor device A20, the first semiconductor element 21 includes a first element body 215 including a second electrode 212, a first pad 215A, and a first gate pad 215B, a first gate pad 215B, and a first gate electrode 213. The first rewiring 216 is conductive. The first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. The first electrode 211 is electrically connected to the first pad 215A. By adopting this configuration, even if the first electrode 211 is conductively bonded to the first conductive layer 12 without using the first spacer 31, a short circuit between the first gate electrode 213 and the first conductive layer 12 can be avoided. can be prevented. This eliminates the need for the first spacer 31 and the second spacer 32, so that the dimension of the semiconductor device A10 in the first direction z can be reduced, and the parasitic inductance of the semiconductor device A10 can be further reduced.

In accordance with the above case, the second semiconductor element 22 includes a first element body 215 including a fourth electrode 222, a second pad 225A, and a second gate pad 225B, a second gate pad 225B, and a second gate electrode 223. and a third rewiring 226 that conducts. The second gate electrode 223 is located on the same side as the third electrode 221 in the first direction z. The third electrode 221 is in contact with the second pad 225A. By adopting this configuration, the dimensions of the second semiconductor element 22 in the first direction z can be made to match the dimensions of the first semiconductor element 21 in the first direction z.

Third embodiment:
A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on FIGS. 35 to 37. In these figures, elements that are the same as or similar to those of the semiconductor device A10 and semiconductor device A20 described above are given the same reference numerals, and redundant explanation will be omitted. Here, for convenience of understanding, FIG. 35 shows the sealing resin 60 transparently. In FIG. 35, the outline of the transparent sealing resin 60 is shown with imaginary lines. In FIG. 35, the XXXVII-XXXVII lines are each indicated by a dashed-dotted line.

In the semiconductor device A30, the configuration of the first terminal 41 is different from the configuration of the semiconductor device A20.

As shown in FIGS. 35 to 37, the area of the mounting surface 41B of the first terminal 41 is larger than the area of the bonding surface 41A of the first terminal 41. When viewed in the first direction z, the bonding surface 41A is surrounded by the periphery of the mounting surface 41B. A step is provided at the end of the first terminal 41 in the direction perpendicular to the first direction z.

The first terminal 41 included in the semiconductor device A30 can be applied not only to the semiconductor device A20 but also to the semiconductor device A10.

Next, the effects of the semiconductor device A30 will be explained.

The semiconductor device A30 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 to which the first terminal 41 is conductively bonded, and a fourth electrode 222 to which the second conductive layer 13 is conductively bonded. The polarity of the second electrode 212 and the polarity of the third electrode 221 are different from each other. The first terminal 41 is exposed from the sealing resin 60. Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce the parasitic inductance of the semiconductor device A30 and improve the heat dissipation of the semiconductor device A30. Furthermore, the semiconductor device A30 has the same configuration as the semiconductor device A10, so that it can achieve the same effects as the semiconductor device A10.

The first terminal 41 has a bonding surface 41A and a mounting surface 41B. The bonding surface 41A is conductively bonded to the second electrode 212 of the first semiconductor element 21 and the third electrode 221 of the second semiconductor element 22. The mounting surface 41B is exposed from the sealing resin 60. The area of the mounting surface 41B is larger than the area of the bonding surface 41A. When viewed in the first direction z, the bonding surface 41A is surrounded by the periphery of the mounting surface 41B. With this configuration, the heat conducted from the first semiconductor element 21 and the second semiconductor element 22 to the bonding surface 41A is easily diffused in a direction perpendicular to the first direction z. Thereby, the thermal resistance of the first terminal 41 in the first direction z can be reduced.

The present disclosure is not limited to the embodiments described above. The specific configuration of each part of the present disclosure can be modified in various ways.

The present disclosure includes the embodiments described in the appendix below.
Additional note 1.
a first conductive layer;
a first semiconductor element having a first electrode and a second electrode located on opposite sides of each other in a first direction, and the first electrode is conductively bonded to the first conductive layer;
a second conductive layer separated from the first conductive layer in a direction perpendicular to the first direction;
a second semiconductor element having a third electrode and a fourth electrode located opposite to each other in the first direction, and the fourth electrode is conductively bonded to the second conductive layer;
a first terminal conductively connected to the second electrode and the third electrode;
a sealing resin that covers the first semiconductor element and the second semiconductor element,
The polarity of the second electrode and the polarity of the third electrode are different from each other,
The semiconductor device, wherein the first terminal is exposed from the sealing resin.
Appendix 2.
The first conductive layer and the second conductive layer further include an insulating layer located on the opposite side of the first semiconductor element and the second semiconductor element with respect to the first conductive layer and the second conductive layer, The semiconductor device according to supplementary note 1, which is bonded to the insulating layer.
Appendix 3.
further comprising a heat dissipation layer located on the opposite side of the first conductive layer and the second conductive layer with respect to the insulating layer,
The semiconductor device according to appendix 2, wherein the heat dissipation layer is bonded to the insulating layer and exposed from the sealing resin.
Appendix 4.
The semiconductor device according to appendix 3, wherein the heat dissipation layer is surrounded by a periphery of the insulating layer when viewed in the first direction.
Appendix 5.
When viewed in the first direction, the heat dissipation layer overlaps the entire first conductive layer and the entire second conductive layer,
The semiconductor device according to appendix 4, wherein the area of the heat dissipation layer is larger than the sum of the area of the first conductive layer and the area of the second conductive layer when viewed in the first direction.
Appendix 6.
The semiconductor device according to appendix 5, wherein each of the first conductive layer, the second conductive layer, and the heat dissipation layer has a thickness greater than a thickness of the insulating layer.
Appendix 7.
The first semiconductor element has a first gate electrode,
further comprising a first gate wiring conductively bonded to the first gate electrode,
7. The semiconductor device according to any one of appendices 3 to 6, wherein the first gate wiring overlaps the insulating layer when viewed in the first direction.
Appendix 8.
The semiconductor device according to appendix 7, wherein the first gate wiring overlaps the heat dissipation layer when viewed in the first direction.
Appendix 9.
The first gate electrode is located on the same side as the first electrode in the first direction,
further comprising a first spacer that electrically connects the first conductive layer and the first electrode,
The first spacer has a first surface facing the first electrode,
9. The semiconductor device according to appendix 7 or 8, wherein the first surface is distant from the first gate electrode when viewed in the first direction.
Appendix 10.
The first spacer has a second surface facing the first conductive layer,
The area of the second surface is larger than the area of the first surface,
The semiconductor device according to appendix 9, wherein the first surface is surrounded by a periphery of the second surface when viewed in the first direction.
Appendix 11.
The first semiconductor element includes a first element body including a first pad and a first gate pad located on a side opposite to the first conductive layer in the first direction, the first gate pad and the first gate. a first rewiring conductive to the electrode;
The first element body includes the second electrode,
The first gate electrode is located on the same side as the second electrode in the first direction,
9. The semiconductor device according to appendix 7 or 8, wherein the first electrode is electrically connected to the first pad.
Appendix 12.
The semiconductor device according to appendix 11, wherein the first electrode is in contact with the first pad.
Appendix 13.
The first semiconductor element has a first resin that covers a part of the first element main body and at least a part of the first rewiring,
The semiconductor device according to appendix 12, wherein the first electrode, the second electrode, and the first gate electrode are exposed from the first resin.
Appendix 14.
The first semiconductor element includes a first detection electrode located on the same side as the first gate electrode in the first direction, and a second rewiring that connects the first pad and the first detection electrode. have,
At least a portion of the second rewiring is covered with the first resin,
The semiconductor device according to attachment 13, wherein the first detection electrode is exposed from the first resin.
Appendix 15.
The second semiconductor element includes a second element body including a second pad and a second gate pad located on a side opposite to a side facing the second conductive layer in the first direction, and a second element body including a second gate pad and a second pad located on a side opposite to the second conductive layer in the first direction; a second gate electrode that is electrically conductive;
The second element body includes the fourth electrode,
The second gate electrode is located on the same side as the third electrode in the first direction,
15. The semiconductor device according to appendix 13 or 14, wherein the third electrode is in contact with the second pad.
Appendix 16.
The first terminal has a bonding surface conductively bonded to the second electrode and the third electrode, and a mounting surface facing opposite to the bonding surface in the first direction and exposed from the sealing resin. , has
The area of the mounting surface is larger than the area of the bonding surface,
16. The semiconductor device according to any one of appendices 1 to 15, wherein the bonding surface is surrounded by a periphery of the mounting surface when viewed in the first direction.
Appendix 17.
a second terminal conductively bonded to the first conductive layer;
further comprising a third terminal conductively bonded to the second conductive layer,
The second terminal and the third terminal are exposed from the sealing resin,
According to any one of appendices 1 to 16, each portion of the second terminal and the third terminal exposed from the sealing resin is bent toward the side where the first terminal is located in the first direction. semiconductor devices.

A10, A20, A30: Semiconductor device 11: Insulating layer 12: First conductive layer 12A: First main surface 13: Second conductive layer 13A: Second main surface 141: First gate conductive layer 142: Second gate conductive layer 151: First detection conductive layer 152: Second detection conductive layer 16: Heat dissipation layer 21: First semiconductor element 211: First electrode 212: Second electrode 213: First gate electrode 214: First detection electrode 215: First Element body 215A: First pad 215B: First gate pad 216: First rewiring 217: Second rewiring 218: First resin 219: Covering layer 22: Second semiconductor element 221: Third electrode 222: Fourth electrode 223: Second gate electrode 224: Second detection electrode 225: Second element body 225A: Second pad 225B: Second gate pad 226: Third rewiring 227: Fourth rewiring 228: Second resin 29: Conductive junction Layer 31: First spacer 311: First part 311A: Second surface 312A: Third surface 313A: Fourth surface 314A: First recess 312: Second part 312A: First surface 312B: Second recess 32: Second Spacer 41: First terminal 41A: Bonding surface 41B: Mounting surface 42: Second terminal 43: Third terminal 441: First gate terminal 442: Second gate terminal 451: First detection terminal 452: Second detection terminal 51: First gate wiring 52: First detection wiring 53: Second gate wiring 54: Second detection wiring 55: First wire 56: Second wire 60: Sealing resin 61: Top surface 62: Bottom surface 63: First side surface 64 : Second side z: First direction x: Second direction y: Third direction

Claims

a first conductive layer;
a first semiconductor element having a first electrode and a second electrode located on opposite sides of each other in a first direction, and the first electrode is conductively bonded to the first conductive layer;
a second conductive layer separated from the first conductive layer in a direction perpendicular to the first direction;
a second semiconductor element having a third electrode and a fourth electrode located opposite to each other in the first direction, and the fourth electrode is conductively bonded to the second conductive layer;
a first terminal conductively connected to the second electrode and the third electrode;
a sealing resin that covers the first semiconductor element and the second semiconductor element,
The polarity of the second electrode and the polarity of the third electrode are different from each other,
The semiconductor device, wherein the first terminal is exposed from the sealing resin.
The first conductive layer and the second conductive layer further include an insulating layer located on the opposite side of the first semiconductor element and the second semiconductor element with respect to the first conductive layer and the second conductive layer, The semiconductor device according to claim 1 , wherein the semiconductor device is bonded to the insulating layer.
further comprising a heat dissipation layer located on the opposite side of the first conductive layer and the second conductive layer with respect to the insulating layer,
3. The semiconductor device according to claim 2, wherein the heat dissipation layer is bonded to the insulating layer and exposed from the sealing resin.
The semiconductor device according to claim 3, wherein the heat dissipation layer is surrounded by a periphery of the insulating layer when viewed in the first direction.
When viewed in the first direction, the heat dissipation layer overlaps the entire first conductive layer and the entire second conductive layer,
5. The semiconductor device according to claim 4, wherein the area of the heat dissipation layer is larger than the sum of the area of the first conductive layer and the area of the second conductive layer when viewed in the first direction.
The semiconductor device according to claim 5, wherein each of the first conductive layer, the second conductive layer, and the heat dissipation layer has a thickness greater than the thickness of the insulating layer.
The first semiconductor element has a first gate electrode,
further comprising a first gate wiring conductively bonded to the first gate electrode,
7. The semiconductor device according to claim 3, wherein the first gate wiring overlaps the insulating layer when viewed in the first direction.
8. The semiconductor device according to claim 7, wherein the first gate wiring overlaps the heat dissipation layer when viewed in the first direction.
The first gate electrode is located on the same side as the first electrode in the first direction,
further comprising a first spacer that electrically connects the first conductive layer and the first electrode,
The first spacer has a first surface facing the first electrode,
9. The semiconductor device according to claim 7, wherein the first surface is distant from the first gate electrode when viewed in the first direction.
The first spacer has a second surface facing the first conductive layer,
The area of the second surface is larger than the area of the first surface,
10. The semiconductor device according to claim 9, wherein the first surface is surrounded by a periphery of the second surface when viewed in the first direction.
The first semiconductor element includes a first element body including a first pad and a first gate pad located on a side opposite to the first conductive layer in the first direction, the first gate pad and the first gate. a first rewiring conductive to the electrode;
The first element body includes the second electrode,
The first gate electrode is located on the same side as the second electrode in the first direction,
9. The semiconductor device according to claim 7, wherein the first electrode is electrically connected to the first pad.
The semiconductor device according to claim 11, wherein the first electrode is in contact with the first pad.
The first semiconductor element has a first resin that covers a part of the first element main body and at least a part of the first rewiring,
13. The semiconductor device according to claim 12, wherein the first electrode, the second electrode, and the first gate electrode are exposed from the first resin.
The first semiconductor element includes a first detection electrode located on the same side as the first gate electrode in the first direction, and a second rewiring that connects the first pad and the first detection electrode. have,
At least a portion of the second rewiring is covered with the first resin,
14. The semiconductor device according to claim 13, wherein the first detection electrode is exposed from the first resin.
The second semiconductor element includes a second element body including a second pad and a second gate pad located on a side opposite to a side facing the second conductive layer in the first direction, and a second element body including a second gate pad and a second pad located on a side opposite to the side facing the second conductive layer in the first direction; a second gate electrode that is electrically conductive;
The second element body includes the fourth electrode,
The second gate electrode is located on the same side as the third electrode in the first direction,
The semiconductor device according to claim 13 or 14, wherein the third electrode is in contact with the second pad.
The first terminal has a bonding surface electrically conductively bonded to the second electrode and the third electrode, and a mounting surface facing opposite to the bonding surface in the first direction and exposed from the sealing resin. , has
The area of the mounting surface is larger than the area of the bonding surface,
16. The semiconductor device according to claim 1, wherein the bonding surface is surrounded by a periphery of the mounting surface when viewed in the first direction.
a second terminal conductively bonded to the first conductive layer;
further comprising a third terminal conductively bonded to the second conductive layer,
The second terminal and the third terminal are exposed from the sealing resin,
17. The method according to claim 1, wherein each portion of the second terminal and the third terminal exposed from the sealing resin is bent toward the side where the first terminal is located in the first direction. The semiconductor device described.