WO2024004208A1 - Electric power conversion device - Google Patents

Abstract

This electric power conversion device having an arm pair (3) in which a first semiconductor switching element (M1) and a second semiconductor switching element (M2) are connected in series between a DC plus terminal and a DC minus terminal is configured to comprise: a third resistance group (6) that is connected in parallel with the first semiconductor switching element (M1); a second resistance group (5) that is connected in parallel with the second semiconductor switching element (M2); a reference-voltage-generating circuit (4) that generates a first reference voltage and a second reference voltage in which a voltage between the plus terminal and the minus terminal is divided; and an abnormality determination unit (11) that, after both semiconductor switching elements (M1, M2) have stopped operating, compares a detection voltage that is divided by the second resistance group (5) and the first and second reference voltages, and determines whether either of the semiconductor switching elements has undergone main breakdown voltage deterioration.

Description

power converter

This application relates to a power conversion device.

In a power conversion device, the power conversion function is realized by turning on/off a plurality of semiconductor switching elements that constitute the power converter. Examples of semiconductor switching elements include voltage-driven semiconductor switching elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate-Bipolar-Transistors). .

As a basic characteristic of this semiconductor switching element, it is required to maintain high insulation characteristics even when its gate is turned off. However, it is conceivable that the insulating properties will be lost due to moisture absorption in the sealing insulating material, potential defects in the semiconductor manufacturing process, and even undesigned overvoltage surges during operation. Therefore, by understanding the deterioration state of the main withstand voltage of the semiconductor switching element, it is expected that it will be possible to eliminate downtime of the power conversion device by replacing the semiconductor switching element before it is destroyed. In particular, since it is thought that the larger the leakage current is, the shorter the time required for destruction to occur, there is a need for a technology that can detect the leakage current with high precision at a very small stage.

As a technique for detecting an abnormality in the main withstand voltage of a semiconductor switching element in a power conversion device, there is a method disclosed in Patent Document 1 or Patent Document 2, for example. The abnormality detection device shown in Patent Document 1 includes one or more parallel power conversion units, and for one parallel power conversion unit, one high select terminal voltage detection section with a corresponding detection resistor, and , one abnormality detection section is provided in each parallel power conversion unit, and the abnormality detection section in each parallel power conversion unit detects an abnormality in each power converter included in the parallel power conversion unit based on the voltage at the collection point.

In the power supply device shown in Patent Document 2, in a configuration including an inverter circuit constituted by two switch elements connected in series, when the inverter circuit stops operating, the voltage at the connection point between the two switch elements becomes the first voltage. The system includes an abnormality detection circuit that sends out an abnormality signal when the reference voltage exceeds the second reference voltage or falls below the second reference voltage.

Japanese Patent Application Publication No. 2019-110720 JP2013-243871A

However, in the technology proposed in Patent Document 1, when the detected voltage value changes compared to a predetermined threshold value, a failure is determined (an abnormality is detected). It is not intended to detect minute leakage currents due to deterioration of the main breakdown voltage of switching elements. Alternatively, in the technology proposed in Patent Document 2, the connection point voltage of an inverter circuit configured by connecting semiconductor switching elements in series is determined by the leakage current between a voltage dividing resistor for voltage detection connected to the connection point and the semiconductor switching element. Since it is determined only by the balance of A situation occurs where it converges to near zero, and therefore normality and abnormality cannot be distinguished with high accuracy. Furthermore, considering the fact that the leakage current of semiconductor switching elements changes nonlinearly depending on the applied voltage, it is necessary to design margins for the reference voltage to distinguish between normal and abnormal conditions in product fields where the main circuit voltage fluctuates widely. There is also the issue that it becomes difficult to ensure the current leakage current, and as a result, highly accurate leakage current detection cannot be achieved.

The present application was made in order to solve the above-mentioned problems, and aims to provide a power conversion device that can accurately determine main breakdown voltage deterioration of a semiconductor switching element.

The power conversion device disclosed in the present application has one of a DC positive terminal and a negative terminal as a first pole terminal and the other as a second pole terminal, and a first semiconductor switching element between the first pole terminal and the midpoint of the arm. is a power conversion device having a pair of arms in which a second semiconductor switching element is connected between the middle point of the arm and the second electrode terminal, the power converter having an abnormality detection section and a gate control section, The abnormality detection unit includes a third resistance group connected in parallel to the first semiconductor switching element and having at least one resistor. a second resistor group including a plurality of series resistors connected in parallel with the second semiconductor switching element so as to divide the voltage applied to the second semiconductor switching element; and the first electrode terminal. a first reference voltage obtained by dividing the voltage between the second electrode terminal; and a voltage different from the first reference voltage, which is obtained by dividing the voltage between the first electrode terminal and the second electrode terminal. a reference voltage generation circuit that generates a second reference voltage; a detection voltage that is a voltage divided by the second resistor group after the power conversion device stops power conversion operation; and a detection voltage that is a voltage divided by the second resistor group; and an abnormality determination section that compares the voltage and the second reference voltage to determine whether the main breakdown voltage of the first semiconductor switching element or the second semiconductor switching element has deteriorated.

According to the present application, it is possible to provide a power conversion device that can accurately determine main breakdown voltage deterioration of a semiconductor switching element.

1 is a diagram showing the configuration of a power conversion device according to Embodiment 1. FIG. 5 is a first timing chart for explaining the operation of the power conversion device according to the first embodiment. FIG. 7 is a second timing chart for explaining the operation of the power conversion device according to the first embodiment. 7 is a third timing chart for explaining the operation of the power conversion device according to the first embodiment. FIG. 3 is a diagram showing another configuration of the power conversion device according to Embodiment 1. FIG. FIG. 3 is a diagram showing the configuration of a power conversion device according to a second embodiment. 7 is a timing chart for explaining the operation of the power conversion device according to Embodiment 2. FIG. FIG. 3 is a diagram showing the configuration of a power conversion device according to a third embodiment. FIG. 7 is a diagram showing the configuration of a power conversion device according to a fourth embodiment. FIG. 7 is a diagram showing the configuration of a power conversion device according to a fifth embodiment. FIG. 7 is a diagram showing the configuration of a power conversion device according to a sixth embodiment. FIG. 2 is a block diagram showing an example of an actual configuration of a gate signal generation section or a gate signal generation section and an abnormality determination section in each embodiment.

Embodiment 1.
Embodiments will be described below based on the drawings. In the following description, similar or corresponding components are indicated by the same reference numerals. In the following description, the state of an element that makes the device inoperable is referred to as "failure," and the state of the element that operates but deteriorates and no longer satisfies required specifications is referred to as "deterioration." Regarding "deterioration," if a test (screening) is conducted before the device is shipped, it is confirmed that the device satisfies the required specifications, quality, and reliability goals of various tests. The target is the element that is

FIG. 1 is a configuration diagram showing the configuration of a power conversion device according to Embodiment 1. The power conversion device includes a first semiconductor switching element M1 forming an upper arm and a second semiconductor switching element M2 forming a lower arm between a positive side potential PA and a negative side potential GA of a DC power source (not shown). The inverter includes a pair of arms (leg circuits) 3 connected in series, and for the sake of simplification, an example of a single-phase inverter configured with one pair of arms is shown here. The arm pair 3 includes a positive terminal P, a negative terminal N, and an arm midpoint C as a connection point between the first semiconductor switching element M1 and the second semiconductor switching element M2.

The first semiconductor switching element M1 and the second semiconductor switching element M2 are configured such that the gate driving section 2H and the gate driving section 2L control the respective gate sources based on the respective on/off command signals SGH and SGL generated by the gate signal generating section 2. The on/off operation is controlled by applying a voltage between them. Here, a portion composed of the gate signal generating section 2, the gate driving section 2H, and the gate driving section 2L will be referred to as a gate control section 1. The general configuration of the gate drive section 2H and gate drive section 2L includes a photocoupler that isolates the on/off command signals SGH and SGL, an isolation communication section such as a level shift or pulse transformer, a buffer that amplifies the isolation signal, and switching characteristics. There is a drive adjustment section such as a gate resistance that adjusts the voltage, and a short circuit protection section that detects a short circuit between the first semiconductor switching element M1 and the second semiconductor switching element M2 and safely cuts it off.

A first resistor group 4 (also referred to as a reference voltage generation circuit 4), which is composed of at least three or more resistors connected in series, is provided between the positive side potential PA and the negative side potential GA of the DC power supply. Here, an example is shown in which three resistors R20, R21, and R22 are connected in series.

A second resistor group 5 configured by connecting two or more resistors in series is provided in parallel with the second semiconductor switching element M2 of the lower arm. An example is shown in which two resistors are connected in series. Similarly, a third resistor group 6 including one or more resistors is provided in parallel with the first semiconductor switching element M1 of the upper arm, and here, the third resistor group 6 includes two resistors R10 and R11. An example of series connection is shown. The present application is not limited to the configuration of the resistor groups shown in the drawings, and the number of resistors connected in series may be increased.

It is preferable to provide a filter capacitor between the connection point of the resistors in the first resistor group 4 and the negative potential GA for stabilizing the reference potentials VrefH and VrefL generated by voltage division. An example is shown in which a filter capacitor C20 is provided between the connection point and the negative potential GA. In addition, a filter capacitor is provided between the connection point of the resistors in the second resistor group 5 and the negative potential GA, if necessary, to remove high-frequency noise superimposed on the detection voltage VdM generated by voltage division. Here, an example is shown in which a filter capacitor C1 is provided between the connection point between the resistor R1 and the resistor R2 and the negative side potential GA.

The reference voltage of the voltage range comparator 7 is a voltage generated by dividing the voltage by the resistors in the first resistor group 4. In this example, the comparator CP1 uses the first reference voltage VrefH, and the comparator CP2 uses the second reference voltage VrefL, which is different from the first reference voltage VrefH, as the reference voltage. Then, this voltage range comparator 7 determines that the detected voltage VdM generated by voltage division by the resistors in the second resistor group 5 is within the range of two different reference voltages (VrefL<VdM<VrefH). However, in this embodiment, when VdM<VrefH, the output SDH of the comparator CP1 becomes a Hi output, and when VrefL<VdM, the output SDL of the comparator CP2 becomes a Hi output. The structure is as follows. Therefore, when VdM≧VrefH, SDH becomes a Lo output, and when VrefL≧VdM, SDL becomes a Lo output.

After the semiconductor switching element stops on/off operation, the abnormality determination unit 11 compares the detected voltage VdM with the first reference voltage VrefH and the second reference voltage VrefL based on the output result of the voltage range comparator 7. , in the case of VrefL≧VdM or VdM≧VrefH, it is determined that the main breakdown voltage of the first semiconductor switching element M1 or the second semiconductor switching element M2 has deteriorated, and a main breakdown voltage abnormal signal FDL is output to the gate signal generation section 2. A warning will be sent along with the notification.

As described above, the abnormality detection unit 10 includes the first resistance group (reference voltage generation circuit) 4. It includes a second resistance group 5, a third resistance group 6, a voltage range comparator 7, and an abnormality determination section 11. Here, a portion composed of the gate control section 1 and the abnormality detection section 10 is referred to as a semiconductor drive control section 100.

Although FIG. 1 only shows the arm pair 3 in which the first semiconductor switching element M1 and the second semiconductor switching element M2 are connected in series for the sake of simplicity, it can also be applied to a power converter device having a plurality of arm pairs. For example, it may be an H-bridge circuit with two arm pairs in parallel, or a three-phase inverter with three arm pairs in parallel.

(Detection method of main breakdown voltage deterioration)
Hereinafter, a method for detecting main breakdown voltage deterioration will be specifically described with reference to signal timing charts. Note that main breakdown voltage deterioration refers to the leakage current that flows between the main terminals of a semiconductor switching element when a voltage is applied between the main terminals of the semiconductor switching element when the semiconductor switching element is off. This refers to a state in which the element has grown larger due to deterioration and no longer satisfies the required specifications. Even if a semiconductor switching element has a degraded main withstand voltage, it can perform normal on/off operations for a while, but in the near future the leakage current will further increase and normal on/off operations will no longer be possible. FIG. 2 is a timing chart of signals during switching operation when the semiconductor switching element is in a healthy state. Based on the upper arm-on command SGH and the lower arm-on command SGL generated by the gate signal generator 2, VGH and VGL are applied to the gates of the first semiconductor switching element M1 of the upper arm and the second semiconductor switching element M2 of the lower arm, respectively. A gate voltage is applied. As a result, the first semiconductor switching element M1 and the second semiconductor switching element M2 are turned on and off, but the upper arm side performs synchronous rectification when the current IsH flows through the diode parallel to the first semiconductor switching element. The side exemplifies the state in which the forward drain current IdL of the second semiconductor switching element is energized/cut off by its on/off operation. At this time, the voltage Vac at the arm midpoint C, which is the connection point between the first semiconductor switching element M1 and the second semiconductor switching element M2, is equal to the voltage VB between the positive potential PA and the negative potential GA in the forward direction of the diode. It changes so that the upper and lower limits are VB+Vf, which is calculated by counting the voltage Vf, and the on-voltage Von caused by the on-resistance of the semiconductor switching element.

The detection voltage VdM generated by voltage division in the second resistor group 5 repeats a state higher than the reference voltage VrefH designed by the resistance value of the first resistor group 4 or a state lower than the reference voltage VrefL, and the second semiconductor The detection voltage VdM changes when the switching element M2 turns on and off. Since deterioration in the main withstand voltage of the semiconductor switching element cannot be detected from the voltage Vac at the arm midpoint C in such a switching state, the abnormality determination unit 11 maintains the deterioration diagnosis permission signal EDL in the Lo state to detect the deterioration in the main withstand voltage. Stop. Thereby, the deterioration detection signal FDL is held in the Lo state, and a Hi state indicating that the main breakdown voltage has deteriorated is prevented from being erroneously output during the switching operation.

FIG. 3 is a timing chart of signals from just before the on-off operation of the semiconductor switching element stops to after it stops when the semiconductor switching element is in a healthy state, and shows a state in which the switching operation state shown in FIG. 2 has transitioned to a state in which both the upper and lower arms are off. It corresponds to When the semiconductor switching elements of the upper and lower arms are both turned off, the source current of the upper arm gradually decreases, reaches zero at time t31, and reaches static zero after resonance due to the main circuit inductance and the parasitic capacitance of the semiconductor switching elements occurs. converge to the state. Correspondingly, the arm midpoint voltage Vac converges to around VB/2, but the convergence value is determined depending on the parasitic leakage currents of the first semiconductor switching element M1 and the second semiconductor switching element M2. Correspondingly, detection voltage VdM converges to a value between reference voltages VrefL and VrefH. At time t32, which is sufficiently after the arm midpoint voltage Vac has settled into the steady state, the deterioration diagnosis enable signal EDL is set to Hi state in the abnormality determination unit 11 to enable main breakdown voltage deterioration detection. Since the reference voltage is designed so that the detection voltage VdM satisfies VrefL<VdM<VrefH in a healthy state, the deterioration detection signal FDL is in the Lo state in which no deterioration is detected.

FIG. 4 is a timing chart of signals after the on/off operation of the semiconductor switching element is stopped in a state where the main breakdown voltage of the first semiconductor switching element M1 has deteriorated. In comparison with FIG. 3, since the detected voltage VdM after the on/off operation of the semiconductor switching element has stopped exceeded the reference voltage VrefH, the comparator CP1 in the voltage range comparator 7 determines the state of VdM≧VrefH, and the abnormality determination unit In No. 11, at time t33, the deterioration detection signal FDL changes to a Hi output indicating that main breakdown voltage deterioration has been detected. The principle why the detected voltage VdM exceeds the reference voltage VrefH after the on-off operation is stopped is due to the total resistance value of the third resistance group 6, the leakage current of the first semiconductor switching element M1, and the parasitic resistance value converted from the applied voltage. This is because the combined resistance becomes smaller than the combined resistance of the total resistance value of the second resistance group 5, the leakage current of the second semiconductor switching element M2, and the parasitic resistance value calculated from the applied voltage. The reference voltage VrefH and the reference voltage VrefL can be designed from the range of the detection target leakage current value and the parasitic leakage current value of a healthy product.

Here, the criterion for determining whether the main withstand voltage has deteriorated may be the time until the detected voltage VdM deviates from the voltage between the reference voltages VrefL and VrefH. That is, if it takes a long time to deviate from the voltage between the two reference voltages, it is not determined that the main withstand voltage has deteriorated, but if the time is short, it is determined that the main withstand voltage has deteriorated. Alternatively, the amount of change in the detection voltage VdM per unit time when the detection voltage VdM deviates from the voltage between the reference voltages VrefL and VrefH may be used as the determination criterion. That is, if the amount of change is small, it is not determined that the main withstand voltage has deteriorated, but if the amount of change is large, it is determined that the main withstand voltage has been deteriorated.

When the main withstand voltage of the second semiconductor switching element M2 deteriorates, the combined resistance of the total resistance value of the second resistance group 5, the leakage current of the second semiconductor switching element M2, and the parasitic resistance value converted from the applied voltage. However, the main withstand voltage is smaller than that without deterioration. Therefore, the detection voltage VdM after the on-off operation is stopped becomes smaller than the reference voltage VrefL. Thereby, it is possible to detect that the main breakdown voltage of the second semiconductor switching element M2 has deteriorated. Note that by making the combined resistance value of the second resistance group 5 and the combined resistance value of the third resistance group 6 equal, the detection accuracy of main breakdown voltage deterioration of the first semiconductor switching element M1 and the second semiconductor switching element M2 can be improved. It can be done equally.

(Method of designing resistance values of second resistance group and third resistance group)
The method of designing the resistance values of the second resistance group 5 and the third resistance group 6 is such that the leakage current value flowing in accordance with the combined resistance value of each resistance group is is larger than the parasitic leakage current value (the current value that flows when each semiconductor switching element is off) between the main terminals (between the terminals through which the main current of each semiconductor switching element flows) in a healthy state, for example, in the initial state at the time of shipment. Design it to be. For example, considering the leakage current set as the main withstand voltage screening condition at the time of shipment of semiconductor switching elements, a detection target leakage current value is determined by adding a margin to prevent false detection, and this is detected accurately. It is conceivable to determine the combined resistance value of each resistance group so that the resistance can be increased.

If the leakage currents in the second resistance group 5 and the third resistance group 6 are too large, the fluctuation range of the detection voltage VdM due to the increase in the leakage currents of the first semiconductor switching element M1 and the second semiconductor switching element M2 becomes small, and the detection voltage VdM becomes smaller. Accuracy deteriorates. Alternatively, if the leakage currents in the second resistance group 5 and the third resistance group 6 are too small, the detection voltage VdM varies greatly with respect to the leakage current within the normal range of the semiconductor switching element, and normality is determined to be abnormal; A problem occurs where an abnormality cannot be detected. For example, if the leakage current of the first semiconductor switching element M1 is at a negligible level and the leakage current of the second semiconductor switching element M2 is equivalent to the screening conditions at the time of shipment, detection when both of these semiconductor switching elements are turned off is detected. Although the voltage VdM is biased toward the lower arm side when the main breakdown voltage is in a healthy state, the resistance values of the second resistance group 5 and the third resistance group 6 may be designed so as not to erroneously detect this.

(Timing for detecting main breakdown voltage deterioration)
Detection of main breakdown voltage deterioration of the first semiconductor switching element M1 and the second semiconductor switching element M2 is performed in a state in which both of them are turned off and the output voltage at the arm midpoint C, which is the series connection point thereof, has converged to a steady value. Specifically, this can be performed when the device is started, stopped, or coasting. Note that the main withstand voltage leakage current increases depending on the junction temperature (temperature at the junction) of the element, so detection may occur immediately after the equipment stops operating when the junction temperature of the semiconductor switching element is higher than the surrounding environment temperature. can determine breakdown voltage deterioration with the highest accuracy.

In addition, since the junction temperature of the switching element is not high when the device is started, high accuracy can be achieved by operating the power converter to raise the junction temperature and detecting at that timing when the temperature is higher than the environmental temperature. Main breakdown voltage deterioration can be determined.

(Operation after detecting deterioration)
If it is determined that the main withstand voltage of the semiconductor switching element has deteriorated, the abnormality determination unit 11 shown in FIG. 1 or 5 notifies the recipient of the abnormality. For example, an abnormality lamp is provided in the device, and the abnormality lamp is turned on when it is determined that the main breakdown voltage has deteriorated. When the abnormality lamp lights up, the device may be immediately stopped. Alternatively, since the abnormality lamp is lit when the switching element is judged to have deteriorated before it is destroyed, even if the abnormality lamp is lit, the equipment continues to operate until the next opportunity to stop. It may be specified that the semiconductor switching element is replaced at any time.

Additionally, if it is determined that the main withstand voltage of a semiconductor switching element has deteriorated, the operation of the power converter is changed to reduce the load on the semiconductor switching element in order to temporarily prolong the life of the semiconductor switching element. Good too. For example, if the original modulation method of the inverter was three-phase modulation, it may be changed to two-phase modulation, or the switching frequency may be lowered to reduce the number of times of switching. Alternatively, stress may be reduced by reducing the load current. In this way, after an abnormality in a semiconductor switching element is detected and a warning is displayed, by temporarily extending the life of the switching element, the equipment can be operated without stopping, and a downtime can be avoided during the planned operation schedule. It becomes possible to operate the device without any time.

(Effect of a configuration in which the reference voltage changes according to the main circuit voltage)
In the first embodiment, the first reference voltage VrefH and the second reference voltage VrefL of the voltage range comparator 7 are set in the first resistor group 4 provided between the main circuit positive side potential PA and the main circuit negative side potential GA. It is generated by dividing the voltage using the resistors. Therefore, when the main circuit voltage decreases, the reference voltage range (VrefH-VrefL) that is determined to be normal by the abnormality determining section 11 changes to decrease. Conversely, when the main circuit voltage increases, these reference voltages change to expand. This was designed in consideration of the fact that the main withstand voltage leakage current increases nonlinearly as the applied voltage increases, and when the main circuit voltage decreases, the leakage current decreases nonlinearly and is detected. It is possible to prevent accuracy from deteriorating or from erroneously detecting normality as abnormality due to a nonlinear increase in leakage current when the main circuit voltage increases. As a result, it is possible to detect minute leakage currents with higher precision than in the past, and therefore the life span of the semiconductor switching element can be extended.

FIG. 5 is a block diagram showing another configuration of the power conversion device according to the first embodiment. In FIG. 1, the voltage divided by the second resistor group 5 provided in parallel to the second semiconductor switching element M2 constituting the negative arm is defined as the detection voltage VdM. In the configuration of FIG. 5, the semiconductor switching element constituting the negative side arm is the first semiconductor switching element M1, the semiconductor switching element constituting the positive side arm is the second semiconductor switching element M2, and the semiconductor switching element constituting the positive side arm is the second semiconductor switching element M2. A second resistor group 5 is provided in parallel with M2, and the voltage divided by this second resistor group 5 is set as the detection voltage VdM.

Further, in the configuration shown in FIG. 1, the first reference voltage VrefH and the second reference voltage VrefL are generated by the reference voltage generation circuit 4, which is the first resistance group consisting of three resistors connected in series. . In the configuration shown in FIG. 5, the first resistor group 4 as a reference voltage generation circuit is connected between a series body of a resistor R23 and a resistor R24 connected between a positive potential PA and a negative potential GA, and a positive potential PA. The resistor R25 and the resistor R26 are connected in series between the resistor R25 and the negative potential GA. The first reference voltage VrefH is generated by dividing the voltage by a series body of a resistor R23 and a resistor R24, and the second reference voltage VrefL is generated by dividing a voltage by a series body of a resistor R25 and a resistor R26. There is. Further, in order to stabilize the reference voltage, a filter capacitor C22 is provided in parallel with the resistor R24, and a filter capacitor C21 is provided in parallel with the resistor R26. In this way, the reference voltage generation circuit 4 divides the voltage between the positive side potential PA and the negative side potential GA to generate a first reference voltage VrefH and a second reference voltage different from the first reference voltage VrefH. Any configuration may be used as long as it is configured to generate the voltage VrefL.

In the case of the configuration shown in FIG. 5, it is preferable that the first reference voltage VrefH, the second reference voltage VrefL, and the detection voltage VdM be configured by a circuit using the positive side potential PA as a reference. Even in the configuration of FIG. 5, similarly to the configuration of FIG. 1, by comparing the detection voltage VdM with the first reference voltage VrefH and the second reference voltage VrefL, It can be determined whether the main breakdown voltage of element M2 has deteriorated.

As described above, the power converter according to the first embodiment has one of the DC positive terminal PA and negative terminal GA as the first pole terminal and the other as the second pole terminal, and the first pole terminal and the arm midpoint C. A power conversion device having a pair of arms in which a first semiconductor switching element M1 is connected between the arm midpoint and a second pole terminal, and a second semiconductor switching element M2 is connected in parallel to the first semiconductor switching element M1. a third resistor group 6 connected to and having at least one resistor; and a plurality of series resistors connected in parallel with the second semiconductor switching element M2 so as to divide the voltage applied to the second semiconductor switching element M2. the first reference voltage VrefH, which is a voltage obtained by dividing the voltage between the first and second electrode terminals, and the voltage between the first and second electrode terminals. A reference voltage generation circuit 4 that generates a divided second reference voltage VrefL that is different from the first reference voltage VrefH, and a first semiconductor switching element M1 and a second semiconductor switching element M2 perform on/off operations. After stopping, when the detection voltage VdM divided by the second resistance group 5 is a voltage deviated from the voltage between the first reference voltage VrefH and the second reference voltage VrefL, the first semiconductor switching element M1 or the second The semiconductor switching element M2 is configured to include an abnormality determination section 11 that determines whether the main withstand voltage has deteriorated.

Therefore, it is possible to accurately detect a state in which the main breakdown voltage of the first semiconductor switching element M1 or the semiconductor switching element M2 has deteriorated.

Embodiment 2.
FIG. 6 is a configuration diagram showing the configuration of a power conversion device according to the second embodiment. In FIG. 6, the abnormality detection section 20 and the gate control section 1 constitute a semiconductor drive control section 200. Hereinafter, only the differences between the abnormality detection section 20 and the abnormality detection section 10 of FIG. 1 will be explained.

The abnormality detection unit 20 is different from the abnormality detection unit 10 in FIG. 1 in that the abnormality determination unit 12 is configured to also detect short circuits or dead time by using the voltage range comparator 7 used for detecting main breakdown voltage deterioration. different. Short circuit detection is to detect a state in which the first semiconductor switching element M1 and the second semiconductor switching element M2 are energized at the same time, that is, a so-called arm short circuit has occurred. A possible situation is a failure of a switching element. Dead time detection is to detect the delay time from generation of the on/off command signal generated by the gate signal generation section 1 until the semiconductor switching element is actually turned on and off. By detecting the dead time and correcting it to the optimum dead time, it is possible to improve the output performance of the power conversion device.

While the main breakdown voltage deterioration diagnosis described in the first embodiment detects a steady state after the inverter is stopped, short circuit detection and dead time detection detect a transient state during switching. Therefore, while main breakdown voltage deterioration diagnosis does not require high responsiveness of the detection circuit, short circuit detection and dead time detection require high detection accuracy. Therefore, short circuit detection and dead time detection require responsiveness of the detection circuit, but accuracy of voltage amplitude is not required. These requirements are in a trade-off relationship with each other. In other words, when increasing the resistance value of the second resistor group 5 to increase the accuracy of detecting leakage current for detecting deterioration of the main withstand voltage, even if the filter capacitor C1 is reduced, the small value of the comparator in the voltage range comparator 7 A problem arises in that the transition time of the detection voltage VdM becomes longer due to the parasitic capacitance, causing a delay in short circuit detection and dead time detection.

In order to solve the above problem, in the second embodiment, the second resistor group 5 includes a resistor R1 (also referred to as a first resistor) on the arm midpoint side and a resistor R2 (second resistor) connected in series with the resistor R1. A speed-up capacitor C2 (also called a second capacitor) is provided in parallel with the resistor R1 on the arm midpoint side of the second resistor group 5. As a result, the steady convergence value of the detection voltage VdM is determined by the resistance ratio in the second resistor group 5, while the transient convergence value of the detection voltage VdM is determined by the speed-up capacitor C2 and the filter capacitor C1 (the first capacitor ) (the input parasitic capacitance of the comparators CP1 and CP2 is also taken into consideration as necessary). Thereby, it is possible to design to optimize the detection accuracy of main breakdown voltage deterioration and the detection delay of short circuit detection and dead time detection. Specifically, the resistance value Rs1 of the resistor R1 on the arm midpoint side of the second resistor group 5, the resistance value Rs2 of the resistor R2 connected in series to the resistor R1, and the filter capacitor connected in parallel to the resistor R1. By setting the capacitance Cs1 of C1 and the capacitance Cs2 of the speed-up capacitor C2 connected in parallel to the resistor R2 so that Rs2/(Rs1+Rs2)<Cs2/(Cs1+Cs2), different detection events can be handled well. can be accommodated. That is, the detection voltage during transients such as short circuit and dead time detection is encouraged to quickly transition to a lower voltage level for short circuit detection or dead time detection determined by the capacitor voltage, while subsequent steady detection The voltage can be set to a high voltage level determined by the resistance ratio for diagnosing main breakdown voltage deterioration. By doing so, short circuit detection and dead time detection, which require high speed, and main breakdown voltage deterioration diagnosis, which requires high accuracy, can be suitably realized using a common determination circuit.

Hereinafter, methods of dead time detection and short circuit detection will be explained with reference to the timing chart of FIG. In general, a semiconductor switching element has a turn-on time (turn-on time ton) for switching from an off state to an on state, and a turn-off time (turn-off time toff) for switching from an on state to an off state. As the gate resistance value of the semiconductor switching element increases, the turn-on time ton and turn-off time toff increase. Furthermore, the turn-on time ton and turn-off time toff increase or decrease depending on variations in electrical characteristics such as gate threshold voltage of the semiconductor switching element and operating conditions such as junction temperature. Taking this into consideration, the upper and lower arm ON command signals SGH and SGL generated by the gate signal generating section 2 are both provided with a sufficient dead time, which is a period for instructing the OFF state. On the other hand, since the output performance of the power conversion device decreases due to the presence of dead time, control is sometimes applied to optimize the dead time by detecting the actual turn-on time ton and turn-off time toff. In the second embodiment, the dead time is optimized by detecting the time when the detection voltage VdM crosses the reference voltage VrefH or VrefL by using the voltage range comparator 7 used for main breakdown voltage deterioration detection. . For example, in FIG. 7, after the lower arm ON command SGL is generated, the ON command is generated by detecting time t41 when the detection voltage VdM becomes lower than the reference voltage VrefL due to a decrease in the arm midpoint voltage Vac. It is possible to detect the dead time from the actual main terminal voltage transition. Based on the detected dead time, the output characteristics of the power conversion device can be improved by correcting the dead time amount by correcting the upper and lower arm ON command signals SGH and SGL generated by the gate signal generating section 2.

Next, a short circuit detection method will be explained. FIG. 7 assumes a state in which the second semiconductor switching element M2 is destroyed and the main withstand voltage is lost at time t42 when the lower arm is in the turn-off operation. In this case, an arm short circuit occurs at the timing when the ON command signal SGH is subsequently transmitted to the upper arm, which is the opposite arm, and the first semiconductor switching element M1 is turned on, and an excessive current flows. As a result, in a normal state, the arm midpoint voltage Vac would rise to VB+Vf, but because the semiconductor switching element M1 is saturated with current, the arm midpoint voltage Vac does not rise, and as a result, the detection voltage VdM is reduced to the reference voltage. It remains below VrefL. That is, a short circuit can be detected from the logical contradiction between the ON command signal transmitted by the gate signal generating section 2 and the detection voltage VdM. As a result, the short circuit detection signal FDS becomes Hi state at time t43 when the filter delay in the abnormality determining section 12 is reflected. When the abnormality determination unit 12 detects a short circuit and the short circuit detection signal FDS becomes Hi, the gate signal generation unit 2 turns off all the ON command signals to stop the operation of the power conversion device. Treatment is common. Furthermore, by increasing the off-gate resistance value when interrupting short-circuit current, overvoltage breakdown can be reliably prevented.

In order to speed up short circuit detection, in this second embodiment, the determination reference voltage used for short circuit detection when the upper arm is turned on is set to VrefL. Similarly, it is assumed that the determination reference voltage used for short circuit detection when the lower arm is turned on is set to VrefH. This is because a preferable one is selected from the selection of the determination reference voltages VrefL and VrefH in order to speed up short circuit detection, and the reason is as follows. Now, assume that the state in which the first semiconductor switching element M1 of the upper arm is turned on after time t42 in FIG. 6 is normal switching. In this case, in normal switching, the arm midpoint voltage Vac rises to VB+Vf, but when VrefH is used as the determination reference voltage, the time at which it exceeds the determination reference value is later than when VrefL is used. That is, it takes time until it can be determined that the switching is normal, and it is therefore necessary to lock the short circuit detection function or mask the detection signal with a low-pass filter until then. As a result, when a short circuit actually occurs, the delay time until the short circuit detection signal FDS is generated increases, and the short circuit protection performance deteriorates. For this reason, it is preferable that the determination reference voltage used for short circuit detection when the upper arm is turned on is VrefL, and the determination reference voltage used for short circuit detection when the lower arm is turned on is VrefH.

Embodiment 3.
FIG. 8 is a circuit diagram showing the configuration of power conversion device 110 according to the third embodiment. Power converter 110 is an inverter that converts DC power from DC power supply 60 into three-phase AC power and supplies it to AC motor 70 . The power converter 110 includes a power converter 30 that has a plurality of semiconductor switching elements and converts it into three-phase alternating current of U, V, and W, and a gate control unit 1A that drives each semiconductor switching element in the power converter 30. A semiconductor drive control section 100A is provided. The semiconductor drive control section 100A has an abnormality detection section 10 having the same configuration as the abnormality detection section 10 of the first embodiment for a U-phase arm pair constituted by a first semiconductor switching element M1 and a second semiconductor switching element M2. It is equipped with The abnormality detection unit 10 is not provided for the semiconductor switching element M3 and the semiconductor switching element M4 that constitute the V-phase arm pair, and for the semiconductor switching element M5 and the semiconductor switching element M6 that constitute the W-phase arm pair.

In this third embodiment, an abnormality detection section 10 having the same configuration as the abnormality detection section 10 of the semiconductor drive control section 100 installed in the power converter device according to the first embodiment is used to detect semiconductor switching elements constituting the power converter 30. Since main breakdown voltage deterioration can be detected in any element, it is possible to obtain the power converter 110 that is inexpensive and can achieve no downtime.

Hereinafter, the principle by which the single abnormality detection section 10 provided in the U phase can detect main breakdown voltage deterioration in any of the semiconductor switching elements constituting the power converter 30 will be explained. Generally, the AC motor 70 has a high insulation characteristic of several hundred megaohms to several gigaohms or more, so that the leakage current generated through the AC motor 70 is not dominant. Therefore, the reference voltage of the abnormality detection section 10 provided in the U phase can be set by taking into account the insulation characteristics of the AC motor 70, without causing a deterioration in the detection accuracy of main withstand voltage deterioration of the semiconductor switching element. can.

As an example, suppose that the main withstand voltage of the semiconductor switching element M5 of the upper arm of the W phase deteriorates and the leakage current increases, the power converter 30 stops the switching operation and the midpoint of each phase arm (upper and lower arm In a state where the potential at the connection point) is stable, the potential at the midpoint of the W-phase arm becomes higher than normal. For example, if the resistance value between both ends of the second resistance group 5 provided in the abnormality detection unit 10 is equal to the resistance value between both ends of the third resistance group 6, the W-phase arm when the main withstand voltage has not deteriorated. While the potential at the midpoint is near half voltage VB/2 of DC voltage VB, when the main breakdown voltage deteriorates, a change occurs in the direction of becoming larger than VB/2. In this case, since the three-phase windings are electrically connected within the AC motor 70, the potential at the midpoint of each arm of the U-phase and V-phase is also equal to the potential of the midpoint of the W-phase arm. Therefore, as in the configuration of FIG. 8, the abnormality detection section 10 provided only in the U phase can detect main breakdown voltage deterioration in any of the semiconductor switching elements constituting the power converter 30. .

Furthermore, although the above explanation assumes that the insulation characteristics of the AC motor 70 are normal, if the insulation characteristics deteriorate for some reason, the potential at the midpoint of the arm will be lower than the half voltage VB/2 of the DC voltage VB. The power converter 110 of this embodiment can also detect the occurrence of insulation deterioration in the AC motor 70 being driven. Note that if the potential at the midpoint of the arm changes in the direction of becoming smaller than the half voltage VB/2 of the DC voltage VB, it cannot be determined whether it is insulation deterioration of the AC motor 70 or main withstand voltage deterioration of the semiconductor switching element. There are cases. In order to reliably determine whether the It is possible to determine whether the main breakdown voltage of the switching element is deteriorating or the insulation of the motor is deteriorating.

Although the power converter 30 is shown as outputting two levels of positive and negative AC voltage, it is also an inverter capable of outputting multi-level voltage by connecting an arbitrary number of semiconductor switching elements in series and parallel. The configuration of this embodiment is also applicable to this embodiment.

Embodiment 4.
FIG. 9 is a diagram showing the configuration of power conversion device 120 according to the fourth embodiment. Hereinafter, points different from the third embodiment will be explained. Similarly to the third embodiment, the power converter 120 of this embodiment is also an inverter that converts DC power from a DC power supply 60 into three-phase AC power and supplies it to an AC motor 70, and each semiconductor switching element is On/off control is performed by a gate control section 1B included in the semiconductor drive control section 200B. The power conversion device 120 according to the fourth embodiment includes abnormality detection sections 20U, 20V, and 20W, each having the same configuration as the abnormality detection section 20 in the second embodiment, as abnormality detection sections provided in the semiconductor drive control section 200B. It differs from the third embodiment in that it is provided for detecting abnormalities in each of the phase, V-phase, and W-phase arm pairs. Similar to the abnormality detecting unit 20 of the second embodiment, the abnormality detecting units 20U, 20V, and 20W detect deterioration of the main withstand voltage of the semiconductor switching element and detect arm short circuit based on the determination results of the respective abnormality determining units. Or detect dead time. In Embodiment 3, the main withstand voltage deterioration of the semiconductor switching element could be determined based on the detected voltage in any arm of the three phases, but arm short circuit detection and dead time detection are It is necessary to detect using the detection voltage at . Therefore, the semiconductor drive control section 200B of this fourth embodiment includes three sets of abnormality detection sections 20U, 20V, and 20W. In the abnormality detection units 20U, 20V, and 20W, when setting the first reference voltage and the second reference voltage to the same voltage, for example, the first reference voltage and the second reference voltage generated by the reference voltage generation circuit provided in the abnormality detection unit 20U. The configuration may be such that the outputs of the two reference voltages are input to the abnormality detection section 20V and the abnormality detection section 20W.

In this way, by integrating the functions of main breakdown voltage deterioration of semiconductor switching elements, arm short circuit detection, and dead time detection, an inexpensive power conversion device 120 that can detect abnormality with high accuracy can be obtained.

Embodiment 5.
FIG. 10 is a diagram showing the configuration of power conversion device 130 according to the fifth embodiment. Hereinafter, differences from Embodiment 3 and Embodiment 4 will be explained. A power converter 130 of this fifth embodiment includes a power converter 31 configured with an arm pair of a semiconductor switching element M7 and a semiconductor switching element M8, and semiconductor switching elements M7 and M8 in the power converter 31. It includes a gate control section 1C to be driven and a semiconductor drive control section 100C having an abnormality detection section 10C. In this case, the power converter 31 is a boost converter that boosts the DC voltage of the DC power supply 60 and supplies it to the DC load 70B. The abnormality detection unit 10C is the abnormality detection unit 10 equipped with the main breakdown voltage deterioration diagnosis function shown in the first embodiment, or the abnormality detection unit 10 with the arm short circuit detection function and/or dead time detection function shown in the second embodiment. It has the same configuration as any of the sections 20.

The power converter 31 includes an arm pair in which a semiconductor switching element M7 and a semiconductor switching element M8 are connected in series, a smoothing capacitor 41 on the input side, a smoothing capacitor 42 on the output side, and a boost reactor 43. In this case as well, it is an inexpensive configuration that has a high-precision main breakdown voltage deterioration diagnosis function for semiconductor switching elements, or a power supply that has an arm short circuit detection function added to the main breakdown voltage deterioration diagnosis function, or even a dead time detection function. A converting device 130 is obtained. Note that although a step-up converter is shown in the above example, the present invention can also be applied to a step-down converter or a buck-boost converter that is a combination of a step-up converter and a step-down converter.

Embodiment 6.
FIG. 11 is a diagram showing the configuration of power conversion device 140 according to the sixth embodiment. Hereinafter, points different from the power conversion device 110 according to the third embodiment shown in FIG. 3 will be explained. The power converter 140 of this embodiment includes a power converter in which a power converter 31 which is a boost converter shown in FIG. 10 is connected to the DC side of the power converter 30 shown in FIG. 8, and each semiconductor switching element. and a semiconductor drive control section 100D having a gate control section 1D that drives the semiconductor drive control section 100D. The semiconductor drive control section 100D includes two sets of an abnormality detection section 10 and an abnormality detection section 10C in order to diagnose main breakdown voltage deterioration of the semiconductor switching elements of the power converter 30 and the power converter 31, respectively. The abnormality detection section 10 has the same configuration as the abnormality detection section 10 of the first embodiment, and the abnormality detection section 10C has the same configuration as the abnormality detection section 10C of the fifth embodiment.

In this case as well, it is possible to obtain the power conversion device 140 that can achieve zero downtime through highly accurate main withstand voltage deterioration diagnosis of semiconductor switching elements with an inexpensive configuration.

The power conversion device 140 boosts the DC voltage of the DC power supply 60 using the power converter 31 which is a step-up converter, and the boosted DC power is converted into AC power by the power converter 30 and supplied to the AC motor 70. The power conversion device 140 operates as a step-up inverter system, and is applied to, for example, an electric vehicle. Note that the power converter 30 in the power converter 140 may be an inverter capable of outputting multi-level voltages. Furthermore, the power converter 31 in the power converter 140 is not limited to a boost converter, but may be a buck converter or a buck-boost converter that is a combination of a boost converter and a buck converter.

In the first to sixth embodiments described above, the semiconductor switching elements are illustrated as MOSFETs, but other semiconductor switching elements having control terminals such as IGBTs may be used. Further, the diode shown in parallel with the MOSFET is not limited to a body diode parasitic to the MOSFET, but may be a diode provided separately.

Further, a wide bandgap semiconductor material having a larger bandgap than Si may be used for the semiconductor switching element of at least one arm pair, which speeds up the switching operation of the semiconductor switching element and reduces loss in the power conversion device. and downsizing. As the wide bandgap semiconductor material, silicon carbide SiC, gallium nitride GaN, gallium oxide-based material GaO, or diamond can be used.

The abnormality determination unit in each of the above embodiments can be configured with a logic circuit or can be configured with arithmetic processing by a processor. The gate driving section can be configured by a circuit that combines an ordinary integrated circuit and circuit elements such as a resistor and a capacitor. Further, the gate signal generating section can also be configured by a logic circuit, an integrated circuit, or other circuit elements such as a resistor. Furthermore, for example, the gate signal generation section 2, or the gate signal generation section and the abnormality determination section may be combined together, and the data may be exchanged with an arithmetic processing unit 21 such as a CPU (Central Processing Unit), as shown in FIG. It can also be configured with a processing device including a storage device 22 for exchanging data, an input/output interface 23 for inputting and outputting signals between the arithmetic processing device 21 and the outside, and the like.

Although various exemplary embodiments and examples are described in this application, various features, aspects, and functions described in one or more embodiments may be more specific to a particular embodiment. The invention is not limited to application, and can be applied to the embodiments alone or in various combinations. Accordingly, countless variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, this includes cases where at least one component is modified, added, or omitted, and cases where at least one component is extracted and combined with components of other embodiments.

1, 1A, 1B, 1C, 1D Gate control section, 2 Gate signal generation section, 3 Arm pair, 4 Reference voltage generation circuit, 5 Second resistance group, 6 Third resistance group, 10, 10C, 20, 20U, 20V , 20W abnormality detection section, 11, 12 abnormality determination section, 100, 100A, 100C, 100D, 200, 200B semiconductor drive control section, M1 first semiconductor switching element, M2 second semiconductor switching element, C arm midpoint, C1 second 1 capacitor, C2 2nd capacitor, GA negative terminal, PA positive terminal, R1 1st resistor, R2 2nd resistor, VdM detection voltage, VrefH 1st reference voltage, VrefL 2nd reference voltage

Claims (16)

1. One of the DC positive and negative terminals is a first pole terminal and the other is a second pole terminal, a first semiconductor switching element is connected between the first pole terminal and the arm midpoint, and a first semiconductor switching element is connected between the arm midpoint and the second pole terminal. A power conversion device having a pair of arms with a second semiconductor switching element connected between the pole terminals,
   a semiconductor drive control unit that has an abnormality detection unit and a gate control unit and controls driving of the first semiconductor switching element and the second semiconductor switching element;
   The abnormality detection section includes:
   a third resistor group connected in parallel to the first semiconductor switching element and having at least one resistor;
   a second resistance group including a plurality of series resistors connected in parallel with the second semiconductor switching element so as to divide the voltage applied to the second semiconductor switching element;
   a first reference voltage obtained by dividing the voltage between the first electrode terminal and the second electrode terminal; and a first reference voltage obtained by dividing the voltage between the first electrode terminal and the second electrode terminal. a reference voltage generation circuit that generates a second reference voltage that is different from the reference voltage;
   After the power conversion device stops power conversion operation, the detected voltage, which is the voltage divided by the second resistance group, is compared with the first reference voltage and the second reference voltage, and A power conversion device comprising: an abnormality determination unit that determines whether the main breakdown voltage of one semiconductor switching element or the second semiconductor switching element has deteriorated.
2. The abnormality determination unit is configured to determine whether the detected voltage is a voltage that deviates from a voltage between the first reference voltage and the second reference voltage after the power conversion device stops power conversion operation. The power conversion device according to claim 1, wherein the semiconductor switching element or the second semiconductor switching element is determined to have degraded main breakdown voltage.
3. The abnormality determination unit is configured to detect that when the first semiconductor switching element or the second semiconductor switching element is turned on, the detection voltage is the detection voltage when the first semiconductor switching element and the second semiconductor switching element are normal. The power conversion device according to claim 1 or 2, wherein when the voltage is logically inconsistent with the voltage, it is determined that the arm pair is in an arm short-circuited state.
4. The power conversion device according to claim 3, having a plurality of the arm pairs, and having the abnormality detection section for each of the arm pairs.
5. One of the DC positive and negative terminals is a first pole terminal and the other is a second pole terminal, a first semiconductor switching element is connected between the first pole terminal and the arm midpoint, and a first semiconductor switching element is connected between the arm midpoint and the second pole terminal. A power conversion device having a plurality of arm pairs with a second semiconductor switching element connected between pole terminals,
   a semiconductor drive control unit that has an abnormality detection unit and a gate control unit and controls the drive of the first semiconductor switching element and the second semiconductor switching element of all the arm pairs;
   The abnormality detection section includes:
   a third resistor group connected in parallel to the first semiconductor switching element of one arm pair among the plurality of arm pairs, and having at least one resistor;
   a second semiconductor switching element including a plurality of series resistors connected in parallel with the second semiconductor switching element of the one arm pair to divide the voltage applied to the second semiconductor switching element of the one arm pair; resistance group,
   a first reference voltage obtained by dividing the voltage between the first electrode terminal and the second electrode terminal; and a first reference voltage obtained by dividing the voltage between the first electrode terminal and the second electrode terminal. a reference voltage generation circuit that generates a second reference voltage that is different from the reference voltage;
   After the power conversion device stops power conversion operation, the detected voltage, which is the voltage divided by the second resistance group, is compared with the first reference voltage and the second reference voltage, and a plurality of A power conversion device comprising: an abnormality determining section that determines whether or not the main withstand voltage of one of the semiconductor switching elements constituting the arm pair has deteriorated.
6. The abnormality determination unit determines the time period from when the power conversion device stops power conversion operation until the detected voltage deviates from a voltage between the first reference voltage and the second reference voltage, or The power conversion device according to claim 1 or 5, wherein it is determined whether the main breakdown voltage has deteriorated based on the amount of change per unit time.
7. 7. The abnormality determination unit determines whether the main breakdown voltage has deteriorated when the temperature of all the semiconductor switching elements is higher than the surrounding environmental temperature. power converter.
8. The power conversion device according to any one of claims 1 to 7, wherein a capacitor is connected in parallel to at least one resistor of the second resistor group.
9. The second resistor group is composed of a first resistor on the arm midpoint side with a resistance value of Rs1, and a second resistor connected to this first resistor with a resistance value of Rs2, which is connected in series, and has a capacitance. A first capacitor with a capacitance of Cs1 is connected in parallel with the second resistor, a second capacitor with a capacitance of Cs2 is connected in parallel with the first resistor, and Rs2/(Rs1+Rs2)<Cs2/(Cs1+Cs2). The power conversion device according to claim 3 or 4, which satisfies the following relationship.
10. The abnormality determination unit is configured to determine whether the detected voltage is equal to or less than the first semiconductor switching element based on an ON command output from a gate signal generation unit provided in the gate control unit to the first semiconductor switching element or the second semiconductor switching element. A dead time is calculated based on the time taken to cross the reference voltage or the second reference voltage, and based on the calculated dead time, the gate signal generating section outputs the first semiconductor switching element and the second semiconductor switching element. The power conversion device according to claim 9, wherein the amount of dead time due to on/off signals of each of the semiconductor switching elements is corrected.
11. The resistance value between both ends of the second resistor group is such that the current value flowing through the second resistor group is such that the value of the current flowing through the second resistor group is between the main terminals in an initial state of the second semiconductor switching element connected in parallel to the second resistor group. The resistance value between both ends of the third resistance group is set to be larger than the parasitic leakage current value, and the value of the current flowing through the third resistance group is set to be larger than the parasitic leakage current value. The power conversion device according to any one of claims 1 to 10, wherein the power conversion device is set to be larger than a leakage current value parasitic between the main terminals in an initial state of the first semiconductor switching element.
12. The power conversion device according to any one of claims 1 to 11, wherein a resistance value between both ends of the second resistance group and a resistance value between both ends of the third resistance group are equal.
13. The semiconductor drive control unit changes the operation of the power conversion device so that the load on the semiconductor switching element is reduced after the abnormality determination unit determines that the main breakdown voltage of one of the semiconductor switching elements has deteriorated. The power conversion device according to any one of claims 1 to 12.
14. The power conversion device includes at least one of a power converter that converts power between DC power and AC power, a step-up converter that steps up a DC voltage, and a step-down converter that steps down a DC voltage. The power conversion device according to any one of claims 1 to 13, which is a conversion device.
15. The arm pair constitutes a power conversion circuit that performs power conversion between DC power and AC power, and when a motor is connected as a load on the AC side, the abnormality determination section determines whether the power conversion After the device stops power conversion operation, when the detected voltage is a voltage that deviates from the voltage between the first reference voltage and the second reference voltage, the main withstand voltage of one of the semiconductor switching elements has deteriorated. The power conversion device according to claim 1 or 5, wherein the power converter determines that the electric motor is present or that insulation of the electric motor is deteriorated.
16. The power conversion device according to any one of claims 1 to 15, wherein the semiconductor switching element constituting at least one arm pair is made of a wide bandgap semiconductor material having a larger bandgap than Si.

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