WO2023140010A1 - Power source circuit - Google Patents

Power source circuit Download PDF

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Publication number
WO2023140010A1
WO2023140010A1 PCT/JP2022/046824 JP2022046824W WO2023140010A1 WO 2023140010 A1 WO2023140010 A1 WO 2023140010A1 JP 2022046824 W JP2022046824 W JP 2022046824W WO 2023140010 A1 WO2023140010 A1 WO 2023140010A1
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WO
WIPO (PCT)
Prior art keywords
circuit
input
winding
power supply
terminal
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PCT/JP2022/046824
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French (fr)
Japanese (ja)
Inventor
規央 鈴木
晃郎 島田
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三菱電機株式会社
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Publication of WO2023140010A1 publication Critical patent/WO2023140010A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to power supply circuits.
  • a power supply circuit is a circuit that generates a constant voltage for a certain input voltage range.
  • a power supply circuit when generating 5V from an input voltage of AC 85V to 264V and when generating 5V from an input voltage of DC 24V, there is a large difference in input voltage range between the two, so it is common to use separate power supplies.
  • a non-insulated power supply (system power supply) is mainly used as a power supply for AC85V to 264V input voltage, and an isolated power supply is mainly used as a power supply for DC24V input voltage.
  • the reference potentials (grounds) of these power supplies are different. Therefore, when a plurality of input voltages are input to one electrical device and the same operation is performed, it is necessary to prepare a plurality of power sources and switching transformers.
  • Patent Document 1 a method of providing a plurality of input windings in one transformer is disclosed.
  • the power supply circuit described in Patent Document 1 requires two windings, one for generating the output voltage and the other for applying the input voltage. Furthermore, in the power supply circuit described in Patent Document 1, it is necessary to electrically separate the output voltage terminal and the input voltage terminal.
  • an object of the present disclosure is to provide a power supply circuit that can be driven by different input voltages of a plurality of grounds, that can generate a plurality of output voltages, and that at least one of the plurality of output voltage terminals is electrically shared with the input voltage terminal.
  • a power supply circuit of the present disclosure includes a switching transformer having a first winding, a second winding, and a third winding, a first circuit, a second circuit, and a third circuit.
  • the first circuit includes a positive input terminal and a negative input terminal configured to receive the voltage of the first power supply, a first switch that switches on or off the application of the input voltage to the first winding, and a first control circuit that controls the first switch.
  • the second circuit includes a second control circuit for switching between receiving the voltage of the second power supply and inducing power in the second winding, or outputting the power induced in the second winding to an external load according to the voltage applied to the first winding.
  • the third circuit includes an output positive terminal and an output negative terminal that output power induced in the third winding according to the voltage applied to the first winding or the second winding, and a feedback circuit that feeds back a feedback signal that varies according to the output voltage generated between the output positive terminal and the output negative terminal to the first control circuit and the second control circuit.
  • the power supply circuit of the present disclosure can be driven by a plurality of input voltages with different grounds, can generate a plurality of output voltages, and can electrically share at least one of the plurality of output voltage terminals with the input voltage terminal.
  • FIG. 1 is a diagram showing a configuration of a power supply circuit 100 according to Embodiment 1;
  • FIG. 3 is a diagram showing waveforms of voltage and current in power supply circuit 100 when input voltage Vin1 is input to first circuit 10 and input voltage Vin2 is not input to second circuit 20 in Embodiment 1.
  • FIG. 3 is a diagram showing waveforms of voltage and current in power supply circuit 100 when input voltage Vin2 is input to second circuit 20 and input voltage Vin1 is not input to first circuit 10 in Embodiment 1.
  • FIG. It is a figure which shows the structure of the power supply circuit of a reference example.
  • FIG. 10 is a diagram showing a configuration of a power supply circuit 200 according to a second embodiment;
  • FIG. 10 is a diagram showing waveforms of voltage and current in the power supply circuit 200 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20A in the second embodiment;
  • FIG. 10 is a diagram showing waveforms of voltage and current in power supply circuit 200 when input voltage Vin2 is input to second circuit 20A and input voltage Vin1 is not input to first circuit 10A in Embodiment 2;
  • FIG. 10 is a diagram showing a configuration of a power supply circuit 200A of a modified example of the second embodiment;
  • FIG. 10 is a diagram showing a configuration of a power supply circuit 300 according to a third embodiment;
  • FIG. 10 is a diagram showing waveforms of voltage and current in power supply circuit 300 when input voltage Vin2 is input to second circuit 20B and input voltage Vin1 is not input to first circuit 10A in Embodiment 3;
  • FIG. 13 is a diagram showing a configuration of a power supply circuit 400 according to a fourth embodiment;
  • FIG. 11 is a diagram showing waveforms of voltage and current in power supply circuit 400 when input voltage Vin2 is input to second circuit 20D and input voltage Vin1 is not input to first circuit 10A in Embodiment 4;
  • FIG. 13 is a diagram showing a configuration of a power supply circuit 400A of a modified example of the fourth embodiment;
  • FIG. 1 is a diagram showing the configuration of a power supply circuit 100 according to the first embodiment.
  • the power supply circuit 100 includes a switching transformer 3 , a first circuit 10 , a second circuit 20 and a third circuit 30 .
  • the switching transformer 3 includes a first winding N1, a second winding N2, and a third winding N3.
  • the winding directions of the first winding N1, the second winding N2 and the third winding N3 are the same.
  • a first end without a polarity point of the first winding N1 faces a second end with a polarity point of the third winding N3.
  • the second end of the first winding N1 with a polarity point faces the first end of the third winding N3 without a polarity point.
  • the first end of the first winding N1 without a polarity point faces the second end of the second winding N2 with a polarity point.
  • the second end of the first winding N1 with a polarity point faces the first end of the second winding N2 without a polarity point.
  • the polar point means the starting point of the winding.
  • the first circuit 10 is configured to be connectable with the first power supply 1 .
  • the first circuit 10 is configured to be able to receive an input voltage Vin1 from the first power supply 1 .
  • the second circuit 20 is configured to be connectable to the second power supply 2 .
  • the second circuit 20 is configured to receive the input voltage Vin2 from the second power supply 2 and to output the output voltage Vout1 to a load (not shown).
  • the third circuit 30 is configured to output the output voltage Vout2 to a load (not shown).
  • the first circuit 10 includes a positive input terminal P12, a negative input terminal N12, a capacitor (first capacitor) 12, a resistor (first resistor) 13, a capacitor (second capacitor) 14, a diode (first diode) 11, a diode (second diode) 15, a switch (first switch) 17, and a first control circuit 501.
  • the input positive terminal P12 and the input negative terminal N12 are connected to the first power supply positive terminal P11 and the first power supply negative terminal N11 of the first power supply 1, respectively.
  • the positive input terminal P12 and the negative input terminal N12 are configured to receive the input voltage Vin1 from the first power supply 1 .
  • the capacitor 12 is connected between the positive input terminal P12 and the negative input terminal N12, and receives the voltage of the first power supply 1 as the input voltage Vin1.
  • the cathode of the diode 11 is connected to the first end of the first winding N1.
  • the anode of diode 15 is connected to the second end of first winding N1.
  • the resistor 13 is connected between the positive input terminal P12 and the anode of the diode 11 and the cathode of the diode 15 .
  • Capacitor 14 is connected between input positive terminal P 12 and the anode of diode 11 and the cathode of diode 15 .
  • the first end of the resistor 13, the first end of the capacitor 14, and the anode of the diode 11 are connected to the positive input terminal P12.
  • a second end of resistor 13 and a second end of capacitor 14 are connected to the cathode of diode 15 .
  • the resistor 13, capacitor 14, and diode 15 constitute an RCD snubber circuit.
  • a first end of the switch 17 is connected to the second end of the first winding N1 and the anode of the diode 15.
  • a second end of the switch 17 is connected to the negative input terminal N12.
  • a switch 17 switches on or off the application of the input voltage to the first winding N1.
  • the first control circuit 501 monitors, for example, the voltage of the input positive terminal P12, and when the voltage of the first power supply 1 is input to the first circuit 10, transmits a detection signal DT indicating that the voltage of the first power supply 1 is input to the first circuit 10 to the second control circuit 502 in the second circuit 20.
  • the first control circuit 501 controls the switch 17 based on the feedback signal FB from the third circuit 30 .
  • a control signal CT1 that the first control circuit 501 outputs to the switch 17 is, for example, a PWM (Pulse Width Modulation) signal.
  • the first control circuit 501 is configured to be driven by power from the first power supply 1 .
  • the second circuit 20 includes a positive input/output terminal P22, a negative input/output terminal N22, a load resistor (fourth resistor) 23, a capacitor (third capacitor) 22, a switch (second switch) 24, a switch (third switch) 25, a diode (third diode) 21, and a second control circuit 502.
  • the input/output positive terminal P22 and the input/output negative terminal N22 are connected to the second power supply positive terminal P21 and the second power supply negative terminal N21 of the second power supply 2, respectively.
  • Input/output positive terminal P22 and input/output negative terminal N22 are configured to be able to receive the voltage of second power supply 2 and to output power induced in second winding N2 according to the voltage applied to first winding N1 to an external load (not shown).
  • the capacitor 22 and the load resistor 23 are connected between the input/output positive terminal P22 and the input/output negative terminal N22. Capacitor 22 and load resistor 23 output an output voltage Vout1 or receive an input voltage Vin2.
  • the switch 24 is configured to switch between outputting the power induced in the second winding N2 to the positive input/output terminal P22 and the negative input/output terminal N22, or inputting power from the second power supply 2 to the second winding N2.
  • the switch 24 has an output state terminal C1 and an input state terminal C2.
  • the input state terminal C2 is connected to the first end of the second winding N2 and the cathode of the diode 21.
  • Output state terminal C 1 is connected to the second end of second winding N 2 and to the first end of switch 25 .
  • the switch 24 switches between connecting the input/output positive terminal P22 to the output state terminal C1 or connecting it to the input state terminal C2 according to the control signal CT3 from the second control circuit 502 .
  • the second end of the switch 25 and the anode of the diode 21 are connected to the input/output negative terminal N22.
  • a switch 25 switches on or off the application of the input voltage to the second winding N2.
  • the input negative terminal N12 and the input/output negative terminal N22 are insulated by, for example, reinforced insulation, so that these potentials become different potentials.
  • the second control circuit 502 switches between receiving the voltage of the second power supply 2 and inducing power in the second winding N2, or outputting the power induced in the second winding N2 according to the voltage applied to the first winding N1 to an external load.
  • the second control circuit 502 controls the switch 24 with the control signal CT3.
  • the second control circuit 502 controls the switch 25 with the control signal CT2 based on the feedback signal FB from the third circuit 30.
  • the control signal CT2 output by the second control circuit 502 to the switch 25 is, for example, a PWM signal.
  • the second control circuit 502 is configured to be driven by power from the second power supply 2 or power (output voltage Vout1) induced in the second winding N2 according to the voltage applied to the first winding N1.
  • the third circuit 30 includes a positive output terminal P31 and a negative output terminal N31, a capacitor 32, a load resistor 33, a diode 31, and a feedback circuit 503.
  • the output positive terminal P31 and the output negative terminal N31 output power induced in the third winding N3 to an external load (not shown) according to the voltage applied to the first winding N1 or the second winding N2.
  • the capacitor 32 and the load resistor 33 are connected between the output positive terminal P31 and the output negative terminal N31. Capacitor 32 and load resistor 33 can output an output voltage Vout2.
  • a first end of the capacitor 32 and a first end of the load resistor 33 are connected to the output positive terminal P31 and the cathode of the diode 31 .
  • a second end of the capacitor 32 and a second end of the load resistor 33 are connected to the output negative terminal N31 and the first end of the third winding N3.
  • the output negative terminal N31 is connected to the first end of the third winding N3.
  • the anode of the diode 31 is connected to the second end of the third winding N3.
  • a cathode of the diode 31 is connected to the output positive terminal P31.
  • the feedback circuit 503 transmits a feedback signal FB that changes according to the output voltage Vout2 generated between the output positive terminal P31 and the output negative terminal N31 to the first control circuit 501 of the first circuit 10 and the second control circuit 502 of the second circuit 20.
  • an isolation element such as a photocoupler can be used.
  • the current of the first winding N1, the current of the second winding N2, and the current of the third winding N3 (hereinafter simply referred to as the N1 current, N2 current, and N3 current, respectively) are positive when flowing from the first end to the second end. In the following, the forward voltage of each diode is ignored for simplicity.
  • FIG. 2 is a diagram showing voltage and current waveforms in the power supply circuit 100 when the input voltage Vin1 is input to the first circuit 10 and the input voltage Vin2 is not input to the second circuit 20 in the first embodiment.
  • the first power supply positive terminal P11 and the input positive terminal P12 are connected, and the first power supply negative terminal N11 and the input negative terminal N12 are connected. At least one of the second power supply positive terminal P21 and the input/output positive terminal P22 and the second power supply negative terminal N21 and the input negative terminal N22 is not connected.
  • the positive input/output terminal P22 is connected to the output state terminal C1.
  • IP Vin1 ⁇ ton1/L1...(A1) Energy is accumulated in the switching transformer 3 by the triangular wave current flowing through the first winding N1.
  • N2 current flows through the circuit loop formed by second winding N2, output state terminal C1, capacitor 22, and diode 21 to produce output voltage Vout1 at positive input/output terminal P22.
  • N3 current flows through the circuit loop formed by third winding N3, diode 31 and capacitor 32 to produce output voltage Vout2 at output positive terminal P31.
  • the N1 current flows through the circuit loop formed by the first winding N1, diode 15, capacitor 14 and diode 11 and develops a snubber voltage across resistor 13 and capacitor 14.
  • the feedback circuit 503 included in the third circuit 30 transmits to the first control circuit 501, for example, a feedback signal FB that varies according to the output voltage Vout2 generated between the positive output terminal P31 and the negative output terminal N31.
  • the first control circuit 501 stabilizes the output voltage Vout2 by changing the flow time ton1 based on the feedback signal FB.
  • the voltage ratio between the output voltage Vout1 and the output voltage Vout2 is generally equal to the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3, as shown below.
  • the average current of the N2 current is equal to the average current flowing through the load resistor 23.
  • the average current of the N3 current is equal to the average current flowing through the load resistor 33.
  • the voltage V17 across the switch 17 after the switch 17 is turned off can be expressed by the following formula using the output voltage Vout2 of the third circuit 30 including the feedback circuit 503, the square root of the ratio between the inductance L1 of the first winding N1 and the inductance L3 of the third winding N3, and the input voltage Vin1.
  • the average value of the N2 current is equal to the sum of the average values of the currents flowing through the load resistor 23 and the external load.
  • the average value of the N3 current is equal to the sum of the average values of the currents flowing through the load resistor 33 and the external load.
  • FIG. 3 is a diagram showing voltage and current waveforms in power supply circuit 100 when input voltage Vin2 is input to second circuit 20 and input voltage Vin1 is not input to first circuit 10 in the first embodiment.
  • the second power supply positive terminal P21 and the input/output positive terminal P22 are connected, and the second power supply negative terminal N21 and the input negative terminal N22 are connected. At least one of the first power supply positive terminal P11 and the input/output positive terminal P12 and the first power supply negative terminal N11 and the input negative terminal N12 is not connected.
  • the second control circuit 502 drives the switch 24 with the control signal CT3 to connect the positive input/output terminal P22 to the input state terminal C2.
  • a peak current Ip2 of the N2 current is expressed by the following equation using the flow time ton2.
  • Ip2 Vin2 ⁇ ton2/L2...(B1) Energy is accumulated in the switching transformer 3 by the triangular wave current flowing through the second winding N2.
  • the stored energy causes a triangular wave current to flow through the first winding N1 and the third winding N3.
  • the N1 current flows through the circuit loop formed by the first winding N1, diode 11, capacitor 14 and diode 15 and develops a voltage across resistor 13 and capacitor 14.
  • FIG. N3 current flows through the circuit loop formed by third winding N3, diode 31 and capacitor 32 to produce output voltage Vout2 at output positive terminal P31.
  • a feedback circuit 503 included in the third circuit 30 transmits to the second control circuit 502, for example, a feedback signal FB that varies according to the output voltage Vout2 generated between the positive output terminal P31 and the negative output terminal N31.
  • the second control circuit 502 stabilizes the output voltage Vout2 by changing the flow time ton2 based on the feedback signal FB.
  • the average current of the N3 current is equal to the average current flowing through the load resistor 33.
  • the voltage V25 across the switch 25 after the switch 25 is turned off can be expressed by the following formula using the output voltage Vout2 of the third circuit including the feedback circuit 503, the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3, and the input voltage Vin2.
  • an external load can be connected to the output positive terminal P31 and the output negative terminal N31, so that the output voltage Vout2 can be provided to the outside and electric power can be supplied to the outside.
  • the average value of the N3 current is equal to the sum of the average values of the currents flowing through the load resistor 33 and the external load.
  • Input voltage Vin1 and input voltage Vin2 may be input at the same time.
  • the switch 24 is controlled by the first control circuit 501 and the second control circuit 502 so that the positive input/output terminal P22 is connected to the output state terminal C1.
  • Power is supplied from the first circuit 10 to the second circuit 20 and the third circuit 30 by the switch 17 driven by the first control circuit 501 and the switching transformer 3 .
  • power is supplied to the load resistor 23 from the input voltage Vin2 or the output voltage Vout2 generated by the second circuit 20, whichever is higher.
  • the power supply circuit 100 has been described above as including one first circuit 10, one second circuit 20, and one third circuit 30, it is not limited to this.
  • the power supply circuit 100 may include multiple first circuits 10 , multiple second circuits 20 , and multiple third circuits 30 .
  • the power supply circuit 100 becomes a multi-input/output power supply circuit. Even in this case, it is sufficient to increase the number of windings after the fourth winding in the switching transformer 3, and there is no need to provide a plurality of switching transformers unlike the conventional configuration shown in FIG.
  • the output voltage Vout1 and the output voltage Vout2 can be output.
  • voltage is applied from the first end of the second winding N2 that has no polarity point, and the second end of the second winding N2 that has a polarity point is switched, so that a step-up operation is possible, and even if the value of the input voltage Vin2 is small, it is possible to output an output voltage Vout2 that is greater than the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 multiplied by the input voltage Vin2.
  • the positive input/output terminal P22 and the negative input/output terminal N22 have both a function as an input terminal for inputting the input voltage Vin2 and a function as an output terminal for outputting the output voltage Vout1.
  • the input terminal and the output terminal can be shared, so the number of terminals can be reduced. As a result, the power supply circuit can be miniaturized. Furthermore, according to the present embodiment, it is possible to allow the user to make a mistake in the wiring of the input/output terminals, thereby improving safety.
  • FIG. 4 is a diagram showing the configuration of the power supply circuit of the reference example.
  • An output voltage Vout1 is generated using the first circuit 40A, the third circuit 50A, and the switching transformer 3A, and the output voltage Vout1 is output from the second power supply positive terminal P21 and the second power supply negative terminal N21.
  • the second power positive terminal P21 and the second power negative terminal N21 are connected to the input/output positive terminal P22 and the input/output negative terminal N22, respectively.
  • An output voltage Vout2 is generated using the first circuit 40B, the third circuit 50B, and the switching transformer 3B, and the output voltage Vout2 is output from the output positive terminal P31 and the output negative terminal N31.
  • the power conversion efficiency of one power source is 80%
  • the power conversion efficiency of the other power source is 80%
  • the overall power conversion efficiency is 64%. Therefore, the power conversion efficiency of the power supply circuit of the reference example is poor.
  • the power supply circuit of the reference example has a problem that it generates a lot of heat. Since the power supply circuit of the reference example requires two switching transformers and two feedback circuits, there is a problem of an increase in size.
  • FIG. 5 is a diagram showing the configuration of the power supply circuit 200 according to the second embodiment.
  • the power supply circuit 200 includes a first circuit 10A, a second circuit 20A, a third circuit 30, and a switching transformer 3.
  • Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated.
  • the first circuit 10A differs from the first circuit 10 of Embodiment 1 in that the first circuit 10A includes an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 47 instead of the switch 17 as the first switch.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the drain of the n-channel MOSFET 55 is connected to the second end of the first winding N1 and the anode of the diode 15.
  • the source of the n-channel MOSFET 55 is connected to the negative input terminal N12.
  • the second circuit 20A differs from the second circuit 20 of Embodiment 1 in that the second circuit 20A includes a relay 54 instead of the switch 24 as the second switch, and an n-channel MOSFET (first transistor) 55 instead of the switch 25 as the third switch.
  • the second circuit 20A further includes a Zener diode 56 connected in parallel with the n-channel MOSFET (first transistor) 55 .
  • the drain of the n-channel MOSFET 55 and the cathode of the Zener diode 56 are connected to the second terminal of the second winding N2 and the output state terminal C1.
  • the source of the n-channel MOSFET 55 and the anode of the Zener diode 56 are connected to the anode of the diode 21, the second end of the load resistor 23, the second end of the capacitor 22, and the input/output negative terminal N22.
  • the Zener voltage Vz of the Zener diode 56 is selected to be less than the drain-source voltage rated voltage of the n-channel MOSFET 55 .
  • the first control circuit 501 operates with the input voltage Vin1.
  • the second control circuit 502 operates with the input voltage Vin2.
  • the relay 54 has a c contact. Even when the power supply circuit 200 is in a non-energized state, the positive input/output terminal P22 is connected to the output state terminal C1. As a result, even when the input voltage Vin2 is not supplied to the second control circuit 502 and the second control circuit 502 is not operating, a loop circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 200 can be activated only by the input voltage Vin1.
  • the second control circuit 502 When the input voltage Vin2 is connected to the second circuit 20A, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, the second control circuit 502 drives the relay 54 by the control signal CT3 to connect the positive input/output terminal P22 to the input state terminal C2. This starts driving the n-channel MOSFET 55 .
  • the second control circuit 502 When the second control circuit 502 receives the detection signal DT from the first control circuit 501, the second control circuit 502 does not drive the relay 54 and maintains the state in which the positive input/output terminal P22 is connected to the output state terminal C1. This allows simultaneous input of the input voltage Vin1 and the input voltage Vin2.
  • FIG. 6 is a diagram showing voltage and current waveforms in the power supply circuit 200 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20A in the second embodiment.
  • FIG. 6 shows the drain-source voltage of the n-channel MOSFET 47 instead of the voltage across the switch 17 shown in FIG. Embodiment 1 shows the operation with an ideal switch and transformer. However, in an actual circuit, the switching transformer 3 has leakage inductance in each winding. Immediately after the n-channel MOSFET 47 is turned off, a surge voltage exceeding the voltage V17 of the above equation (A3) is generated. This surge voltage is suppressed below the drain-source rated voltage of n-channel MOSFET 47 by resistor 13, capacitor 14, and diode 15, which are RCD snubber circuits.
  • the drain-source voltage of the n-channel MOSFET 47 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 47, the parasitic capacitance of the diode 11, and the inductance L1 of the first winding N1.
  • FIG. 7 is a diagram showing voltage and current waveforms in the power supply circuit 200 when the input voltage Vin2 is input to the second circuit 20A and the input voltage Vin1 is not input to the first circuit 10A in the second embodiment.
  • the Zener voltage Vz of the Zener diode 56 is selected to be lower than the drain-source voltage rated voltage of the n-channel MOSFET 55. Therefore, as shown in FIG. 7, the surge voltage is clamped at Vz, and the n-channel MOSFET 55 can be protected with a simple configuration.
  • FIG. 8 is a diagram showing a configuration of a power supply circuit 200A according to a modification of the second embodiment.
  • the power supply circuit 200A includes a first circuit 10A, a second circuit 20C, a third circuit 30, and a switching transformer 3.
  • Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
  • the second circuit 20C differs from the second circuit 20A of the second embodiment in that the second circuit 20C includes an RCD snubber circuit 89 connected across the second winding N2 instead of the Zener diode 56.
  • the RCD snubber circuit 89 comprises a resistor 81, a capacitor 82 and a diode 83.
  • the anode of the diode 83 is connected to the second end of the second winding N2 and the output state terminal C1.
  • the cathode of diode 83 is connected to the first end of resistor 81 and the first end of capacitor 82 .
  • the second end of resistor 81 and the second end of capacitor 82 are connected to the first end of second winding N2, the cathode of diode 21, and input state terminal C2.
  • the effect of suppressing the drain-source voltage of the n-channel MOSFET 55 can be obtained, similar to the Zener diode 56 in the second embodiment.
  • FIG. 9 is a diagram showing the configuration of a power supply circuit 300 according to the third embodiment.
  • the power supply circuit 300 includes a first circuit 10A, a second circuit 20B, a third circuit 30, and a switching transformer 3.
  • Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
  • the second circuit 20B differs from the second circuit 20A of the second embodiment in that instead of the relay 54, the second circuit 20B includes a diode (fourth diode) 61, a diode (fifth diode) 62, a p-channel MOSFET (second transistor) 63, an n-channel MOSFET (third transistor) 64, a resistor (second resistor) 65, and a resistor (third resistor) 66.
  • the second circuit 20B does not include the Zener diode 56.
  • a Zener diode 56 is provided to suppress a surge voltage generated across the n-channel MOSFET 55 when it is turned off.
  • the Zener diode 56 is not provided because a circuit for suppressing the surge voltage is not required.
  • the anode of the diode 62 is connected to the second end of the second winding N2 and the drain (first electrode) of the n-channel MOSFET 55.
  • the cathode of diode 62 is connected to the source (first electrode) of p-channel MOSFET 63, the first end of resistor 65, the first end of capacitor 22, the first end of load resistor 23, and input/output positive terminal P22.
  • the drain (second electrode) of the p-channel MOSFET 63 is connected to the anode of the diode 61 .
  • the cathode of diode 61 is connected to the first end of second winding N2 and the cathode of diode 21 .
  • a gate (control electrode) of the p-channel MOSFET 63 is connected to the second end of the resistor 65 and the first end of the resistor 66 .
  • a second end of resistor 66 is connected to the drain (first electrode) of n-channel MOSFET 64 .
  • the source (second electrode) of the n-channel MOSFET 64 is connected to the anode of the diode 21, the source (second electrode) of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the negative input/output terminal N22.
  • a control signal CT4 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 64 and the gate (control electrode) of the n-channel MOSFET 55 .
  • the first control circuit 501 operates with the input voltage Vin1.
  • the second control circuit 502 operates with the input voltage Vin2.
  • the first control circuit 501 controls the n-channel MOSFET 47.
  • the N2 current flows through the circuit loop formed by the second winding N2, the diode 62, the capacitor 22, and the diode 21 to generate the output voltage Vout1 at the input/output positive terminal P22.
  • the circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 300 can be activated only by the input voltage Vin1.
  • the power supply circuit 300 can be operated in the same manner as the power supply circuit 200 shown in the second embodiment.
  • FIG. 10 is a diagram showing voltage and current waveforms in power supply circuit 300 when input voltage Vin2 is input to second circuit 20B and input voltage Vin1 is not input to first circuit 10A in the third embodiment.
  • the second control circuit 502 receives the input voltage Vin2 and starts up.
  • the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, it starts driving the n-channel MOSFET 55 and the n-channel MOSFET 64 by the control signal CT4.
  • the n-channel MOSFET 64 is provided to drive the gate of the p-channel MOSFET 63 .
  • the gate-source voltage of the p-channel MOSFET 63 is 0, and the p-channel MOSFET 63 is off.
  • the n-channel MOSFET 64 is on, the gate-source voltage of the p-channel MOSFET 63 becomes a value obtained by dividing Vin2 by the resistors 65 and 66, and the p-channel MOSFET 63 is turned on.
  • the resistor 66 is unnecessary and can be shorted. That is, the second terminal of the resistor 65 and the drain of the N-channel MOSFET 64 should be connected.
  • the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 can be driven simultaneously.
  • the drain-source voltage of the n-channel MOSFET 55 is zero.
  • a triangular current corresponding to the inductance L2 and the input voltage Vin2 flows through the circuit loop formed by the capacitor 22, the p-channel MOSFET 63, the diode 61, the second winding N2, and the n-channel MOSFET 55.
  • the peak current Ip3 of the N2 current is expressed by the following equation using the flow time ton2, similarly to the power supply circuit 100 of the first embodiment and the power supply circuit 200 of the second embodiment.
  • Ip3 Vin2 ⁇ ton2/L2...(C1) As a result, energy is stored in the switching transformer 3 .
  • the stored energy causes a triangular wave current to flow through the first winding N1 and the third winding N3.
  • the voltage between the drain and source of the n-channel MOSFET 55 is equal to the input voltage Vin2 in the period when the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 are all turned off (hereinafter referred to as "off period").
  • off period the period when the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 are all turned off.
  • the drain-source voltage of the n-channel MOSFET 55 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 55, the parasitic capacitance between the drain and source of the p-channel MOSFET 63, the parasitic capacitance of the diode 61, the parasitic capacitance of the diode 62, and the inductance L2 of the second winding N2.
  • the simultaneous input of the input voltage Vin1 and the input voltage Vin2 can be allowed by not driving the n-channel MOSFET 55 and the n-channel MOSFET 64.
  • the power supply circuit 300 of the third embodiment is a highly efficient power supply circuit as compared with the power supply circuit 200 of the second embodiment in which energy is consumed by the Zener diode 56 .
  • the limit value LM is represented by the following formula.
  • the power supply circuit 300 of the third embodiment does not need to drive the relay 54 when the input voltage Vin2 is input, so the power supply circuit 300 can be started at high speed. Since the power supply circuit 300 of the third embodiment does not need to drive the relay 54, the size of the second control circuit 502 can be reduced.
  • the relay 54 has been described as being configured by a relay having a c-contact, it is not limited to this.
  • the relay 54 may be configured by combining a relay having an a-contact and a relay having a b-contact.
  • As the relay 54 (a) a semiconductor analog switch, (b) a photoMOS relay, (c) a photovoltaic output photocoupler and MOSFET, (d) a photothyristor, or the like can be used.
  • a bipolar transistor can be used instead of a MOSFET.
  • the n-channel MOSFET can be composed of an NPN transistor
  • the p-channel MOSFET can be composed of a PNP transistor.
  • the resistance 65 can be reduced.
  • FIG. 11 is a diagram showing the configuration of a power supply circuit 400 according to the fourth embodiment.
  • the power supply circuit 400 includes a first circuit 10A, a second circuit 20D, a third circuit 30, and a switching transformer 3.
  • Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
  • the second circuit 20D differs from the second circuit 20A of the second embodiment in that the second circuit 20D includes an inductor 74 instead of the relay 54, and an n-channel MOSFET 71 and an inverter 73 instead of the diode 21.
  • a first end of the inductor 74 without a polarity point is connected to the first end of the capacitor 22, the first end of the load resistor 23, and the input/output positive terminal P22.
  • the second poled end of inductor 74 is connected to the second poled end of second winding N 2 and the drain of n-channel MOSFET 55 . Let the inductance of the inductor 74 be L74.
  • the drain of the n-channel MOSFET 71 is connected to the non-polarized first end of the second winding N2.
  • the source of the n-channel MOSFET 71 is connected to the source of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the positive input/output terminal P22.
  • the gate of n-channel MOSFET 71 is connected to the output of inverter 73 and the input of inverter 73 is connected to the gate of n-channel MOSFET 55 .
  • the n-channel MOSFET 55 is arranged between a first node ND1 between the second end of the second winding N2 having a polarity point and the inductor 74, and a second node ND2 between the input/output negative terminal N22 and the n-channel MOSFET 71.
  • a control signal CT5 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 55 and the input of the inverter 73 .
  • the first control circuit 501 operates with the input voltage Vin1.
  • the second control circuit 502 operates with the input voltage Vin2.
  • the first control circuit 501 controls the n-channel MOSFET 47.
  • the second control circuit 502 turns off the n-channel MOSFET 55 and turns on the n-channel MOSFET 71 .
  • the N2 current flows through the circuit loop formed by the second winding N2, the inductor 74, the capacitor 22, and the n-channel MOSFET 71 to generate the output voltage Vout1 at the input/output positive terminal P22.
  • the circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 300 can be activated only by the input voltage Vin1.
  • the power supply circuit 300 can be operated in the same manner as the power supply circuit 200 shown in the second embodiment.
  • FIG. 12 is a diagram showing voltage and current waveforms in power supply circuit 300 when input voltage Vin2 is input to second circuit 20D and input voltage Vin1 is not input to first circuit 10A in the fourth embodiment.
  • the second control circuit 502 receives the input voltage Vin2 and starts up.
  • the control signal CT5 starts driving the n-channel MOSFET 55 and the n-channel MOSFET 71.
  • the inverter 73 causes the level of the gate signal of the n-channel MOSFET 71 to be the level of the gate signal of the n-channel MOSFET 55 inverted. Therefore, in this embodiment, the n-channel MOSFET 55 and the n-channel MOSFET 71 can be alternately driven.
  • the drain-source voltage of the n-channel MOSFET 55 is zero.
  • a triangular wave current corresponding to the inductance L74 and the input voltage Vin2 flows through the circuit loop formed by the capacitor 22, the inductor 74, and the n-channel MOSFET 55. Energy is thereby stored in the inductor 74 .
  • the voltage applied between the drain and source of the n-channel MOSFET 55 is the product of the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 and the output voltage Vout2.
  • the drain-source voltage of the n-channel MOSFET 55 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 55 and the inductance L74.
  • the n-channel MOSFET 71 is on, the inductance L74 and the inductance L2 of the second winding N2 are excited by the input voltage Vin2, the current of the inductor 74 increases, and the current of the second winding N2 decreases. After that, the n-channel MOSFET 55 is turned on again in the next period.
  • the simultaneous input of the input voltage Vin1 and the input voltage Vin2 can be allowed by not driving the n-channel MOSFET 55 and the n-channel MOSFET 71.
  • the power supply circuit 400 since the power supply circuit 400 has the inductor 74, it is possible to perform a step-up operation, and even when the value of the input voltage Vin2 is small, it is possible to output an output voltage Vout2 that is higher than the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 multiplied by the input voltage Vin2.
  • the gate signal of the n-channel MOSFET 55 and the gate signal of the n-channel MOSFET 71 may be provided with a suitable dead time, or may be individually controlled by the second control circuit 502.
  • the ON time of the gate signal is smaller than the value obtained by subtracting ton3 from T shown in FIG.
  • FIG. 13 is a diagram showing a configuration of a power supply circuit 400A according to a modification of the fourth embodiment.
  • the power supply circuit 400A includes a first circuit 10A, a second circuit 20E, a third circuit 30, and a switching transformer 3.
  • Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 200 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
  • the second circuit 20E differs from the second circuit 20D of the fourth embodiment in that the second circuit 20E includes a rectifier circuit 77 connected across the second winding N2.
  • a rectifier circuit 77 includes a capacitor 76 and an n-channel MOSFET 72 .
  • a capacitor 76 and an n-channel MOSFET 72 are connected in series between a first node ND1 and a second node ND2.
  • a first end of the capacitor 76 is connected to the second end of the second winding N2, the second end of the inductor 74, and the drain of the n-channel MOSFET 55.
  • a second end of capacitor 76 is connected to the drain of n-channel MOSFET 72 .
  • the source of the n-channel MOSFET 72 is connected to the sources of the n-channel MOSFET 71, the source of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the positive input/output terminal P22.
  • a control signal CT6 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 72 .
  • the second control circuit 502 controls the n-channel MOSFET 72 with the control signal CT6 based on the detection signal DT from the first control circuit 501 of the first circuit 10.
  • the second control circuit 502 When the input voltage Vin1 is input, the second control circuit 502 receives the output voltage Vout1 and starts up. When the second control circuit 502 detects that the detection signal DT is sent from the first control circuit 501, that is, that the input voltage Vin1 is connected, the second control circuit 502 turns on the control signal CT6 to turn on the n-channel MOSFET 72.
  • the N2 current flows through the circuit loop composed of the second winding N2, the capacitor 76, and the n-channel MOSFET 72.
  • the influence of the inductor 74 which is a parasitic component for the inductance L2 of the second winding N2, can be suppressed, and a decrease in the output voltage Vout1 can be prevented.
  • the inductor 74 and the capacitor 22 form an LC filter for the output voltage Vout1, and obtain the effect of reducing the differential mode noise output to the output voltage Vout1.
  • the second control circuit 502 When the input voltage Vin2 is input, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, the second control circuit 502 turns off the control signal CT6 to turn off the n-channel MOSFET 72 and disconnect the capacitor 76 from the circuit.

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Abstract

A first circuit (10) includes an input positive electrode terminal (P12) and an input negative electrode terminal (N12) that are configured so as to be able to receive a voltage from a first power source (1), and a first switch (18) that switches the application of an input voltage to a first winding (N1) on and off. A second circuit (20) includes a second control circuit (502) that switches whether a voltage from a second power source (2) is received and power is induced in a second winding (N2), or power that was induced in the second winding (N2) in accordance with the voltage applied to the first winding (N1) is outputted to an external load. A third circuit (30) includes an output positive electrode terminal (P31) and an output negative electrode terminal (N31) that output power which was induced in a third winding (N3) in accordance with the voltage applied to the first winding (N1) or the second winding (N2).

Description

電源回路power circuit
 本開示は、電源回路に関する。 The present disclosure relates to power supply circuits.
 電源回路は、ある入力電圧範囲に対し、一定の電圧を生成する回路である。しかしながら、例えば、AC85V~264Vの入力電圧から5Vを生成する場合と、DC24Vの入力電圧から5Vを生成する場合とでは、両者の入力電圧の範囲の差が大きいため、別の電源を用いるのが通常である。 A power supply circuit is a circuit that generates a constant voltage for a certain input voltage range. However, for example, when generating 5V from an input voltage of AC 85V to 264V and when generating 5V from an input voltage of DC 24V, there is a large difference in input voltage range between the two, so it is common to use separate power supplies.
 AC85V~264Vの入力電圧の電源として非絶縁電源(系統電源)が主に用いられ、DC24Vの入力電圧の電源として絶縁電源が主に用いられる。これらの電源の基準電位(グランド)が異なる。したがって、1つの電気機器に、複数の入力電圧を入力して同様の動作をさせる場合に、複数個の電源およびスイッチングトランスを用意する必要がある。 A non-insulated power supply (system power supply) is mainly used as a power supply for AC85V to 264V input voltage, and an isolated power supply is mainly used as a power supply for DC24V input voltage. The reference potentials (grounds) of these power supplies are different. Therefore, when a plurality of input voltages are input to one electrical device and the same operation is performed, it is necessary to prepare a plurality of power sources and switching transformers.
 このような課題を解決するため、特許文献1に記載されているように、1つのトランスに複数の入力巻線を設ける方式が開示されている。 In order to solve such problems, as described in Patent Document 1, a method of providing a plurality of input windings in one transformer is disclosed.
特開平9-098544号公報JP-A-9-098544
 しかしながら、特許文献1に記載の電源回路では、出力電圧を生成する巻線と、入力電圧を印加する巻線の2つを必要とする。さらに、特許文献1に記載の電源回路では、出力電圧端子と、入力電圧端子とを電気的に分離する必要がある。 However, the power supply circuit described in Patent Document 1 requires two windings, one for generating the output voltage and the other for applying the input voltage. Furthermore, in the power supply circuit described in Patent Document 1, it is necessary to electrically separate the output voltage terminal and the input voltage terminal.
 それゆえに、本開示の目的は、複数のグランドの異なる入力電圧で駆動でき、かつ複数の出力電圧を生成することができるとともに、複数の出力電圧端子のうち、少なくとも1つは、入力電圧端子と電気的に共通化された電源回路を提供することである。 Therefore, an object of the present disclosure is to provide a power supply circuit that can be driven by different input voltages of a plurality of grounds, that can generate a plurality of output voltages, and that at least one of the plurality of output voltage terminals is electrically shared with the input voltage terminal.
 本開示の電源回路は、第1巻線と第2巻線と第3巻線とを有するスイッチングトランスと、第1回路と、第2回路と、第3回路とを備える。第1回路は、第1電源の電圧を受けることが可能に構成される入力正極端子および入力負極端子と、第1巻線への入力電圧の印加をオンまたはオフに切り替える第1のスイッチと、第1のスイッチを制御する第1制御回路とを含む。第2回路は、第2電源の電圧を受けて第2巻線に電力を誘起するか、または第1巻線に印加された電圧に応じて第2巻線に誘起された電力を外部負荷に出力するかを切替える第2制御回路を含む。第3回路は、第1巻線または第2巻線に印加された電圧に応じて、第3巻線に誘起された電力を出力する出力正極端子および出力負極端子と、出力正極端子と出力負極端子との間に生成された出力電圧に応じて変化するフィードバック信号を第1制御回路および第2制御回路に帰還するフィードバック回路とを含む。 A power supply circuit of the present disclosure includes a switching transformer having a first winding, a second winding, and a third winding, a first circuit, a second circuit, and a third circuit. The first circuit includes a positive input terminal and a negative input terminal configured to receive the voltage of the first power supply, a first switch that switches on or off the application of the input voltage to the first winding, and a first control circuit that controls the first switch. The second circuit includes a second control circuit for switching between receiving the voltage of the second power supply and inducing power in the second winding, or outputting the power induced in the second winding to an external load according to the voltage applied to the first winding. The third circuit includes an output positive terminal and an output negative terminal that output power induced in the third winding according to the voltage applied to the first winding or the second winding, and a feedback circuit that feeds back a feedback signal that varies according to the output voltage generated between the output positive terminal and the output negative terminal to the first control circuit and the second control circuit.
 本開示の電源回路によれば、複数のグランドの異なる入力電圧で駆動でき、かつ複数の出力電圧を生成することができるとともに、複数の出力電圧端子のうち、少なくとも1つは、入力電圧端子と電気的に共通化することできる。 According to the power supply circuit of the present disclosure, it can be driven by a plurality of input voltages with different grounds, can generate a plurality of output voltages, and can electrically share at least one of the plurality of output voltage terminals with the input voltage terminal.
実施の形態1の電源回路100の構成を示す図である。1 is a diagram showing a configuration of a power supply circuit 100 according to Embodiment 1; FIG. 実施の形態1における入力電圧Vin1が第1回路10に入力され、入力電圧Vin2が第2回路20に入力されていない場合の電源回路100内の電圧および電流の波形を表す図である。3 is a diagram showing waveforms of voltage and current in power supply circuit 100 when input voltage Vin1 is input to first circuit 10 and input voltage Vin2 is not input to second circuit 20 in Embodiment 1. FIG. 実施の形態1における入力電圧Vin2が第2回路20に入力され、かつ入力電圧Vin1が第1回路10に入力されていない場合の電源回路100内の電圧および電流の波形を表す図である。3 is a diagram showing waveforms of voltage and current in power supply circuit 100 when input voltage Vin2 is input to second circuit 20 and input voltage Vin1 is not input to first circuit 10 in Embodiment 1. FIG. 参考例の電源回路の構成を示す図である。It is a figure which shows the structure of the power supply circuit of a reference example. 実施の形態2の電源回路200の構成を示す図である。FIG. 10 is a diagram showing a configuration of a power supply circuit 200 according to a second embodiment; FIG. 実施の形態2における入力電圧Vin1が第1回路10Aに入力され、入力電圧Vin2が第2回路20Aに入力されていない場合の電源回路200内の電圧および電流の波形を表す図である。FIG. 10 is a diagram showing waveforms of voltage and current in the power supply circuit 200 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20A in the second embodiment; 実施の形態2における入力電圧Vin2が第2回路20Aに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路200内の電圧および電流の波形を表す図である。FIG. 10 is a diagram showing waveforms of voltage and current in power supply circuit 200 when input voltage Vin2 is input to second circuit 20A and input voltage Vin1 is not input to first circuit 10A in Embodiment 2; 実施の形態2の変形例の電源回路200Aの構成を示す図である。FIG. 10 is a diagram showing a configuration of a power supply circuit 200A of a modified example of the second embodiment; 実施の形態3の電源回路300の構成を示す図である。FIG. 10 is a diagram showing a configuration of a power supply circuit 300 according to a third embodiment; FIG. 実施の形態3における入力電圧Vin2が第2回路20Bに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路300内の電圧および電流の波形を表す図である。FIG. 10 is a diagram showing waveforms of voltage and current in power supply circuit 300 when input voltage Vin2 is input to second circuit 20B and input voltage Vin1 is not input to first circuit 10A in Embodiment 3; 実施の形態4の電源回路400の構成を示す図である。FIG. 13 is a diagram showing a configuration of a power supply circuit 400 according to a fourth embodiment; FIG. 実施の形態4における入力電圧Vin2が第2回路20Dに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路400内の電圧および電流の波形を表す図である。FIG. 11 is a diagram showing waveforms of voltage and current in power supply circuit 400 when input voltage Vin2 is input to second circuit 20D and input voltage Vin1 is not input to first circuit 10A in Embodiment 4; 実施の形態4の変形例の電源回路400Aの構成を示す図である。FIG. 13 is a diagram showing a configuration of a power supply circuit 400A of a modified example of the fourth embodiment;
 以下、実施の形態について、図面を参照しながら詳細に説明する。なお、図中同一又は相当部分には同一符号を付してその説明は繰返さない。以下で説明する各実施の形態または変形例は、適宜選択的に組み合わされてもよい。 Hereinafter, embodiments will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated. Each embodiment or modified example described below may be selectively combined as appropriate.
 実施の形態1.
 <構成>
 図1は、実施の形態1の電源回路100の構成を示す図である。
Embodiment 1.
<Configuration>
FIG. 1 is a diagram showing the configuration of a power supply circuit 100 according to the first embodiment.
 電源回路100は、スイッチングトランス3と、第1回路10と、第2回路20と、第3回路30とを備える。 The power supply circuit 100 includes a switching transformer 3 , a first circuit 10 , a second circuit 20 and a third circuit 30 .
 スイッチングトランス3は、第1巻線N1と、第2巻線N2と、第3巻線N3とを含む。第1巻線N1、第2巻線N2、および第3巻線N3の巻き方向は、同一である。第1巻線N1の極性点のない第1端と、第3巻線N3の極性点のある第2端とが対向する。第1巻線N1の極性点のある第2端と、第3巻線N3の極性点のない第1端とが対向する。同様に、第1巻線N1の極性点のない第1端と、第2巻線N2の極性点のある第2端とが対向する。第1巻線N1の極性点のある第2端と、第2巻線N2の極性点のない第1端とが対向する。ここで、極性点は、巻線の巻き始めの点を意味する。 The switching transformer 3 includes a first winding N1, a second winding N2, and a third winding N3. The winding directions of the first winding N1, the second winding N2 and the third winding N3 are the same. A first end without a polarity point of the first winding N1 faces a second end with a polarity point of the third winding N3. The second end of the first winding N1 with a polarity point faces the first end of the third winding N3 without a polarity point. Similarly, the first end of the first winding N1 without a polarity point faces the second end of the second winding N2 with a polarity point. The second end of the first winding N1 with a polarity point faces the first end of the second winding N2 without a polarity point. Here, the polar point means the starting point of the winding.
 第1回路10は、第1電源1と接続可能に構成される。第1回路10は、第1電源1からの入力電圧Vin1を入力可能に構成される。第2回路20は、第2電源2と接続可能に構成される。第2回路20は、第2電源2からの入力電圧Vin2を入力可能に構成され、かつ出力電圧Vout1を図示しない負荷に出力可能に構成される。第3回路30は、出力電圧Vout2を図示しない負荷に出力可能に構成される。 The first circuit 10 is configured to be connectable with the first power supply 1 . The first circuit 10 is configured to be able to receive an input voltage Vin1 from the first power supply 1 . The second circuit 20 is configured to be connectable to the second power supply 2 . The second circuit 20 is configured to receive the input voltage Vin2 from the second power supply 2 and to output the output voltage Vout1 to a load (not shown). The third circuit 30 is configured to output the output voltage Vout2 to a load (not shown).
 第1回路10は、入力正極端子P12および入力負極端子N12と、コンデンサ(第1のコンデンサ)12と、抵抗(第1の抵抗)13と、コンデンサ(第2のコンデンサ)14と、ダイオード(第1のダイオード)11と、ダイオード(第2のダイオード)15と、スイッチ(第1のスイッチ)17と、第1制御回路501とを備える。 The first circuit 10 includes a positive input terminal P12, a negative input terminal N12, a capacitor (first capacitor) 12, a resistor (first resistor) 13, a capacitor (second capacitor) 14, a diode (first diode) 11, a diode (second diode) 15, a switch (first switch) 17, and a first control circuit 501.
 入力正極端子P12および入力負極端子N12は、第1電源1の第1電源正極端子P11および第1電源負極端子N11にそれぞれ接続される。入力正極端子P12および入力負極端子N12は、第1電源1からの入力電圧Vin1を入力可能に構成される。 The input positive terminal P12 and the input negative terminal N12 are connected to the first power supply positive terminal P11 and the first power supply negative terminal N11 of the first power supply 1, respectively. The positive input terminal P12 and the negative input terminal N12 are configured to receive the input voltage Vin1 from the first power supply 1 .
 コンデンサ12は、入力正極端子P12と入力負極端子N12との間に接続され、第1電源1の電圧を入力電圧Vin1として受ける。 The capacitor 12 is connected between the positive input terminal P12 and the negative input terminal N12, and receives the voltage of the first power supply 1 as the input voltage Vin1.
 ダイオード11のカソードは、第1巻線N1の第1端に接続される。ダイオード15のアノードは、第1巻線N1の第2端に接続される。 The cathode of the diode 11 is connected to the first end of the first winding N1. The anode of diode 15 is connected to the second end of first winding N1.
 抵抗13は、入力正極端子P12およびダイオード11のアノードと、ダイオード15のカソードとの間に接続される。コンデンサ14は、入力正極端子P12およびダイオード11のアノードと、ダイオード15のカソードとの間に接続される。 The resistor 13 is connected between the positive input terminal P12 and the anode of the diode 11 and the cathode of the diode 15 . Capacitor 14 is connected between input positive terminal P 12 and the anode of diode 11 and the cathode of diode 15 .
 抵抗13の第1端、コンデンサ14の第1端、およびダイオード11のアノードは、入力正極端子P12に接続される。抵抗13の第2端、およびコンデンサ14の第2端は、ダイオード15のカソードに接続される。 The first end of the resistor 13, the first end of the capacitor 14, and the anode of the diode 11 are connected to the positive input terminal P12. A second end of resistor 13 and a second end of capacitor 14 are connected to the cathode of diode 15 .
 抵抗13、コンデンサ14、およびダイオード15によって、RCDスナバ回路が構成される。 The resistor 13, capacitor 14, and diode 15 constitute an RCD snubber circuit.
 スイッチ17の第1端は、第1巻線N1の第2端およびダイオード15のアノードに接続される。スイッチ17の第2端は、入力負極端子N12に接続される。スイッチ17は、第1巻線N1への入力電圧の印加をオンまたはオフに切り替える。 A first end of the switch 17 is connected to the second end of the first winding N1 and the anode of the diode 15. A second end of the switch 17 is connected to the negative input terminal N12. A switch 17 switches on or off the application of the input voltage to the first winding N1.
 第1制御回路501は、例えば入力正極端子P12の電圧を監視することによって、第1回路10に第1電源1の電圧が入力されている場合には、第1回路10に第1電源1の電圧が入力されていることを表す検出信号DTを第2回路20内の第2制御回路502に伝達する。第1制御回路501は、第3回路30からのフィードバック信号FBに基づいて、スイッチ17を制御する。 The first control circuit 501 monitors, for example, the voltage of the input positive terminal P12, and when the voltage of the first power supply 1 is input to the first circuit 10, transmits a detection signal DT indicating that the voltage of the first power supply 1 is input to the first circuit 10 to the second control circuit 502 in the second circuit 20. The first control circuit 501 controls the switch 17 based on the feedback signal FB from the third circuit 30 .
 第1制御回路501が第2制御回路502に検出信号DTを伝達するためには、例えばフォトカプラのような絶縁素子を用いることができる。第1制御回路501がスイッチ17に対して出力する制御信号CT1は、たとえばPWM(Pulse Width Modulation)信号である。第1制御回路501は、第1電源1からの電力によって駆動可能に構成される。 In order for the first control circuit 501 to transmit the detection signal DT to the second control circuit 502, an insulating element such as a photocoupler can be used. A control signal CT1 that the first control circuit 501 outputs to the switch 17 is, for example, a PWM (Pulse Width Modulation) signal. The first control circuit 501 is configured to be driven by power from the first power supply 1 .
 第2回路20は、入出力正極端子P22および入出力負極端子N22と、負荷抵抗(第4の抵抗)23と、コンデンサ(第3のコンデンサ)22と、スイッチ(第2のスイッチ)24と、スイッチ(第3のスイッチ)25と、ダイオード(第3のダイオード)21と、第2制御回路502とを備える。 The second circuit 20 includes a positive input/output terminal P22, a negative input/output terminal N22, a load resistor (fourth resistor) 23, a capacitor (third capacitor) 22, a switch (second switch) 24, a switch (third switch) 25, a diode (third diode) 21, and a second control circuit 502.
 入出力正極端子P22および入出力負極端子N22は、第2電源2の第2電源正極端子P21および第2電源負極端子N21にそれぞれ接続される。入出力正極端子P22および入出力負極端子N22は、第2電源2の電圧を受けることが可能であり、かつ第1巻線N1に印加された電圧に応じて第2巻線N2に誘起された電力を図示しない外部負荷に出力することを可能に構成される。 The input/output positive terminal P22 and the input/output negative terminal N22 are connected to the second power supply positive terminal P21 and the second power supply negative terminal N21 of the second power supply 2, respectively. Input/output positive terminal P22 and input/output negative terminal N22 are configured to be able to receive the voltage of second power supply 2 and to output power induced in second winding N2 according to the voltage applied to first winding N1 to an external load (not shown).
 コンデンサ22および負荷抵抗23は、入出力正極端子P22と入出力負極端子N22との間に接続される。コンデンサ22および負荷抵抗23は、出力電圧Vout1を出力するか、または入力電圧Vin2を受ける。 The capacitor 22 and the load resistor 23 are connected between the input/output positive terminal P22 and the input/output negative terminal N22. Capacitor 22 and load resistor 23 output an output voltage Vout1 or receive an input voltage Vin2.
 スイッチ24は、第2巻線N2に誘起された電力を入出力正極端子P22および入出力負極端子N22に出力するか、または第2電源2からの電力を第2巻線N2に入力するかを切り替えるように構成される。 The switch 24 is configured to switch between outputting the power induced in the second winding N2 to the positive input/output terminal P22 and the negative input/output terminal N22, or inputting power from the second power supply 2 to the second winding N2.
 スイッチ24は、出力状態端子C1と、入力状態端子C2とを備える。入力状態端子C2は、第2巻線N2の第1端、およびダイオード21のカソードに接続される。出力状態端子C1は、第2巻線N2の第2端、およびスイッチ25の第1端に接続される。 The switch 24 has an output state terminal C1 and an input state terminal C2. The input state terminal C2 is connected to the first end of the second winding N2 and the cathode of the diode 21. Output state terminal C 1 is connected to the second end of second winding N 2 and to the first end of switch 25 .
 スイッチ24は、第2制御回路502からの制御信号CT3によって、入出力正極端子P22を、出力状態端子C1と接続するか、あるいは入力状態端子C2と接続するかを切り替える。 The switch 24 switches between connecting the input/output positive terminal P22 to the output state terminal C1 or connecting it to the input state terminal C2 according to the control signal CT3 from the second control circuit 502 .
 スイッチ25の第2端と、ダイオード21のアノードは、入出力負極端子N22に接続される。スイッチ25は、第2巻線N2への入力電圧の印加をオンまたはオフに切り替える。 The second end of the switch 25 and the anode of the diode 21 are connected to the input/output negative terminal N22. A switch 25 switches on or off the application of the input voltage to the second winding N2.
 入力負極端子N12と入出力負極端子N22とは、例えば強化絶縁によって絶縁されることによって、これらの電位は、異なる電位となる。 The input negative terminal N12 and the input/output negative terminal N22 are insulated by, for example, reinforced insulation, so that these potentials become different potentials.
 第2制御回路502は、第2電源2の電圧を受けて第2巻線N2に電力を誘起するか、または第1巻線N1に印加された電圧に応じて第2巻線N2に誘起された電力を外部負荷に出力するかを切替える。 The second control circuit 502 switches between receiving the voltage of the second power supply 2 and inducing power in the second winding N2, or outputting the power induced in the second winding N2 according to the voltage applied to the first winding N1 to an external load.
 第2制御回路502は、第1回路10の第1制御回路501からの検出信号DTに基づいて、制御信号CT3によって、スイッチ24を制御する。第2制御回路502は、第3回路30からのフィードバック信号FBに基づいて、制御信号CT2によってスイッチ25を制御する。 Based on the detection signal DT from the first control circuit 501 of the first circuit 10, the second control circuit 502 controls the switch 24 with the control signal CT3. The second control circuit 502 controls the switch 25 with the control signal CT2 based on the feedback signal FB from the third circuit 30. FIG.
 第2制御回路502がスイッチ25に対して出力する制御信号CT2は、たとえばPWM信号である。第2制御回路502は、第2電源2からの電力、または第1巻線N1に印加された電圧に応じて第2巻線N2に誘起された電力(出力電圧Vout1)によって駆動可能に構成される。 The control signal CT2 output by the second control circuit 502 to the switch 25 is, for example, a PWM signal. The second control circuit 502 is configured to be driven by power from the second power supply 2 or power (output voltage Vout1) induced in the second winding N2 according to the voltage applied to the first winding N1.
 第3回路30は、出力正極端子P31および出力負極端子N31と、コンデンサ32と、負荷抵抗33と、ダイオード31と、フィードバック回路503とを備える。 The third circuit 30 includes a positive output terminal P31 and a negative output terminal N31, a capacitor 32, a load resistor 33, a diode 31, and a feedback circuit 503.
 出力正極端子P31および出力負極端子N31は、第1巻線N1または第2巻線N2に印加された電圧に応じて、第3巻線N3に誘起された電力を図示しない外部負荷に出力する。 The output positive terminal P31 and the output negative terminal N31 output power induced in the third winding N3 to an external load (not shown) according to the voltage applied to the first winding N1 or the second winding N2.
 コンデンサ32および負荷抵抗33は、出力正極端子P31および出力負極端子N31の間に接続される。コンデンサ32および負荷抵抗33は、出力電圧Vout2を出力することができる。 The capacitor 32 and the load resistor 33 are connected between the output positive terminal P31 and the output negative terminal N31. Capacitor 32 and load resistor 33 can output an output voltage Vout2.
 コンデンサ32の第1端および負荷抵抗33の第1端は、出力正極端子P31およびダイオード31のカソードに接続される。コンデンサ32の第2端および負荷抵抗33の第2端は、出力負極端子N31および第3巻線N3の第1端に接続される。 A first end of the capacitor 32 and a first end of the load resistor 33 are connected to the output positive terminal P31 and the cathode of the diode 31 . A second end of the capacitor 32 and a second end of the load resistor 33 are connected to the output negative terminal N31 and the first end of the third winding N3.
 出力負極端子N31は、第3巻線N3の第1端が接続される。第3巻線N3の第2端は、ダイオード31のアノードが接続される。ダイオード31のカソードは、出力正極端子P31に接続される。 The output negative terminal N31 is connected to the first end of the third winding N3. The anode of the diode 31 is connected to the second end of the third winding N3. A cathode of the diode 31 is connected to the output positive terminal P31.
 フィードバック回路503は、出力正極端子P31と出力負極端子N31との間に生成された出力電圧Vout2に応じて変化するフィードバック信号FBを第1回路10の第1制御回路501および第2回路20の第2制御回路502に伝達する。フィードバック回路503が第1制御回路501または第2制御回路502にフィードバック信号FBを伝達するためには、例えばフォトカプラのような絶縁素子を用いることができる。 The feedback circuit 503 transmits a feedback signal FB that changes according to the output voltage Vout2 generated between the output positive terminal P31 and the output negative terminal N31 to the first control circuit 501 of the first circuit 10 and the second control circuit 502 of the second circuit 20. For the feedback circuit 503 to transmit the feedback signal FB to the first control circuit 501 or the second control circuit 502, an isolation element such as a photocoupler can be used.
 <動作1>
 図2および図3を参照して、実施の形態1の電源回路100内の動作を説明する。図2および図3において、スイッチ17の両端電圧は、入力負極端子N12の側を0としている。
<Action 1>
The operation in power supply circuit 100 of the first embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 and 3, the voltage across the switch 17 is 0 on the side of the negative input terminal N12.
 第1巻線N1の電流、第2巻線N2の電流、および第3巻線N3の電流(以下ではそれぞれ、単にN1電流、N2電流、およびN3電流と呼ぶ)は、それぞれ、第1端から、第2端に流れる電流を正としている。また以下では、簡単のため各ダイオードの順方向電圧は無視する。 The current of the first winding N1, the current of the second winding N2, and the current of the third winding N3 (hereinafter simply referred to as the N1 current, N2 current, and N3 current, respectively) are positive when flowing from the first end to the second end. In the following, the forward voltage of each diode is ignored for simplicity.
 図2は、実施の形態1における入力電圧Vin1が第1回路10に入力され、入力電圧Vin2が第2回路20に入力されていない場合の電源回路100内の電圧および電流の波形を表す図である。 FIG. 2 is a diagram showing voltage and current waveforms in the power supply circuit 100 when the input voltage Vin1 is input to the first circuit 10 and the input voltage Vin2 is not input to the second circuit 20 in the first embodiment.
 すなわち、第1電源正極端子P11と入力正極端子P12とが接続され、第1電源負極端子N11と入力負極端子N12とが接続されている。第2電源正極端子P21と入出力正極端子P22との間、および第2電源負極端子N21と入力負極端子N22との間のうち少なくとも1つが接続されていない。第1制御回路501および第2制御回路502によって、スイッチ24を制御することによって、入出力正極端子P22が出力状態端子C1と接続されている。 That is, the first power supply positive terminal P11 and the input positive terminal P12 are connected, and the first power supply negative terminal N11 and the input negative terminal N12 are connected. At least one of the second power supply positive terminal P21 and the input/output positive terminal P22 and the second power supply negative terminal N21 and the input negative terminal N22 is not connected. By controlling the switch 24 by the first control circuit 501 and the second control circuit 502, the positive input/output terminal P22 is connected to the output state terminal C1.
 このような状態において、第1制御回路501によって駆動されるスイッチ17とスイッチングトランス3によって、第1回路10から、第2回路20および第3回路30に電力が供給される。 In this state, power is supplied from the first circuit 10 to the second circuit 20 and the third circuit 30 by the switch 17 and the switching transformer 3 driven by the first control circuit 501 .
 図2に示すように、スイッチ17がオンの時、スイッチ17の両端電圧は0となり、第1巻線N1には、第1巻線N1のインダクタンスL1と入力電圧Vin1とに応じた三角波電流が流れる。N1電流のピーク電流Ipは、流通時間ton1を用いて次の式で表される。 As shown in FIG. 2, when the switch 17 is on, the voltage across the switch 17 is 0, and a triangular wave current flows through the first winding N1 according to the inductance L1 of the first winding N1 and the input voltage Vin1. A peak current Ip of the N1 current is expressed by the following equation using the flow time ton1.
 Ip=Vin1×ton1/L1…(A1)
 第1巻線N1に三角波電流が流れることによって、スイッチングトランス3にエネルギーが蓄積される。
IP=Vin1×ton1/L1…(A1)
Energy is accumulated in the switching transformer 3 by the triangular wave current flowing through the first winding N1.
 スイッチ17がオフとなると、蓄積したエネルギーによって、第2巻線N2および第3巻線N3に三角波電流が流れる。N2電流は、第2巻線N2、出力状態端子C1、コンデンサ22、およびダイオード21で形成される回路ループを流れ、入出力正極端子P22に出力電圧Vout1を生成する。N3電流は、第3巻線N3、ダイオード31、およびコンデンサ32で形成される回路ループを流れ、出力正極端子P31に出力電圧Vout2を生成する。N1電流は、第1巻線N1、ダイオード15、コンデンサ14、およびダイオード11で形成される回路ループを流れ、抵抗13およびコンデンサ14の両端にスナバ電圧を発生させる。 When the switch 17 is turned off, the stored energy causes a triangular wave current to flow through the second winding N2 and the third winding N3. N2 current flows through the circuit loop formed by second winding N2, output state terminal C1, capacitor 22, and diode 21 to produce output voltage Vout1 at positive input/output terminal P22. N3 current flows through the circuit loop formed by third winding N3, diode 31 and capacitor 32 to produce output voltage Vout2 at output positive terminal P31. The N1 current flows through the circuit loop formed by the first winding N1, diode 15, capacitor 14 and diode 11 and develops a snubber voltage across resistor 13 and capacitor 14. FIG.
 第3回路30に含まれるフィードバック回路503は、例えば、出力正極端子P31と出力負極端子N31との間に生成された出力電圧Vout2に応じて変化するフィードバック信号FBを第1制御回路501に伝達する。第1制御回路501は、フィードバック信号FBに基づいて、流通時間ton1を変化させることによって出力電圧Vout2を安定化させる。 The feedback circuit 503 included in the third circuit 30 transmits to the first control circuit 501, for example, a feedback signal FB that varies according to the output voltage Vout2 generated between the positive output terminal P31 and the negative output terminal N31. The first control circuit 501 stabilizes the output voltage Vout2 by changing the flow time ton1 based on the feedback signal FB.
 出力電圧Vout1と出力電圧Vout2の電圧比は、以下に示すように、一般的に第2巻線N2のインダクタンスL2および第3巻線のN3のインダクタンスL3の比率の平方根と等しくなる。 The voltage ratio between the output voltage Vout1 and the output voltage Vout2 is generally equal to the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3, as shown below.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
 入出力正極端子P22および入出力負極端子N22に外部負荷が接続されていない場合は、N2電流の平均電流が、負荷抵抗23に流れる平均電流と等しくなる。 When no external load is connected to the positive input/output terminal P22 and the negative input/output terminal N22, the average current of the N2 current is equal to the average current flowing through the load resistor 23.
 同様に、出力正極端子P31および出力負極端子N31に外部負荷が接続されていない場合は、N3電流の平均電流が、負荷抵抗33に流れる平均電流と等しくなる。 Similarly, when no external load is connected to the output positive terminal P31 and the output negative terminal N31, the average current of the N3 current is equal to the average current flowing through the load resistor 33.
 スイッチ17がオフとなった後のスイッチ17の両端電圧V17は、フィードバック回路503を含む第3回路30の出力電圧Vout2と、第1巻線N1のインダクタンスL1と第3巻線のN3のインダクタンスL3との比率の平方根と、入力電圧Vin1とを用いて、以下の式で表すことができる。 The voltage V17 across the switch 17 after the switch 17 is turned off can be expressed by the following formula using the output voltage Vout2 of the third circuit 30 including the feedback circuit 503, the square root of the ratio between the inductance L1 of the first winding N1 and the inductance L3 of the third winding N3, and the input voltage Vin1.
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
 さらに、N3電流の流通が終了して、N3電流が0になると、スイッチングトランス3の各巻線に印加される電圧は0となって、スイッチ17の両端電圧はVin1となる。その後再び、スイッチ17がオンとなる。 Furthermore, when the flow of the N3 current ends and the N3 current becomes 0, the voltage applied to each winding of the switching transformer 3 becomes 0, and the voltage across the switch 17 becomes Vin1. After that, the switch 17 is turned on again.
 <動作1の拡張性>
 ここで、図1に記載はないが、入出力正極端子P22および入出力負極端子N22、出力正極端子P31および出力負極端子N31には、それぞれ外部負荷を接続することができるので、それぞれ出力電圧Vout1、Vout2を外部に提供し、外部に電力を供給することができる。
<Extensibility of operation 1>
Here, although not shown in FIG. 1, external loads can be connected to the input/output positive terminal P22, the input/output negative terminal N22, the output positive terminal P31, and the output negative terminal N31, respectively.
 この場合、N2電流の平均値は、負荷抵抗23と外部負荷に流れる電流の平均値の和と等しくなる。同様に、N3電流の平均値は、負荷抵抗33と外部負荷に流れる電流の平均値の和と等しくなる。 In this case, the average value of the N2 current is equal to the sum of the average values of the currents flowing through the load resistor 23 and the external load. Similarly, the average value of the N3 current is equal to the sum of the average values of the currents flowing through the load resistor 33 and the external load.
 <動作2>
 図3は、実施の形態1における入力電圧Vin2が第2回路20に入力され、かつ入力電圧Vin1が第1回路10に入力されていない場合の電源回路100内の電圧および電流の波形を表す図である。
<Action 2>
FIG. 3 is a diagram showing voltage and current waveforms in power supply circuit 100 when input voltage Vin2 is input to second circuit 20 and input voltage Vin1 is not input to first circuit 10 in the first embodiment.
 すなわち、第2電源正極端子P21と入出力正極端子P22とが接続され、第2電源負極端子N21と入力負極端子N22とが接続されている。第1電源正極端子P11と入出力正極端子P12との間、および第1電源負極端子N11と入力負極端子N12との間のうち少なくとも1つが接続されていない。 That is, the second power supply positive terminal P21 and the input/output positive terminal P22 are connected, and the second power supply negative terminal N21 and the input negative terminal N22 are connected. At least one of the first power supply positive terminal P11 and the input/output positive terminal P12 and the first power supply negative terminal N11 and the input negative terminal N12 is not connected.
 第2制御回路502は、第1制御回路501から検出信号DTが送られてこない場合には、制御信号CT3によってスイッチ24を駆動し、入出力正極端子P22を入力状態端子C2に接続する。 When the detection signal DT is not sent from the first control circuit 501, the second control circuit 502 drives the switch 24 with the control signal CT3 to connect the positive input/output terminal P22 to the input state terminal C2.
 このような状態において、第2制御回路502によって駆動されるスイッチ25とスイッチングトランス3とによって、第2回路20から、第1回路10および第3回路30に電力が供給される。 In this state, power is supplied from the second circuit 20 to the first circuit 10 and the third circuit 30 by the switch 25 and the switching transformer 3 driven by the second control circuit 502 .
 スイッチ25がオンの時、スイッチ25の両端電圧は0となる。コンデンサ22、入力状態端子C2、第2巻線N2、およびスイッチ25で形成される回路ループに、第2巻線N2のインダクタンスL2と入力電圧Vin2とに応じた三角波電流が流れる。N2電流のピーク電流Ip2は、流通時間ton2を用いて次の式で表される。 When the switch 25 is on, the voltage across the switch 25 is 0. A triangular current corresponding to the inductance L2 of the second winding N2 and the input voltage Vin2 flows through the circuit loop formed by the capacitor 22, the input state terminal C2, the second winding N2, and the switch 25. A peak current Ip2 of the N2 current is expressed by the following equation using the flow time ton2.
 Ip2=Vin2×ton2/L2…(B1)
 第2巻線N2に三角波電流が流れることによって、スイッチングトランス3にエネルギーが蓄積される。
Ip2=Vin2×ton2/L2…(B1)
Energy is accumulated in the switching transformer 3 by the triangular wave current flowing through the second winding N2.
 スイッチ25がオフとなると、蓄積したエネルギーによって、第1巻線N1および第3巻線N3に三角波電流が流れる。N1電流は、第1巻線N1、ダイオード11、コンデンサ14、およびダイオード15で形成される回路ループを流れ、抵抗13およびコンデンサ14の両端に電圧を発生させる。N3電流は、第3巻線N3、ダイオード31、およびコンデンサ32で形成される回路ループを流れ、出力正極端子P31に出力電圧Vout2を生成する。 When the switch 25 is turned off, the stored energy causes a triangular wave current to flow through the first winding N1 and the third winding N3. The N1 current flows through the circuit loop formed by the first winding N1, diode 11, capacitor 14 and diode 15 and develops a voltage across resistor 13 and capacitor 14. FIG. N3 current flows through the circuit loop formed by third winding N3, diode 31 and capacitor 32 to produce output voltage Vout2 at output positive terminal P31.
 第3回路30に含まれるフィードバック回路503は、例えば、出力正極端子P31と出力負極端子N31との間に生成された出力電圧Vout2に応じて変化するフィードバック信号FBを第2制御回路502に伝達する。第2制御回路502は、フィードバック信号FBに基づいて、流通時間ton2を変化させることによって出力電圧Vout2を安定化させる。 A feedback circuit 503 included in the third circuit 30 transmits to the second control circuit 502, for example, a feedback signal FB that varies according to the output voltage Vout2 generated between the positive output terminal P31 and the negative output terminal N31. The second control circuit 502 stabilizes the output voltage Vout2 by changing the flow time ton2 based on the feedback signal FB.
 出力正極端子P31および出力負極端子N31に外部負荷が接続されていない場合は、N3電流の平均電流が、負荷抵抗33に流れる平均電流と等しくなる。 When no external load is connected to the output positive terminal P31 and the output negative terminal N31, the average current of the N3 current is equal to the average current flowing through the load resistor 33.
 スイッチ25がオフとなった後のスイッチ25の両端電圧V25は、フィードバック回路503を含む第3回路の出力電圧Vout2と、第2巻線N2のインダクタンスL2および第3巻線のN3のインダクタンスL3の比率の平方根と入力電圧Vin2とを用いて、以下の式で表すことができる。 The voltage V25 across the switch 25 after the switch 25 is turned off can be expressed by the following formula using the output voltage Vout2 of the third circuit including the feedback circuit 503, the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3, and the input voltage Vin2.
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
 さらに、N3電流の流通が終了し、N3電流が0になると、スイッチングトランス3の各巻線に印加される電圧は0となって、スイッチ25の両端電圧はVin2となる。その後再び、スイッチ25がオンとなる。 Further, when the flow of the N3 current ends and the N3 current becomes 0, the voltage applied to each winding of the switching transformer 3 becomes 0, and the voltage across the switch 25 becomes Vin2. After that, the switch 25 is turned on again.
 <動作2の拡張性>
 図1に記載はないが、出力正極端子P31および出力負極端子N31には、外部負荷を接続することができるので、出力電圧Vout2を外部に提供し、外部に電力を供給することができる。この場合、N3電流の平均値は、負荷抵抗33と外部負荷に流れる電流の平均値の和と等しくなる。
<Extensibility of operation 2>
Although not shown in FIG. 1, an external load can be connected to the output positive terminal P31 and the output negative terminal N31, so that the output voltage Vout2 can be provided to the outside and electric power can be supplied to the outside. In this case, the average value of the N3 current is equal to the sum of the average values of the currents flowing through the load resistor 33 and the external load.
 <共通の拡張性>
 上記では、入力電圧Vin1および入力電圧Vin2のうちのいずれか一方が入力される場合について説明したが、これに限定されるものではない。入力電圧Vin1および入力電圧Vin2は同時に入力されてもよい。この場合、スイッチ24は、第1制御回路501および第2制御回路502によって、入出力正極端子P22が出力状態端子C1に接続されるように制御される。第1制御回路501によって駆動されるスイッチ17と、スイッチングトランス3によって、第1回路10から、第2回路20および第3回路30に電力が供給される。この時、入力電圧Vin2と、第2回路20で生成された出力電圧Vout2とのうち電圧の高い方から負荷抵抗23に電力が供給される。
<Common extensibility>
Although the case where either one of the input voltage Vin1 and the input voltage Vin2 is input has been described above, the present invention is not limited to this. Input voltage Vin1 and input voltage Vin2 may be input at the same time. In this case, the switch 24 is controlled by the first control circuit 501 and the second control circuit 502 so that the positive input/output terminal P22 is connected to the output state terminal C1. Power is supplied from the first circuit 10 to the second circuit 20 and the third circuit 30 by the switch 17 driven by the first control circuit 501 and the switching transformer 3 . At this time, power is supplied to the load resistor 23 from the input voltage Vin2 or the output voltage Vout2 generated by the second circuit 20, whichever is higher.
 上記では、電源回路100は、1個の第1回路10、1個の第2回路20、および1個の第3回路30を備えるものとして説明したが、これに限定されるものではない。電源回路100は、複数個の第1回路10、複数個の第2回路20、および複数個の第3回路30を備えるものとしてもよい。この場合、電源回路100は、多入出力電源回路となる。この場合であってもスイッチングトランス3には、第4巻線以降を増やすだけでよく、以下に示す図4で示した従来構成のようにスイッチングトランスを複数設ける必要はない。 Although the power supply circuit 100 has been described above as including one first circuit 10, one second circuit 20, and one third circuit 30, it is not limited to this. The power supply circuit 100 may include multiple first circuits 10 , multiple second circuits 20 , and multiple third circuits 30 . In this case, the power supply circuit 100 becomes a multi-input/output power supply circuit. Even in this case, it is sufficient to increase the number of windings after the fourth winding in the switching transformer 3, and there is no need to provide a plurality of switching transformers unlike the conventional configuration shown in FIG.
 <効果>
 以上説明したように、本実施の形態では、電源回路100には、入力電圧Vin1および入力電圧Vin2のうちの少なくとも1つが入力されていれば、出力電圧Vout1、および出力電圧Vout2を出力できる。また、第2巻線N2の極性点のない第1端から電圧を印加し、第2巻線N2の極性点のある第2端をスイッチングしているため、昇圧動作が可能であり、入力電圧Vin2の値が小さい場合であっても、第2巻線N2のインダクタンスL2および第3巻線N3のインダクタンスL3の比率の平方根に入力電圧Vin2を乗じた値よりも大きな出力電圧Vout2を出力することができる。
<effect>
As described above, in the present embodiment, if at least one of the input voltage Vin1 and the input voltage Vin2 is input to the power supply circuit 100, the output voltage Vout1 and the output voltage Vout2 can be output. In addition, voltage is applied from the first end of the second winding N2 that has no polarity point, and the second end of the second winding N2 that has a polarity point is switched, so that a step-up operation is possible, and even if the value of the input voltage Vin2 is small, it is possible to output an output voltage Vout2 that is greater than the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 multiplied by the input voltage Vin2.
 また、入出力正極端子P22および入出力負極端子N22は、入力電圧Vin2を入力する入力端子としての機能と、出力電圧Vout1を出力する出力端子としての機能を兼ね備える。従来において、入力用のスイッチングトランスの巻線と、出力用のスイッチングトランスの巻線とを個別に備える必要があったのに対して、本実施の形態では、スイッチングトランス3の巻線を削減することができるので、スイッチングトランス3を小型にすることができる。 In addition, the positive input/output terminal P22 and the negative input/output terminal N22 have both a function as an input terminal for inputting the input voltage Vin2 and a function as an output terminal for outputting the output voltage Vout1. Conventionally, it was necessary to separately provide the windings of the switching transformer for input and the windings of the switching transformer for output.
 さらに、本実施の形態では、入力端子と出力端子とを共通化することができるので、端子数を削減することができる。その結果、電源回路を小型化することができる。さらに、本実施の形態によれば、ユーザーの入出力端子の配線の間違いを許容することができ、安全性が向上する。 Furthermore, in this embodiment, the input terminal and the output terminal can be shared, so the number of terminals can be reduced. As a result, the power supply circuit can be miniaturized. Furthermore, according to the present embodiment, it is possible to allow the user to make a mistake in the wiring of the input/output terminals, thereby improving safety.
 <参考例>
 図4は、参考例の電源回路の構成を示す図である。
<Reference example>
FIG. 4 is a diagram showing the configuration of the power supply circuit of the reference example.
 第1回路40A、第3回路50A、およびスイッチングトランス3Aを用いて、出力電圧Vout1を生成し、第2電源正極端子P21および第2電源負極端子N21から出力電圧Vout1を出力する。第2電源正極端子P21および第2電源負極端子N21はそれぞれ、入出力正極端子P22および入出力負極端子N22と接続される。 An output voltage Vout1 is generated using the first circuit 40A, the third circuit 50A, and the switching transformer 3A, and the output voltage Vout1 is output from the second power supply positive terminal P21 and the second power supply negative terminal N21. The second power positive terminal P21 and the second power negative terminal N21 are connected to the input/output positive terminal P22 and the input/output negative terminal N22, respectively.
 第1回路40B、第3回路50B、およびスイッチングトランス3Bを用いて、出力電圧Vout2を生成し、出力正極端子P31および出力負極端子N31から出力電圧Vout2を出力する。 An output voltage Vout2 is generated using the first circuit 40B, the third circuit 50B, and the switching transformer 3B, and the output voltage Vout2 is output from the output positive terminal P31 and the output negative terminal N31.
 例えば一方の電源(第1回路40A、スイッチングトランス3A、および第3回路50A)の電力変換効率が80%、他方の電源(第1回路40B、スイッチングトランス3B、および第3回路50B)の電力変換効率が80%とすると、全体の電力変換効率は64%となる。よって、参考例の電源回路の電力変換効率が悪い。参考例の電源回路は、発熱が多いという問題がある。参考例の電源回路は、スイッチングトランスおよびフィードバック回路が2つ必要となるので、大型化するという問題がある。 For example, if the power conversion efficiency of one power source (first circuit 40A, switching transformer 3A, and third circuit 50A) is 80%, and the power conversion efficiency of the other power source (first circuit 40B, switching transformer 3B, and third circuit 50B) is 80%, the overall power conversion efficiency is 64%. Therefore, the power conversion efficiency of the power supply circuit of the reference example is poor. The power supply circuit of the reference example has a problem that it generates a lot of heat. Since the power supply circuit of the reference example requires two switching transformers and two feedback circuits, there is a problem of an increase in size.
 これに対し、本実施の形態によれば、2段構成の電源を用いる必要はないので、小型で電力変換効率がよい電源回路を提供することができる。 On the other hand, according to the present embodiment, since it is not necessary to use a two-stage power supply, it is possible to provide a compact power supply circuit with high power conversion efficiency.
 また、前述のようにスイッチングトランス3に巻線を追加して多出力電源回路とした場合、入力電圧を切り替えたとしても、各出力電圧の起動シーケンス(立ち上がりの順番)が同一となり、設計が容易となる。 Also, as described above, when windings are added to the switching transformer 3 to form a multi-output power supply circuit, even if the input voltage is switched, the startup sequence (order of rise) of each output voltage will be the same, making design easier.
 実施の形態2.
 <構成>
 図5は、実施の形態2の電源回路200の構成を示す図である。
Embodiment 2.
<Configuration>
FIG. 5 is a diagram showing the configuration of the power supply circuit 200 according to the second embodiment.
 電源回路200は、第1回路10Aと、第2回路20Aと、第3回路30と、スイッチングトランス3とを備える。第3回路30およびスイッチングトランス3は、実施の形態1の電源回路100に含まれる第3回路30およびスイッチングトランス3と同様なので、説明を繰り返さない。 The power supply circuit 200 includes a first circuit 10A, a second circuit 20A, a third circuit 30, and a switching transformer 3. Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated.
 第1回路10Aが、実施の形態1の第1回路10と相違する点は、第1回路10Aが、第1のスイッチとして、スイッチ17の代わりにnチャネルMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)47を備える点である。 The first circuit 10A differs from the first circuit 10 of Embodiment 1 in that the first circuit 10A includes an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 47 instead of the switch 17 as the first switch.
 nチャネルMOSFET55のドレインが第1巻線N1の第2端、およびダイオード15のアノードに接続される。nチャネルMOSFET55のソースは、入力負極端子N12に接続される。 The drain of the n-channel MOSFET 55 is connected to the second end of the first winding N1 and the anode of the diode 15. The source of the n-channel MOSFET 55 is connected to the negative input terminal N12.
 第2回路20Aが、実施の形態1の第2回路20と相違する点は、第2回路20Aは、第2のスイッチとして、スイッチ24の代わりにリレー54を備え、第3のスイッチとしてスイッチ25の代わりにnチャネルMOSFET(第1のトランジスタ)55を備える点である。第2回路20Aは、さらに、nチャネルMOSFET(第1のトランジスタ)55と並列に接続されるツェナーダイオード56を備える。 The second circuit 20A differs from the second circuit 20 of Embodiment 1 in that the second circuit 20A includes a relay 54 instead of the switch 24 as the second switch, and an n-channel MOSFET (first transistor) 55 instead of the switch 25 as the third switch. The second circuit 20A further includes a Zener diode 56 connected in parallel with the n-channel MOSFET (first transistor) 55 .
 nチャネルMOSFET55のドレインおよびツェナーダイオード56のカソードが第2巻線N2の第2端子、および出力状態端子C1に接続される。 The drain of the n-channel MOSFET 55 and the cathode of the Zener diode 56 are connected to the second terminal of the second winding N2 and the output state terminal C1.
 nチャネルMOSFET55のソースおよびツェナーダイオード56のアノードがダイオード21のアノード、負荷抵抗23の第2端、コンデンサ22の第2端、および入出力負極端子N22に接続される。 The source of the n-channel MOSFET 55 and the anode of the Zener diode 56 are connected to the anode of the diode 21, the second end of the load resistor 23, the second end of the capacitor 22, and the input/output negative terminal N22.
 ツェナーダイオード56のツェナー電圧Vzは、nチャネルMOSFET55のドレイン-ソース間電圧定格電圧以下のものが選定されている。 The Zener voltage Vz of the Zener diode 56 is selected to be less than the drain-source voltage rated voltage of the n-channel MOSFET 55 .
 第1制御回路501は、入力電圧Vin1によって動作する。第2制御回路502は、入力電圧Vin2によって動作する。 The first control circuit 501 operates with the input voltage Vin1. The second control circuit 502 operates with the input voltage Vin2.
 リレー54は、c接点を有する。電源回路200が無通電状態であっても、入出力正極端子P22が出力状態端子C1に接続される。これにより、第2制御回路502に入力電圧Vin2が供給されておらず、第2制御回路502が動作していない状態であっても、ループ回路が形成されて、出力電圧Vout1を出力することができる。すなわち入力電圧Vin1のみによる電源回路200の起動を可能にする。 The relay 54 has a c contact. Even when the power supply circuit 200 is in a non-energized state, the positive input/output terminal P22 is connected to the output state terminal C1. As a result, even when the input voltage Vin2 is not supplied to the second control circuit 502 and the second control circuit 502 is not operating, a loop circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 200 can be activated only by the input voltage Vin1.
 第2回路20Aに入力電圧Vin2が接続されている場合、第2制御回路502は、入力電圧Vin2を受けて起動する。第2制御回路502は、第1制御回路501から検出信号DTが送られてこないこと、すなわち入力電圧Vin1が接続されていないことを検出した場合、制御信号CT3によってリレー54を駆動して、入出力正極端子P22を入力状態端子C2に接続する。これによって、nチャネルMOSFET55の駆動を開始する。 When the input voltage Vin2 is connected to the second circuit 20A, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, the second control circuit 502 drives the relay 54 by the control signal CT3 to connect the positive input/output terminal P22 to the input state terminal C2. This starts driving the n-channel MOSFET 55 .
 第2制御回路502は、第1制御回路501から検出信号DTを受け取った場合は、リレー54を駆動せず、入出力正極端子P22が出力状態端子C1に接続されている状態を維持する。これによって、入力電圧Vin1および入力電圧Vin2の同時入力を許容することができる。 When the second control circuit 502 receives the detection signal DT from the first control circuit 501, the second control circuit 502 does not drive the relay 54 and maintains the state in which the positive input/output terminal P22 is connected to the output state terminal C1. This allows simultaneous input of the input voltage Vin1 and the input voltage Vin2.
 <動作1>
 図6は、実施の形態2における入力電圧Vin1が第1回路10Aに入力され、入力電圧Vin2が第2回路20Aに入力されていない場合の電源回路200内の電圧および電流の波形を表す図である。
<Action 1>
FIG. 6 is a diagram showing voltage and current waveforms in the power supply circuit 200 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20A in the second embodiment.
 図6では、図2で示したスイッチ17の両端電圧の代わりに、nチャネルMOSFET47のドレイン-ソース間電圧が示されている。実施の形態1では、理想的なスイッチおよびトランスでの動作を示した。しかしながら、実際の回路では、スイッチングトランス3は各巻線に漏れインダクタンスを有する。nチャネルMOSFET47がオフした直後は、前述の式(A3)の電圧V17を超えるサージ電圧が発生する。このサージ電圧は、RCDスナバ回路である抵抗13、コンデンサ14、およびダイオード15によって、nチャネルMOSFET47のドレイン-ソース間定格電圧以下に抑制される。 6 shows the drain-source voltage of the n-channel MOSFET 47 instead of the voltage across the switch 17 shown in FIG. Embodiment 1 shows the operation with an ideal switch and transformer. However, in an actual circuit, the switching transformer 3 has leakage inductance in each winding. Immediately after the n-channel MOSFET 47 is turned off, a surge voltage exceeding the voltage V17 of the above equation (A3) is generated. This surge voltage is suppressed below the drain-source rated voltage of n-channel MOSFET 47 by resistor 13, capacitor 14, and diode 15, which are RCD snubber circuits.
 N3電流が0になった後、nチャネルMOSFET47のドレイン-ソース間の寄生容量、ダイオード11の寄生容量、および第1巻線N1のインダクタンスL1によって、nチャネルMOSFET47のドレイン-ソース間電圧は振動する。 After the N3 current becomes 0, the drain-source voltage of the n-channel MOSFET 47 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 47, the parasitic capacitance of the diode 11, and the inductance L1 of the first winding N1.
 <動作2>
 図7は、実施の形態2における入力電圧Vin2が第2回路20Aに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路200内の電圧および電流の波形を表す図である。
<Action 2>
FIG. 7 is a diagram showing voltage and current waveforms in the power supply circuit 200 when the input voltage Vin2 is input to the second circuit 20A and the input voltage Vin1 is not input to the first circuit 10A in the second embodiment.
 図7では、図3で示したスイッチ25の両端電圧の代わりに、nチャネルMOSFET55のドレイン-ソース間電圧が示されている。nチャネルMOSFET55がオフした直後は、前述の式(B3)の電圧V25を超えるサージ電圧が発生する。 In FIG. 7, instead of the voltage across the switch 25 shown in FIG. 3, the drain-source voltage of the n-channel MOSFET 55 is shown. Immediately after the n-channel MOSFET 55 is turned off, a surge voltage exceeding the voltage V25 of the above equation (B3) is generated.
 ここで、ツェナーダイオード56のツェナー電圧Vzは、nチャネルMOSFET55のドレイン-ソース間電圧定格電圧以下のものが選定されているので、図7に示すように、サージ電圧はVzでクランプされ、簡易な構成でnチャネルMOSFET55を保護することができる。 Here, the Zener voltage Vz of the Zener diode 56 is selected to be lower than the drain-source voltage rated voltage of the n-channel MOSFET 55. Therefore, as shown in FIG. 7, the surge voltage is clamped at Vz, and the n-channel MOSFET 55 can be protected with a simple configuration.
 <実施の形態2の独自の効果>
 ツェナーダイオード56により、入力電圧Vin2により電源回路200が駆動している場合でも、回路を故障させることなく安定的に動作させることができ、発生するノイズを抑制することができる。
<Effect unique to the second embodiment>
With the Zener diode 56, even when the power supply circuit 200 is driven by the input voltage Vin2, the circuit can be stably operated without failure, and noise generated can be suppressed.
 <実施の形態2の変形例>
 図8は、実施の形態2の変形例の電源回路200Aの構成を示す図である。
<Modification of Embodiment 2>
FIG. 8 is a diagram showing a configuration of a power supply circuit 200A according to a modification of the second embodiment.
 電源回路200Aは、第1回路10Aと、第2回路20Cと、第3回路30と、スイッチングトランス3とを備える。第3回路30およびスイッチングトランス3は、実施の形態1の電源回路100に含まれる第3回路30およびスイッチングトランス3と同様なので、説明を繰り返さない。第1回路10Aは、実施の形態2の電源回路200に含まれる第1回路10Aと同様なので、説明を繰り返さない。 The power supply circuit 200A includes a first circuit 10A, a second circuit 20C, a third circuit 30, and a switching transformer 3. Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
 第2回路20Cが、実施の形態2の第2回路20Aと相違する点は、第2回路20Cが、ツェナーダイオード56の代わりに、第2巻線N2の両端に接続されるRCDスナバ回路89を備える点である。 The second circuit 20C differs from the second circuit 20A of the second embodiment in that the second circuit 20C includes an RCD snubber circuit 89 connected across the second winding N2 instead of the Zener diode 56.
 RCDスナバ回路89は、抵抗81と、コンデンサ82と、ダイオード83とを備える。 The RCD snubber circuit 89 comprises a resistor 81, a capacitor 82 and a diode 83.
 ダイオード83のアノードは、第2巻線N2の第2端および出力状態端子C1に接続される。ダイオード83のカソードは、抵抗81の第1端およびコンデンサ82の第1端と接続される。 The anode of the diode 83 is connected to the second end of the second winding N2 and the output state terminal C1. The cathode of diode 83 is connected to the first end of resistor 81 and the first end of capacitor 82 .
 抵抗81の第2端およびコンデンサ82の第2端は、第2巻線N2の第1端、ダイオード21のカソード、および入力状態端子C2と接続される。 The second end of resistor 81 and the second end of capacitor 82 are connected to the first end of second winding N2, the cathode of diode 21, and input state terminal C2.
 本変形例においても、実施の形態2におけるツェナーダイオード56と同様に、nチャネルMOSFET55のドレイン-ソース間電圧を抑制する効果を得られる。 Also in this modified example, the effect of suppressing the drain-source voltage of the n-channel MOSFET 55 can be obtained, similar to the Zener diode 56 in the second embodiment.
 実施の形態3.
 <構成>
 図9は、実施の形態3の電源回路300の構成を示す図である。
Embodiment 3.
<Configuration>
FIG. 9 is a diagram showing the configuration of a power supply circuit 300 according to the third embodiment.
 電源回路300は、第1回路10Aと、第2回路20Bと、第3回路30と、スイッチングトランス3とを備える。第3回路30およびスイッチングトランス3は、実施の形態1の電源回路100に含まれる第3回路30およびスイッチングトランス3と同様なので、説明を繰り返さない。第1回路10Aは、実施の形態2の電源回路200に含まれる第1回路10Aと同様なので、説明を繰り返さない。 The power supply circuit 300 includes a first circuit 10A, a second circuit 20B, a third circuit 30, and a switching transformer 3. Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
 第2回路20Bが、実施の形態2の第2回路20Aと相違する点は、第2回路20Bは、リレー54の代わりに、ダイオード(第4のダイオード)61、ダイオード(第5のダイオード)62、pチャネルMOSFET(第2のトランジスタ)63、nチャネルMOSFET(第3のトランジスタ)64、抵抗(第2の抵抗)65、および抵抗(第3の抵抗)66を備える点である。 The second circuit 20B differs from the second circuit 20A of the second embodiment in that instead of the relay 54, the second circuit 20B includes a diode (fourth diode) 61, a diode (fifth diode) 62, a p-channel MOSFET (second transistor) 63, an n-channel MOSFET (third transistor) 64, a resistor (second resistor) 65, and a resistor (third resistor) 66.
 第2回路20Bは、ツェナーダイオード56を備えない。実施の形態2では、nチャネルMOSFET55がオフした際に、その両端に発生するサージ電圧を抑制するために、ツェナーダイオード56が設けられている。実施の形態3では、nチャネルMOSFET55がオフした際、第2巻線N2に流れていた電流はダイオード62を導通することによって、入力電圧Vin2に回生され、nチャネルMOSFET55の両端電圧はVin2に維持される。よって、実施の形態3では、サージ電圧を抑制する回路は必要なくなるため、ツェナーダイオード56が設けられない。 The second circuit 20B does not include the Zener diode 56. In the second embodiment, a Zener diode 56 is provided to suppress a surge voltage generated across the n-channel MOSFET 55 when it is turned off. In the third embodiment, when the n-channel MOSFET 55 is turned off, the current flowing through the second winding N2 is regenerated to the input voltage Vin2 by conducting the diode 62, and the voltage across the n-channel MOSFET 55 is maintained at Vin2. Therefore, in the third embodiment, the Zener diode 56 is not provided because a circuit for suppressing the surge voltage is not required.
 ダイオード62のアノードは、第2巻線N2の第2端、およびnチャネルMOSFET55のドレイン(第1電極)に接続される。ダイオード62のカソードは、pチャネルMOSFET63のソース(第1電極)と、抵抗65の第1端と、コンデンサ22の第1端と、負荷抵抗23の第1端と、入出力正極端子P22と接続される。 The anode of the diode 62 is connected to the second end of the second winding N2 and the drain (first electrode) of the n-channel MOSFET 55. The cathode of diode 62 is connected to the source (first electrode) of p-channel MOSFET 63, the first end of resistor 65, the first end of capacitor 22, the first end of load resistor 23, and input/output positive terminal P22.
 pチャネルMOSFET63のドレイン(第2電極)は、ダイオード61のアノードに接続される。ダイオード61のカソードは、第2巻線N2の第1端、およびダイオード21のカソードに接続される。 The drain (second electrode) of the p-channel MOSFET 63 is connected to the anode of the diode 61 . The cathode of diode 61 is connected to the first end of second winding N2 and the cathode of diode 21 .
 pチャネルMOSFET63のゲート(制御電極)は、抵抗65の第2端と、抵抗66の第1端に接続される。抵抗66の第2端はnチャネルMOSFET64のドレイン(第1電極)に接続される。nチャネルMOSFET64のソース(第2電極)は、ダイオード21のアノード、nチャネルMOSFET55のソース(第2電極)、コンデンサ22の第2端、負荷抵抗23の第2端、および入出力負極端子N22と接続されている。 A gate (control electrode) of the p-channel MOSFET 63 is connected to the second end of the resistor 65 and the first end of the resistor 66 . A second end of resistor 66 is connected to the drain (first electrode) of n-channel MOSFET 64 . The source (second electrode) of the n-channel MOSFET 64 is connected to the anode of the diode 21, the source (second electrode) of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the negative input/output terminal N22.
 nチャネルMOSFET64のゲート(制御電極)およびnチャネルMOSFET55のゲート(制御電極)には、第2制御回路502からの制御信号CT4が入力される。 A control signal CT4 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 64 and the gate (control electrode) of the n-channel MOSFET 55 .
 第1制御回路501は、入力電圧Vin1によって動作する。第2制御回路502は、入力電圧Vin2によって動作する。 The first control circuit 501 operates with the input voltage Vin1. The second control circuit 502 operates with the input voltage Vin2.
 <動作1>
 入力電圧Vin1が第1回路10Aに入力され、入力電圧Vin2が第2回路20Bに入力されていない場合の電源回路300の動作は、実施の形態2と同様なので、図示は省略する。
<Action 1>
Since the operation of the power supply circuit 300 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20B is the same as in the second embodiment, the illustration is omitted.
 入力電圧Vin1が入力されている場合、第1制御回路501がnチャネルMOSFET47を制御する。 When the input voltage Vin1 is input, the first control circuit 501 controls the n-channel MOSFET 47.
 nチャネルMOSFET47がオフのとき、N2電流は、第2巻線N2、ダイオード62、コンデンサ22、およびダイオード21で形成される回路ループを流れ、入出力正極端子P22に出力電圧Vout1を生成する。 When the n-channel MOSFET 47 is off, the N2 current flows through the circuit loop formed by the second winding N2, the diode 62, the capacitor 22, and the diode 21 to generate the output voltage Vout1 at the input/output positive terminal P22.
 これにより、第2制御回路502に電力が供給されておらず、第2制御回路502が動作していない状態であっても回路が形成され、出力電圧Vout1を出力することができる。すなわち入力電圧Vin1のみによる電源回路300の起動が可能になる。 Thus, even when power is not supplied to the second control circuit 502 and the second control circuit 502 is not operating, the circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 300 can be activated only by the input voltage Vin1.
 一方、nチャネルMOSFET47がオンの時は、ダイオード21およびダイオード61によって、回路ループが形成できず、N2電流は流れることができずに0となる。したがって、電源回路300を、実施の形態2で示した電源回路200と同様に動作させることができる。 On the other hand, when the n-channel MOSFET 47 is on, a circuit loop cannot be formed by the diodes 21 and 61, and the N2 current cannot flow and becomes 0. Therefore, the power supply circuit 300 can be operated in the same manner as the power supply circuit 200 shown in the second embodiment.
 <動作2>
 図10は、実施の形態3における入力電圧Vin2が第2回路20Bに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路300内の電圧および電流の波形を表す図である。
<Action 2>
FIG. 10 is a diagram showing voltage and current waveforms in power supply circuit 300 when input voltage Vin2 is input to second circuit 20B and input voltage Vin1 is not input to first circuit 10A in the third embodiment.
 入力電圧Vin2が入力されている場合、第2制御回路502は、入力電圧Vin2を受けて起動する。第2制御回路502は、第1制御回路501から検出信号DTが送られてこないこと、すなわち入力電圧Vin1が接続されていないことを検出した場合、制御信号CT4によって、nチャネルMOSFET55およびnチャネルMOSFET64の駆動を開始させる。 When the input voltage Vin2 is input, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, it starts driving the n-channel MOSFET 55 and the n-channel MOSFET 64 by the control signal CT4.
 nチャネルMOSFET64は、pチャネルMOSFET63のゲートを駆動するために設けられている。nチャネルMOSFET64がオフの時、pチャネルMOSFET63のゲート-ソース間電圧は0となり、pチャネルMOSFET63はオフとなる。一方、nチャネルMOSFET64がオンの時は、pチャネルMOSFET63のゲート-ソース間電圧は、Vin2を抵抗65と抵抗66とによって分圧した値となり、pチャネルMOSFET63がオンとなる。ただし、pチャネルMOSFET63のゲート-ソース間電圧の許容値が、入力電圧Vin2よりも大きい場合は、抵抗66は不要であり、ショートできる。すなわち、抵抗65の第2端と、NチャネルMOSFET64のドレインとを接続すればよい。 The n-channel MOSFET 64 is provided to drive the gate of the p-channel MOSFET 63 . When the n-channel MOSFET 64 is off, the gate-source voltage of the p-channel MOSFET 63 is 0, and the p-channel MOSFET 63 is off. On the other hand, when the n-channel MOSFET 64 is on, the gate-source voltage of the p-channel MOSFET 63 becomes a value obtained by dividing Vin2 by the resistors 65 and 66, and the p-channel MOSFET 63 is turned on. However, if the allowable value of the gate-source voltage of the p-channel MOSFET 63 is greater than the input voltage Vin2, the resistor 66 is unnecessary and can be shorted. That is, the second terminal of the resistor 65 and the drain of the N-channel MOSFET 64 should be connected.
 したがって、本実施の形態では、nチャネルMOSFET55、nチャネルMOSFET64、およびpチャネルMOSFET63を同時に駆動することができる。 Therefore, in this embodiment, the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 can be driven simultaneously.
 図10に示すように、nチャネルMOSFET55、nチャネルMOSFET64、およびpチャネルMOSFET63がすべてオンの時、nチャネルMOSFET55のドレイン-ソース間電圧は0となる。この場合、コンデンサ22、pチャネルMOSFET63、ダイオード61、第2巻線N2、およびnチャネルMOSFET55で形成される回路ループに、インダクタンスL2および入力電圧Vin2に応じた三角波電流が流れる。N2電流のピーク電流Ip3は、実施の形態1の電源回路100、および実施の形態2の電源回路200と同様に、流通時間ton2を用いて次の式で表される。 As shown in FIG. 10, when the n-channel MOSFET 55, n-channel MOSFET 64, and p-channel MOSFET 63 are all on, the drain-source voltage of the n-channel MOSFET 55 is zero. In this case, a triangular current corresponding to the inductance L2 and the input voltage Vin2 flows through the circuit loop formed by the capacitor 22, the p-channel MOSFET 63, the diode 61, the second winding N2, and the n-channel MOSFET 55. The peak current Ip3 of the N2 current is expressed by the following equation using the flow time ton2, similarly to the power supply circuit 100 of the first embodiment and the power supply circuit 200 of the second embodiment.
 Ip3=Vin2×ton2/L2…(C1)
 これにより、スイッチングトランス3にエネルギーを蓄積する。
Ip3=Vin2×ton2/L2…(C1)
As a result, energy is stored in the switching transformer 3 .
 nチャネルMOSFET55、nチャネルMOSFET64、およびpチャネルMOSFET63がオフとなると、蓄積したエネルギーが第1巻線N1および第3巻線N3に三角波電流が流れる。 When the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 are turned off, the stored energy causes a triangular wave current to flow through the first winding N1 and the third winding N3.
 一方、実施の形態3の電源回路300においては、nチャネルMOSFET55、nチャネルMOSFET64、およびpチャネルMOSFET63がすべてオフとなる区間(以下、オフ区間)において、nチャネルMOSFET55のドレイン-ソース間電圧は、入力電圧Vin2と等しくなる。オフ区間では、第2巻線N2の有する漏れインダクタンスにより、ダイオード62とダイオード21とが導通して、第2巻線N2に印加される電圧が入力電圧Vin2にクランプされるためである。 On the other hand, in the power supply circuit 300 of the third embodiment, the voltage between the drain and source of the n-channel MOSFET 55 is equal to the input voltage Vin2 in the period when the n-channel MOSFET 55, the n-channel MOSFET 64, and the p-channel MOSFET 63 are all turned off (hereinafter referred to as "off period"). This is because the leakage inductance of the second winding N2 causes conduction between the diode 62 and the diode 21 in the off period, and the voltage applied to the second winding N2 is clamped to the input voltage Vin2.
 N3電流の流通が終了し、N3電流が0になると、nチャネルMOSFET55のドレイン-ソース間の寄生容量と、pチャネルMOSFET63のドレイン-ソース間の寄生容量と、ダイオード61の寄生容量と、ダイオード62の寄生容量と、第2巻線N2のインダクタンスL2とによって、nチャネルMOSFET55のドレイン-ソース間電圧は振動する。 When the flow of the N3 current ends and the N3 current becomes 0, the drain-source voltage of the n-channel MOSFET 55 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 55, the parasitic capacitance between the drain and source of the p-channel MOSFET 63, the parasitic capacitance of the diode 61, the parasitic capacitance of the diode 62, and the inductance L2 of the second winding N2.
 なお、第2制御回路502が、第1制御回路501から検出信号DTを受け取った場合は、nチャネルMOSFET55およびnチャネルMOSFET64を駆動しないことによって、入力電圧Vin1と、入力電圧Vin2との同時入力を許容することができる。 When the second control circuit 502 receives the detection signal DT from the first control circuit 501, the simultaneous input of the input voltage Vin1 and the input voltage Vin2 can be allowed by not driving the n-channel MOSFET 55 and the n-channel MOSFET 64.
 <実施の形態3の独自の効果>
 電源回路300に入力電圧Vin2を入力した場合に、第2巻線N2の有する漏れインダクタンスを流れる電流は、第2電源2に回生することになる。したがって、実施の形態3の電源回路300は、ツェナーダイオード56でエネルギーを消費する実施の形態2の電源回路200と比較して、高効率な電源回路となる。
<Effect unique to the third embodiment>
When the input voltage Vin2 is input to the power supply circuit 300, the current flowing through the leakage inductance of the second winding N2 is regenerated to the second power supply 2. FIG. Therefore, the power supply circuit 300 of the third embodiment is a highly efficient power supply circuit as compared with the power supply circuit 200 of the second embodiment in which energy is consumed by the Zener diode 56 .
 また、入力電圧Vin2を入力した場合の動作で、オフ区間で、第2巻線N2に印加される電圧が入力電圧Vin2にクランプされることは、原理的に第3回路30で生成する出力電圧Vout2に上限をかけられることを意味している。その制限値LMは、以下の式で表される。 In addition, in the operation when the input voltage Vin2 is input, the voltage applied to the second winding N2 is clamped to the input voltage Vin2 in the off period, which means that the output voltage Vout2 generated by the third circuit 30 can be capped theoretically. The limit value LM is represented by the following formula.
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
 これにより、出力電圧Vout2の過電圧保護回路が不要となり、回路を小型化することができる。 This eliminates the need for an overvoltage protection circuit for the output voltage Vout2, allowing the circuit to be miniaturized.
 実施の形態2の電源回路200と比較して、実施の形態3の電源回路300では、入力電圧Vin2を入力した場合、リレー54の駆動が不要であるため、電源回路300を高速に起動することができる。実施の形態3の電源回路300では、リレー54の駆動が不要となるため、第2制御回路502を小型化することができる。 Compared to the power supply circuit 200 of the second embodiment, the power supply circuit 300 of the third embodiment does not need to drive the relay 54 when the input voltage Vin2 is input, so the power supply circuit 300 can be started at high speed. Since the power supply circuit 300 of the third embodiment does not need to drive the relay 54, the size of the second control circuit 502 can be reduced.
 <拡張性と効果>
 上記の実施の形態2、3では各部品を具体的に示したが、これらの部品を回路を切り替える機能を有する他の部品で置き換えたとしても同等の効果を得ることができる。
<Expandability and effectiveness>
Although each component is specifically shown in the second and third embodiments, equivalent effects can be obtained even if these components are replaced with other components having a circuit switching function.
 例えば、リレー54が、c接点を有するリレーによって構成されると説明したが、これに限定されるものではない。リレー54をa接点を有するリレーとb接点を有するリレーとを組み合わせて構成してもよい。リレー54として、(a)半導体アナログスイッチ、(b)フォトモスリレー、(c)フォトボル出力フォトカプラおよびMOSFET、(d)フォトサイリスタ等を用いることができる。 For example, although the relay 54 has been described as being configured by a relay having a c-contact, it is not limited to this. The relay 54 may be configured by combining a relay having an a-contact and a relay having a b-contact. As the relay 54, (a) a semiconductor analog switch, (b) a photoMOS relay, (c) a photovoltaic output photocoupler and MOSFET, (d) a photothyristor, or the like can be used.
 また、MOSFETの代わりにバイポーラトランジスタを使用することもできる。この場合、nチャネルMOSFETはNPNトランジスタ、pチャネルMOSFETはPNPトランジスタで構成することができる。これにより、抵抗65を削減することができる。 Also, a bipolar transistor can be used instead of a MOSFET. In this case, the n-channel MOSFET can be composed of an NPN transistor, and the p-channel MOSFET can be composed of a PNP transistor. Thereby, the resistance 65 can be reduced.
 実施の形態4.
 <構成>
 図11は、実施の形態4の電源回路400の構成を示す図である。
Embodiment 4.
<Configuration>
FIG. 11 is a diagram showing the configuration of a power supply circuit 400 according to the fourth embodiment.
 電源回路400は、第1回路10Aと、第2回路20Dと、第3回路30と、スイッチングトランス3とを備える。第3回路30およびスイッチングトランス3は、実施の形態1の電源回路100に含まれる第3回路30およびスイッチングトランス3と同様なので、説明を繰り返さない。第1回路10Aは、実施の形態2の電源回路200に含まれる第1回路10Aと同様なので、説明を繰り返さない。 The power supply circuit 400 includes a first circuit 10A, a second circuit 20D, a third circuit 30, and a switching transformer 3. Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 100 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
 第2回路20Dが、実施の形態2の第2回路20Aと相違する点は、第2回路20Dは、リレー54の代わりに、インダクタ74を備え、ダイオード21の代わりに、nチャネルMOSFET71、およびインバータ73を備える点である。 The second circuit 20D differs from the second circuit 20A of the second embodiment in that the second circuit 20D includes an inductor 74 instead of the relay 54, and an n-channel MOSFET 71 and an inverter 73 instead of the diode 21.
 インダクタ74の極性点のない第1端は、コンデンサ22の第1端と、負荷抵抗23の第1端と、入出力正極端子P22と接続される。インダクタ74の極性点のある第2端は、第2巻線N2の極性点のある第2端およびnチャネルMOSFET55のドレインに接続される。インダクタ74のインダクタンスをL74とする。 A first end of the inductor 74 without a polarity point is connected to the first end of the capacitor 22, the first end of the load resistor 23, and the input/output positive terminal P22. The second poled end of inductor 74 is connected to the second poled end of second winding N 2 and the drain of n-channel MOSFET 55 . Let the inductance of the inductor 74 be L74.
 nチャネルMOSFET71のドレインは、第2巻線N2の極性点のない第1端に接続される。nチャネルMOSFET71のソースは、nチャネルMOSFET55のソースと、コンデンサ22の第2端と、負荷抵抗23の第2端と、入出力正極端子P22と接続される。nチャネルMOSFET71のゲートは、インバータ73の出力に接続され、インバータ73の入力は、nチャネルMOSFET55のゲートに接続されている。 The drain of the n-channel MOSFET 71 is connected to the non-polarized first end of the second winding N2. The source of the n-channel MOSFET 71 is connected to the source of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the positive input/output terminal P22. The gate of n-channel MOSFET 71 is connected to the output of inverter 73 and the input of inverter 73 is connected to the gate of n-channel MOSFET 55 .
 nチャネルMOSFET55は、第2巻線N2の極性点のある第2端とインダクタ74との間の第1のノードND1と、入出力負極端子N22とnチャネルMOSFET71との間の第2のノードND2との間に配置される。 The n-channel MOSFET 55 is arranged between a first node ND1 between the second end of the second winding N2 having a polarity point and the inductor 74, and a second node ND2 between the input/output negative terminal N22 and the n-channel MOSFET 71.
 nチャネルMOSFET55のゲート(制御電極)およびインバータ73の入力には、第2制御回路502からの制御信号CT5が入力される。 A control signal CT5 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 55 and the input of the inverter 73 .
 第1制御回路501は、入力電圧Vin1によって動作する。第2制御回路502は、入力電圧Vin2によって動作する。 The first control circuit 501 operates with the input voltage Vin1. The second control circuit 502 operates with the input voltage Vin2.
 <動作1>
 入力電圧Vin1が第1回路10Aに入力され、入力電圧Vin2が第2回路20Dに入力されていない場合の電源回路400の動作は、実施の形態2と同様なので、図示は省略する。
<Action 1>
Since the operation of the power supply circuit 400 when the input voltage Vin1 is input to the first circuit 10A and the input voltage Vin2 is not input to the second circuit 20D is the same as that of the second embodiment, the illustration is omitted.
 入力電圧Vin1が入力されている場合、第1制御回路501がnチャネルMOSFET47を制御する。 When the input voltage Vin1 is input, the first control circuit 501 controls the n-channel MOSFET 47.
 第2制御回路502によって、nチャネルMOSFET55がオフとなり、nチャネルMOSFET71がオンとなる。 The second control circuit 502 turns off the n-channel MOSFET 55 and turns on the n-channel MOSFET 71 .
 nチャネルMOSFET47がオフのとき、N2電流は、第2巻線N2、インダクタ74、コンデンサ22、およびnチャネルMOSFET71で形成される回路ループを流れ、入出力正極端子P22に出力電圧Vout1を生成する。 When the n-channel MOSFET 47 is off, the N2 current flows through the circuit loop formed by the second winding N2, the inductor 74, the capacitor 22, and the n-channel MOSFET 71 to generate the output voltage Vout1 at the input/output positive terminal P22.
 これにより、第2制御回路502に電力が供給されておらず、第2制御回路502が動作していない状態であっても回路が形成され、出力電圧Vout1を出力することができる。すなわち入力電圧Vin1のみによる電源回路300の起動が可能になる。 Thus, even when power is not supplied to the second control circuit 502 and the second control circuit 502 is not operating, the circuit is formed and the output voltage Vout1 can be output. That is, the power supply circuit 300 can be activated only by the input voltage Vin1.
 一方、nチャネルMOSFET47がオンの時は、nチャネルMOSFET71によって、回路ループが形成できず、N2電流は流れることができずに0となる。したがって、電源回路300を、実施の形態2で示した電源回路200と同様に動作させることができる。 On the other hand, when the n-channel MOSFET 47 is on, a circuit loop cannot be formed by the n-channel MOSFET 71, and the N2 current cannot flow and becomes 0. Therefore, the power supply circuit 300 can be operated in the same manner as the power supply circuit 200 shown in the second embodiment.
  <動作2>
 図12は、実施の形態4における入力電圧Vin2が第2回路20Dに入力され、かつ入力電圧Vin1が第1回路10Aに入力されていない場合の電源回路300内の電圧および電流の波形を表す図である。
<Action 2>
FIG. 12 is a diagram showing voltage and current waveforms in power supply circuit 300 when input voltage Vin2 is input to second circuit 20D and input voltage Vin1 is not input to first circuit 10A in the fourth embodiment.
 入力電圧Vin2が入力されている場合、第2制御回路502は、入力電圧Vin2を受けて起動する。第2制御回路502は、第1制御回路501から検出信号DTが送られてこないこと、すなわち入力電圧Vin1が接続されていないことを検出した場合、制御信号CT5によって、nチャネルMOSFET55およびnチャネルMOSFET71の駆動を開始させる。 When the input voltage Vin2 is input, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, the control signal CT5 starts driving the n-channel MOSFET 55 and the n-channel MOSFET 71.
 インバータ73によって、nチャネルMOSFET71のゲート信号のレベルは、nチャネルMOSFET55のゲート信号のレベルを反転したものとなる。したがって、本実施の形態では、nチャネルMOSFET55とnチャネルMOSFET71とを交互に駆動することができる。 The inverter 73 causes the level of the gate signal of the n-channel MOSFET 71 to be the level of the gate signal of the n-channel MOSFET 55 inverted. Therefore, in this embodiment, the n-channel MOSFET 55 and the n-channel MOSFET 71 can be alternately driven.
 図12に示すように、nチャネルMOSFET55がオン、かつnチャネルMOSFET71がオフの時、nチャネルMOSFET55のドレイン-ソース間電圧は0となる。この場合、コンデンサ22、インダクタ74、およびnチャネルMOSFET55で形成される回路ループに、インダクタンスL74および入力電圧Vin2に応じた三角波電流が流れる。これにより、インダクタ74にエネルギーが蓄積される。 As shown in FIG. 12, when the n-channel MOSFET 55 is on and the n-channel MOSFET 71 is off, the drain-source voltage of the n-channel MOSFET 55 is zero. In this case, a triangular wave current corresponding to the inductance L74 and the input voltage Vin2 flows through the circuit loop formed by the capacitor 22, the inductor 74, and the n-channel MOSFET 55. Energy is thereby stored in the inductor 74 .
 nチャネルMOSFET55がオフ、かつnチャネルMOSFET71がオンとなると、第2巻線N2に、入力電圧Vin2とインダクタ74に発生する逆起電圧RVとを足し合わせた電圧が印加され、第1巻線N1および第3巻線N3に三角波電流が流れる。この時、nチャネルMOSFET55のドレイン-ソース間に印加される電圧は、第2巻線N2のインダクタンスL2および第3巻線N3のインダクタンスL3の比率の平方根と出力電圧Vout2との積となる、この積が入力電圧Vin2とインダクタ74に発生する逆起電圧RVとを足し合わせた電圧と等しくなる。 When the n-channel MOSFET 55 is turned off and the n-channel MOSFET 71 is turned on, a voltage obtained by adding the input voltage Vin2 and the counter electromotive voltage RV generated in the inductor 74 is applied to the second winding N2, and a triangular wave current flows through the first winding N1 and the third winding N3. At this time, the voltage applied between the drain and source of the n-channel MOSFET 55 is the product of the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 and the output voltage Vout2.
 N3電流の流通が終了し、N3電流が0になると、nチャネルMOSFET55のドレイン-ソース間の寄生容量と、インダクタンスL74とによって、nチャネルMOSFET55のドレイン-ソース間電圧は振動する。また、この間、nチャネルMOSFET71がオンしている場合は、インダクタンスL74と第2巻線N2のインダクタンスL2は、入力電圧Vin2によって励磁され、インダクタ74の電流は増加し、第2巻線N2の電流は減少する。その後、次の周期で再びnチャネルMOFET55がオンする。 When the flow of the N3 current ends and the N3 current becomes 0, the drain-source voltage of the n-channel MOSFET 55 oscillates due to the parasitic capacitance between the drain and source of the n-channel MOSFET 55 and the inductance L74. During this time, when the n-channel MOSFET 71 is on, the inductance L74 and the inductance L2 of the second winding N2 are excited by the input voltage Vin2, the current of the inductor 74 increases, and the current of the second winding N2 decreases. After that, the n-channel MOSFET 55 is turned on again in the next period.
 なお、第2制御回路502が、第1制御回路501から検出信号DTを受け取った場合は、nチャネルMOSFET55およびnチャネルMOSFET71を駆動しないことによって、入力電圧Vin1と、入力電圧Vin2との同時入力を許容することができる。 When the second control circuit 502 receives the detection signal DT from the first control circuit 501, the simultaneous input of the input voltage Vin1 and the input voltage Vin2 can be allowed by not driving the n-channel MOSFET 55 and the n-channel MOSFET 71.
 <実施の形態4の独自の効果>
 第2巻線N2の極性点のある第2端から電圧を印加し、第2巻線N2の極性点のない第1端をスイッチングした場合、第2巻線N2のインダクタンスL2および第3巻線のN3のインダクタンスL3の比率の平方根に入力電圧Vin2を乗じた値を上限とした出力電圧Vou2しか出力することができない。すなわち入力電圧Vin2の低下に対して脆弱な電源となる。しかしながら、電源回路400はインダクタ74を有しているため、昇圧動作が可能であり、入力電圧Vin2の値が小さい場合であっても、第2巻線N2のインダクタンスL2および第3巻線のN3のインダクタンスL3の比率の平方根に入力電圧Vin2を乗じた値よりも大きな出力電圧Vout2を出力することができる。
<Effect unique to the fourth embodiment>
When a voltage is applied from the second end of the second winding N2, which has a polarity point, and the first end of the second winding N2, which has no polarity point, is switched, only the output voltage Vou2 whose upper limit is the value obtained by multiplying the input voltage Vin2 by the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 can be output. That is, the power supply is vulnerable to a drop in the input voltage Vin2. However, since the power supply circuit 400 has the inductor 74, it is possible to perform a step-up operation, and even when the value of the input voltage Vin2 is small, it is possible to output an output voltage Vout2 that is higher than the square root of the ratio of the inductance L2 of the second winding N2 and the inductance L3 of the third winding N3 multiplied by the input voltage Vin2.
 <拡張性と効果>
 上記の説明では、インダクタ74に極性を示したが、極性を逆にしたとしても同様の効果を奏する。
<Expandability and effectiveness>
Although the polarity of the inductor 74 is shown in the above description, the same effect can be obtained even if the polarity is reversed.
 また、簡単のためにインバータ73を用いて説明したが、nチャネルMOSFET55のゲート信号と、nチャネルMOSFET71のゲート信号には相応なデッドタイムを設けてもよいし、第2制御回路502によって個別に制御されてもよい。nチャネルMOSFET71のゲート信号を個別に制御する場合、そのゲート信号のオン時間は、図12に示すTからton3を減算して得られる値よりも小さくすると、nチャネルMOSFET71のドレイン―ソースに印加されるサージ電圧が小さくなる。 In addition, although the inverter 73 was used for the sake of simplicity, the gate signal of the n-channel MOSFET 55 and the gate signal of the n-channel MOSFET 71 may be provided with a suitable dead time, or may be individually controlled by the second control circuit 502. When controlling the gate signal of the n-channel MOSFET 71 individually, if the ON time of the gate signal is smaller than the value obtained by subtracting ton3 from T shown in FIG.
 <実施の形態4の変形例>
 図13は、実施の形態4の変形例の電源回路400Aの構成を示す図である。
<Modification of Embodiment 4>
FIG. 13 is a diagram showing a configuration of a power supply circuit 400A according to a modification of the fourth embodiment.
 電源回路400Aは、第1回路10Aと、第2回路20Eと、第3回路30と、スイッチングトランス3とを備える。第3回路30およびスイッチングトランス3は、実施の形態1の電源回路200に含まれる第3回路30およびスイッチングトランス3と同様なので、説明を繰り返さない。第1回路10Aは、実施の形態2の電源回路200に含まれる第1回路10Aと同様なので、説明を繰り返さない。 The power supply circuit 400A includes a first circuit 10A, a second circuit 20E, a third circuit 30, and a switching transformer 3. Third circuit 30 and switching transformer 3 are the same as third circuit 30 and switching transformer 3 included in power supply circuit 200 of the first embodiment, and therefore description thereof will not be repeated. Since first circuit 10A is the same as first circuit 10A included in power supply circuit 200 of the second embodiment, description thereof will not be repeated.
 第2回路20Eが、実施の形態4の第2回路20Dと相違する点は、第2回路20Eが、第2巻線N2の両端に接続される整流回路77を備える点である。 The second circuit 20E differs from the second circuit 20D of the fourth embodiment in that the second circuit 20E includes a rectifier circuit 77 connected across the second winding N2.
 整流回路77は、コンデンサ76と、nチャネルMOSFET72とを備える。第1のノードND1と第2のノードND2との間に、コンデンサ76およびnチャネルMOSFET72は、直列に接続される。 A rectifier circuit 77 includes a capacitor 76 and an n-channel MOSFET 72 . A capacitor 76 and an n-channel MOSFET 72 are connected in series between a first node ND1 and a second node ND2.
 コンデンサ76の第1端は、第2巻線N2の第2端、インダクタ74の第2端、およびnチャネルMOSFET55のドレインに接続される。コンデンサ76の第2端は、nチャネルMOFET72のドレインに接続される。 A first end of the capacitor 76 is connected to the second end of the second winding N2, the second end of the inductor 74, and the drain of the n-channel MOSFET 55. A second end of capacitor 76 is connected to the drain of n-channel MOSFET 72 .
 nチャネルMOSFET72のソースは、nチャネルMOSFET71のソースと、nチャネルMOSFET55のソースと、コンデンサ22の第2端と、負荷抵抗23の第2端と、入出力正極端子P22と接続される。 The source of the n-channel MOSFET 72 is connected to the sources of the n-channel MOSFET 71, the source of the n-channel MOSFET 55, the second end of the capacitor 22, the second end of the load resistor 23, and the positive input/output terminal P22.
 nチャネルMOSFET72のゲート(制御電極)には、第2制御回路502からの制御信号CT6が入力される。 A control signal CT6 from the second control circuit 502 is input to the gate (control electrode) of the n-channel MOSFET 72 .
 第2制御回路502は、第1回路10の第1制御回路501からの検出信号DTに基づいて、制御信号CT6によって、nチャネルMOSFET72を制御する。 The second control circuit 502 controls the n-channel MOSFET 72 with the control signal CT6 based on the detection signal DT from the first control circuit 501 of the first circuit 10.
 入力電圧Vin1が入力されている場合、第2制御回路502は、出力電圧Vout1を受けて起動する。第2制御回路502は、第1制御回路501から検出信号DTが送られていること、すなわち入力電圧Vin1が接続されていることを検出した場合、制御信号CT6をオンすることで、nチャネルMOSFET72をオンする。 When the input voltage Vin1 is input, the second control circuit 502 receives the output voltage Vout1 and starts up. When the second control circuit 502 detects that the detection signal DT is sent from the first control circuit 501, that is, that the input voltage Vin1 is connected, the second control circuit 502 turns on the control signal CT6 to turn on the n-channel MOSFET 72.
 これにより、入力電圧Vin1が接続されている場合、N2電流は、第2巻線N2、コンデンサ76、およびnチャネルMOSFET72で構成される回路ループに流れる。その結果、電源回路400Aにおいて、第2巻線N2のインダクタンスL2にとって、寄生成分となるインダクタ74の影響を抑制し、出力電圧Vout1が低下することを防止できる。 Thus, when the input voltage Vin1 is connected, the N2 current flows through the circuit loop composed of the second winding N2, the capacitor 76, and the n-channel MOSFET 72. As a result, in the power supply circuit 400A, the influence of the inductor 74, which is a parasitic component for the inductance L2 of the second winding N2, can be suppressed, and a decrease in the output voltage Vout1 can be prevented.
 また、インダクタ74とコンデンサ22は、出力電圧Vout1にとってLCフィルタを形成しており、出力電圧Vout1に出力されるディファレンシャルモードノイズを低減する効果を得る。 Also, the inductor 74 and the capacitor 22 form an LC filter for the output voltage Vout1, and obtain the effect of reducing the differential mode noise output to the output voltage Vout1.
 なお、入力電圧Vin2が入力されている場合は、第2制御回路502は、入力電圧Vin2を受けて起動する。第2制御回路502は、第1制御回路501から検出信号DTが送られてこないこと、すなわち入力電圧Vin1が接続されていないことを検出した場合、制御信号CT6をオフすることで、nチャネルMOSFET72をオフし、コンデンサ76を回路から切り離す。 When the input voltage Vin2 is input, the second control circuit 502 receives the input voltage Vin2 and starts up. When the second control circuit 502 detects that the detection signal DT is not sent from the first control circuit 501, that is, that the input voltage Vin1 is not connected, the second control circuit 502 turns off the control signal CT6 to turn off the n-channel MOSFET 72 and disconnect the capacitor 76 from the circuit.
 今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本開示の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of claims rather than the above description, and is intended to include all changes within the meaning and scope of equivalence to the scope of claims.
1 第1電源、2 第2電源、3,3A,3B スイッチングトランス、10,10A,40A,40B 第1回路、11,15,21,31,61,62,83 ダイオード、12,14,22,32,76,82 コンデンサ、13,65,66,81 抵抗、17,24,25 スイッチ、20,20A,20B,20C,20D,20E 第2回路、23,33 負荷抵抗、30,50A,50B 第3回路、47,55,63,64,71,72 MOSFET、54 リレー、56 ツェナーダイオード、89 スナバ回路、100,200,200A,300 電源回路、501 第1制御回路、502 第2制御回路、503 フィードバック回路、C1 出力状態端子、C2 入力状態端子、N1 第1巻線、N2 第2巻線、N3 第3巻線、N11,N12,N21,N22,N31 負極端子、P11,P12,P21,P22,P31 正極端子、73 インバータ、74 インダクタ、77 整流回路。 1 first power supply, 2 second power supply, 3, 3A, 3B switching transformer, 10, 10A, 40A, 40B first circuit, 11, 15, 21, 31, 61, 62, 83 diode, 12, 14, 22, 32, 76, 82 capacitor, 13, 65, 66, 81 resistor, 17, 24, 25 switch, 20, 20A, 20B, 20C, 20D, 20E Second circuit, 23, 33 Load resistance, 30, 50A, 50B Third circuit, 47, 55, 63, 64, 71, 72 MOSFET, 54 Relay, 56 Zener diode, 89 Snubber circuit, 100, 200, 200A, 300 Power supply circuit, 501 First control circuit, 502 Second control circuit, 503 Feedback circuit, C1 output state terminal, C2 input state terminal, N1 first winding, N2 second winding, N3 third winding, N11, N12, N21, N22, N31 negative terminal, P11, P12, P21, P22, P31 positive terminal, 73 inverter, 74 inductor, 77 rectifier circuit.

Claims (15)

  1.  第1巻線と第2巻線と第3巻線とを有するスイッチングトランスと、
     第1回路と、第2回路と、第3回路とを備え、
     前記第1回路は、
     第1電源の電圧を受けることが可能に構成される入力正極端子および入力負極端子と、
     前記第1巻線への入力電圧の印加をオンまたはオフに切り替える第1のスイッチと、
     前記第1のスイッチを制御する第1制御回路と、を含み、
     前記第2回路は、
     第2電源の電圧を受けて前記第2巻線に電力を誘起するか、または前記第1巻線に印加された電圧に応じて前記第2巻線に誘起された電力を外部負荷に出力するかを切替える第2制御回路を含み、
     前記第3回路は、
     前記第1巻線または前記第2巻線に印加された電圧に応じて、前記第3巻線に誘起された電力を出力する出力正極端子および出力負極端子と、
     前記出力正極端子と前記出力負極端子との間に生成された出力電圧に応じて変化するフィードバック信号を前記第1制御回路および前記第2制御回路に帰還するフィードバック回路と、を含む、電源回路。
    a switching transformer having a first winding, a second winding, and a third winding;
    comprising a first circuit, a second circuit, and a third circuit;
    The first circuit is
    an input positive terminal and an input negative terminal configured to receive the voltage of the first power supply;
    a first switch that turns on or off application of an input voltage to the first winding;
    a first control circuit that controls the first switch;
    The second circuit is
    a second control circuit for switching between receiving the voltage of a second power supply and inducing power in the second winding, or outputting the power induced in the second winding to an external load according to the voltage applied to the first winding,
    The third circuit is
    an output positive terminal and an output negative terminal for outputting the power induced in the third winding according to the voltage applied to the first winding or the second winding;
    a feedback circuit that feeds back a feedback signal that varies according to the output voltage generated between the output positive terminal and the output negative terminal to the first control circuit and the second control circuit.
  2.  前記第2回路は、
     前記第2電源の電圧を受けることが可能であり、かつ前記第1巻線に印加された電圧に応じて前記第2巻線に誘起された電力を出力することが可能に構成される入出力正極端子および入出力負極端子と、
     前記第2巻線に誘起された電力を前記入出力正極端子および前記入出力負極端子に出力するか、または前記第2電源からの電力を前記第2巻線に入力するかを切り替えるように構成された第2のスイッチと、
     前記第2巻線への入力電圧の印加をオンまたはオフに切り替える第3のスイッチと、を含み、
     前記第2制御回路は、前記第2のスイッチおよび前記第3のスイッチを制御する、請求項1記載の電源回路。
    The second circuit is
    an input/output positive terminal and an input/output negative terminal capable of receiving the voltage of the second power supply and outputting the power induced in the second winding according to the voltage applied to the first winding;
    a second switch configured to switch between outputting the power induced in the second winding to the positive input/output terminal and the negative input/output terminal or inputting power from the second power supply to the second winding;
    a third switch that turns on or off the application of the input voltage to the second winding;
    2. The power supply circuit according to claim 1, wherein said second control circuit controls said second switch and said third switch.
  3.  前記第1回路は、さらに、
     前記入力正極端子と前記入力負極端子との間に接続される第1のコンデンサと、
     前記第1巻線の第1端に接続されるカソードを有する第1のダイオードと、
     前記第1巻線の第2端に接続されるアノードを有する第2のダイオードと、
     前記入力正極端子および前記第1のダイオードのアノードと、前記第2のダイオードのカソードとの間に接続される第1の抵抗と、
     前記入力正極端子および前記第1のダイオードのアノードと、前記第2のダイオードのカソードとの間に接続される第2のコンデンサとを含み、
     前記第1のスイッチの第1端は、前記第1巻線の前記第2端および前記第2のダイオードのアノードに接続され、前記第1のスイッチの第2端は、前記入力負極端子に接続される、請求項1または2記載の電源回路。
    The first circuit further comprises:
    a first capacitor connected between the positive input terminal and the negative input terminal;
    a first diode having a cathode connected to the first end of the first winding;
    a second diode having an anode connected to the second end of the first winding;
    a first resistor connected between the positive input terminal and the anode of the first diode and the cathode of the second diode;
    a second capacitor connected between the positive input terminal and the anode of the first diode and the cathode of the second diode;
    3. The power supply circuit according to claim 1, wherein a first end of said first switch is connected to said second end of said first winding and an anode of said second diode, and a second end of said first switch is connected to said input negative terminal.
  4.  前記第1制御回路は、前記フィードバック信号に基づいて、前記第1のスイッチを制御し、前記第2制御回路は、前記フィードバック信号に基づいて、前記第3のスイッチを制御する、請求項2または3記載の電源回路。 4. The power supply circuit according to claim 2 or 3, wherein said first control circuit controls said first switch based on said feedback signal, and said second control circuit controls said third switch based on said feedback signal.
  5.  前記第1制御回路は、前記第1回路に前記第1電源の電圧が入力されている場合に検出信号を前記第2制御回路へ送り、
     前記第2制御回路は、前記第1制御回路からの前記検出信号に基づいて、前記第2のスイッチを制御する、請求項2または3記載の電源回路。
    The first control circuit sends a detection signal to the second control circuit when the voltage of the first power supply is input to the first circuit,
    4. The power supply circuit according to claim 2, wherein said second control circuit controls said second switch based on said detection signal from said first control circuit.
  6.  前記第1制御回路は、前記第1電源からの電力によって駆動され、
     前記第2制御回路は、前記第2電源からの電力によって駆動される、請求項5に記載の電源回路。
    The first control circuit is driven by power from the first power supply,
    6. The power supply circuit according to claim 5, wherein said second control circuit is driven by power from said second power supply.
  7.  前記第2回路は、さらに、
     第3のダイオードを備え、
     前記第2のスイッチは、
     出力状態端子および入力状態端子を含み、
     前記入力状態端子は、前記第2巻線の第1端および前記第3のダイオードのカソードに接続され、
     前記出力状態端子は、前記第3のスイッチの第1端および前記第2巻線の第2端に接続され、
     前記第3のスイッチの第2端は、前記第3のダイオードのアノードおよび前記入出力負極端子に接続され、
     前記第2のスイッチは、前記入出力正極端子と前記出力状態端子とを接続するか、あるいは前記入出力正極端子と前記入力状態端子とを接続するかを切り替える、請求項6記載の電源回路。
    The second circuit further comprises:
    comprising a third diode;
    The second switch is
    including an output state terminal and an input state terminal,
    the input state terminal is connected to the first end of the second winding and the cathode of the third diode;
    the output state terminal is connected to a first end of the third switch and a second end of the second winding;
    a second end of the third switch is connected to the anode of the third diode and the input/output negative terminal;
    7. The power supply circuit according to claim 6, wherein said second switch switches between connecting said positive input/output terminal and said output state terminal or connecting said positive input/output terminal and said input state terminal.
  8.  前記第2のスイッチは、リレーによって構成され、
     前記第2制御回路が動作しないときに、前記リレーによって、前記入出力正極端子が前記出力状態端子に接続される、請求項7記載の電源回路。
    The second switch is configured by a relay,
    8. The power supply circuit of claim 7, wherein said relay connects said input/output positive terminal to said output state terminal when said second control circuit is inoperative.
  9.  前記第3のスイッチは、第1のトランジスタによって構成され、
     前記第2回路は、さらに前記第1のトランジスタに並列に接続されたツェナーダイオードを含む、請求項7記載の電源回路。
    the third switch is composed of a first transistor,
    8. The power supply circuit of claim 7, wherein said second circuit further includes a Zener diode connected in parallel with said first transistor.
  10.  前記第1のトランジスタは、nチャネルMOSFETであり、
     前記ツェナーダイオードのツェナー電圧は、前記第1のトランジスタのドレイン-ソース間電圧定格電圧以下である、請求項9記載の電源回路。
    the first transistor is an n-channel MOSFET;
    10. The power supply circuit according to claim 9, wherein the Zener voltage of said Zener diode is equal to or less than the drain-source voltage rated voltage of said first transistor.
  11.  前記第3のスイッチは、第1のトランジスタによって構成され、
     前記第2回路は、さらに、前記第2巻線の両端に接続されるスナバ回路を備える、請求項7に記載の電源回路。
    the third switch is composed of a first transistor,
    8. The power supply circuit of claim 7, wherein said second circuit further comprises a snubber circuit connected across said second winding.
  12.  前記第2回路は、さらに、
     第3のダイオードを備え、
     前記第3のスイッチは、第1のトランジスタによって構成され、
     前記第2のスイッチは、
     第4のダイオード、第5のダイオード、第2のトランジスタ、第3のトランジスタ、第2の抵抗、および第3の抵抗を備え、
     前記第5のダイオードのアノードは、前記第2巻線の第2端、および前記第1のトランジスタの第1電極に接続され、前記第5のダイオードのカソードは、前記第2のトランジスタの第1電極と、前記第2の抵抗の第1端と、前記入出力正極端子と接続され、
     前記第2のトランジスタの第2電極は、前記第4のダイオードのアノードに接続され、前記第4のダイオードのカソードは、前記第2巻線の第1端、および前記第3のダイオードのカソードに接続され、
     前記第2のトランジスタの制御電極は、前記第2の抵抗の第2端と、前記第3の抵抗の第1端に接続され、前記第3の抵抗の第2端は、前記第3のトランジスタの第1電極に接続され、前記第3のトランジスタの第2電極は、前記第3のダイオードのアノード、前記第1のトランジスタの第2電極、および前記入出力負極端子と接続され、
     前記第2制御回路は、前記第1のトランジスタの制御電極、および前記第3のトランジスタの制御電極に制御信号を出力する、請求項6記載の電源回路。
    The second circuit further comprises:
    comprising a third diode;
    the third switch is composed of a first transistor,
    The second switch is
    a fourth diode, a fifth diode, a second transistor, a third transistor, a second resistor, and a third resistor;
    the anode of the fifth diode is connected to the second end of the second winding and the first electrode of the first transistor, the cathode of the fifth diode is connected to the first electrode of the second transistor, the first end of the second resistor, and the positive input/output terminal;
    the second electrode of the second transistor is connected to the anode of the fourth diode, the cathode of the fourth diode is connected to the first end of the second winding and the cathode of the third diode;
    a control electrode of the second transistor is connected to a second end of the second resistor and a first end of the third resistor, a second end of the third resistor is connected to a first electrode of the third transistor, a second electrode of the third transistor is connected to the anode of the third diode, a second electrode of the first transistor, and the negative input/output terminal;
    7. The power supply circuit according to claim 6, wherein said second control circuit outputs control signals to the control electrode of said first transistor and the control electrode of said third transistor.
  13.  前記第2回路は、
     前記第2電源の電圧を受けることが可能であり、かつ前記第1巻線に印加された電圧に応じて前記第2巻線に誘起された電力を出力することが可能に構成される入出力正極端子および入出力負極端子と、
     前記入出力負極端子と、前記第2巻線の第1端との間に配置された第4のトランジスタと、
     前記入出力正極端子と、前記第2巻線の第2端との間に配置されたインダクタと、
     前記第2巻線の前記第2端と前記インダクタとの間の第1のノードと、前記入出力負極端子と前記第4のトランジスタとの間の第2のノードとの間に配置された第5のトランジスタと含み、
     前記第2制御回路は、前記第4のトランジスタをオンに設定するときには、前記第5のトランジスタをオフに設定し、前記第4のトランジスタをオフに設定するときには、前記第5のトランジスタをオンに設定する、請求項1記載の電源回路。
    The second circuit is
    an input/output positive terminal and an input/output negative terminal capable of receiving the voltage of the second power supply and outputting the power induced in the second winding according to the voltage applied to the first winding;
    a fourth transistor disposed between the input/output negative terminal and the first end of the second winding;
    an inductor disposed between the positive input/output terminal and a second end of the second winding;
    a fifth transistor disposed between a first node between the second end of the second winding and the inductor and a second node between the negative input/output terminal and the fourth transistor;
    2. The power supply circuit according to claim 1, wherein the second control circuit turns off the fifth transistor when turning on the fourth transistor, and turns on the fifth transistor when turning off the fourth transistor.
  14.  前記第2回路は、さらに、
     前記第1のノードと前記第2のノードとの間に、直列に接続された第3のコンデンサおよび第6のトランジスタとを含む、請求項13記載の電源回路。
    The second circuit further comprises:
    14. A power supply circuit according to claim 13, comprising a third capacitor and a sixth transistor connected in series between said first node and said second node.
  15.  前記第2回路は、さらに、
     前記入出力正極端子と前記入出力負極端子との間に並列に接続される第4のコンデンサおよび第4の抵抗を備える、請求項7~14のいずれか1項に記載の電源回路。
    The second circuit further comprises:
    15. The power supply circuit according to claim 7, comprising a fourth capacitor and a fourth resistor connected in parallel between said positive input/output terminal and said negative input/output terminal.
PCT/JP2022/046824 2022-01-20 2022-12-20 Power source circuit WO2023140010A1 (en)

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JPH11196573A (en) * 1997-12-26 1999-07-21 Tohoku Ricoh Co Ltd Snubber circuit of switching power supply
JP2004147404A (en) * 2002-10-23 2004-05-20 Cosel Co Ltd Drive circuit for synchronous rectification type forward converter
JP2008206304A (en) * 2007-02-20 2008-09-04 Tdk Corp Switching power supply device
JP2014183634A (en) * 2013-03-18 2014-09-29 Panasonic Corp Power converter and power conditioner
JP2019221070A (en) * 2018-06-20 2019-12-26 新電元工業株式会社 Switching power supply device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11196573A (en) * 1997-12-26 1999-07-21 Tohoku Ricoh Co Ltd Snubber circuit of switching power supply
JP2004147404A (en) * 2002-10-23 2004-05-20 Cosel Co Ltd Drive circuit for synchronous rectification type forward converter
JP2008206304A (en) * 2007-02-20 2008-09-04 Tdk Corp Switching power supply device
JP2014183634A (en) * 2013-03-18 2014-09-29 Panasonic Corp Power converter and power conditioner
JP2019221070A (en) * 2018-06-20 2019-12-26 新電元工業株式会社 Switching power supply device

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