WO2022185533A1

WO2022185533A1 - Inverter device

Info

Publication number: WO2022185533A1
Application number: PCT/JP2021/008711
Authority: WO
Inventors: 里早三浦; 正人半田; 圭一朗志津
Original assignee: 三菱電機株式会社
Priority date: 2021-03-05
Filing date: 2021-03-05
Publication date: 2022-09-09
Also published as: JP7471504B2; JPWO2022185533A1

Abstract

This inverter device (100) is provided with an inverter module (8) that controls a current to be applied to a compressor by a switching operation, electrolytic capacitors (2-5) that smooth a current supplied to the inverter module (8), DC lines (9, 14) connected to the inverter module (8) and the electrolytic capacitors (2-5) and through which a negative electrode-side current flows, and DC lines (10, 12) connected to the inverter module (8) and the electrolytic capacitors and through which a positive electrode-side current flows. The DC lines (9, 14) are disposed and duplicated on a first layer and a second layer, and the DC lines (10, 12) are disposed and duplicated on a third layer and a fourth layer.

Description

Inverter device

The present disclosure relates to an inverter device that converts DC voltage into AC voltage.

It is desired that the inverter device be miniaturized. In the inverter device described in Patent Document 1, a cylindrical insulator is sandwiched between a cylindrical positive electrode side bus bar metal plate and a cylindrical negative electrode side bus bar metal plate, and a pair of positive electrode side bus bar metal plates and a negative electrode side bus bar metal plate are provided. A substrate structure is realized in which the busbar metal plate is opposed.

JP-A-9-205778

However, in the technique of Patent Document 1, the positive electrode side bus bar metal plate, the negative electrode side bus bar metal plate, and the insulator need to be cylindrical, so there is a problem that it is difficult to reduce the size of the inverter device. rice field.

The present disclosure has been made in view of the above, and aims to obtain an inverter device that is easily miniaturized.

In order to solve the above-described problems and achieve the object, the inverter device of the present disclosure includes an inverter module that controls the current supplied to the compressor by switching operation, and an electrolytic capacitor that smoothes the current supplied to the inverter module. and Further, the inverter device of the present disclosure includes a first power supply line that is connected to the inverter module and the electrolytic capacitor and through which the negative current flows, and a first power supply line that is connected to the inverter module and the electrolytic capacitor and through which the positive current flows. and a second power supply line. The first power supply line is arranged on the first layer and on the second layer and is duplicated, and the second power supply line is arranged on the third layer and on the fourth layer and is duplicated. there is

According to the present disclosure, it is possible to easily miniaturize the inverter device.

1 is a perspective view showing the configuration of an inverter device according to an embodiment; FIG. BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing which shows the structure of the inverter apparatus concerning embodiment FIG. 4 is a diagram for explaining stray capacitance in a comparative inverter device in which the P line and the N line are not duplicated; FIG. 4 is a diagram for explaining stray capacitance in an inverter device according to an embodiment in which P lines and N lines are duplicated;

Below, the inverter device according to the embodiment of the present disclosure will be described in detail based on the drawings.

Embodiment.
FIG. 1 is a perspective view of the configuration of an inverter device according to an embodiment. FIG. 2 is a cross-sectional view showing the configuration of the inverter device according to the embodiment. In the embodiment, the two axes in the plane parallel to the upper surface of the substrate 1A of the inverter device 100 and perpendicular to each other are defined as the X-axis and the Y-axis. Also, the axis orthogonal to the X-axis and the Y-axis is defined as the Z-axis. In the following description, the positive Z-axis direction may be referred to as the upper side of the inverter device 100 and the negative Z-axis direction may be referred to as the lower side of the inverter device 100 .

The inverter device 100 is a device that converts a DC voltage into an AC voltage by switching operation. The inverter device 100 includes a base material 1A that is a base material for the first layer, a base material 1B that is a base material for the second layer, a base material 1C that is a base material for the third layer, and a fourth layer. and a base material 1D that is the base material of the eye. The base material 1A is the first base material, and the base material 1B is the second base material. The base material 1C is the third base material, and the base material 1D is the fourth base material.

FIG. 1 shows the state of the inverter device 100 before the base materials 1A to 1D are joined. FIG. 2 shows a cross-sectional configuration of the inverter device 100 when the inverter device 100 is cut along a plane parallel to the XZ plane.

The base materials 1A to 1D are each formed using a plate-like member having a rectangular top surface and bottom surface. The substrates 1A to 1D have top and bottom surfaces of the same size and shape. The substrates 1A-1D are insulators. Examples of substrates 1A-1D are printed circuit boards.

The

base materials

1A and 1B are joined so that the bottom surface of the base material 1A and the top surface of the base material 1B overlap. Moreover, the

base materials

1B and 1C are joined so that the bottom surface of the base material 1B and the top surface of the base material 1C overlap. Moreover, the

base materials

1C and 1D are joined so that the bottom surface of the base material 1C and the top surface of the base material 1D overlap. The substrates 1A to 1D are joined together so that the vertices of the plate members overlap when viewed from the Z-axis direction.

On the substrate 1A, electrolytic capacitors 2 to 5, an inverter module 8, a DC (Direct Current) line (N line) 9, which is a power line on the low potential side of the inverter module 8 and through which current on the negative electrode side flows. , an overcurrent cutoff circuit 6 and a gate voltage control circuit 7 .

The electrolytic capacitors 2-5 smooth the current supplied to the inverter module 8. The electrolytic capacitors 2-5 are used as an electrolytic capacitor 32, which will be described later. The overcurrent cutoff circuit 6 cuts off the overcurrent flowing through the inverter module 8 by controlling the current flowing through the inverter module 8 .

The gate voltage control circuit 7, which is a control circuit, controls the current flowing through the inverter module 8 by controlling the gate voltage of the semiconductor switching elements (semiconductor switching elements 33 to 38 described later) included in the inverter module 8.

The inverter module 8 is a module corresponding to the inverter circuit section 39 which will be described later. The inverter module 8 drives the compressor 40 by controlling the current supplied to the compressor 40 (described later) by switching operation.

In addition, the base material 1B is a power line on the high potential side and has a DC line (P line) 10 through which current on the positive electrode side flows, and the base material 1C is a power line on the high potential side and is on the positive electrode side. has a DC line (P line) 12 through which a current of . The substrate 1D also has a DC line (N line) 14, which is a power line on the low-potential side and through which current on the negative electrode side flows.

The DC line 9 is arranged as a wiring pattern on the upper surface of the base material 1A, and the DC line 10 is arranged as a wiring pattern on the upper surface of the base material 1B. The DC lines 12 are arranged as wiring patterns on the upper surface of the substrate 1C, and the DC lines 14 are arranged as wiring patterns on the upper surface of the substrate 1D.

The DC lines 9 and 14 are the first power lines, and the DC lines 10 and 12 are the second power lines. The layer on the substrate 1A on which the DC lines 9 are arranged is the first layer, and the layer on the substrate 1D on which the DC lines 14 are arranged is the second layer. The layer on the substrate 1B on which the DC lines 10 are arranged is the third layer, and the layer on the substrate 1C on which the DC lines 12 are arranged is the fourth layer. DC line 9 is the first line and DC line 14 is the second line. DC line 10 is the third line and DC line 12 is the fourth line.

The DC line 10, which is a P line, is arranged on the top surface of the base material 1B, and is formed as an inner layer between the

base materials

1A and 1B by joining the bottom surface of the base material 1A and the top surface of the base material 1B. .

In addition, the DC line 12, which is the P line, is arranged on the upper surface of the base material 1C, and the bottom surface of the base material 1B and the upper surface of the base material 1C are joined to form an inner layer between the

base materials

1B and 1C. be done.

In addition, the DC line 14, which is the N line, is arranged on the upper surface of the base material 1D, and the bottom surface of the base material 1C and the upper surface of the base material 1D are joined to form an inner layer between the

base materials

1C and 1D. be done.

The DC line 14 has the same shape and size pattern as the DC line 9 and is arranged below the DC line 9 . The DC line 12 has the same shape and size pattern as the DC line 10 and is arranged below the DC line 10 .

The DC line 9 connects the inverter module 8 and the

electrolytic capacitors

2 and 4. The DC line 14 is arranged at the same position as the DC line 9 when the inverter device 100 is viewed from the Z-axis direction.

The DC lines 10, 12 are arranged at positions connecting the inverter module 8 and the

electrolytic capacitors

3, 5 when the inverter device 100 is viewed from the Z-axis direction. The DC line 12 is arranged at the same position as the DC line 10 when the inverter device 100 is viewed from the Z-axis direction.

The substrates 1A-1C are provided with through-

holes

47, 49 passing through the substrates 1A-1C, and the

DC lines

9, 14 are connected through the through-

holes

47, 49. Further, the base material 1B is provided with through

holes

48 and 50 penetrating through the base material 1B, and the DC lines 10 and 12 are connected through the through

holes

48 and 50, respectively. All of the

DC lines

9 , 10 , 12 , 14 are thereby connected to the inverter module 8 . Thus, the

DC lines

9 and 14 are duplicated within the inverter device 100 . Also, the DC lines 10 and 12 are duplicated within the inverter device 100 . Through

holes

47 and 49 are first through holes, and through

holes

48 and 50 are second through holes.

In this way, the inverter device 100 is formed into four layers by stacking the base materials 1A to 1D. Thereby, the

DC lines

9 and 14 can be duplicated, and the DC lines 10 and 12 can be duplicated. Therefore, the pattern width for one layer of P lines can be halved, and the pattern width for one layer of N lines can be halved. Empty space in the substrate 1A increases. Also, the patterns of the

DC lines

9, 10, 12, 14 can be drawn around in the inner layer portions of the substrates 1A to 1D. As a result, in the inverter device 100, the degree of freedom in pattern routing of the

DC lines

9, 10, 12, 14 is improved.

By improving the degree of freedom of pattern routing of the

DC lines

9, 10, 12, 14, the distance between the components connected to the

DC lines

9, 10, 12, 14 can be shortened. Specifically, the distance between the inverter module 8 connected to the

DC lines

9, 14 and the

electrolytic capacitors

2, 4 can be shortened. Also, the distance between the inverter module 8 connected to the DC lines 10, 12 and the

electrolytic capacitors

3, 5 can be shortened. As a result, the pattern wiring lengths of the

DC lines

9, 10, 12, and 14 are shortened, and the line impedance can be reduced.

When the

DC lines

9, 10, 12, and 14 are not coated and impurities (sulfur, salt, etc.) that allow current to flow adhere to the substrates 1A to 1D, the impurities are affected by humidity and the like. It absorbs moisture and turns into an aqueous solution. In this case, when current is passed through the substrates 1A to 1D, a potential difference is generated between the patterns of the

DC lines

9, 10, 12, and 14 via the aqueous solution, causing current to flow. As a result, the pattern is electrolyzed and corroded.

In the inverter device 100 of the present embodiment, the DC lines 10 and 12, which are the P lines on the high potential side, are internalized and doubled with the base material 1B, which is an insulator, interposed therebetween. As a result, the DC lines 10 and 12, which are P lines, are prevented from generating a potential difference between them and the

DC lines

9, 14, which are N lines, and the adhesion of impurities can be prevented. Also, since the P line has a higher potential than the N line, a potential difference is more likely to occur and impurities are more likely to adhere. In addition, since the DC line 14, which is the N line, is formed as an inner layer, it is possible to prevent impurities from adhering to the DC line 14 as well, thereby obtaining an anticorrosion effect. In inverter device 100, only DC line 9 needs to be coated for corrosion prevention.

Here, the stray capacitance between the P line and the N line when the P line and the N line are not duplicated, and the stray capacitance between the P line and the N line when the P line and the N line are duplicated capacity.

FIG. 3 is a diagram for explaining stray capacitance in a comparative inverter device in which the P line and the N line are not duplicated. FIG. 4 is a diagram for explaining stray capacitance in an inverter device according to an embodiment in which P lines and N lines are duplicated; 3 and 4, the

stray capacitances

41 and 42 are illustrated as capacitors. Also, in FIG. 4, the

stray capacitances

45 and 46 are illustrated as capacitors.

FIG. 3 shows a circuit diagram of the inverter device 101 of the comparative example and stray capacitance generated in the inverter device 101. FIG. FIG. 4 shows a circuit diagram of the inverter device 100 according to the embodiment and stray capacitance generated in the inverter device 100. As shown in FIG. 3 and 4, illustration of the overcurrent cutoff circuit 6 and the gate voltage control circuit 7 is omitted.

Since the inverter device 101 and the inverter device 100 have the same circuit configuration except for duplication of the DC line, the circuit configuration of the inverter device 100 will be described here.

The inverter device 100 is connected to the AC power supply 16 and the compressor 40 . The inverter device 100 includes a noise filter circuit section 21, a resistor 22, a relay 23, a diode bridge 24,

reactors

25 and 26, a converter circuit section 31, an electrolytic capacitor 32, and an inverter circuit section 39. there is

The noise filter circuit section 21 has

coils

17 and 18 and

capacitors

19 and 20 . In the noise filter circuit section 21 , the coil 17 is connected to the capacitor 19 , the capacitor 19 is connected to the coil 18 , the coil 18 is connected to the capacitor 20 , and the capacitor 20 is connected to the coil 17 . The AC power supply 16 is connected to a connection point between the coil 17 and the capacitor 19 and to a connection point between the coil 18 and the capacitor 19 .

A connection point between the capacitor 20 and the coil 17 is connected to one end of the resistor 22 and one end of the relay 23 . A connection point connecting the other end of the resistor 22 and the other end of the relay 23 is connected to the diode bridge 24 . A connection point between the coil 18 and the capacitor 20 is connected to a diode bridge 24 .

The diode bridge 24 is connected to one end of the reactor 25 and one end of the reactor 26 . Also, the diode bridge 24 is connected to a connection point between the electrolytic capacitor 32 and the inverter circuit section 39 .

The converter circuit section 31 has

diodes

27 and 28 and

semiconductor switching elements

29 and 30 . Each of the

semiconductor switching elements

29 and 30 is constructed by connecting a transistor and a diode in parallel.

The anode of the diode 27 is connected to the other end of the reactor 25, the collector of the transistor provided in the semiconductor switching element 30, and the cathode of the diode. The anode of the diode 28 is connected to the other end of the reactor 26, the collector of the transistor provided in the semiconductor switching element 29, and the cathode of the diode. A connection point connecting the cathode of the diode 27 and the cathode of the diode 28 is connected to the electrolytic capacitor 32 .

The emitters of the transistors and the anodes of the diodes provided in the

semiconductor switching elements

29 and 30 are connected to connection lines that connect the diode bridge 24 and the electrolytic capacitor 32, respectively.

The inverter circuit section 39 has semiconductor switching elements 33-38. The inverter circuit section 39 is a circuit in which a plurality of transistors and diodes are connected in parallel and formed into a three-phase bridge. Specifically, inverter circuit section 39 has three legs, and each leg is connected in parallel between bus 43 and bus 44 . Bus 43 is a duplicated P line, ie DC lines 10,12, and bus 44 is a duplicated N line,

ie DC lines

9,14.

Note that the inverter device 101 has

bus lines

51 and 52 instead of the

bus lines

43 and 44 . The bus 51 is a non-duplicated P-line, and the bus 52 is a non-duplexed N-line.

The first leg is a circuit section in which a semiconductor switching element 33 that is a U-phase upper arm switching element and a semiconductor switching element 34 that is a U-phase lower arm switching element are connected in series.

The second leg is a circuit section in which a semiconductor switching element 35 that is a V-phase upper arm switching element and a semiconductor switching element 36 that is a V-phase lower arm switching element are connected in series.

The third leg is a circuit section in which a semiconductor switching element 37, which is a W-phase upper arm switching element, and a semiconductor switching element 38, which is a W-phase lower arm switching element, are connected in series.

The bus 43 is connected to the connection point between the

diodes

27 and 28 and the electrolytic capacitor 32 . In addition, U-phase, V-phase, and W-phase upper arm switching elements are connected to the bus 43 . Specifically, a transistor collector and a diode cathode provided in each of

semiconductor switching elements

33 , 35 and 37 are connected to bus line 43 .

The bus 44 is connected to the connection point between the diode bridge 24 and the electrolytic capacitor 32 . In addition, U-phase, V-phase, and W-phase lower arm switching elements are connected to the bus 44 . Specifically, the transistor emitter and the diode anode of each of the

semiconductor switching elements

34 , 36 , 38 are connected to the bus 44 .

A connection point between the

semiconductor switching elements

33 and 34 , a connection point between the

semiconductor switching elements

35 and 36 , and a connection point between the

semiconductor switching elements

37 and 38 are connected to the compressor 40 .

When an AC voltage is output from the AC power supply 16 to the inverter device 100 , the AC voltage is applied to the noise filter circuit section 21 and the converter circuit section 31 , and the AC voltage is forward-converted to the inverter circuit section 39 as a DC voltage. A voltage is applied. As a result, the inverter circuit unit 39 reversely converts the DC voltage and outputs an AC current to drive the compressor 40 .

In this case, in the inverter device 101,

stray capacitances

41 and 42 are included between the P line and the N line of the DC lines, that is, between the

bus lines

51 and 52.

Similarly, in the inverter device 100,

stray capacitances

bus lines

43 and 44. Furthermore, in the inverter device 100,

stray capacitances

45 and 46 are included between the

buses

43 and 44 due to the duplication of the DC lines. A stray capacitance 45 is a stray capacitance between the

DC lines

9 and 10 , and a stray capacitance 46 is a stray capacitance between the DC lines 12 and 14 . In the inverter device 100, since the DC line is duplicated, the stray capacitance between the P line and the N line increases more than when the DC line is not duplicated.

Thus, in the inverter device 100, stray capacitance is included between the P line and the N line, that is, between the

bus lines

43 and 44. Therefore, in the inverter device 100, since the DC line is duplicated, the portion where the P line and the N line overlap increases, so the stray capacitance between the P line and the N line also increases. That is, due to the duplication of the DC lines, stray capacitance is generated between the

DC lines

9 and 10 and stray capacitance is generated between the DC lines 12 and 14 .

In this way, the

inverter devices

100 and 101 include the

capacitors

19 and 20 mounted in the noise filter circuit section 21 and the capacitors corresponding to the

stray capacitances

41 and 42 included in the pattern between the P line and the N line. has Furthermore, the inverter device 100 has capacitors corresponding to the increased

stray capacitances

45 and 46 due to the duplication of the DC lines.

Thus, in the inverter device 100, the

stray capacitances

45 and 46 are generated due to the duplication of the DC lines, so noise on the substrates 1A to 1D can be easily absorbed. Therefore, the inverter device 100 has improved noise resistance.

The size of the inverter device 100 can be easily reduced because it is not necessary to configure the positive electrode side busbar and the negative electrode side busbar with tubular metal plates. In the case of an inverter device in which the positive electrode side busbar and the negative electrode side busbar are made of cylindrical metal plates, the area of the DC line that comes into contact with air increases, so the coating area of the DC line increases. Production cost is high.

On the other hand, in the inverter device 100, the base materials 1A to 1D are laminated and the DC lines 10, 12, 14 are internalized, so the DC lines 9 may be coated. Since the area of the DC line 9 is smaller than that of the DC line provided in the inverter device 101, the cost of coating for corrosion prevention can be kept low.

Thus, according to the embodiment, the DC lines 10, 12 and the

DC lines

9, 14 are doubled and the substrates 1A to 1D are laminated, so that the pattern width of the DC lines is halved. As a result, the degree of freedom in routing the pattern of the DC line 9 increases, and the area in which the inverter module 8, the electrolytic capacitors 2 to 5, and other electronic components can be arranged becomes wider. As a result, the distance between the components on the base material 1A can be shortened, and since the DC line 9 is the only DC line to be arranged on the base material 1A, the area of the top surface of the base material 1A can be reduced. Become. Therefore, a miniaturized inverter device 100 can be realized.

Also, since the DC lines 10, 12 and the

DC lines

9, 14 are duplicated, the stray capacitance between the DC lines increases, noise is easily absorbed, and noise resistance is improved.

In addition, since the DC lines 10, 12, 14 are internalized by laminating the base materials 1A to 1D, the DC lines 10, 12, 14 do not need to be coated for corrosion prevention. Therefore, the cost of the anti-corrosion coating can be kept low.

The configuration shown in the above embodiment is an example, and can be combined with another known technique, and part of the configuration can be omitted or changed without departing from the scope of the invention. It is possible.

1A to 1D base material, 2 to 5, 32 electrolytic capacitor, 6 overcurrent cutoff circuit, 7 gate voltage control circuit, 8 inverter module, 9, 10, 12, 14 DC line, 16 AC power supply, 17, 18 coil, 19 , 20 capacitor, 21 noise filter circuit, 22 resistor, 23 relay, 24 diode bridge, 25, 26 reactor, 27, 28 diode, 29, 30, 33 to 38 semiconductor switching element, 31 converter circuit, 39 inverter circuit , 40 compressor, 41, 42, 45, 46 floating capacity, 43, 44, 51, 52 busbar, 47-50 through hole, 100, 101 inverter device.

Claims

an inverter module that controls current supplied to the compressor by switching operation;
an electrolytic capacitor that smoothes the current supplied to the inverter module;
a first power supply line connected to the inverter module and the electrolytic capacitor and through which current on the negative electrode side flows;
a second power supply line connected to the inverter module and the electrolytic capacitor and through which positive current flows;
with
the first power supply line is arranged and duplicated on the first layer and the second layer;
The second power supply line is arranged and duplicated on the third layer and the fourth layer,
inverter device.
a first base on which the inverter module and the electrolytic capacitor are arranged;
a second substrate bonded to the bottom surface of the first substrate;
a third substrate bonded to the bottom surface of the second substrate;
a fourth substrate bonded to the bottom surface of the third substrate;
further comprising
the first layer is a layer on the first substrate;
the second layer is a layer on the fourth substrate;
the third layer is a layer on the second substrate;
The fourth layer is a layer on the third substrate,
The inverter device according to claim 1.
the first power supply line is duplicated using a first line arranged on the first layer and a second line arranged on the second layer;
the second power supply line is duplicated using a third line arranged on the third layer and a fourth line arranged on the fourth layer;
The first line and the second line are patterns of the same shape and size,
The third line and the fourth line are patterns of the same shape and size,
The inverter device according to claim 2.
the first line and the second line are connected via a first through hole,
The third line and the fourth line are connected via a second through hole,
The inverter device according to claim 3.
An overcurrent cutoff circuit that cuts off an overcurrent flowing through the inverter module and a control circuit that controls the current flowing through the inverter module are arranged on the first substrate.
The inverter device according to any one of claims 2 to 4.