WO2021049091A1

WO2021049091A1 - Electric power conversion device and railway vehicle electric system

Info

Publication number: WO2021049091A1
Application number: PCT/JP2020/017352
Authority: WO
Inventors: 徹増田; 早川　誠一; 高柳　雄治
Original assignee: 株式会社日立パワーデバイス
Priority date: 2019-09-13
Filing date: 2020-04-22
Publication date: 2021-03-18
Also published as: JP7133524B2; JP2021044996A

Abstract

Provided is an electric power conversion device that is obtained by parallel connection of a plurality of power semiconductor modules and that can reduce switching loss while suppressing parasitic oscillation generated during switching operation. This electric power conversion device is provided with: a plurality of power semiconductor modules; a gate driving circuit for driving the plurality of power semiconductor modules; and an arm circuit configured from a gate wiring circuit that is connected between the gate driving circuit and the plurality of power semiconductor modules and that is for parallel connection of the plurality of power semiconductor modules with respect to the gate driving circuit. The electric power conversion device is characterized in that the gate wiring circuit has a plurality of impedance circuits respectively corresponding to the plurality of power semiconductor modules, the impedance value of each of the impedance circuits is changed in conjunction with the frequency of a voltage applied to the impedance circuit, the impedance value becomes small at low frequencies, and the impedance value becomes great at high frequencies.

Description

Power converter, rail vehicle electrical system

The present invention relates to a power conversion device configured by connecting a plurality of power semiconductor modules in parallel to each other, and more particularly to a configuration of a gate wiring circuit connecting a gate drive circuit and a gate of a power semiconductor chip mounted on the module.

Power converters are used for power control and motor control of industrial equipment, electric railroad vehicles, hybrid vehicles, electric vehicles, etc., and electric parts such as power semiconductor modules and capacitors, and wiring and electric parts that connect them. It is composed of a radiator that dissipates heat generated by power loss, and supplies power to loads such as motors and system wiring.

The power converter is required to output a predetermined output current to the load circuit, and the value of the output current differs depending on its application and customer specifications. Therefore, depending on the output current, the rated current of a single power semiconductor module may be insufficient, and a method of satisfying the required output current by connecting a plurality of power semiconductor modules in parallel is adopted.

However, when multiple power semiconductor modules are connected in parallel and driven using a single gate drive circuit, parasitic vibration of voltage or current occurs at the turn-on or turn-off timing during switching, and its attenuation is reduced. If it is insufficient, it grows to oscillation with a large amplitude. In this case, parasitic oscillation is superimposed on the gate voltage having the smallest voltage rating in the power semiconductor module, and an operation exceeding the rated voltage occurs. As a result, the gate portion of the semiconductor element mounted on the power semiconductor module may be damaged, leading to the destruction of the module.

In order to avoid this problem, a gate resistor with a relatively large resistance value is connected to the gate of each power semiconductor module. For example, in Patent Document 1, parasitic oscillation is suppressed by a damping resistor provided on the output side of the gate drive circuit. However, if a gate resistor having a relatively large resistance value is connected as described above, the current (gate current) value for driving the gate of the power semiconductor module to be driven by the gate drive circuit becomes small. As a result, the turn-on time and the turn-off time become long at the same time, and there is a side effect that the loss at the time of switching, that is, the turn-on loss and the turn-off loss both increase.

As an example of solving the above problem, in Patent Document 2, on the premise that the parasitic oscillation generated at the time of switching occurs at either the turn-on or turn-off timing, the loss during the switching operation in which the parasitic oscillation does not occur does not increase. As described above, the diode element is introduced so that the gate resistance looks different depending on the direction of the gate current.

FIG. 1 of Patent Document 2 includes a plurality of semiconductor switching elements (T1a, T1b) and a plurality of balance resistance portions (Ra, Rb) connected in parallel to each other, and the balance resistance portion includes, for example, a resistor R3a and a diode D2a. An example in which the balance resistor portion Ra is configured by the parallel circuit with the above is shown. With this configuration, the resistance value can be switched between different values when turning on and when turning off.

Japanese Unexamined Patent Publication No. 2003-88098 International Publication No. 2017/0236367

However, with the means shown in Patent Document 2 above, in the switching operation in which parasitic oscillation occurs between turn-on and turn-off, the switching time becomes long and an increase in switching loss cannot be avoided.

In recent years, the development of new devices such as SiC and GaN as elements for power semiconductor modules has been remarkable, and the switching operation (turn-on, turn-off, or recovery operation) in which parasitic oscillation occurs is not uniform, and a more fundamental solution is required. Is.

Therefore, a means for suppressing parasitic oscillation while shortening the switching time in both turn-on and turn-off switching operations is desired.

Therefore, an object of the present invention is a power conversion device capable of reducing switching loss while suppressing parasitic oscillation generated during switching operation in a power conversion device configured by connecting a plurality of power semiconductor modules in parallel with each other. The purpose is to provide an electric system for railway vehicles to be installed.

In order to solve the above problems, the present invention is connected between a plurality of power semiconductor modules, a gate drive circuit for driving and controlling the plurality of power semiconductor modules, and the plurality of power semiconductor modules and the gate drive circuit. A power conversion device including an arm circuit composed of a gate wiring circuit for connecting the plurality of power semiconductor modules in parallel to the gate drive circuit, wherein the gate wiring circuit is the plurality of power semiconductor modules. It has a plurality of impedance circuits corresponding to each of the above, and the impedance value of the impedance circuit changes depending on the frequency of the voltage applied to the impedance circuit. It is characterized in that the impedance value increases at the frequency.

Further, the present invention is connected between a plurality of power semiconductor modules, a gate drive circuit for driving and controlling the plurality of power semiconductor modules, and the plurality of power semiconductor modules and the gate drive circuit, and is connected to the gate drive circuit. On the other hand, it is a power conversion device provided with an arm circuit composed of a gate wiring circuit for connecting the plurality of power semiconductor modules in parallel to each other, and each of the plurality of power semiconductor modules is a power semiconductor module together with a power semiconductor transistor. It has an impedance circuit built in the power semiconductor transistor and connected in series between the gate terminal of the power semiconductor transistor and the gate drive circuit, and the impedance value of the impedance circuit depends on the frequency of the voltage applied to the impedance circuit. It is characterized in that the impedance value is small in the low frequency range and the impedance value is large in the high frequency range.

Further, the present invention includes a pantograph, a breaker connected to the pantograph, a reactor connected to the breaker, a power conversion device connected to the reactor, and an electric motor connected to the power conversion device. , The power conversion device is the power conversion device according to any one of the above.

According to the present invention, in a power conversion device configured by connecting a plurality of power semiconductor modules in parallel to each other, a power conversion device capable of reducing switching loss while suppressing parasitic oscillation generated during switching operation and a power conversion device thereof are mounted. A railroad vehicle electrical system can be realized.

Issues, configurations and effects other than those described above will be clarified by the explanation of the following embodiments.

It is a figure which shows the arm circuit of the power conversion apparatus of Example 1. FIG. It is a figure which shows the transient response waveform of the voltage Vgs when the parasitic oscillation does not occur in a gate voltage. It is a figure which shows the distribution of the amplitude for each frequency of the gate voltage waveform when the parasitic oscillation does not occur in the gate voltage. It is a figure which shows the transient response waveform of the voltage Vgs when the parasitic oscillation is superimposed on the gate voltage. It is a figure which shows the distribution of the amplitude for each frequency of the gate voltage waveform when the parasitic oscillation is superimposed on the gate voltage. It is a figure which shows the impedance circuit of the power conversion apparatus of Example 1. It is a figure which shows the effect of this invention. It is a figure which shows the effect of this invention. It is a figure which shows the arm circuit of the power conversion apparatus of Example 2. It is a figure which shows the railroad vehicle electric system of Example 3. It is a figure which shows the impedance circuit of the power conversion apparatus of Example 4. It is a figure which shows the impedance circuit of the power conversion apparatus of Example 5. It is a figure which shows the impedance circuit of the power conversion apparatus of Example 5. It is a figure which shows the impedance circuit of the power conversion apparatus of Example 6.

Hereinafter, examples of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of overlapping portions will be omitted.

The power conversion device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4C. In this embodiment, first, an example in which parasitic oscillation occurs in a power conversion device using power semiconductor modules connected in parallel will be shown, and the behavior of the gate voltage waveform in that case will be described.

Here, the gate voltage (Vgs) indicates the voltage between the gate drive terminal and the source sense drive terminal, which are the output terminals of the gate drive circuit, or the voltage between the gate terminal and the source sense terminal of the power semiconductor module. For the gate voltage between the specified terminals, the terminal name will be specified below.

FIGS. 2A and 2B show an example in which parasitic oscillation does not occur in the gate voltage during switching in a power conversion device including power semiconductor modules connected in parallel.

FIG. 2A is a transient response waveform of the voltage Vgs between the gate terminal and the source sense terminal during the turn-on operation. Vgs changes from the off-voltage VGSM to the on-voltage VGSP. The rate of change of the voltage waveform is gradual, and in the time range shown in the figure, it operates within the gate voltage ratings on both the positive and negative sides (within the upper and lower limits of the gate voltage rating).

The FFT analysis result (FFT: Fast Fourier Transform) of this waveform is shown in FIG. 2B. The horizontal axis is the logarithmic display of frequencies, and the vertical axis is the value of the voltage amplitude analyzed for each frequency. As can be seen from FIG. 2B, in the low frequency range, the amplitude has a large distribution corresponding to the transient response of Vgs. In the high frequency range, the amplitude level is smaller than that in the low frequency range, and as long as Vgs operates normally without parasitic oscillation, the frequency distribution that responds to the transient waveform is mainly in the low frequency range. It can be said that it occurs.

On the other hand, FIGS. 3A and 3B show a case where parasitic oscillation is superimposed on a turn-on waveform of the same Vgs. In the transient response waveform of FIG. 3A, parasitic oscillation occurs at the timing when Vgs approaches VGSP, which is the on-voltage. The vibration amplitude of the oscillation is large, and the waveform is such that it exceeds the maximum rating of the gate on both the positive side and the negative side. In this case, the gate portion of the power semiconductor chip mounted on the power semiconductor module may be damaged and destroyed. Further, as shown in FIG. 3B, it is clear that the amplitude value of the gate voltage waveform for each frequency increases in the high frequency range due to the influence of the generated vibration (gate voltage parasitic oscillation vibration). .. The parasitic oscillation vibration shown in FIG. 3A vibrates at a specific frequency. This is because when this waveform is viewed as an amplitude distribution for each frequency, the amplitude increases at the high frequency centered on the specific frequency.

The following can be seen from the comparison of the presence or absence of parasitic oscillation in the above gate voltage waveform.

(1) The frequency distribution of the gate waveform that operates normally without parasitic oscillation is concentrated in the low frequency range.

(2) When parasitic oscillation occurs, its frequency distribution is superimposed on the high frequency.

If the amplitude of the resonance voltage and the resonance current can be reduced in the frequency range occupied by the transient response waveform of the parasitic oscillation, that is, the high frequency, the parasitic oscillation will not occur and the gate voltage will be used within the rated range. can do.

Next, the configuration of the power conversion device of this embodiment will be described with reference to FIG. FIG. 1 is a diagram showing an arm circuit 90 constituting the power conversion device of this embodiment. The arm circuit 90 is composed of a gate drive circuit 1, a plurality of power semiconductor modules 10a to 10n, and a plurality of impedance circuits 20a to 20n constituting a gate wiring circuit.

The impedance circuits 20a to 20n are circuits that connect the gate drive terminal and the source sense drive terminal of the gate drive circuit 1 and the gate terminal and the source sense terminal of each of the power semiconductor modules 10a to 10n.

One end of the impedance circuits 20a to 20n corresponding to each of the power semiconductor modules 10a to 10n is collectively connected to the gate drive terminal nGDg and the source sense drive terminal nGDss of the gate drive circuit 1, and other than each of the impedance circuits 20a to 20n. The ends are connected to the gate terminals and source sense terminals of the corresponding power semiconductor modules 10a to 10n, respectively.

The gate drive circuit 1 receives a control circuit signal from the control circuit of the power converter at the terminal nCNT, and controls the drive of the power semiconductor modules 10a to 10n via the gate drive terminal nGDg and the source sense drive terminal nGDss.

The number of power semiconductor modules 10a to 10n is two or more, and the drain terminal is connected to each other at the terminal nD and the source terminal is connected to each other at the terminal nS. The gate terminal and the source sense terminal are connected to an impedance circuit constituting a gate wiring circuit described later. The number of parallel connections of the power semiconductor module is two or more natural numbers n, and the upper limit thereof is not limited.

As shown in FIG. 1, the gate wiring circuit is composed of wiring that electrically connects to a plurality of impedance circuits 20a to 20n. The gate drive terminal nGDg and the source sense drive terminal nGDss are used as inputs of the gate wiring circuit, and the gate drive terminal nGDg and the source sense drive terminal nGDss are branched in parallel to the impedance circuits 20a to 20n corresponding to each of the power semiconductor modules 10a to 10n. ..

The impedance circuits 20a to 20n are connected to the gate terminals and source sense terminals of the power semiconductor modules 10a to 10n at the output terminals nPMga to nPMgn and terminals nPMssa to nPMssn. The length of the electrical connection wiring of the gate wiring circuit is such that the electrical length generated from the gate drive terminal nGDg and the source sense drive terminal nGDss to each of the gate terminals and source sense terminals of the power semiconductor modules 10a to 10n is uniform. It is preferable that it is designed and implemented so as to be.

However, even if the uniformity of the electric length is impaired, the time delay error of the voltage waveform and the current waveform that the gate drive circuit 1 drives toward the power semiconductor modules 10a to 10n (the gate drive waveform between the power semiconductor modules). Needless to say, the delay error) is acceptable within a range that does not affect the operation of the power semiconductor modules 10a to 10n.

The impedance circuits 20a to 20n suppress the parasitic oscillation generated due to the resonance between the gates of the power semiconductor modules 10a to 10n connected in parallel with each other, and the switching operation of the power semiconductor modules 10a to 10n, that is, the turn-on operation. It is used to shorten the time required for turn-off operation and reduce switching loss.

An example of the structure is shown in the impedance circuit 20a of FIG. In the impedance circuit 20a, the resistor R1a and the inductor L1a are connected in series to the parallel circuit of the resistor R1a in the gate wiring path, and the source sense wiring path is arranged with electrical wiring.

Since the impedance of the inductor L1a is low at low frequencies and high at high frequencies, the resistor R1a in parallel with L1a is short-circuited with low impedance at low frequencies, and looks like the value of the resistor R1a at high frequencies. .. Here, the values of the resistors R1a to R1n and the resistors R2a to R2n in FIG. 1 are shown below as R1 and R2, respectively.

An example of the operation of the impedance circuit of this embodiment will be described with reference to FIGS. 4A to 4C.
4A to 4C show the characteristics calculated for the impedance between the terminals of the

impedance circuits

20a and 20b taken out from FIG.

FIG. 4A is a circuit in which only the

impedance circuits

20a and 20b are taken out from FIG. 1 and their effects are examined. FIG. 4B shows the frequency dependence of the impedance value from the gate drive terminal nGDg and the source sense drive terminal nGDss to the terminal nPMga and the terminal nPMssa. Specifically, since the terminal nGDss and the terminal nPMssa are connected by electrical wiring, the impedance value from the gate drive terminal nGDg to the terminal nPMga is shown. In the case of the circuit configuration of FIG. 4A, as shown by the solid line in FIG. 4B, the short-circuit effect of the inductor L1 is effective at low frequencies, and the impedance of the resistance value R2 is generated.

On the other hand, at the high frequency, it looks like a series circuit of the resistor R1 and the resistor R2, so the impedance determined by R1 + R2 is generated. The mid-range frequency between the low-frequency and high-frequency is the switching range of the above impedance 2 values (R1, R1 + R2). The

impedance circuits

20a and 20b always have a configuration in which the impedance value of the high frequency frequency is higher than the impedance value of the low frequency frequency.

The frequency dependence of the impedance shown in FIG. 4C indicates the impedance value generated between the two terminals of the terminal nPMga and the terminal nPMssa and the two terminals of the terminal nPMgb and the terminal nPMssb. Specifically, since the terminal nPMssa and the terminal nPMssb are connected by electrical wiring, the impedance value from the terminal nPMga to the terminal nPMgb is shown. That is, the path is a series circuit of the impedance circuit 20a and the impedance circuit 20b. This path corresponds to the connection path between the gate terminals of the

power semiconductor modules

10a and 10b (shown in FIG. 1) connected in parallel.

From the impedance characteristics of FIG. 4C, the impedance becomes a value of 2. (R1 + R2) at the high frequency, and the resistance can be increased by 2.R1 compared to the value of 2.R2 at the low frequency. Due to the dependence of this impedance on the frequency domain (low and high frequencies), the problem to be solved by the present invention, "while suppressing the parasitic oscillation generated due to the resonance between the gates of the power semiconductor modules connected in parallel". , Speeding up the switching operation of the power semiconductor module ”is made possible.

The characteristics of the broken lines shown in FIGS. 4B and 4C show the characteristics when L1 (L1a, L1b) is not introduced into the impedance circuit 20 (20a, 20b) (without L1). In this case, in FIG. 4B, resistors R1 + R2 are generated as the impedance of the gate path between the gate drive terminal nGDg and the source sense drive terminal nGDss and the terminal nPMga and the terminal nPMssa terminal regardless of the low frequency range and the high frequency range. ..

Further, as shown in FIG. 4C, a resistor 2 (R1 + R2) is generated between the two terminals of the terminal nPMga and the terminal nPMgssa and the two terminals of the terminal nPMgb and the terminal nPMgssb.
When the inductor L1 (L1a, L1b) is not introduced, impedance having a high resistance value is generated. In this case, the effect of damping the resonance between the gates of the power semiconductor modules connected in parallel can be obtained. The turn-on time and turn-off time of the switching operation become long, and the switching loss increases.

As described above, the power conversion device of this embodiment includes a plurality of power semiconductor modules 10a to 10n, a gate drive circuit 1 for driving and controlling a plurality of power semiconductor modules 10a to 10n, and a plurality of power semiconductor modules 10a to 10a. An arm circuit 90 is provided which is connected between 10n and the gate drive circuit 1 and is composed of a gate wiring circuit for connecting a plurality of power semiconductor modules 10a to 10n in parallel to the gate drive circuit 1. Has a plurality of impedance circuits 20a to 20n corresponding to each of the plurality of power semiconductor modules 10a to 10n, and each impedance value of the impedance circuits 20a to 20n depends on the frequency of the voltage applied to the impedance circuit. The impedance value is small at low frequencies and large at high frequencies.

Further, in the impedance circuit 20a, one end of the first resistor (resistor R1a) and one end of the inductor L1a are connected to each other, and the other end of the first resistor (resistor R1a) and the other end of the inductor L1a are connected to each other. It is configured to have a connected parallel circuit and a second resistor (resistor R2a) connected in series to the parallel circuit.

If the effect of this embodiment described above can be obtained only by the parallel circuit of the first resistor (resistor R1a) and the inductor L1a, there may be a configuration in which the second resistor (resistor R2a) is not provided.

This makes it possible to reduce switching loss while suppressing parasitic oscillation that occurs during high-speed switching operation in a power conversion device that is configured by connecting multiple power semiconductor modules in parallel with each other.

The resistance value of the first resistor (resistor R1a) needs to be larger than the resistance value of the second resistor (resistor R2a) (R1> R2). As shown in FIG. 4B, the resistance value of R2 can be set low by using the impedance circuit of the present invention, but at twice the low R2 (R1 + R2), the impedance in the high frequency range is low and practical. Not the target. Therefore, it is necessary to qualitatively set R1> R2.

Further, in order to maximize the effect of the present invention, the resistance value of the first resistor (resistor R1a) is set to 3 times or more (for example, 3 times to 4 times) the resistance value of the second resistor (resistor R2a). It is more preferable to set it to about twice).

The power conversion device according to the second embodiment of the present invention will be described with reference to FIG. Similar to the first embodiment (FIG. 1), it is a diagram showing an arm circuit 90 constituting a power conversion device. The arm circuit 90 of this embodiment includes a gate drive circuit 1, a plurality of power semiconductor modules 11a to 11n, and a gate wiring circuit.

The gate wiring circuit is a circuit that connects the gate drive terminal nGDg of the gate drive circuit 1, the source sense drive terminal nGDss, and the gate terminals and source sense terminals of the power semiconductor modules 11a to 11n. In this embodiment, the gate wiring circuit is composed of wiring for electrical connection.

The power semiconductor modules 11a to 11n of this embodiment are characterized in their internal configuration, and the impedance circuits 21a to 21n are arranged in the gate wiring path inside the module. That is, each of the impedance circuits 21a to 21n is configured to be built in each of the power semiconductor modules 11a to 11n.

The configurations of the impedance circuits 21a to 21n are the same as those of the impedance circuits 20a to 20n shown in the first embodiment (FIG. 1), and the description of the connection configuration and the change in the impedance value depending on the frequency domain will be omitted.

As described above, in the power conversion device of the present embodiment, the plurality of power semiconductor modules 11a to 11n, the gate drive circuit 1 for driving and controlling the plurality of power semiconductor modules 11a to 11n, and the plurality of power semiconductor modules 11a to 11a to It is provided with an arm circuit 90 which is connected between 11n and the gate drive circuit 1 and is composed of a gate wiring circuit which connects a plurality of power semiconductor modules 11a to 11n in parallel to the gate drive circuit 1 and has a plurality of powers. Each of the semiconductor modules 11a to 11n has impedance circuits 21a to 21n which are built in the power semiconductor modules 11a to 11n together with the power semiconductor transistor and are connected in series between the gate terminal of the power semiconductor transistor and the gate drive circuit 1. The impedance values of the impedance circuits 21a to 21n change depending on the frequency of the voltage applied to the impedance circuits, so that the impedance value is small in the low frequency range and large in the high frequency range. It is configured in.

In this embodiment, the following advantages occur by arranging the impedance circuits 21a to 21n inside the power semiconductor modules 11a to 11n, respectively.

(1) The configuration of the gate wiring circuit is simplified, and the assembly man-hours can be reduced.

(2) Power semiconductors by incorporating impedance circuits 21a to 21n whose frequency dependence has been adjusted in advance so as to suppress parasitic oscillation that may occur between the gates of parallel modules in consideration of the characteristics of the power semiconductor element built into the module. In the design of parallel connection of modules, the design effort for parasitic oscillation between gates is not required.

The railway vehicle electric system according to the third embodiment of the present invention will be described with reference to FIG. FIG. 6 is an example in which a railroad vehicle electric system including a three-phase power conversion device is configured by using the arm circuit 90 shown in the first or second embodiment.

The railroad vehicle electric system of this embodiment is composed of a pantograph 100, a circuit breaker 200, a reactor 300, a power conversion device 400, and an electric motor 500 as a load.

The power conversion device 400 includes a capacitor 4 and a control circuit 3. The capacitor 4 holds a main voltage Vcc, the control circuit 3 generates a control signal of a gate drive circuit, and each of the six arm circuits 90a to 90f. Inputs are made to the gate drive circuits 1a to 1f, respectively.

The

arm circuits

90a and 90b form a first phase inverter leg, similarly, the

arm circuits

90c and 90d form a second phase inverter leg, and the arm circuits 90e and 90f form a third phase inverter leg. The output line of each inverter leg is connected to the motor 500. The arm circuits 90a to 90f are composed of gate drive circuits 1a to 1f and parallel connection circuits (parallel module circuits) 2a to 2f of power semiconductor modules, respectively.

The advantage of this example is
(1) By using an arm circuit including a parallel configuration of power semiconductor modules using the impedance circuit of the present invention, it is possible to configure a three-phase power conversion device with low switching loss while suppressing gate parasitic oscillation between modules. it can.

As a result, the parallel connection of the power semiconductor module can be easily designed so as to meet the specification value of the output current output to the electric motor 500, the availability of the power semiconductor module used for the railway vehicle electric system is improved, and the design manpower is reduced. Can be made to.

(2) In order to satisfy the required current specifications for the motor 500, the current specifications can be set without providing an excessive margin by connecting small power semiconductor modules in parallel.

As a result, the power converter can be configured with the minimum number of parallel power semiconductor modules required, and the switching loss can be set low, so that the volume of the radiator included in the power converter can also be reduced. Therefore, the power conversion device can be miniaturized, and the railroad vehicle electric system can be miniaturized.

The power conversion device according to the fourth embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 is a gate wiring circuit configured by using the

impedance circuits

22a and 22b. The

impedance circuits

22a and 22b of this embodiment use a magnetic core for the inductor L1 (L1a, L1b). (Inductors L1a and L1b in FIG. 7 are indicated by symbols with cores.)
The advantages newly obtained by the impedance circuit of this embodiment by using the magnetic core are
(1) By confining the magnetic flux generated by the current flowing through the inductor by the magnetic core in the core, the coil wiring length required to satisfy the predetermined inductance value of the inductor L1 (L1a, L1b) can be shortened. ..

As a result, the component volume of the inductor L1 (L1a, L1b) can be reduced, and the impedance circuit 22 (22a, 22b) can be miniaturized as compared with the impedance circuits 20 and 21 of the first and second embodiments. ..

(2) In terms of the frequency dependence of the magnetic permeability of the magnetic core, the effect of increasing the inductance value of the inductor L1 (L1a, L1b) with frequency by using the magnetic core whose absolute value of impedance increases at high frequencies is effective. can get.

Therefore, the frequency dependence of the impedance of the impedance circuit described in the first embodiment, that is, the impedance values R2 (low frequency) to R1 + R2 (high frequency) or 2 · R2 (low) shown in FIGS. 4B and 4C. The rate of change in impedance from (regional frequency) to 2 (R1 + R2) (high frequency) becomes steep. As a result, the discrimination between the low frequency and the high frequency is improved.

As described above, in the power conversion device of this embodiment, the inductor L1 (L1a, L1b) is configured by winding the coil wiring around the magnetic core. It is desirable that this magnetic core has high impedance magnetic permeability at high frequencies. The effect of this embodiment described above can be further enhanced.

The power conversion device according to the fifth embodiment of the present invention will be described with reference to FIGS. 8A and 8B.
FIG. 8A is a gate wiring circuit configured by using the impedance circuit 23ab. In the impedance circuit 23ab of this embodiment, the inductor L1a and the inductor L1b are arranged in parallel on the resistor R1a and the resistor R1b, respectively, and a common magnetic core is used for the inductor L1a and the inductor L1b. The basic effect of using the magnetic core is as described in Example 4.

As an advantage of this embodiment,
(1) By sharing the magnetic core between adjacent impedance circuits, the magnetic flux generated in the core can be doubled, and the effective dielectric constant can be increased.

As a result, the component volumes of the inductor L1a and the inductor L1b can be further reduced, and the impedance circuit 23ab can be significantly miniaturized as compared with the impedance circuits 20 and 21 of the first and second embodiments. ..

FIG. 8B is a diagram showing a specific form in which a magnetic core is shared between adjacent impedance circuits. As shown in FIG. 8B, the advantage of the above (1) can be obtained by sharing one magnetic core 30 between L1a and L1b and mounting the magnetic core 30 in consideration of the winding direction of the coil wiring.

As described above, the power conversion device of the present embodiment includes a plurality of impedance circuits, and in two impedance circuits arranged adjacent to each other, one magnetic core constituting each inductor L1a and L1b is used. It is configured to be shared by two magnetic cores.

The power conversion device according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a diagram showing a gate wiring circuit and a source sense wiring circuit configured by using the

impedance circuits

24a and 24b. The impedance circuit 24a is a gate wiring circuit configured by connecting the resistor R2a in series to a parallel circuit of the resistor R1a and the inductor L1a, and a source sense configured by connecting the resistor R4a in series to the parallel circuit of the resistor R3a and the inductor L2a. It has both a wiring circuit. The impedance circuit 24b is also configured in the same manner as the impedance circuit 24a.

The advantage obtained by using a frequency-dependent impedance circuit for the source sense wiring circuit in addition to the gate wiring circuit is
(1) Resonance generated between the gates of modules connected in parallel grows to parasitic oscillation. The resulting resonance voltage and resonance current pass not only through the wiring between the gate terminals between the modules but also through the gate-source capacitance of the module (for example, in the case of a MOSFET) and the source terminal and the source sense terminal.

Therefore, the effect of suppressing parasitic oscillation can be further enhanced by arranging the frequency-dependent impedance circuit of the present invention also in the source sense wiring which is the passage of resonance.

The circuit constants (R1, L1, R2 and R3, L2, R4) of the gate wiring circuit and the source sense wiring circuit do not necessarily have to be equal to each other.

In other words, in the power conversion device of the present embodiment, a source that is connected between the plurality of power semiconductor modules and the gate drive circuit 1 and connects the plurality of power semiconductor modules to the gate drive circuit 1 in parallel with each other. A sense wiring circuit is provided, and impedance circuits (24a, 24b) are arranged in both a gate wiring circuit and a source sense wiring circuit, respectively.

According to each embodiment of the present invention described above, in a power conversion device configured by connecting a plurality of power semiconductor modules in parallel to each other, a power capable of reducing switching loss while suppressing parasitic oscillation generated during switching operation. It is possible to realize a conversion device and a railway vehicle electric system equipped with the conversion device.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

For example, if the values of the resistor and the inductor in the impedance circuit are feasible values, the values, the realization method, and the mounting method are not particularly limited. Further, in the description of the present invention, the J-FET type (junction type field effect transistor) unipolar device is used as opposed to the MOSFET type (MOS type field effect transistor) in which the power semiconductor chip of the power semiconductor module is used in this embodiment. Then, even when the device is replaced with one of the bipolar devices such as the IGBT type (insulated gate bipolar transistor), and the drain is replaced with the collector and the source is replaced with the emitter among the functions of the terminals, the present invention The effect does not change. In this case, the "source sense wiring circuit (source sense wiring path)" of each embodiment is replaced with the "emitter sense wiring circuit (emitter sense wiring path)".

Further, as shown in the third embodiment (FIG. 6), the form of the power semiconductor module of the arm circuit is not limited to the 1in1 configuration, and even when the upper and lower arms are configured by using the power semiconductor having the 2in1 configuration. The effect of the present invention can be obtained.

Further, in Example 3 (FIG. 6), an example in which the power conversion device of the present invention is applied to a railway vehicle electric system has been described, but it can be applied to a PCS (Power Conditioning System) for photovoltaic power generation, a power conversion device for an electric vehicle, or the like. Needless to say, it is also applicable.

1,1a to 1f: Gate drive circuit, 2,2a to 2f: Parallel connection circuit of power semiconductor module, 3: Control circuit, 4: Capacitor, 10,10a to 10n, 11,11a to 11n: Power semiconductor module, 20a ~ 20n, 21a ~ 21n, 22a, 22b, 22ab, 23ab, 24a, 24b: Impedance circuit, 30: Magnetic core, 90, 90a ~ 90f: Arm circuit, 100: Pantograph, 200: Breaker, 300: Reactor, 400 : Power converter, 500: Electric circuit, L1, L1a to L1n: Inductor, R1, R1a to R1n, R2, R3, R4: Resistor

Claims

With multiple power semiconductor modules
A gate drive circuit that drives and controls the plurality of power semiconductor modules,
A power conversion device including an arm circuit connected between the plurality of power semiconductor modules and the gate drive circuit and composed of a gate wiring circuit for connecting the plurality of power semiconductor modules in parallel to the gate drive circuit. And
The gate wiring circuit has a plurality of impedance circuits corresponding to each of the plurality of power semiconductor modules.
The impedance value of the impedance circuit changes depending on the frequency of the voltage applied to the impedance circuit, and the impedance value is small in the low frequency range and large in the high frequency range. Conversion device.
With multiple power semiconductor modules
A gate drive circuit that drives and controls the plurality of power semiconductor modules,
A power conversion device including an arm circuit connected between the plurality of power semiconductor modules and the gate drive circuit and composed of a gate wiring circuit for connecting the plurality of power semiconductor modules in parallel to the gate drive circuit. And
Each of the plurality of power semiconductor modules has an impedance circuit built in the power semiconductor module together with the power semiconductor transistor and connected in series between the gate terminal of the power semiconductor transistor and the gate drive circuit.
The impedance value of the impedance circuit changes depending on the frequency of the voltage applied to the impedance circuit, and the impedance value is small in the low frequency range and large in the high frequency range. Conversion device.
The power conversion device according to claim 1 or 2.
The impedance circuit includes a parallel circuit in which one end of the first resistor and one end of the inductor are connected to each other, and the other end of the first resistor and the other end of the inductor are connected to each other, and the parallel circuit. A power converter characterized by having a second resistor connected in series to the circuit.
The power conversion device according to claim 3.
A power conversion device characterized in that the resistance value of the first resistor is larger than the resistance value of the second resistor.
The power conversion device according to claim 4.
A power conversion device characterized in that the resistance value of the first resistor is three times or more the resistance value of the second resistor.
The power conversion device according to claim 3.
The inductor is a power conversion device characterized in that a coil wiring is wound around a magnetic core.
The power conversion device according to claim 6.
The magnetic core is a power conversion device having a high impedance magnetic permeability in the high frequency range.
The power conversion device according to claim 6.
A plurality of the impedance circuits are provided.
A power conversion device characterized in that, in two impedance circuits arranged adjacent to each other, the magnetic cores constituting the respective inductors are shared by one magnetic core.
The power conversion device according to claim 1 or 2.
A source sense wiring circuit or an emitter sense wiring circuit which is connected between the plurality of power semiconductor modules and the gate drive circuit and connects the plurality of power semiconductor modules in parallel to the gate drive circuit is provided.
A power conversion device, wherein the impedance circuit is arranged in both the gate wiring circuit and the source sense wiring circuit or the emitter sense wiring circuit, respectively.
Pantograph and
The circuit breaker connected to the pantograph and
The reactor connected to the circuit breaker and
The power converter connected to the reactor and
The electric motor connected to the power conversion device is provided.
The railway vehicle electric system, wherein the power conversion device is the power conversion device according to any one of claims 1 to 9.