WO2018179234A1

WO2018179234A1 - H-bridge converter and power conditioner

Info

Publication number: WO2018179234A1
Application number: PCT/JP2017/013268
Authority: WO
Inventors: 洋一森島; 大輔兒嶋; 涼夫齋藤
Original assignee: 株式会社東芝
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04
Also published as: JPWO2018179234A1

Abstract

The H-bridge converter according to an embodiment is provided with: an HF-leg 13 having a plurality of sub-legs connected in parallel, said sub-legs each including a pair of switching devices connected in series between a DC positive voltage bus line P and a DC negative voltage bus line N; an LF-leg 15 connected in parallel with the HF-leg 13 and having a pair of switching devices connected in series between the DC positive voltage bus line P and the DC negative voltage bus line N; a plurality of AC output terminals H1-H3, L0 electrically connected to between the pairs of switching devices, respectively; and a control circuit CTR controlling the HF-leg 13 on the basis of a multiphase interleaving method in which the conducting phases of the switching devices of the sub-legs are shifted to each other and controlling the LF-leg 15 to switch the output every half cycle of an output fundamental frequency f0.

Description

H-bridge converter and power conditioner

Embodiments of the present invention relate to an H-type bridge converter and a power conditioner using the H-type bridge converter.

Conventionally, in a power conditioner that connects a DC power source such as a battery and a single-phase AC system using, for example, an H-type bridge converter, PWM control is used to obtain an AC current waveform with a low current ripple. It is common. The H-bridge converter has two legs in which a positive arm between a DC positive voltage bus and an AC output terminal and a negative arm between an AC output terminal and a DC negative voltage bus are connected in series. In the control, the two legs are _subjected to PWM control with the switching frequency f _PWM , thereby obtaining an alternating current waveform with a low current ripple having a PWM frequency (= 2 × f _PWM ) equivalent to the equivalent switching frequency. .

However, since the switching device constituting the positive arm or the negative arm cuts off the full load current at the switching frequency, the switching loss is increased and the apparatus may be increased in size.

On the other hand, one of the two legs of the H-type bridge converter is a high-frequency switching leg (hereinafter referred to as HF leg) that performs PWM control of the switching frequency f _PWM , and the other is the output fundamental frequency f ₀ . A method of outputting an alternating voltage has been proposed as a low-frequency switching leg (hereinafter referred to as LF leg) that is switched every half cycle.

In addition to the above proposals, switching devices (specifically MOSFETs) with low switching loss are applied to the HF leg, and switching devices (specifically power transistors) with low conduction loss are applied to the LF leg. By doing so, a method for reducing the loss is known, and a single-phase inverter applying this method has also been proposed.

Furthermore, as a method for reducing current ripple, there is a K-phase interleave method in which a plurality of K sub-converters are connected in parallel to form a single converter in a DC / DC converter as an example. A method has been proposed in which the current ripple is reduced by shifting the pulse by (2π / K) [rad].

In addition to the DC / DC converter, the multiphase interleave method can be applied to a converter in which the input and output may be direct current or alternating current, and there is a proposal that adjusts the current balance. It is made.

Japanese Patent Laid-Open No. 60-2000770 Japanese Patent Laid-Open No. 5-38155 JP 61-142961 A JP2015-220976A

In the H-bridge converter, if an AC current waveform with a smaller current ripple is to be obtained, it is necessary to increase the switching frequency f _PWM of the PWM control, resulting in an increase in switching loss and a decrease in power conversion efficiency. In order to suppress the heat generation and temperature of the switching device, there is a problem that the apparatus must be enlarged.

In addition, if the entire H-bridge converter, that is, both the HF leg and the LF leg, are realized by the interleave method, the number of parts increases, the apparatus becomes large, and the control becomes complicated. There was a problem.

Also, a clear control method is not necessarily proposed for current balance control in the interleave method of the H-type bridge converter, for example, current balance control when operating the power conditioner with output voltage control.

The embodiment of the present invention has been made in view of the above circumstances, and in the case of obtaining an alternating current waveform having the same current ripple, improves the power conversion efficiency, is small, and has a main circuit and a control circuit. An object of the present invention is to provide an H-type bridge converter and a power conditioner using the H-type bridge converter that can be easily realized as hardware.

The H-bridge converter according to the embodiment includes an HF leg in which a plurality of sub-legs including a pair of switching devices connected in series between a DC positive voltage bus and a DC negative voltage bus are connected in parallel; and the DC positive voltage A pair of switching devices are connected in series between the bus and the DC negative voltage bus, and are electrically connected to the LF leg connected in parallel to the HF leg and each of the pair of switching devices. The HF leg is controlled based on a multiphase interleaving method in which conduction phases of the plurality of AC output terminals and the plurality of sub-leg switching devices are shifted, and the output is switched every half cycle of the output fundamental frequency. And a control circuit for controlling the LF leg.

FIG. 1 is a block diagram illustrating a configuration example of an H-type bridge converter and a power conditioner according to the first embodiment. FIG. 2 is a diagram showing an example of a voltage reference to be generated by the H-bridge converter shown in FIG. FIG. 3 is a diagram showing a configuration example of a control circuit that performs voltage control of the H-bridge converter according to the voltage reference shown in FIG. FIG. 4 is a waveform diagram for schematically explaining an example of an operation in which the HF leg of the H-type bridge converter performs PWM control to generate a gate signal in the control circuit of FIG. FIG. 5 is a block diagram illustrating a configuration example of the H-type bridge converter and the power conditioner according to the second embodiment. FIG. 6 is a block diagram illustrating a configuration example of the control circuit of the power conditioner according to the second embodiment. FIG. 7 is a diagram illustrating a configuration example of a PCS current control circuit that performs current control in the control circuit of the power conditioner illustrated in FIG. 6.

Embodiment

Hereinafter, the H-type bridge converter of the embodiment and the power conditioner using the H-type bridge converter will be described in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration example of an H-type bridge converter and a power conditioner according to the first embodiment.
The power conditioner of this embodiment is a power conditioner connected between the DC power source 11 and the single-phase AC system 12, and includes an LF leg 15, an HF leg 13, reactors L1, L2, and L3, and a control. Circuit CTR. The H-type bridge converter of this embodiment includes an LF leg 15, an HF leg 13, and a control circuit CTR.
The power conditioner of the present embodiment is configured to generate a line voltage v ₀ to be supplied to the single-phase AC system 12, and the line voltage v ₀ is obtained from the phase voltage v _h of the HF leg 13 to the phase of the LF leg 15. is a value obtained by subtracting the voltage v _L. The phase voltage v _h and the phase voltage v _L are potentials based on the intermediate voltage point O of the DC power supply 11.

The HF leg 13 includes a plurality of sub-legs connected in parallel and AC output terminals H1 to H3, and includes a pair of switching devices in which each of the plurality of sub-legs is connected in series. In each of the plurality of sub-legs of the HF leg 13, the pair of switching devices and the AC output terminals H1 to H3 are electrically connected. The LF leg 15 includes a pair of switching devices connected in series and an AC output terminal L0, and is connected to the HF leg 13 in parallel. The pair of switching devices of the LF leg 15 and the AC output terminal L0 are electrically connected.

The HF leg 13 is a K-phase interleave circuit that performs PWM control at, for example, the switching frequency f _PWM . In the present embodiment, an example when K = 3 is shown. In the present embodiment, the switching frequency f _PWM is, for example, 13333 Hz (1/3 of 40 kHz). The HF leg 13 includes a first subleg, a second subleg, and a third subleg. The first subleg, the second subleg, and the third subleg are connected in parallel to each other.

The first subleg includes an upper arm and a lower arm connected in series with each other. The upper arm includes a switching device 131 connected between the DC positive voltage bus P and the AC output terminal H1, and an antiparallel diode 131a. The lower arm includes a switching device 132 connected between the AC output terminal H1 and the DC negative voltage bus N, and an antiparallel diode 132a.

The second subleg has an upper arm and a lower arm connected in series with each other. The upper arm includes a switching device 133 connected between the DC positive voltage bus P and the AC output terminal H2, and an antiparallel diode 133a. The lower arm includes a switching device 134 connected between the AC output terminal H2 and the DC negative voltage bus N, and an antiparallel diode 134a.

The third subleg has an upper arm and a lower arm connected in series with each other. The upper arm includes a switching device 135 connected between the DC positive voltage bus P and the AC output terminal H3, and an antiparallel diode 135a. The lower arm includes a switching device 136 connected between the AC output terminal H3 and the DC negative voltage bus N, and an antiparallel diode 136a.

The AC output terminal H1 connected to the first subleg is electrically connected to the AC terminal H0 via the reactor L1. The AC output terminal H2 connected to the second sub-leg is electrically connected to the AC terminal H0 via the reactor L2. The AC output terminal H3 connected to the third subleg is electrically connected to the AC terminal H0 via the reactor L3. AC terminal H <b> 0 is electrically connected to one terminal of single-phase AC system 12.

In the present embodiment, an alternating current output from the AC output terminals H1 and i _1, the alternating current output from the AC output terminal H2 and i _2, an alternating current output from the AC output terminal H3 i ₃ and then, the AC current output from the AC terminal H0 to single phase AC system 12 and the i _0. The alternating current i ₀ is the sum of the alternating currents i ₁ , i ₂ , i ₃ .

LF leg 15 is for operating to switch the output every half cycle of the output fundamental frequency f _0, and a upper arm and the lower arm connected in series with each other. In the present embodiment, the fundamental frequency _{f 0} is, for example, 50 Hz. The upper arm includes a switching device 151 that is connected between the direct current positive voltage bus P and the alternating current output terminal L0 and incorporates an antiparallel diode. The lower arm includes a switching device 152 that is connected between the AC output terminal L0 and the DC negative voltage bus N and incorporates an antiparallel diode. The AC output terminal L0 is electrically connected to one terminal of the single-phase AC system 12.

In the example of FIG. 1, the reactor L1, the reactor L2, and the reactor L3 are described as separate circuit elements, but the three reactors are magnetically coupled to increase the operating frequency as one reactor having three windings. You may comprise as follows. In other words, at least one reactor is provided between the AC output terminals H1 to H3 and the AC terminal H0, and the AC output terminal H1 is electrically connected to the AC terminal H0 via the winding of one reactor, and the AC output Terminal H2 is electrically connected to AC terminal H0 via the other winding of one reactor, and AC output terminal H3 is electrically connected to AC terminal H0 via the other winding of one reactor. It is good also as a structure. By reducing the number of components, the inverter can be reduced in size.

As a control method for the H-bridge converter of the power conditioner, there are a method of controlling a single-phase AC voltage as an output voltage to a sine wave (voltage control method), and an AC current flowing through a single-phase AC system as an output current And a method for controlling the current to a sine wave (current control method).

Hereinafter, the voltage control method of the H-bridge converter will be described with reference to the drawings. Although only the voltage control method will be described in the present embodiment, the present invention is not limited to this, and it is not excluded to control the H-bridge converter of the present embodiment by the current control method. .

FIG. 2 is a diagram showing an example of a voltage reference to be generated by the H-bridge converter shown in FIG.
Here, the single-phase AC voltage reference v ₀ ^* , the voltage reference v _H ^* of the HF leg 13, and the voltage reference v _L ^* of the LF leg 15 are shown.

The voltage reference v _H ^* to be generated in the HF leg 13 is a voltage obtained by viewing the AC output terminals H1, H2, and H3 of the HF leg 13 with reference to the intermediate voltage point O of the DC power supply 11, and the HF leg phase voltage and It is called voltage.

The voltage reference v _L ^* to be generated in the LF leg 15 indicates a voltage when the AC output terminal L0 of the LF leg 15 is viewed with reference to the intermediate voltage point O of the DC power supply 11, and is a voltage called an LF leg phase voltage. .

The single-phase AC voltage reference v ₀ ^* is the difference between the voltage reference v _H ^* to be generated in the HF leg 13 and the voltage reference v _L ^* to be generated in the LF leg 15 (v ₀ ^* = v _H ^* −v _L ^* ) And is a voltage called a line voltage reference generated by the HF leg 13 and the LF leg 15.

Therefore, in the voltage control method, the HF leg 13 generates the actual voltage v _H corresponding to the voltage reference v _H ^* by PWM control, and the LF leg 15 corresponds to the one-pulse actual voltage corresponding to the rectangular wave voltage reference v _L ^*. v _L and thus the may be generated.

FIG. 3 is a diagram showing a configuration example of a control circuit that performs voltage control of the H-bridge converter according to the voltage reference shown in FIG.
The control circuit CTR includes a line voltage reference generation circuit 21, an HF leg phase voltage reference generation circuit 22, an LF leg phase voltage reference generation circuit 23, a 120 ° phase difference triangular wave carrier wave generation circuit 24, and a PWM waveform generation circuit 251. 252, 253,

negation circuits

261, 262, 263, phase average current

difference detection circuits

271, 272,

current detectors

281, 282, 283 (shown in FIG. 1),

subtracters

291, 292,

current Control circuits

301 and 302,

adders

311 and 312, and a negation circuit 32 are provided.

The line voltage reference generation circuit 21 receives an output voltage command value V ₀ ^* for commanding the magnitude of the AC voltage from the outside, and a single-phase AC frequency (output fundamental wave frequency) f ₀ (= ω ₀ / 2π). A sine wave line voltage reference v ₀ ^* is generated.

The HF leg phase voltage reference generation circuit 22 receives the line voltage reference v ₀ ^* from the line voltage reference generation circuit 21 and generates the HF leg phase voltage reference v _H ^* .
The LF leg phase voltage reference generation circuit 23 receives the line voltage reference v ₀ ^* from the line voltage reference generation circuit 21 and generates the LF leg phase voltage reference v _L ^* .

The LF leg phase voltage reference v _L ^* is output as the positive voltage bus potential (+ E / 2) or the negative voltage bus potential (-E / 2) of the DC voltage E. If the DC voltage E is determined, the actual voltage v _L is determined. Therefore, in the LF leg phase voltage reference generation circuit 23, the amplitude of the LF leg phase voltage reference v _L ^* is a waveform that is originally determined by the DC voltage E. On the other hand, the HF leg phase voltage reference generation circuit 22 calculates a waveform that changes the amplitude of the HF leg phase voltage reference v _H ^* in accordance with the change in the amplitude of the line voltage reference v ₀ ^* .

Here, if there is no unbalance in the average AC currents i _1AVE , i _2AVE , i _3AVE in a predetermined period of the first sub-leg, the second sub-leg, and the third sub-leg constituting the three-phase interleave circuit, the current balance is obtained. Therefore, the phase voltage reference v _H1 ^* in the first sub-leg of the HF leg 13 is equal to the HF leg phase voltage reference v _H ^* .

In this case, the PWM waveform generation circuit 251 receives the phase voltage reference v _H1 ^* in the first subleg as a modulation wave, and receives the carrier voltage v _T1 in the first subleg from the 120 ° phase difference triangular wave carrier generation circuit 24. The gate signals G _Q11 and G _Q12 to be _supplied to the upper arm switching device 131 and the lower arm switching device 132 are generated.

Specifically, the output signal of the PWM waveform generation circuit 251 is a gate signal _GQ11 to be given to the switching device 131. The output signal of the PWM waveform generation circuit 251 becomes a gate signal _GQ12 to be _supplied to the switching device 132 via the negation circuit 261. Therefore, the gate signal _GQ11 and the gate signal _GQ12 have waveforms inverted from each other.

FIG. 4 is a waveform diagram for schematically explaining an example of an operation in which the HF leg of the H-type bridge converter performs PWM control to generate a gate signal in the control circuit of FIG.
The 120 ° phase difference triangular wave carrier wave generation circuit 24 generates a carrier voltage v _T1 in the first sub-leg, a carrier voltage v _T2 in the second sub-leg, and a carrier voltage v _T3 in the third sub-leg. As shown in FIG. 4, the carrier is a continuous triangular wave PWM control frequency _{f PWM.} The three triangular waves (carrier voltages) v _T1 , v _T2 , and v _T3 are at the level of the PWM control frequency f _PWM and each have a phase of 120 ° (= 2π / K [rad]) (K = 3 in this embodiment). It's off. In the upper part of FIG. 4, the bold line indicates the carrier voltage v _T1 in the first sub-leg, the thin line indicates the carrier voltage v _T2 in the second sub-leg, and the broken line indicates the carrier voltage v _T3 in the third sub-leg.

In the present embodiment, since the HF leg includes three sub-legs, the triangular waves (carrier wave voltages) v _T1 , v _T2 , and v _T3 have a phase difference of 120 ° from each other, but the triangular wave (carrier wave voltage) And the phase difference thereof are appropriately changed according to the number of sub-legs.

Further, FIG. 4 shows the phase voltage reference v _H1 ^* and the carrier voltage v _T1 , the gate signal G _Q11 applied to the upper arm switching device 131 of the first sub-leg of the HF leg, and the gate signal applied to the lower arm switching device 132. An example with _GQ12 is shown.

The PWM waveform generation circuit 251 compares the phase voltage reference v _H1 ^* and the carrier voltage v _T1 in the first subleg, generates a gate signal G _Q11 based on the comparison result, and outputs it. That is, the gate signal _{GQ11 supplied} to the switching device 131 is turned on during the phase voltage reference v _H1 ^* > carrier voltage v _T1 and turned off during the phase voltage reference v _H1 ^* <carrier voltage v _T1 . The gate signal _GQ21 given to the switching device 132 is a signal obtained by inverting the gate signal _GQ11 , and is turned on in the period of the phase voltage reference v _H1 ^* <carrier voltage v _T1 and the phase voltage reference v _H1 ^* > carrier. It turned off for a period of voltage _{v T1.}

The PWM waveform generation circuit 252 receives the phase voltage reference v _H2 ^* of the second sub-leg as a modulation wave, and has a phase of 120 ° with respect to the carrier voltage v _T1 in the first sub-leg from the 120 ° phase difference triangular wave carrier generation circuit 24. The second sub-leg carrier voltage v _T2 is received.

The PWM waveform generation circuit 252 and the NOT circuit 262 generates and outputs the gate signal _{G Q22} when applied to the gate signal _{G Q12} and the switching device 134 of the lower arm to be given to switching device 133 of the upper arm of second Saburegu.

The PWM waveform generation circuit 253 receives the phase voltage reference v _H3 ^* of the third sub-leg as a modulation wave, and is phased by 120 ° with respect to the carrier voltage v _T2 in the second sub-leg from the 120 ° phase difference triangular wave carrier generation circuit 24. The carrier voltage v _T3 of the third sub-leg delayed is received.

The PWM waveform generation circuit 253 and the negation circuit 263 generate and output a gate signal G _Q13 to be supplied to the switching device 135 of the upper arm of the third subleg and a gate signal G _Q23 to be supplied to the switching device 136 of the lower arm.

By performing the PWM control as described above, the instantaneous alternating currents i ₁ , i ₂ , i ₃ of the first sub-leg, the second sub-leg, and the third sub-leg are expressed as current waveforms having ripples that increase / decrease at the frequency f _PWM. Become. However, the pulse of the gate signal applied to the switching devices of the first sub-leg, the second sub-leg, and the third sub-leg has a conduction phase of 120 ° because the carrier voltages v _T1 , v _T2 , and v _T3 are shifted by 120 °. It's off. For this reason, the instantaneous alternating current i ₀ obtained by adding the instantaneous alternating currents i ₁ , i ₂ , and i ₃ becomes a current waveform having a ripple that increases and decreases at a PWM frequency (3 × f _PWM ) that is three times the frequency. The switching frequency can be tripled.

Up to this point, when there is no imbalance in the average AC currents i _1AVE , i _2AVE , i _3AVE for a predetermined period output from the first sub-leg, the second sub-leg, and the third sub-leg, the first sub-leg, the second sub-leg, An example of the operation for generating the gate signal of the third subleg has been described.

However, for example, if there is non-uniformity in the hardware of each sub-leg circuit actually manufactured, this causes an _{imbalance in} the average alternating currents i _1AVE , i _2AVE , i _3AVE . Therefore, in this embodiment, the _inverter is _reduced in _size by balancing the average alternating currents i _1AVE , i _2AVE , and i _3AVE by control.

The phase average current

difference detection circuits

271 and 272 receive the instantaneous alternating currents i ₁ , i ₂ , and i ₃ , calculate the difference between the output alternating current of each phase and the three-phase current average value, and output it.
That is, the phase average current difference detection circuit 271 receives the instantaneous alternating currents i ₁ , i ₂ , i ₃ detected by the

current detectors

281, 282, and 283, and receives the average alternating current i _1AVE of the first subleg, mean and alternating current _{i 2AVE} second Saburegu, mean and alternating current _{i 3AVE} third Saburegu total _i 0AVE average alternating current _{_{_{(= i 1AVE + i 2AVE +}}} i 3AVE) and with an average alternating current of the first Saburegu A difference Δi _1AVE = i _1AVE − (1/3) i _0AVE between i _1AVE and the three-phase current average value (average value of the total average AC current i _0AVE ) is calculated and output.

The average current difference detection circuit 272 receives the instantaneous alternating currents i ₁ , i ₂ , i ₃ detected by the

current detectors

281, 282, 283, and receives the average alternating current i _1AVE of the first _subleg and the second subleg. I mean and alternating current _{i 2AVE} of mean and alternating current _{i 3AVE} third Saburegu, by using the sum _i 0AVE average alternating current _{_{_{(= i 1AVE + i 2AVE +}}} i 3AVE), the average AC current _{i 2AVE} second Saburegu The difference Δi _2AVE = i _2AVE- (1/3) i _0AVE from the three-phase current average value (average value of the total average AC current i _0AVE ) is calculated and output.

The subtractor 291 subtracts the reference value from the current difference Δi _1AVE output from the average current difference detection circuit 271 and outputs the result. In this embodiment, the reference value is zero.
The subtractor 292 subtracts the reference value from the current difference Δi _2AVE output from the average current difference detection circuit 272 and outputs the result. In this embodiment, the reference value is zero.

The current control circuit 301 is a control circuit including at least an integration element, and amplifies the value output from the subtractor 291 to generate and output the phase voltage reference correction signal v _Had1 ^* in the first subleg.

The current control circuit 302 is a control circuit including at least an integration element, and amplifies the value output from the subtractor 292 to generate and output the phase voltage reference correction signal v _Had2 ^* in the second subleg.
In the present embodiment, the

current control circuits

301 and 302 perform proportional integral (PI) control.

The adder 311 adds the phase voltage reference correction signal v _Had1 ^* and the HF leg phase voltage reference v _H ^*, and outputs the result as the phase voltage reference v _H1 ^* of the first subleg.
The adder 312 adds the phase voltage reference correction signal v _Had2 ^* and the HF leg phase voltage reference v _H ^*, and outputs the result as the phase voltage reference v _H2 ^* of the second sub-leg.

In addition, since the HF leg 13 of this embodiment is a three-phase interleave system, the current balance of the third phase can be obtained by controlling the current balance of two of the three phases. Therefore, for the third sub-leg, it is not necessary to correct the HF leg phase voltage reference v _H ^* by the correction signal in the same way as the first leg and the second leg, and the phase voltage reference in the third sub-leg is the HF leg. Use phase voltage reference v _H ^* .

Next, an example of the control operation of the LF leg 15 will be described.
The LF leg phase voltage reference generation circuit 23 receives the line voltage reference v ₀ ^* generated by the line voltage reference generation circuit 21 and generates an LF leg phase voltage reference v _L ^* . For example, as shown in FIG. 2, the LF leg voltage reference v _L ^* is output by switching the potentials of the DC positive voltage bus and the DC negative voltage bus according to the frequency f ₀ of the single-phase AC system. That is, the LF leg phase voltage reference generation circuit 23 only _needs to generate one pulse of the actual voltage v _L , and the LF leg voltage reference v _L ^* is a rectangular wave signal. The LF leg voltage reference v _L ^* output from the LF leg phase voltage reference generation circuit 23 is a gate signal G _Q3 provided to the switching device 153.

The negation circuit 32 inverts the LF leg voltage reference v _L ^* and outputs a gate signal G _Q4 to be _supplied to the switching device 152. That is, when the LF leg voltage reference v _L ^* is −E / 2, the switching device 152 is turned on.

In an ordinary H-bridge converter, in an ordinary PWM control in which two legs are switched at the same PWM frequency, the equivalent switching frequency of the alternating current waveform is doubled. On the other hand, when the above-described H-type bridge converter of the present embodiment and its control method are employed, the equivalent switching frequency is almost tripled because the switching frequency of the HF leg is dominant. Therefore, in order to obtain the same equivalent switching frequency, it is possible to operate at a frequency that is 2/3 of the PWM frequency used for normal PWM control, and switching loss can be reduced.

Further, by adopting the above-described H-type bridge converter of the present embodiment and its control method, if the LF leg 15 is switched at the same PWM frequency as the switching frequency of normal PWM control, an equivalent switching in an AC current waveform is performed. The frequency is 1.5 times, and the ripple can be further reduced, leading to improvement of the waveform near the zero cross of the AC waveform, especially total harmonic distortion (THD) or electromagnetic interference (EMI). Can be reduced.

Next, the types of switching devices that can be used in the above-described H-type bridge converter will be described.

The HF leg 13 includes three-phase sub-legs, and an IGBT (Insulated Gate-Bipolar-Transistor) having a current capacity of 1/3 is used as the switching

devices

131, 132, 133, 134, 135, 136 constituting the sub-legs. Can do.

As a switching device of the HF leg 13, it is known to use a MOSFET as a device having a small switching loss. However, in this embodiment, the interleaving method is applied to the HF leg 13, so that the ratio of switching loss is relatively reduced by reducing the switching frequency to 1/3 of the necessary frequency, and the characteristic of low conduction loss is achieved. In addition, it is possible to use the IGBT that is also included. Note that the six IGBTs used in the HF leg 13 may be configured as one package.

The LF leg 15 has one leg including switching

devices

151 and 152 connected in series. The switching

devices

151 and 152 are MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistors) or Super- Junction MOSFETs can be used.

As a switching device of the LF leg 15, not only the switching loss is low, but depending on the selection of the capacitance of the device, a large reduction in conduction loss can be expected by using a MOSFET, in particular, a super-junction MOSFET.

As described above, by using an IGBT for the HF leg 13 and a MOSFET or a super-junction MOSFET for the LF leg 15, it is possible to provide an H-bridge converter that reduces switching loss and reduces conduction loss. It becomes possible.

As described above, according to the present embodiment, when an alternating current waveform having the same current ripple is obtained, the power conversion efficiency is improved, the size is small, and the main circuit and the control circuit can be easily realized as hardware. It is possible to provide an H-type bridge converter and a power conditioner using the H-type bridge converter.

FIG. 5 is a block diagram illustrating a configuration example of an H-type bridge converter according to the second embodiment and a power conditioner using the H-type bridge converter.
In the present embodiment, a power conditioner including the H-bridge converter of the first embodiment will be described below with reference to the drawings. In the following description, the same components as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

The power conditioner of the present embodiment is configured such that the power conditioner of the first embodiment described above is connected to the single-phase AC system 12 so that single-phase AC system interconnection operation is possible. The power conditioner of the present embodiment switches the connection from the single-phase AC system 12 to the AC load 41 when a power failure occurs in the single-phase AC system 12 and supplies the AC load 41 with power. The power supply operation (generally called self-sustained operation) is configured to be possible.

The first subleg is electrically connected to the AC terminal H0 via the reactor L1, the second subleg is electrically connected to the AC terminal H0 via the reactor L2, and the third subleg is connected to the AC terminal H0 via the reactor L3. And is electrically connected. In other words, the first subleg, the second subleg, and the third subleg are connected in parallel to the AC terminal H0.

When performing the single-phase AC system interconnection operation, the AC terminal H0 is connected to one terminal of the single-phase AC system 12 on the a side of the switching circuit 421. At this time, when a power failure or the like occurs in the single-phase AC system 12, the switching circuit 421 is switched from the a side to the b side, and the AC terminal H0 is connected to one terminal of the AC load 41.

FIG. 6 is a block diagram illustrating a configuration example of the control circuit of the power conditioner according to the second embodiment.
In the present embodiment, for example, the control circuit CTR switches the output current control so as to perform the output voltage control during the single-phase AC grid connection operation and performs the output voltage control during the AC load power supply operation, thereby controlling the H-type bridge converter.

The control circuit CTR includes a single-phase AC grid connection operation command circuit 43, a PCS current control circuit 44, a switching circuit a side input command circuit 45, an AC load power supply operation command circuit 46, and a PCS voltage control circuit 47. , A switching circuit b-side input command circuit 48,

switches

431 and 432, and a switching circuit 421 (shown in FIG. 5) and 422.

The single-phase AC system interconnection operation command circuit 43 determines, for example, whether or not the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside. When the AC system 12 is normal, the single-phase AC system interconnection operation signal _SGC is output.

The AC load power supply operation command circuit 46 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside, and When the AC system 12 is normal, the AC load power supply operation command circuit 46 does not output the AC load power supply operation signal _SLC .

The switch 431 is turned on by a single-phase AC grid interconnection operation signal _SGC .
PCS current control circuit 44, the single-phase AC system interconnection operation command circuit 43 receives single-phase AC system interconnection operation signal S _GC to perform output current control.

That is, the PCS current control circuit 44 gives an output current command value I ₀ ^* for commanding the magnitude of the AC current from the outside via the switch 431 input by the single-phase AC grid connection operation signal S _GC . It is done. Further, the PCS current control circuit 44 includes the voltage v _{0 of} the single-phase AC system 12 detected by the voltage detector 53, the first subleg, the second subleg, and the third subleg detected by the

current detectors

281, 282, and 283. Gate currents G _Q11 , G _Q12 , G _Q13 , G _Q21 , G _Q22 , G _Q23 , G _Q13 , G _Q3 , G _{Q4 of the} current alternating currents i ₁ , i ₂ , i _3. Is generated and output. These gate signals G _Q11 , G _Q12 , G _Q13 , G _Q21 , G _Q22 , G _Q23 , G _Q13 , G _Q3 , G _Q4 are connected to the

switching devices

131, 133, 135, via the a side of the switching circuit 422. 132, 134, 136, 151, 152.
The operation in which the PCS current control circuit 44 performs output current control will be described in detail later with reference to FIG.

Switching circuit a side closing command circuit 45, the single-phase AC system interconnection operation command circuit 43 receives a single-phase AC system interconnection operation signal S _GC, the switching circuit of the switching circuit 421 and the control circuit of the main circuit 422 In response to this, a command is output to switch to the a side. By switching circuit 422 is switched, the gate signal _G Q11 output from the PCS current control circuit _{_{_{_{44, G Q12, G Q13,}}}} G Q21, G Q22, G Q23, G Q13, G Q3, G Q4 is, the control circuit CTR Are output to the

switching devices

31, 133, 135, 132, 134, 136, 151, and 152.

On the other hand, the single-phase AC system interconnection operation command circuit 43 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside. When an abnormality such as a power failure occurs in the single-phase AC system 12, the single-phase AC system interconnection operation command circuit 43 does not output the single-phase AC system interconnection operation signal _SGC .

The AC load power supply operation command circuit 46 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside, and When an abnormality such as a power failure occurs in the AC system 12 (when it is not normal), the AC load power supply operation command circuit 46 outputs an AC load power supply operation signal _SLC .

The switch 432 is turned on by an AC load power supply operation signal _SLC .
PCS voltage control circuit 47 receives the AC load power supply operation signals S _LC from the AC load power supply operation command circuit 46 performs output voltage control.

That is, the PCS voltage control circuit 47 is given an output voltage command value V ₀ ^* for commanding the magnitude of the AC voltage from the outside via the switch 432 input by the AC load power supply operation signal S _LC . Further, the PCS voltage control circuit 47 receives the AC currents i ₁ , i ₂ , and i ₃ of the first subleg, the second subleg, and the third subleg detected by the

current detectors

281, 282, and 283, and performs voltage control. the gate signal _G Q11 of the _{_{_{_{results, G Q12, G Q13, G}}}} Q21, G Q22, G Q23, G Q13, G Q3, to generate a _{G Q4} output. These gate signals G _Q11 , G _Q12 , G _Q13 , G _Q21 , G _Q22 , G _Q23 , G _Q13 , G _Q3 , G _Q4 are connected to the

switching devices

131, 133, 135, via the b side of the switching circuit 422. 132, 134, 136, 151, 152. The operation of the PCS voltage control circuit 47 is the same as that of the control circuit CTR of the first embodiment described above, and thus the description thereof is omitted in this embodiment.

Switching circuit b side closing command circuit 48 receives the AC load power supply operation signals S _LC from the AC load power supply operation command circuit 46 for the switching circuit 422 of the switching circuit 421 and the control circuit of the main circuit, b-side Command to switch to. By switching circuit 422 is switched, PCS voltage control circuit 47 a gate signal _G Q11 output _{_{_{_{from, G Q12, G Q13, G}}}} Q21, G Q22, G Q23, G Q13, G Q3, G Q4 is, the control circuit CTR Are output to the

switching devices

31, 133, 135, 132, 134, 136, 151, and 152.

FIG. 7 is a diagram illustrating a configuration example of a PCS current control circuit that performs current control in the control circuit of the power conditioner illustrated in FIG. 6.
The PCS current control circuit 44 includes a 1/3 multiplier 51, a multiplier 52, a line voltage peak value detection circuit 54, a divider 55,

subtracters

561, 562, and 563, and

current control circuits

571 and 572. 573, positive / negative polarity discrimination circuit 58, 120 ° phase difference triangular wave carrier wave generation circuit 24, PWM

waveform generation circuits

251, 252, 253, and

negation circuits

261, 262, 263.

The 1/3 multiplier 51 receives an output current command value I ₀ ^* for commanding the magnitude of the AC current from the outside, and outputs the AC current magnitude command value I ₀ ^* / 3.
The multiplier 52 receives and multiplies the AC current magnitude command value I ₀ ^* / 3 and the output signal v ₀ / V _{0 of the} divider 55 (power factor 1, sine wave of magnitude 1). To obtain and output current references i ₁ ^* , i ₂ ^* , i ₃ ^* of each sub-leg of the three-phase interleave.

The line voltage peak value detection circuit 54 receives the voltage v ₀ of the single-phase AC system 12 detected by the voltage detector 53 shown in FIG. 5, obtains the AC voltage peak value V ₀ from the voltage v ₀ and outputs it.

Divider 55 receives the voltages _{v 0} and AC voltage peak value _{V 0,} and outputs the operation signal _v 0 / _{V 0} to the multiplier 52 and the positive and negative determination circuit 58. That is, the signal v ₀ / V ₀ is a sine wave having a power factor of 1 and a magnitude of 1 input to the multiplier 52.

The subtractor 561 subtracts the actual current i ₁ detected by the current detector 281 from the current reference i ₁ ^* and outputs the result to the current control circuit 571.
The subtractor 562 subtracts the actual current i ₂ detected by the current detector 282 from the current reference i ₂ ^* and outputs the result to the current control circuit 572.
The subtractor 563 subtracts the actual current i ₃ detected by the current detector 283 from the current reference i ₃ ^* and outputs the result to the current control circuit 573.

The current control circuit 571 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 561 becomes zero, and generates and outputs the phase voltage reference v _H1 ^* in the first subleg. In the present embodiment, the current control circuit 571 performs proportional-integral control.

The current control circuit 572 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 562 becomes zero, and generates and outputs the phase voltage reference v _H2 ^* in the second subleg. In the present embodiment, the current control circuit 572 performs proportional-integral control.

The current control circuit 573 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 563 becomes zero, and generates and outputs the phase voltage reference v _H3 ^* in the third subleg. In the present embodiment, the current control circuit 573 performs proportional-integral control.

The 120 ° phase difference triangular wave carrier wave generation circuit 24, the PWM

waveform generation circuits

251, 252, and 253, and the

negation circuits

261, 262, and 263 are the same as those described in the first embodiment.

That is, the 120 ° phase difference triangular wave carrier wave generation circuit 24 generates the carrier voltage v _T1 in the first sub-leg, the carrier voltage v _T2 in the second sub-leg, and the carrier voltage v _T3 in the third sub-leg. For example, as shown in FIG. 4, the carrier is a continuous triangular wave PWM control frequency _{f PWM.} The three triangular waves (carrier voltages) v _T1 , v _T2 , and v _T3 are at the level of the PWM control frequency f _PWM and each have a phase of 120 ° (= 2π / K [rad]) (K = 3 in this embodiment). It's off.

The PWM waveform generation circuit 251 receives the phase voltage reference v _H1 ^* as a modulation wave, and outputs a gate signal G _Q11 to be _supplied to the switching device 131 to the switching device 131 and the negation circuit 261. NOT circuit 261 inverts the gate signal _{G Q11,} and generates and outputs a gate signal _{G Q21} to be supplied to the switching device 132.

The PWM waveform generation circuit 252 receives the phase voltage reference v _H2 ^* as a modulation wave, and outputs a gate signal G _Q12 to be _supplied to the switching device 133 to the switching device 133 and the negative circuit 262. NOT circuit 262 inverts the gate signal _{G Q12,} and generates and outputs a gate signal _{G Q22} to be supplied to the switching device 134.

The PWM waveform generation circuit 253 receives the phase voltage reference v _H3 ^* as a modulation wave, and outputs a gate signal G _Q13 to be _supplied to the switching device 135 to the switching device 135 and the negation circuit 263. The negation circuit 263 inverts the gate signal G _Q13 to generate and output a gate signal G _Q23 to be _supplied to the switching device 136.

On the other hand, since the phase of the output signal v ₀ / V ₀ of the divider 55 is an AC voltage phase, it can be used to control the LF leg 15 as in the case of output voltage control. In other words, the potential of the DC positive voltage bus and the DC negative voltage bus may be switched and output in accordance with the frequency f ₀ of the single-phase AC system.

For example, LF leg-phase voltage reference generation circuit of the control circuit CTR shown in FIG. 3 23 is for generating and outputting a LF leg-phase voltage reference v _L ^* and receive line voltage reference v ₀ ^*. Similarly, the positive / negative polarity discrimination circuit 58 receives the signal v ₀ / V ₀ , generates a one-pulse rectangular wave signal (gate signal G _Q4 ), and outputs it to the switching device 152 and the negative circuit 32. To do.

NOT circuit 32 receives the gate signal G _Q4 output from a polarity discriminating circuit 58, and outputs a gate signal G _Q3 obtained by inverting the value. When (v ₀ / V ₀ )> 0, the switching device 152 is turned on by the gate signal G _Q4 and the switching device 151 is turned off by the gate signal G _Q3 . When (v ₀ / V ₀ ) <0, the switching device 152 is turned off by the gate signal G _Q4 and the switching device 151 is turned on by the gate signal G _Q3 .
In this embodiment, the types of switching devices that can be used for the H-type bridge converter are the same as those in the first embodiment.

As described above, according to the present embodiment, when an alternating current waveform having the same current ripple is obtained, the power conversion efficiency is improved, the size is small, and the main circuit and the control circuit can be easily realized as hardware. An H-type bridge converter and a power conditioner can be provided.

Furthermore, according to the present embodiment, it is possible to switch between the single-phase AC grid interconnection operation and the AC load power supply operation, and it is possible to provide a highly versatile H-bridge converter and power conditioner.

Although one embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

Claims

An HF leg in which a plurality of sub-legs including a pair of switching devices connected in series between a DC positive voltage bus and a DC negative voltage bus are connected in parallel;
A pair of switching devices are connected in series between the DC positive voltage bus and the DC negative voltage bus, and an LF leg connected in parallel with the HF leg;
A plurality of AC output terminals electrically connected to each of the pair of switching devices;
A control circuit for controlling the LF leg to control the HF leg based on a multi-phase interleaving method in which conduction phases of the switching devices of the plurality of sub-legs are shifted, and to switch the output every half cycle of the output fundamental frequency; An H-type bridge converter comprising:
The H-bridge converter according to claim 1, wherein the switching device of the HF leg is an IGBT, and the switching device of the LF leg is a MOSFET or a super-junction MOSFET.
The H-type bridge converter according to claim 1 or 2,
One AC terminal electrically connected to a plurality of AC output terminals of the HF leg;
At least one reactor provided between a plurality of AC output terminals of the HF leg and the AC terminal;
A switching circuit that switches the electrical connection of the AC terminal to either a terminal connected to a load or a terminal connected to a single-phase AC system,
The control circuit includes the HF leg and the HF leg so that the output current of the H-type bridge converter becomes a sine wave when the AC terminal and the single-phase AC system are electrically connected by the switching circuit. When the LF leg is controlled and the AC terminal and the load are electrically connected by the switching circuit, the HF leg and the HF leg are set so that the output voltage of the H-type bridge converter is a sine wave. A power conditioner that controls the LF leg.