WO2018166650A1

WO2018166650A1 - Method for operating a first converter and a second converter

Info

Publication number: WO2018166650A1
Application number: PCT/EP2018/000090
Authority: WO
Inventors: Ricardo RICHTER; Stefan Zeh; Martin Weinmann
Original assignee: Diehl Ako Stiftung & Co. Kg
Priority date: 2017-03-14
Filing date: 2018-03-06
Publication date: 2018-09-20
Also published as: DE102017009836A1; EP3596818A1

Abstract

The invention relates to a method (34) for operating a first converter (4) and a second converter (6), each of which has a bridge circuit (16) having switchable semiconductor switches (18). The switchable semiconductor switches (18) of the first converter (4) are triggered at first switching times (42), and the switchable semiconductor switches (18) of the second converter (6) are triggered at second switching times (44). The first switching times (42) and the second switching times (44) are created in such a way that repeatedly occurring time frames (56) containing neither first switching times (42) nor second switching times (44) are formed.

Description

Diehl AKO Foundation & Co. KG, 88239 Wangen

Method for operating a first converter and a

second inverter

The invention relates to a method for operating a first converter and a second converter, each having a bridge circuit with switchable semiconductor switches. The invention further relates to a device with a first converter and with a second converter.

From EP 1 983 641 A2 it is known that a central control unit controls several converter bridges. The inverter bridges are synchronized and drive the same load (e.g., motor). Synchronization is accomplished by introducing chokes into the circuit. The aim of the synchronization is to reduce ring currents through the parallel-connected inverter bridges.

The synchronization of inverter bridges for driving the same load is also known from EP 2 270 970 A1. To reduce ring currents through the inverters, the pulse widths and switching times of all half bridges are synchronized on the same phase. The method assumes that the same load is operated and thus the respective pulse widths are the same.

US 7,584,009 B2 describes the parallel operation of single-phase converters for audio applications, where the audio inverters are controlled by various digital controllers to increase the audio quality. Synchronization is achieved by supplying all digital controllers with the same CPU clock line. In addition, a control line is used, on which the master transmits synchronization pulses. However, this synchronization pulse only has the purpose that the slaves can check their synchronicity and can switch off if necessary. The problem with this design is that the inverters interfere with each other. From EP 1 995 863 A2 converters are known, which are connected in parallel to a three-phase network. In order to keep the harmonic voltage distortions in the connected three-phase network low, the PWM periods are synchronized and operated out of phase. Synchronization occurs when a master sends out pulses and the slaves adjust their PWM carrier.

DE 10 2005 052 702 B4 describes a hardware circuit which can delay PWM signals. The invention is based on the object, a particularly suitable method for operating a first inverter and a second converter, each having a bridge circuit with switchable semiconductor switches, and a particularly suitable device with a driven by a first inverter first load and one by means of a second Specify inverter driven second load, advantageously a disturbance of the inverter is reduced and advantageously avoided.

With regard to the method, this object is achieved by the features of claim 1 and in terms of the device by the features of claim 9 according to the invention. Advantageous developments and refinements are the subject of the respective subclaims.

The method is used to operate a first converter and a second converter. In this case, the first converter in particular serves the energization of a first load and the second converter of the energization of a second load. The first and the second load are different and, for example, each an electric motor, in particular a brushless electric motor, such as a brushless DC motor (BLDC). Suitably, the electric motors are synchronous motors. Alternatively, at least one of the electric motors is an asynchronous motor. Each inverter has a number of switchable semiconductors, which are each connected together to form a bridge circuit. The

Bridge circuits are each arranged in particular between an upper and a lower potential, wherein the two potentials are electrical potentials between which, for example, an electrical voltage between 100 volts and 2,000 volts, between 200 volts and 800 volts and for example equal to 500 volts is applied. Each bridge circuit preferably comprises a number of bridge branches, which are connected in parallel between the two potentials. For example, each of the Bridge branches in each case two of the switchable semiconductor switches, which are suitably connected in series. In summary, each bridge circuit expediently has three half-bridges (bridge branches), which each comprise two of the switchable semiconductor switches. The switchable semiconductor switches are expediently power semiconductor switches, which are in particular provided and configured to switch an electrical voltage greater than 200 volts, 300 volts, 400 volts, 500 volts or 1,000 volts. Suitably, the semiconductor switches are provided and configured to carry an electrical current greater than 2 amperes, 5 amps or 10 amps. The switchable semiconductor switches are, for example, field-effect transistors, in particular MOSFETs, JFETs, GTOs or IGBTs. For example, a diode, in particular a free-wheeling diode, is connected in parallel with each of the switchable semiconductor switches.

Preferably, each inverter has six such switchable semiconductor switches, and the switchable semiconductor switches are each connected to a B6 bridge, which thus has three bridge arms. Conveniently, the inverters are designed as inverters, by means of which a three-phase alternating current is expediently generated during operation. The first converter and the second converter expediently each have a control, by means of which the respective switchable semiconductor switches are controlled. For this purpose, the controls are expediently signal-technically and / or electrically coupled to the respective switchable semiconductor switches. Suitably, the method is for operating a device having the two inverters. The device itself is for example a heat pump.

The method provides that the switchable semiconductor switches of the first inverter are driven to first switching times. Each of the switchable semiconductor switches of the first converter is assigned at least a portion of the first switching times. For each of the first switching times, the switching state of the respectively associated switchable semiconductor switch is changed and this thus offset from an electrically conductive to an electrically non-conductive or from an electrically non-conductive to an electrically conductive state. Likewise, the switchable semiconductor switches of the second inverter are driven to second switching times. In turn, each of the switchable semiconductor switches is assigned in each case at least a number of the second switching times. At each second switching time of the switching state of the respective associated switchable semiconductor switch is changed, and thus this of an electrically conductive in an electrically non-conductive or by an electrically non-conductive in an electrically conductive state. The first and second switching times are determined in particular based on an operating point, wherein the operating point for the first inverter, for example, is different from the operating point of the second inverter, so that the first switching times differ from the second switching points. The first switching times and the second switching times are determined such that repeatedly occurring time windows are formed within which neither first switching times nor second switching times are present. The time windows are in particular time corridors. Suitably, the time windows occur periodically repeatedly. Appropriately, the two inverters are driven in such a way that overlap the time windows occurring at least partially in time. For example, the method is used for the operation of other converters, wherein here, the switching points of the other inverter are set so that they are outside the time window.

Each switching operation of the switchable semiconductor switches generates electromagnetic waves, which couple to any lines, any electronics and / or control of the respective inverter and the other inverter and can lead to significant disturbances there. Switching disturbances are observed from one inverter to the other. Due to the method, the turn-on time for the upper and lower switchable semiconductor switches of the respective bridge circuit is limited, which is why the temporal corridors (time window) arise in which there are no switching faults. As a result, a disturbance of the inverter is avoided or at least reduced in the temporal corridors.

Suitably, one or more measured values are recorded during the time window. In particular, the detection of the measured value or of the multiple measured values takes place within each of the occurring time windows, and for example at least one assigned measured value is detected in the first converter and in the second converter, so that two or more measured values are recorded after the time window has expired. For example, the same measured value is in turn recorded in the temporally subsequent time window. Alternatively, other readings are collected. Due to the detection of the measured values, measurement data are therefore available, by means of which the state of the respective converter can be determined, for example, and / or which serve to drive the inverters, and in particular to generate the (first and / or second) switching times. The mutual influencing of the converters due to the switching operations of the switchable semiconductor switches is particularly disturbing if the measured values are recorded in the same way. In other words, analogue measurement Signals falsified due to mutual interference. Due to the time window thus adulteration is avoided. Thus measurements can take place within the time windows (corridors) without being affected by the switching of the switchable semiconductor switches. The measured value is, for example, an electrical current flow, so that during the time window the electric current flow is detected. In this way, a power of the respective converter is comparatively easily determinable, and the electric current flow can be detected unadulterated during the time window. In summary, measurement data are acquired at least in part of the time windows.

Preferably, each of the inverters comprises a number of terminals, the number being conveniently equal to the number of electrical phases created by the respective inverter. Conveniently, each terminal is electrically contacted with a bridge branch of the respective bridge circuit. In the assembled state, the current load is supplied by means of the connection terminals, which are electrically connected to the respective load. The first and / or second switching times are preferably created such that during the time window no electrical potential difference between the terminals of the first inverter is applied. Also, there is no electrical potential difference between the terminals of the second inverter during the time window. Preferably, the electrical potential of the electrical phases of each inverter is the same. For example, at least during a portion of the time slots, there is an electrical potential difference between the terminals of the first inverter and the terminals of the second inverter, or during the time slots, the electrical potential of the terminals of the first inverter is equal to the electrical potential of the terminals of the second inverter.

Suitably, in this case all electrical current phases of the bridge circuit are clamped to the lower (electrical) potential (the negative pole of a possible voltage intermediate circuit). In this case, for example, the same voltage intermediate circuit is assigned to the first converter and the second converter, or each of the two converters is assigned a different voltage intermediate circuit in each case. For example, an electric current flow and / or an electrical voltage generated by the converter is generated by means of space vector modulation. Expediently, a zero vector is present during the time window, so that the measured value detection expediently takes place during the zero vector, provided that the measured value detection is present. In summary, a space vector modulation is preferably used, wherein the converters are expediently 3-phase (current phase). Suitably, control is done by means of space vector modulation. Thus, there are a total of 8 switching states for the three electrical current phases, which can each be connected to the upper or the lower potential. Those switching states which establish a connection of the upper potential via the respective load, in particular the motor, to the lower potential are called in particular active switching states. In particular, the two switching states which connect all current phases at the same potential are referred to as free-wheeling state, also referred to as zero vector. In a particularly advantageous development, the zero vector is applied in the time windows. In summary, the measured value is detected in the zero vector, where preferably all terminals and thus also the current phases of the bridge circuits are clamped to the negative pole (lower potential) of the potential voltage intermediate circuit.

For example, the first switching times or the second switching times, suitably both the first switching times and the second switching times, by means of pulse width modulation (PWM) created. In other words, the first converter and the second converter are operated with pulse width modulation. In this case, the first converter is assigned a first frequency and a first phase and the second converter has a second frequency and a second phase. The first and second frequencies are suitably between 4 kHz and a few hundred kHz, such as 800 kHz, 700 kHz, 600 kHz, 500 kHz, 400 kHz, 300 kHz or 200 kHz. Suitably, the first frequency and / or the second frequency is between 4 kHz and 100 kHz. Preferably, the first frequency and / or the second frequency is 8 kHz. Due to the frequencies, periods of pulse width modulation are defined. The first phase or the second phase determines the respective time at which the periods corresponding to the respective frequency start, and is determined, for example, with respect to an absolute time or with respect to a relative time, such as the switching on of one of the two converters.

For example, the first inverter and the second inverter assigned to different PWM carrier signals, which expediently each have the associated frequency. The position of the PWM carrier signals in particular is determined by means of the respective phase (first phase and / or second phase). Suitably, the PWM carrier signals of the first and the second converter are similar, for example, a sawtooth function, wherein the PWM carrier signals of the two converters expediently only due to the respective frequency and / or the respective phase se differentiate. For example, a centered or an asymmetric pulse width modulation is used. In summary, the switching times of the respective switchable semiconductor switches are created by means of pulse width modulation. Suitably, the first converter or the second converter, expediently both converters, are digitally controlled in pulse-width modulation, wherein, for example, one controller is assigned to each converter, so that a different digital controller is used as controller for each converter.

In summary, in particular the bridge circuits are operated with the pulse width modulation (PWM). The output terminals (current phases) of each inverter are electrically connected via the switchable semiconductor switches of the respective half-bridge either to the upper or to the lower potential (DC link potential). The change between the potentials takes place, for example, periodically with a carrier frequency (first frequency, second frequency) from 4 kHz to a few 100 kHz. Within one period, the pulse width - the duration of the dwell time at the upper potential (DC link potential) - varies, in particular as a function of a voltage requirement. In this way, the resulting average electrical voltage per period is adjusted and by modulation of the pulse width in each phase, the current size is suitably regulated.

In summary, a centered PWM method is used in particular. Each inverter preferably comprises a phase counter for generating a PWM carrier signal, which is reset after a PWM period and repeats the process cyclically. In other words, the phase counter is reset at the first and second frequencies, respectively. In the centered PWM, the switching times (on and off timing) of each switchable semiconductor switch are placed symmetrically about the middle of each period (period center). In this way, for example, the turn-on of one of the switchable semiconductor switch (upper semiconductor switch) is determined, and preferably the connection of the associated terminal to the upper potential. The rest of the time, while this switchable semiconductor switch is turned off, the further switchable semiconductor switch of the same bridge branch (lower semiconductor switch) is driven to connect the terminal and thus the current phase with the low lower potential.

In summary, in particular the first and the second inverter pulse width modulated inverter, each with the bridge circuit, wherein the pulse width of each Inverter is controlled such that the time window (temporal corridor) arise in which no semiconductor switch of the bridge circuits is switched. If several inverters are present, they also have additional frequencies and further phases.

The time windows are expediently determined on the basis of the first phase and the first frequency. Suitably, the time windows thus periodically occur at the first frequency, an integer multiple of the first frequency, or a rational fraction of the first frequency. For example, an end or a beginning of the time window is selected such that it corresponds to the end or the beginning of each of the periods defined by means of the first phase and the first frequency. Expediently, however, provided that in particular a centered pulse width modulation is used, the time window exists in the middle of each period and thus corresponds to the beginning of the first period plus half of the period defined by means of the first frequency. Alternatively or particularly preferably in combination with this, during each period, which is defined by means of the first frequency, there is a further time window which, for example, is associated with the beginning and / or the end of the respective period. Suitably, the time window is symmetrical with respect to the mid-point of the period and / or the beginning or end of each period defined by the first frequency. Due to the determination of the time window based on the first phase and the first frequency, the time windows are known in advance. Therefore, especially when a measured value is detected, operation is simplified.

For example, a power request to the first inverter or to the second inverter is determined. Suitably, the power requirement is determined for both the first inverter and the second inverter, for example, with different power requirements to the two inverters. On the basis of the power demand, the first switching times and the second switching times are determined. Those first switching times and those second switching times that are outside the time windows are used unchanged as first or second switching times. For example, those first switching times and those second switching times that are within at least one of the time slots are discarded in one alternative. Conveniently, the temporally following switching time is also discarded, so that discarded at each rejection two switching times and thus ignored. As a result- of which two operations of one of the switchable semiconductor switches are not performed so that the time slots are present.

In an alternative to this, those first switching times and those second switching times that are within at least one of the time windows are shifted to a limit of the time window within which the first or second switching times were originally. These shifted first and second switching times are now used as the first and second switching times. Thus, the totality of any shifted and non-shifted switching times forms the first and second switching times. Due to the shift or discarding the output by means of the two inverter power does not correspond to the power requirement, which is why provided by the two converters either a slightly too large or a slightly too small power. However, it is ensured in this case that during the time window no first and second switching times are present, so that any detection of a measured value is not disturbed.

In summary, the active switching states are suitably limited in time or lengthened and / or the freewheeling states, if necessary, preferably extended or shortened, in particular for the creation of the time windows. If the switch-on time of a switchable semiconductor switch undershoots or exceeds the limit of one of the time windows, then either the switch-on time is limited to the corridor limit (limitation of the time window) or the switchable semiconductor switch, in particular one of the current phases, lingers at the original / closest potential for the entire cycle duration ,

Conveniently, an integer multiple of the first frequency is selected as the second frequency. In particular, the time slots having the first frequency occur in this way, and the time slots are already known in advance because of this. In summary, the carrier frequencies of the pulse width modulation of the two inverters differ by a whole multiple, wherein the first and the second frequency are each a carrier frequency. The lower carrier frequency is for example between 4 kHz and 10 kHz and suitably between 4 kHz and 8 kHz. The higher carrier frequency, ie the second frequency, is for example between 8 kHz and 20 kHz and expediently between 8 kHz and 16 kHz. Suitably, the second free frequency twice as high as the first frequency. If a plurality of inverters are present, all frequencies are expediently integer multiples of the first frequency, so that the first frequency represents the lowest frequency of the device comprising the inverters.

Certain constraints sometimes require the two inverters to operate at different PWM carrier frequencies (first frequency, second frequency). In this case, in particular, the second converter is operated with a PWM carrier frequency (the second frequency), which is an integer multiple of the first frequency. For example, the first inverter is for operating a high power motor and has the first frequency (lowest carrier frequency) of 8 kHz. By means of the second converter, a lower power motor is operated at the second frequency of 16 kHz. Thus, the time slots with a frequency of 16 kHz result for both frequencies, which enables a sampling of the possible measured values recorded with a sampling rate of 16 kHz. In an alternative, the time slots occur at a frequency of 8 kHz, and the sampling of the acquired measured values is filtered accordingly, so that the measured values recorded within the time windows are weighted more heavily.

Suitably, the second phase is shifted such that the first phase corresponds to the second phase. In other words, the distance of the second phase to the first phase, if any, is reduced so that it is converted to zero (0), and therefore, after the displacement, the distance of the two phases from each other is zero (0). As a result, at each period with the first frequency also starts a period with the second frequency. Thus, the time window is also determined based on the second phase and the second frequency and occurs only at certain times, for example, at the beginning or end of each period with the second frequency. A difference between the two phases occurs, for example, at a start of the inverter / the method, unless the two pulse width modulations are started simultaneously. Alternatively, such a phase offset occurs if a fault occurs in one of the two inverters during operation, such as the PWM carrier signal. For adaptation, ie for shifting, for example, a period is changed, in particular one of the periods of the second converter. By way of example, one of the periods is lengthened or shortened, so that the distance between the two phases relative to one another is zero (0). Particularly preferred is the shift or adaptation of the second phase. In other words, a shift of the second phase takes place at most around a certain section. In other words, one of the periods of the second inverter is only shortened or shortened by the section. If, following this, the second phase still does not correspond to the first phase, a new shift takes place. In other words, the shift is carried out at several periods in succession, so that the second phase of the first phase corresponds to the number of shifts. In this way, there is no abrupt transition during the displacement of the second phase, so that a load driven by means of the second converter is loaded comparatively little mechanically.

In an advantageous alternative, a synchronization pulse is emitted by the first converter via a synchronization line connecting the first converter with at least one further converter, by means of which a switch-free time window is formed in a predetermined time relation in the at least one further converter.

For example, the first and the second inverter are interconnected, suitably by means of a BUS system. In particular, the first converter is used as a master converter and the second converter as a slave converter. In this case, the pulse width modulation of the slave converter, that is to say of the second converter, is expediently synchronized to the pulse width modulation of the master converter, that is to say of the first converter. In other words, the second phase is shifted such that the first phase corresponds to the second phase. Conveniently, a synchronization line is used for this, by means of which the two converters are connected to each other by signal technology. The synchronization line is in particular a temporary and / or functional component of the possible BUS system. If further inverters are present, these are expediently slave inverters, and the phase difference of the pulse width modulation of the further slave converters for pulse width modulation of the master inverter is measured and the phases of the further converters are adapted such that they also correspond to the first phase.

In summary, the period duration of the pulse width modulation of the respective bridge circuits is synchronized with the pulse width modulation of the master bridge. Inverter (first inverter) set, in particular adjusted. The pulse width of the second converter and of any further converter is controlled, for example regulated, by limiting and synchronizing the pulse width of the second and any further converters. In other words, the first inverter is the master inverter and the second inverter is a slave inverter, whereby the slave

Inverter the pulse width modulation of the slave inverter is synchronized to the pulse width modulation of the master inverter, preferably via the synchronization line. Advantageously, the phase difference of the pulse width modulation for pulse width modulation of the master inverter is measured on each additional (slave) converter. Appropriately, the period of the pulse width modulation of the respective

Bridge circuits adjusted to a synchronization with the master pulse width modulation.

The device is, for example, a heat pump and has a first load which is driven by means of a first converter. In addition, the device comprises a second load which is driven by means of a second converter. The first load or load is suitably a brushless motor, the first load being suitably mechanically separated from the second load. The loads are, for example, brushless electric motors, in particular synchronous or asynchronous motors. For example, the inverters are inverters. Each converter has, for example, a control unit (control), which is in particular a digital controller. Each inverter has a bridge circuit with switchable semiconductors. In this case, the switchable semiconductor switches of the respective converter are expediently interconnected to form a B6 circuit, and each bridge circuit thus has three bridge branches (half bridges), each of which comprises two of the switchable semiconductor switches. With each bridge branch, a current phase is preferably conducted against a connection terminal of the respective converter.

The converters are operated in accordance with a method in which the switchable semiconductor switches of the first converter are driven at first switching times, and in which the switchable semiconductor switches of the second converter are driven at second switching times. The first switching times and the second switching times are set such that recurring time windows are formed, within which neither first switching times nor second switching times are present. In particular, the time windows occur periodically. For example, includes the device is a control unit, for example a microcontroller, which is suitable, in particular provided and configured to carry out the method.

For example, both converters are controlled by means of a common digital control. By means of the same digital control unit, the possible pulse width modulations of the current phases can be easily synchronized, since all pulse width modulations are connected to the same clock line and the possible phase counters can be started simultaneously. Thus, a realization of the time windows is simplified, and any detection of measured values, in particular a scanning process for the electrical currents, can take place within the time windows.

At least two different digital controllers (control units) are preferably used for the control of the bridge circuits. By "different" is meant, in particular, that any pulse width modulations, in particular any PWM generators, of the different digital controllers do not per se know the phase position (phase) of the other digital controller. Typically, these at least two different digital controllers also each have their own clock in the form of a quartz oscillator. In other words, the pulse width modulations are independent of each other. When using several digital control units (microcontroller), the pulse width modulations have no common clock line, and pulse width modulation of the respective inverter start at different times.

In order to increase the quality of any detected measured values and / or to reduce interference between the inverters, the pulse width modulations of the two inverters are preferably synchronized, and the respective pulse widths of the two inverters are particularly limited so that the time windows are formed. During the time window, the switching state of no switchable semiconductor switch is changed. Any sampling of the measured values takes place during one of the time windows, wherein the sampled value is, for example, an analog value which is converted into a digital value by means of an AD conversion. Appropriately, a measured value is detected for each current phase.

In particular, both inverters are guided against a common intermediate circuit (voltage intermediate circuit), which has two different potentials, namely a lower and an upper potential. The potential difference between the two potentials is suitably between 100 volts and 1,000 volts. Alternatively, the inverters, preferably the bridge circuits of the inverters, are fed from two different intermediate circuits (DC intermediate circuits). In particular, the intermediate circuit or the intermediate circuits are each a component of the device. For example, the intermediate circuit is fed by means of a rectifier. For example, the inverters are digitally controlled inverters. In summary, in particular the two bridge circuits (converter bridges) are electrically connected to the same DC voltage intermediate circuit. Alternatively, the bridge circuits are fed from different DC voltage intermediate circuits. For example, one of the inverters associated DC link is fed by means of an active front end (PFC), and the other inverter is associated with a further DC link, which in turn is fed without active PFC from a (utility) network.

In an advantageous development of the first inverter is connected to at least one other inverter via a synchronization line.

The invention further relates to the parallel operation of at least two brushless motors such. B. synchronous motors - also called brushless DC motors - or asynchronous motors. Each motor is powered by one inverter. Thus, there are at least two inverters operated according to the above method. The inverters are, for example, digitally controlled (drive)

Inverter. As a "digitally controlled (drive) inverter" in particular a power electronics in the form of a self-commutated six-pulse bridge circuit (converter bridge) with six switchable semiconductor switches, such as power transistors, and its digital control understood.

The bridge circuits are supplied with a DC electrical voltage from a DC intermediate circuit and supply at the output terminals a three-phase current (current phases) for the connected motor. The control of the switchable semiconductor switch (power transistors) is advantageously carried out by means of a digital control unit such. As a microcontroller or digital signal processor. The feeding DC voltage of the inverter is preferably generated from the AC voltage network by means of a mains rectifier (rectifier). The refinements and advantages embodied in connection with the method / parallel operation are also to be transferred analogously to the device and vice versa.

Embodiments of the invention will be explained in more detail with reference to a drawing. Show:

1 is a simplified equivalent circuit diagram of a device with a first converter and with a second converter,

2 schematically simplified, a development of the device,

3 shows a method for operating the device,

4 shows a time profile of first and second switching times as well as time windows without switching times,

Fig. 5-7 simplifies the creation of the switching times, and

Fig. 8 shows a shift of a second phase of the second inverter.

Corresponding parts are provided in all figures with the same reference numerals.

FIG. 1 shows a simplified equivalent circuit diagram of a device 2 with a first converter 4 and a second converter 6. By means of the first converter 4, a first load 8 and by means of the second converter 6, a second load 10 is driven. The first load 8 and the second load 10 are each three-phase brushless synchronous motors, and the first inverter 4 is the same, preferably identical, to the second inverter 6. The first inverter 4 has three first terminals 12, which are electrically connected to the first load eighth are contacted. One of the connection terminals 12 is assigned to a first current phase 13a, a further one of the connection terminals 12 to a second current phase 13b and the remaining terminal 12 to a third current phase 13c. In other words, the first inverter 4 is three-phase. Besides, each one is the terminals 12 each contacted with a bridge branch 14 of a bridge circuit 16. In this case, each of the bridge branches 14 has two switchable semiconductor switches 18 in the form of MOSFETs. Thus, the bridge circuit 16 is a switching circuit, and between the series-connected switchable semiconductor switches 18 of each of the bridge branches 14 is a contact point with the terminals 12th

The bridge branches 18 are connected between an upper potential 20 and a lower potential 22, which are each electrical potentials. Here are by means of three of the switchable semiconductor switch 18, namely the so-called upper switchable

Semiconductor switch, the terminals 12 against the upper potential 20 feasible. In other words, upon actuation of the upper semiconductor switches 18, the terminals 12 are set to the upper potential 20. If the upper semiconductor switches 18 are not actuated, and thus are in the electrically non-conductive state, the lower semiconductor switches 18, that is, the remaining semiconductor switches 18 of the first inverter 14 are actuated, and the terminals 12 are electrically contacted with the lower potential 22, so that the terminals 12 and the respective terminal 12 has the lower potential 22. The upper potential 20 and the lower potential 22 are conducted against a DC link capacitor 24, by means of which the potential difference between the upper and the lower potential 20, 22 in the amount of, for example, 500 volts is provided. The intermediate circuit capacitor 24 itself is a component of a (DC) intermediate circuit 26, which is fed by means of a rectifier, not shown, which is coupled to a utility network. In addition, the first converter 4 has a control unit 28, by means of which the semiconductor switches 18 are actuated as a function of requirements. For this purpose, the control unit 18 is electrically contacted in a manner not shown with the gates of the switchable semiconductor switch 18. The second inverter 6 is the same principle, preferably identical, to the first inverter 4 and thus also has the bridge circuit 16 with the semiconductor switches 18 and the terminals 12 and the control unit 28. The control unit 28 of the first converter 4 is signal-connected by means of a synchronization line (SYNC line) 30 to the control unit 28 of the second converter 6. To reduce a susceptibility to the synchronization line 30 is not shown in detail RC filter damped. The lower potential 22 of the second inverter 6 is directed against the lower potential 22 of the first converter 4, and the upper potential 20 of the second converter 6 is directed against the upper potential 20 of the first converter 4, so that the second converter 6 is also electrically connected to the intermediate circuit capacitor 24 connected is. In summary, the two inverters 4, 6 are guided against the common (direct current) intermediate circuit 26.

2, a development of the device 2 is shown. This has a number of other inverters 32, which are connected by means of the synchronization line 30 with the first inverter 4 and the second inverter 6 signal technology. The other inverters 32 are also of the same principle, preferably of identical construction, to the first and the second converter 4, 6 and the synchronization line 30 is a component of a BUS system, by means of which all converters 4, 6, 32 are connected to each other by signal technology. Here, the first inverter 4 forms a master inverter and the second inverter 6 and the other inverter 32 form slave inverters. The setting or assignment as a master inverter or slave inverter by means of programming the respective control unit 28. If only the first and the second inverter 4, 6 are present, they are also interconnected as a bus system, and the first inverter 4 is the master inverter, and the second inverter 6 is the slave inverter.

FIG. 3 shows a method 34 for operating the device 2. In a first step 36, a power demand 38 to the first inverter 4 and to the second inverter 6 is determined. The power requirement 38 corresponds to the power by means of which the respective load 8, 10 is to be operated. In particular, the power demand 38 varies over time and / or the power demand 8 to the first inverter 4 is different from the power demand 38 to the second inverter. In a subsequent second step 40, first switching times 42 are determined for the switchable semiconductor switches 18 of the first converter 4 and second switching times 44 for the switchable semiconductor switches 18 of the second converter 6, as shown in FIG. 4. Here, the switching times 42, 44 are each assigned to one of the switchable semiconductor switches 18 of the respective converter 4, 6, and at the respective switching times 42, 44 by means of the control unit 28 of the respective half conductor switch 18 is actuated, so that it is set from the electrically conductive to the electrically non-conductive state or from the electrically non-conductive to the electrically conductive state. The first switching times 42 are created by means of pulse width modulation, wherein the first inverter 4 is assigned a first frequency 46 and a first phase 48. On the basis of the first frequency 46, a period 50 is determined, and based on the first phase 48 it is determined at which absolute or relative time the respective periods 50 start. During a period 50, a phase counter 52 is counted, which is set to an initial value at the beginning of the period 50 and continuously counted up to the end of the period 50. Here, each of the periods 50 has a period midpoint 54 that characterizes the midpoint of each of the periods 50. The period centers 54 also occur at the first frequency 46. The first switching times 42 of each of the periods 50 are arranged symmetrically in time about the period center point 54 of the respective period 50. Here, at the start and end of each of the periods 50, the upper semiconductor switches 18, ie those connected between the upper potential 20 and the terminals 12, are in the electrically non-conducting state, so that the first, second and third current phases 13a, 13b, 13c the lower potential 22 has.

In the example, based on the power requirement 38, first one period 50 of one of the first switching times 42 assigned to the semiconductor switches 18 of the bridge branch 14 associated with the first current phase 13a, so that the upper semiconductor switch 18 and the lower semiconductor switch 18 of this bridge branch 14 to the first Switching time 42 would be operated. Here, the actuation of the two takes place

Semiconductor switch 18 at the same time or by a relatively small time offset from each other, so that a short circuit between the two potentials 20, 22 is avoided. In other words, first the lower semiconductor switch and subsequently the upper semiconductor switch 18 is actuated thereon. As a result, the first current phase 13a has first the lower potential 22 and then the upper potential 20.

Following this there is per period 50 one of the first switching times 42 for the semiconductor switches 18, which are associated with the second current phase 13b. Following this, there are the first switching times 42 for the third current phase 13 c, which thus temporally after the first switching times 42 for the second current phase 13 b and for the first current phase 13a. Following this, the period center 54 occurs in time. This is followed by one of the first switching times 42 for the third current phase 13c, then one of the first switching times 42 for the second current phase 13b, and then one of the first switching times 42 for the first current phase 13a.

As a result, time windows 56 are formed, within which no first switching times 42 are present, namely the period center 54 and the beginning or the end of each of the periods 50th Thus, the time window 56 based on the period center 54 and / or the beginning of the period or which in turn are determined based on the first phase 48 and the first frequency 46. Therefore, the time slots 56 are determined based on the first phase 48 and the first frequency 46. For the second inverter 6, the second switching times 44 are also created in the same manner. The second switching times 44 are also created by means of pulse width modulation, the second switching times 44 in turn being arranged symmetrically with respect to each of the period centers 54 of each of the periods 50 of the second converter 6. In other words, it is again a centered PWM method. Here, the second inverter 6, a second frequency 58 and a second phase 60 are assigned. Consequently, the duration of the period 50 of the second inverter 6 differs from the period 50 of the first converter 4. The second

Frequency 58 is 16 kHz and the first frequency 46 is 8 kHz. Thus, an integer multiple, namely twice the first frequency 46 is selected as the second frequency 58. At the beginning and at the end of each of the periods 50 and around the period center 54 each of the

Periods 50 of the second inverter 6 are formed second time windows 62, during which the first phase 13a, the second phase 13b and the third phase 13c of the second inverter 6 either at the lower potential 22 or at the upper potential 20, wherein either all upper Semiconductor switch 18 or all lower semiconductor switches 18 are actuated. Every second of the second time windows 62 is simultaneously one of

Time window 56, so that during the time window 56, neither the first switching times 42, nor the second switching times 44 are present. In other words, the first switching times 42 and the second switching times 44 are placed such that neither the first switching times 42 nor the second switching times are present during the repeatedly occurring time windows 56. For this purpose, the second phase 60 is such synchronized with the first phase 48, for which the synchronization line 30 is used, so that every other of the periods 50 of the second inverter 6 starts simultaneously with one of the periods 50 of the first inverter 4. To ensure that always the time window 56 are realized, a first

Barrier 64, a second barrier 66, a third barrier 68 and a fourth

Barrier 70 used. The second barrier 66 and the third barrier 68 as well as the first barrier 64 and the fourth barrier 70 are arranged symmetrically about the period center 54 of the respective period 50 and are the same for all periods 50 of the first converter 4 and of the second converter 6.

If, as shown in FIG. 5 for the third current phase 13c, the first switching times 42 lie between the second barrier 66 and the third barrier 68, for example based on the power requirement 38, the first switching times 42 would be within the time window 56. If this is the case, those switching times which are within the time window 56 are shifted to the limit of the time window 56, ie to the second and third barrier 66, 68, as shown in FIG. In a further alternative, which is shown in FIG. 7, the switching instants 42, which would lie within the time window 56, are rejected, so that there are fewer first switching times 42 for the third current phase 13c. This adjustment of the first switching times is carried out in the same way for the second switching times 44 for the second inverter 6. In addition, those switching times 42, 44, not between the first barrier 64 and the second barrier 66 or between the third barrier 68 and the fourth Barrier 70 are located, so are located in particular between the fourth barrier 70 and the first barrier 64, the limitation of the respective time window 56, ie on the first barrier 64 and the fourth barrier 70, moved or rejected. Also, the shift or the throw, provided that the second switching times 44 within the second time window

62 would be located.

In a subsequent third step 72, the semiconductor switches 18 are driven in accordance with the first and second switching times 52, ie in each case to the first and second switching times 42, 44th In a fourth step 74, the takes place substantially at the same time as the third operation 72, a measured value 76 is recorded during the time window 56. The measured value 76 is an electric current flow which is associated with the respective electrical phase 13a, 13b, 13c and which consequently leads the respective electrical phase 13a, 13b, 13c. The detection of the electric current flow takes place in an analogous manner, due to the absence of switching operations of the semiconductor switches 18 during the time window 56 no excessive electromagnetic waves are emitted, which couple into the control unit 28 and any other lines, not shown, and which would falsify the measurement process , As a result, an accuracy is increased and the influence of the inverter 4, 6 with each other avoided.

Furthermore, a fifth step 78 is carried out, which adjusts the second phase 60 of the first phase 48, so that the second period 50 of the second converter 6 start at the same time as the periods 50 of the first converter 4. In other words, the fifth step 78 is executed so that the second phase 60 corresponds to the first phase 48, and the period centers 54 are the same time. As shown in FIG. 8, in this example, the second frequency 58 is equal to the first frequency 46, so that the duration of the periods 50 of the first inverter 4 correspond to the duration of the periods 50 of the second inverter 6.

In FIG. 8, the first phase 48 and the second phase 56 are unequal, so that a phase offset 80 arises between the period centers 54 of the two phase counters 42. As a result, the time slots 56 are not present or shortened. Whenever the period center 54 of the first converter 4 occurs, a synchronization pulse 81 is transmitted via the synchronization line by means of the control unit 28 of the first converter 4

30 to the control unit 28 of the second inverter 6 passed. Based on the synchronization pulse 81, the phase offset 80 in the second inverter 6, which acts as a slave inverter is calculated. Phase offset 80 is fed to a controller 82 of control unit 28, which is, for example, a PI controller. By means of the controller 82, the period 50 of the second inverter is adjusted, which is thus the manipulated variable of the controller 82. Here, the period 50 is shortened or extended by a portion 84, so that the second frequency 58 is changed. After this (shortened) period 50, the phase counter 52 restarts and the next period 50 starts. Due to the shortening of the period 50, the phase offset 80 is reduced during the subsequent period 50, and by means of the regulator 82 a shortening of the period is again effected. 50. After repeated execution, the phase offset 80 is thus removed, and the first phase 48 corresponds to the second phase 60.

Conveniently, the controller output - the phase offset 80 - is limited to a maximum portion 84 in the positive or negative direction. Due to the section 84, the shift to a tolerance band is limited by the duration of the period 50 of the second converter 6, which is why a change of the second frequency 58, ie the PWM frequency of the second converter 6, is comparatively small. Due to the constant repetition of the shift until the phase offset 80 equals zero (0), the controller 82 oscillates and synchronizes the periods 50 of the two inverters 4, 6. Here, the synchronization to the periods 50 of the first inverter 4, which is the master -Umrichter is.

1 shows a simplified equivalent circuit diagram of the three-phase converters 4, 6 for converting a DC voltage into a 3-phase AC voltage in each case. The device 2 has the DC link capacitor 24 and

the bridge circuit 16 in the form of a six-pulse bridge circuit. The three terminals 12 are respectively connected in the middle, between the upper and lower semiconductor switches 18, which are power switches. By changing the switching states, the respective terminal 12, and thus also the associated current phase 13a, 13b, 13c optionally connected to the upper or to the lower potential 20, 22, which are provided by the DC link capacitor 24, and it can be an electric current via the terminals 12 flow.

4 outlines the phase counter 52 of the first converter 4 and the phase counter 52 of the second converter 6, each of which is a component of a centered pulse width modulation. Here, the pulse width modulation (PWM) of the first inverter 4 is a master PWM, and the pulse width modulation of the second inverter 6 is a slave PWM. Based on the pulse width modulation, the three current phases 13a, 13b, 13c are controlled or created. In this PWM form, the on and off timings of the upper (switchable) semiconductor switches 18 are placed symmetrically about the period centers 54.

The barriers 64, 66, 68, 70 each form an intersection point with the phase counter 52 and define a minimum and maximum turn-on time of the switchable semiconductor switches 18. By limiting the turn-on of the switchable semiconductor switch 18, the time window 56 arise in which none of the switchable semiconductor switch 18 changes its state. The lower half of the figure shows the same principle for the slave PWM, which has the second frequency 58, which for example is twice the first frequency 46, ie twice the frequency to the master PWM. The pulse width modulation each guarantees two time windows 56 within a period 50. Thus, the time windows 56, 62 are possible for both pulse width modulations. Within these time windows 56, 62 correspondingly low-noise measurements can take place. FIG. 2 illustrates the connection of the different control units 28 of the inverters 4, 6, 32, which are digital controllers (microcontrollers), each with its own PWM unit. One of the digital controllers (microcontroller), namely the control unit 28 of the first converter 4, assumes the role of the master, which transmits a synchronization signal, namely the synchronization pulse 81 occurring at the first frequency 46. All other digital controllers (microcontrollers) act as slaves (14) and receive the synchronization signal. All subscribers of this network, among other possible communication circuits, are connected to the common synchronization line 30 (SYNC line) on which the synchronization signal passes from the master to the slaves.

FIG. 8 shows signals of the two inverters 4, 6, whose two control units 28 (digital controllers / microcontrollers) are connected via the synchronization line 30 (SYNC line) as in FIG. 2. The upper PWM of the first inverter 4 operates as a master and transmits the synchronization pulse 81 on the synchronization line 30 at a defined time. The underlying PWM of the second inverter 6 assumes the role of a slave and synchronizes via the Regler82, which slightly changes the second frequency.

The time difference between the incoming synchronization pulse 81 and the own defined time, namely the respective period center 54, forms the

Phase offset 80 (phase error) and serves as an input to the controller 82. The controller output of the controller 82 then changes the period of the next PWM cycle. If the phase offset 80 has been canceled by the control, the master of the first converter 4 and slave PWM of the second converter and any further converter 32 run synchronously. The time windows 56 (temporal corridors) represent a time range, a time interval, in which none of the switchable semiconductor switches 18 switches. The switch-on of the respective upper switchable semiconductor switch 18 are limited by the first and fourth barrier 64, 70 and the second and third barrier 66, 68 such that within the time window 56 none of the three bridge arms 14 of each inverter 4, 6, 32 performs a switching operation ,

If a duty cycle were to be requested, which would fall into the time window 56 formed around the respective period center 54, then the duty cycle of the affected current phase 3a, 3b, 3c is corrected to the respective, in particular nearest, barrier 64, 66 or to 0% - per after which border is closer. If a duty cycle were to be requested which would fall within the time window 56 formed at the beginning / end of the respective periods, the duty cycle of the affected phase is corrected to the first or fourth limit 64, 70 or to the period limit (± 100% or Phase counter start or end value) - whichever is closer.

The scanning of the phase currents preferably takes place in the region of the time windows 56. In this example, when the phase counter 52 is reset to its initial value. Here, the terminals 12 (motor terminals) are clamped to the lower potential 22 (negative pole) of the DC intermediate circuit 26, which can measure the electric currents directly via simple current measuring resistors of the microcontroller.

If all the PWMs of a single inverter are controlled by the same microcontroller, it offers the possibility to synchronize all PWMs. The method 34, however, describes the synchronization of the PWMs on different inverters 4, 6, 32 by means of their respective control units 28 (digital control units / microcontroller). The method is illustrated in FIGS. 3 to 8. In this case, one of the control units 28 (microcontroller) acts as a master and transmits the synchronization pulse 81 (SYNC pulse) in each PWM cycle on the synchronization line 30 (SYNC line) provided for this purpose. This synchronization line 30 connects all the controllers 28 to each other, the master can send on this line and all slaves can receive on it. It does not matter if Master and Slaves are with the same PWM frequency or whether all inverters are operated at an integer multiple of the lowest frequency. The smallest (PWM) frequency is preferably reserved for the master. The synchronization pulse 81 is generated directly by the master controller (control unit 28 of the first inverter 4).

Each participating PWM control preferably has its own phase counter 52 which linearly resolves the period 50 (PWM carrier period) determined by means of the respective frequency 46, 58 into a few hundred finely granular steps. If the phase counter 52 of the first inverter 4 passes a certain value (SYNC time), in the example shown the period center 54, the synchronization pulse 81 is set to the

Synchronization line 30 given.

The SYNC timing of the first inverter 4 - ie the timing of the synchronization pulse 81 (SYNC pulse) within the period 50 of the first inverter 4 (master PWM period / CNTRsync master key) - is the other converters 6, 32 participants due to appropriate initialization known. The second inverter 6 and any further converters 32 hold the state of their own phase counter 52 as CNTR_SlavePhase upon receipt of the synchronization pulse 81. On the basis of the count of the own phase counter 52 (CNTRsiavePhase) and the known SYNC time of the first inverter 4 (CNTR _Sy ncMasterPhase) the separate phase offset 80 (phase error) is determined in each slave (second inverter 6, further inverter 32).

This phase offset 80 is used as input to the controller 82 (eg, PI controller). The output of the controller 82 - the manipulated variable - is the duration of the own period 50. Depending on the implementation, the controller 82 influences the duration of the current period 50, ie the current PWM cycle T _PW M (n), or the subsequent period 50 , ie the next PWM cycle TpwM (n + 1):

Phase offset 80 = CNTRsyncMasterPase - CNTRsiavePhase

TPWM (n + 1) = TPW - f re _g ier (phase offset 80)

The output of the regulator is limited by the section 84 to a tolerance band around the nominal period so that the change of the PWM frequency is only very small. By continually repeating this process, the controller 82 oscillates and synchronizes with the master PWM. The susceptibility of the synchronizing Slaves can be improved by attenuating the SYNC line with an RC filter.

The present method 34 is used inter alia, the low-interference measurement of analog signals in a plurality of digitally controlled pulse width modulated drive inverters 4, 6, 32 in parallel with at least two different digital control units 28. The pulse widths of the bridge circuits 16 each inverter 4, 6, 32 are limited so that in each inverter 4, 6, 32 cyclically recurring time window 56 (temporal corridor) arise in which no circuit breaker (switchable semiconductor switch 18) switches. Furthermore, the phases 48, 60 of the pulse width modulations of the individual digital controllers 28 are synchronized so that these time slots 56 of all the inverters 4, 6, 32 involved occur simultaneously. This makes it possible to periodically scan one or more analog measured values 76 (measuring signals) on one or more (drive) converters 4, 6, 32 within the time windows 56. To synchronize the synchronization line 30, which connects a master and its slaves together. The master controller 28 repetitively sends the synchronization pulse 81 (master SYNC signal) to the slaves, and these optionally change their PWM frequency minimally so that their phase 60 coincides with the synchronization pulse 81 (master SYNC signal).

In summary, the invention relates to a method for operating at least two pulse width modulated converters 4, 6, 32 with a bridge circuit 16 (converter bridge) for controlling motors 8, 10, with at least two controllers 28, wherein the pulse width of each inverter 4, 6, 32 is controlled such that a time window 56 (temporal corridor) arises in which no switchable semiconductor switch 18 (power switch) of the bridge circuit 16 is switched.

The invention is not limited to the embodiments described above. Rather, other variants of the invention can be derived therefrom by the person skilled in the art without departing from the subject matter of the invention. In particular, all the individual features described in connection with the individual embodiments are also combinable with one another in other ways, without departing from the subject matter of the invention. LIST OF REFERENCE NUMBERS

2 device

4 first inverter

6 second inverter

8 first load

10 second load

12 connection terminal

13a first phase of the current

13b second current phase

13c third current phase

14 bridge branch

16 bridge circuit

18 switchable semiconductor switch

20 upper potential

22 lower potential

24 DC link capacitor

26 DC link

28 control unit

30 synchronization line

32 additional inverters

34 procedure

36 first step

38 power requirement

40 second step

42 first switching time

44 second switching time

46 first frequency

48 first phase

50 period

52 phase counter

54 Period center

56 time slots

58 second frequency

60 second phase second time window first barrier second barrier third barrier fourth barrier third step fourth step

Measured value fifth work step

phase displacement

synchronization pulse

regulator

section

Claims

PATENT CLAIMS

Method (34) for operating a first converter (4) and a second converter (6), each having a bridge circuit (16) with switchable semiconductor switches (18),

- Wherein the switchable semiconductor switches (18) of the first inverter (4) are driven to first switching times (42),

- Wherein the switchable semiconductor switches (18) of the second converter (6) are driven to second switching times (44), and

- Wherein the first switching times (42) and the second switching times (44) are created such that repeatedly occurring time windows (56) are formed within which neither first switching times (42) nor second switching times (44).

Method (34) according to claim 1,

characterized,

in that one or more measured values (76), in particular an electrical current flow, are detected during the time window (56), and / or that no electrical potential difference is applied between terminals (12) of the converters (4, 6) during the time window (56).

Method (34) according to claim 1 or 2,

characterized,

in that the first switching times (42) and the second switching times (44) are created by means of pulse width modulation, wherein the first converter (4) has a first frequency (46) and a first phase (48) and the second converter (6) has a second frequency ( 58) and a second phase (60).

Method (34) according to claim 3,

characterized,

in that the time windows (56) are determined on the basis of the first phase (48) and the first frequency (46).

Method (34) according to claim 4, characterized,

a power requirement (38) is determined for the first converter (4) and / or the second converter (6), by means of which the switching times (42, 44) are determined, wherein those switching times (42, 44) are used unchanged are outside the time slots (56), and wherein those switching times (42, 44) that are within one of the time slots (56) are discarded or shifted to a limit (64, 66, 68, 70) of that time slot (56) become.

Method (34) according to one of claims 3 to 5,

characterized,

that an integer multiple of the first frequency (46) is selected as the second frequency (58).

Method (34) according to claim 6,

characterized,

the second phase (60) is shifted such that the first phase (48) corresponds to the second phase (60).

Method (34) according to claim 7,

characterized,

that the shift is limited.

Method (34) according to one of the preceding claims,

characterized,

a synchronization pulse (81) is emitted by the first converter (4) via a synchronization line (30) connecting the first converter (4) with at least one further converter (6), by which a synchronization pulse (81) is emitted in the at least one further converter (6 , 32) a switch-free time window (56, 62) is formed in a predetermined time relationship.

10. Device (2), in particular heat pump, with a means of a first inverter (4) driven first load (8), and with a second inverter (6) driven second load (10), wherein the first and the second order - are operated (4, 6) according to a method (34) according to one of claims 1 to 9.

11. Device (2) according to claim 10,

characterized,

that the two converters (4, 6) are guided against a common intermediate circuit (26).

12. Device (2) according to claim 10 or 11,

characterized,

in that the first converter (4) is connected to at least one further converter (6, 32) via a synchronization line (30).