WO2017088921A1

WO2017088921A1 - Adjustable speed drive system and method

Info

Publication number: WO2017088921A1
Application number: PCT/EP2015/077732
Authority: WO
Inventors: Radu Dan Lazar
Original assignee: Danfoss Power Electronics A/S
Priority date: 2015-11-26
Filing date: 2015-11-26
Publication date: 2017-06-01

Abstract

A multi-phase inverter having a plurality of pulse width modulation pulses is described. In the event that the duty cycle of a pulse of a plurality of pulse width modulation pulses of the multi-phase inverter is above an upper threshold and/or below a lower threshold, the duty cycle of said pulse is adjusted accordingly and the duty cycles of the other pulses in the plurality are adjusted by the same amount.

Description

ADJUSTABLE SPEED DRIVE SYSTEM AND METHOD FIELD OF THE INVENTION

The present invention relates to adjustable speed drives, for example adjustable speed drives for controlling a motor.

BACKGROUND OF THE INVENTION

Adjustable speed drives typically include an inverter having switching elements controlled using a pulse width modulation (PWM) scheme.

When driving a multi-phase load, PWM pulses are used to determine when switching elements of an inverter are on and off. A particular problem occurs as the duty cycle of a PWM pulse approaches unity (such that the high side switches of the inverter are almost always on). Such a pulse can require one or more of the inverter switches to be switched on and off (or off then on) for a short period of a duty cycle, which can results in the output voltage not changing as required because the transistors might not be fully on or off. A similar problem occurs as the duty cycle of a PWM pulse approaches zero.

This problem can to some extent be addressed using minimum pulse filtering. However, existing solutions are not ideal.

The present invention seeks to address at least some of the problems outlined above.

SUMMARY OF THE INVENTION

The present invention provides a method comprising determining whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold, and, if so, adjusting the duty cycle of said pulse accordingly and adjusting the duty cycles of the other pulses in the plurality by the same amount.

The present invention further provides a controller (e.g. for a PWM module of a multi-phase inverter) configured to determine whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold, and, if so, to adjust the duty cycle of said pulse accordingly and to adjust the duty cycles of the other pulses in the plurality by the same amount.

The present invention also provides a pulse width modulation signal generation system of a multi-phase inverter system comprising : means for determining whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold; means for adjusting the duty cycle of said pulse accordingly in the event that the duty cycle of a pulse of the plurality of pulse width modulation pulses is above the upper threshold and/or below the lower threshold; and means for adjusting the duty cycles of the other pulses in the plurality by the same amount.

The present invention yet further provides a multi-phase inverter having a plurality of pulse width modulation pulses. In the event that the duty cycle of a pulse of a plurality of pulse width modulation pulses of the multi-phase inverter is above an upper threshold and/or below a lower threshold, the duty cycle of said pulse is adjusted accordingly and the duty cycles of the other pulses in the plurality are adjusted by the same amount. The present invention seeks to reduce distortion that occurs in some traditional minimum pulse filtering techniques and to increase the linear region of the output voltage of the inverter. The invention may determine whether the duty cycle of a longest pulse of a plurality of pulse width modulation pulses of the multi-phase inverter is above the upper threshold and, if so, adjust the duty cycle of said longest pulse accordingly and adjust the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount. Adjusting the duty cycle of the longest pulse may comprise increasing the duty cycle of said longest pulse (typically to unity). By adjusting all of the pulses by the same amount, the difference between duty cycles can be maintained and the output voltage corresponding to the new duty cycle values need not change. The invention may further comprising determining whether a duty cycle of a shortest pulse of the plurality of pulse width modulation pulses is below the lower threshold and, if so, adjusting the duty cycle of said shortest pulse accordingly and adjusting the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount. Adjusting the duty cycle of the shortest pulse may comprise reducing the duty cycle of said shortest pulse (typically to zero). As noted above, by adjusting all of the pulses by the same amount, the difference between duty cycles can be maintained and the output voltage corresponding to the new duty cycle values need not change.

The invention may further comprise reducing the duty cycle of each of the plurality of pulse width modulation pulses of the multi-phase inverter in the event that one of the duty cycles is above a second upper threshold and below a first upper threshold (the first upper threshold may be closer to unity than the second upper threshold). For example, the duty cycle of the longest pulse may be reduced to the second upper threshold and the duty cycles of the other pulses reduced by the same amounts. This may result in smaller adjustments being made to the duty cycles in some circumstances than increasing the duty cycle of the longest pulse to unity.

The invention may further comprise increasing the duty cycle of each of the plurality of pulse width modulation pulses in the event that one of the duty cycles is above a first lower threshold and below a second lower threshold (the first lower threshold may be closer to zero than the second lower threshold). For example, the duty cycle of the shortest pulse may be increased to the second lower threshold and the duty cycles of the other pulses increased by the same amounts. This may result in a smaller adjustments being made to the duty cycles in some circumstances than reducing the duty cycle of the shortest pulse to zero.

The invention may include the step of determining the duty cycle of one or more of the plurality of pulse width modulation pulses of the multi-phase inverter.

Some forms of the invention include ordering the plurality of pulse width modulation pulses in order to identify the pulse with the longest duty cycle and/or the pulse with the shortest duty cycle. Further, the invention may include determining whether it is more likely that the pulse with the longest duty cycle is above the upper threshold or the pulse with the shortest duty cycle is below the lower threshold.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in further detail with reference to the following schematic drawings, in which :

Figure 1 shows an inverter drive system ;

Figure 2 shows an inverter that may be used in the inverter drive system of Figure 1 ;

Figures 3 and 4 show PWM pulses in accordance with aspects of the invention ;

Figures 5 and 6 are flow charts of algorithms in accordance with aspects of the invention;

Figures 7 and 8 show PWM switching pulses in accordance with aspects of the invention ;

Figure 9 is a flow chart of an algorithm in accordance with an aspect of the invention; and

Figure 10 show PWM switching pulses in accordance with an aspect of the invention .

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 is a block diagram of a system, indicated generally by the reference numeral 1 , including an adjustable speed drive (ASD) . The system 1 comprises an AC power supply 2, an ASD 4 and a load 6 (such as a three- phase motor) . The ASD 4 includes a rectifier 8 (often a diode-based rectifier, as shown in Figure 1, although alternatives, such as advanced front end rectifiers are known), a DC link capacitor 10, an inverter 12 and a control module 14.

The output of the AC power source 2 is connected to the input of the rectifier 8. The output of the rectifier 8 provides DC power to the inverter 12. As described further below, the inverter 12 includes a switching module used to convert the DC voltage into an AC voltage having a frequency and phase dependent on gate control signals. The gate control signals are typically provided by the control module 14. In this way, the frequency and phase of each input to the load 6 can be controlled .

The inverter 12 is typically in two-way communication with the control module 14. The inverter 12 may monitor currents and voltages in each of the three connections to the load 6 (assuming a three-phase load is being driven) and may provide current and voltage data to the control module 14 (although the use of both current and voltage sensors is by no means essential) . The control module 14 may make use of the current and/or voltage data (where available) when generating the gate control signals required to operate the load as desired ; another arrangement is to estimate the currents from the drawn voltages and the switching patterns - other control arrangements also exist.

Although the system 1 is used to drive a load, such as a motor, this is not essential to the invention . For example, the principles of the present invention are applicable for use in grid-connected inverters such as solar inverters or wind inverters.

Figure 2 shows details of an exemplary implementation of the inverter 12.

As shown in Figure 2, the inverter 12 comprises first, second and third high- sided switching elements (Tl , T2 and T3) and first, second and third low- sided switching elements (T4, T5 and T6) . Each switching element may, for example, be an insulated-gate bipolar transistor (IGBT) or a MOSFET transistor. As shown in Figure 2, each of the switching elements (Tl to T6) is associated with a corresponding free-wheeling diode (Dl to D6) . The exemplary inverter 12 is a three-phase inverter generating three outputs : U, V and W. The three phases of the inverter 12 provide inputs to the three-phases of the load 6 in the system 1 described above. Of course, the inverter 12 could be modified to provide a different number of outputs in order to drive a different load (such as a load with more or fewer than three phases) .

The first high-sided switching element Tl and the first low-sided switching element T4 are connected together between the positive and negative DC terminals. The mid-point of those switching elements provides the U-phase output. In a similar manner, the second high-sided switching element T2 and the second low-sided switching element T5 are connected together between the positive and negative DC terminals with the mid-point of those switching elements providing the V-phase output. Furthermore, the third high-sided switching element T3 and the third low-sided switching element T6 are connected together between the positive and negative DC terminals with the mid-point of those switching elements providing the W-phase output.

The inverter 12 is a 2-level, 6 transistor inverter. As will be apparent to those skilled in the art, the principles of the present invention are applicable to different inverters, such as 3-level inverters. The description of the inverter 12 is provided by way of example to help illustrate the principles of the present invention .

Figure 3 shows PWM pulses (indicated generally by the reference numeral 30) for the high-sided switching elements (Tl to T3) in an exemplary use of the inverter 12. The PWM pulses are typically generated by (or under the control of) the control module 14.

The PWM pulses for the phases U, V and W are depicted within a switching period . As shown in Figure 3, the three PWM pulses are arranged

symmetrically around a dashed centre line. This type of arrangement is typical for a three-phase motor controller and is often referred to as centre- aligned or double-sided modulation . In a centre-aligned PWM modulation scheme, the symmetry of each PWM pulse is maintained as the duty cycle is altered . Although the examples described herein make use of centre-aligned modulation, the principles of the present invention can also be applied to asymmetrical modulation schemes.

A problem arises with the PWM modulation scheme shown in Figure 3 as the duty cycle of the U-phase signal (or any other phase) approaches unity.

Since the pulse shown in Figure 3 may be immediately followed by a similar pulse, a pulse approaching a unity duty cycle will require the first switching element Tl to turn off (near the end of the pulse shown in Figure 3) and then almost immediately turn on again (at the start of the next pulse) . If the duty cycle is sufficiently close to unity, then, as discussed above, the switching off then on of the switching element Tl may result in the output voltage not changing as required because the transistors might not be fully on or off. A similar problem occurs as the duty cycle of the W-phase signal (or any other phase) approaches zero. Here, the switching element T3 will be required to turn on and then off again very quickly such that there is a risk that the transistor are not fully switched on or off during this process. Figure 4 shows PWM pulses, indicated generally by the reference numeral 40, showing an exemplary solution to the problem outlined above.

Figure 4 shows three pulses: pulse U, pulse V and Pulse W. On the left, the three initial, unfiltered, pulses are shown. Assume that the minimum switching times for switching elements of an inverter (such as inverter 12) being driven by the PWM pulses 40 is 2xMinPulse. Thus, any pulse that has a duty cycle more that (1 - 2xMinPulse) will violate the minimum switching times of the inverter. Similarly, any pulse that has a duty cycle less than (2xMinPulse) will violate the minimum switching times of the inverter.

For a symmetrical pulse to have a duty cycle less that (1 - 2xMinPulse), the pulse must switch at a time more that MinPulse away from the beginning and end of the pulse. Similarly, for a symmetrical pulse to have a duty cycle of more than (2xMinPulse), the pulse must switch at a time more that MinPulse away from the centre point of the pulse.

As shown in Figure 4, Pulse U has a duty cycle greater than (1 - 2xMinPulse) and therefore violates the minimum switching time of the inverter. Pulse V has a duty cycle less than (1 - 2xMinPulse) and more than (2xMinPulse) and therefore complies with the minimum switching time requirement of the inverter. Pulse W has a duty cycle less than (2xMinPulse) and therefore violates the minimum switching time requirements of the inverter. In Figure 4, pulses U and W are modified so that they comply with the minimum switching times of the inverter. Thus, as shown in Figure 4, the duty cycle of Pulse U is increased to unity, the duty cycle of Pulse V is unchanged and the duty cycle of Pulse W is reduced to zero. Changing the duty cycle of PWM pulses used to drive the inverter 12 will distort the output provided to the load 6. To compensate, the amount by which a particular phase is modified to comply with the minimum pulse requirements can be recorded and an equal and opposite adjustment made to the next PWM pulse. Thus, in the example of Figure 4, since the duty cycle of Pulse U has been increased, the duty cycle of phase U of the next pulse may be reduced by the same amount. Similarly, since the duty cycle of Pulse W has been reduced, the duty cycle of phase W of the next pulse may be increased by the same amount.

A problem with the minimum pulse filtering arrangement described above with reference to Figure 4 is that the adjustment of the different phases of the inverter switching signals inevitably introduces distortion into the signals driving the load 6.

Figure 5 is a flow chart of an algorithm, indicated generally by the reference numeral 50, in accordance with an aspect of the invention.

The algorithm 50 starts at step 52, where the duty cycles of the switches of an inverter are calculated. In the exemplary algorithm 50, three duty cycles are calculated (d_Ufv,w), but of course, a different number of duty cycles might be calculated if the output of the inverter has more or fewer phases.

Next, at step 54, the calculated duty cycles (du,v,w) are adjusted dependent on an accumulated error (err) determined in step 60 (described further below). The step 54 outputs compensated duty cycles (du,v,wcom_P = du,v,w - err) that compensates for previous minimum pulse filtering or adjustment steps. The compensated duty cycles are subjected to a shifting algorithm at step 56. Exemplary shifting algorithms are described in detail below. The shifted pulses are the passed through a minimum pulse filter at step 58. As is described in detail below, the use of the shifting algorithm at step 56 will reduce the li kelihood that the minimum pulse filter step 58 is required to adjust the PWM pulses.

In the event that the shifting algorithm 56 or the minimum pulse filtering step 58 adjusts any of the PWM pulses, the change is recoded as an error (err) in step 60 of the algorithm 50. This error is compensated by ma king an equal and opposite adjustment to the next PWM pulse in step 54 (as described further above) .

Following step 58, the algorithm 50 finishes at step 62, where the PWM signals, suitably adjusted (if necessary) are sent to the PWM registers (that may, for example, be stored in the control module 14 of the exemplary system 1 ) and used to drive the inverter switches (such as the inverter switches described above with reference to Figure 2) . Figure 6 is a flow chart of an algorithm, indicated generally by the reference numeral 70, in accordance with an aspect of the invention . The algorithm 70 is an exemplary implementation of the step 56 of the algorithm 50 described above. The algorithm 70 starts at step 72, then, at step 74, the pulses are ordered by length (such that the longest pulse (MaxPulse) and shortest pulse

(MinPulse) as used later in the algorithm are determined) . The algorithm then moves to step 76. At step 76, the complementary of the duty cycle of the longest pulse ( 1 - dutyMaxPulse) and the duty cycle of the shortest pulse (dutyMinPule) are compared . It is then determined whether or not ( 1 -dutyMaxPulse) is less than dutyMinPulse. If so, then the longest pulse is more li kely to need to be adjusted . Similarly, if ( 1 -dutyMaxPulse) is not less dutyMinPulse, then the shortest pulse is more li kely to need to be adjusted .

From step 76, if ( 1-dutyMaxPulse) < dutyM inPulse, then algorithm 70 moves to step 78. Otherwise, the algorithm 70 moves to step 82.

At step 78, it is determined whether or not the duty cycle of the longest pulse (MaxPulse) is longer than a given threshold (referred to as

2ndUpperThreshold in Figure 6), expressed mathematically as : (MaxPulse > 2ndUpperThreshold) . In the example of Figure 4, the relevant threshold might determine whether or not the duty cycle of the longest pulse is greater than ( 1 - 2xM inPulse) and therefore does not comply with the minimum pulse requirements. If the MaxPulse > 2ndUpperThreshold, the algorithm 70 moves to step 80 : otherwise, the algorithm 70 terminates at step 86.

At step 82, it is determined whether or not the duty cycle of the shortest pulse (MinPulse) is shorter than a given threshold (referred to as

2nd l_owerThreshold in Figure 6), expressed mathematically as : (MinPulse < 2nd l_owerThreshold) . Referring to Figure 4, the relevant threshold might determine whether or not the duty cycle of the shortest pulse is less than (2xMinPulse) and therefore does not comply with the minimum pulse requirements. If the MinPulse < 2ndl_owerThreshold, the algorithm 70 moves to step 84 : otherwise, the algorithm 70 terminates at step 86. At step 80, the duty cycle of all of the PWM pulses is increased . The algorithm 70 then terminates at step 86.

At step 84, the duty cycle of all of the PWM pulses is reduced . The algorithm 70 then terminates at step 86.

In the algorithm 70, the phases of all the PWM pulses are either increased by the same amount (in step 80), reduced by the same amount (in step 84) or left unchanged . It should be noted that by changing the duty cycles of all pulses by the same amount, the difference between duty cycles is

maintained and the output voltage corresponding to the new duty cycle values will not change. At the same time, the minimum pulse areas are avoided in many instances. By doing this the output voltage in these areas is not distorted and the output voltage linearity is maintained .

Figures 7 and 8 show PWM switching pulses, indicated generally by the reference numerals 90 and 100 respectively, in accordance with aspects of the invention . Figures 7 and 8 both show switching signals for three phases : namely phase U, phase V and phase W. Original signals are shown on the left: signals adjusted in accordance with the algorithm 70 are shown on the right.

In the switching pulses 90 shown in Figure 7, phase U has a duty cycle that is greater than ( 1 - 2xMinPulse) . Thus, as required by step 80 of the algorithm 70, the duty cycle of each of the phases is increased . As shown in Figure 7, the duty cycle of phase U is increased to unity, whilst the duty cycles of phases V and W are increased by the same amount. In the switching pulses 100 shown in Figure 8, phase W has a duty cycle that is less than (2xMinPulse) . Thus, as required by step 84 of the algorithm 70, the duty cycle of each of the phases is reduced . As shown in Figure 8, the duty cycle of phase W is increased to zero, whilst the duty cycles of phases U and V are reduced by the same amount.

Figure 9 is a flow chart of an algorithm, indicated generally by the reference numeral 1 10, in accordance with an aspect of the invention . The algorithm 1 10 is similar to the algorithm 70 described above, but determines whether or not to increase or decrease the duty cycles of the PWM signals in a different way.

As with the algorithm 70 described above, the algorithm 1 10 starts at step 1 12 and then moves to step 114, where the pulses are ordered by length (such that the longest pulse (MaxPulse) and shortest pulse (MinPulse) as used later in the algorithm are determined) . The algorithm then moves to step 1 16.

At step 116, it is determined whether the longest pulse (MaxPulse) has a duty cycle greater than a second upper threshold (MaxPulse >

2ndUpperThreshold) . The second upper threshold is the point at which the PWM pulse will need to be adjusted to meet the minimum pulse

requirements. If MaxPulse > 2ndUpperThreshold, the algorithm 1 10 moves to step 1 18 : otherwise, the algorithm 1 10 moves to step 120.

At step 120, it is determined whether the shortest pulse (MinPulse) has a duty cycle less than a second lower threshold (M inPulse <

2nd l_owerThreshold) . The second lower threshold is the point at which the PWM pulse will need to be adjusted to meet the minimum pulse requirements. If MinPulse < 2ndLowerThreshold, the algorithm 1 10 moves to step 122 : otherwise, the algorithm 1 10 terminates at step 128.

At step 118, it is determined whether or not the duty cycle of the longest pulse (MaxPulse) is longer than a first upper threshold (MaxPulse >

IstUpperThreshold) . As described further with reference to Figure 10 below, the first upper threshold is closer to unity than the second upper threshold . If MaxPulse > IstUpperThreshold, the algorithm 110 moves to step 124 : otherwise, the algorithm 1 10 moves to step 126.

At step 122, it is determined whether or not the duty cycle of the shortest pulse (MinPulse) is shorter than a first lower threshold (M inPulse <

IstLowerThreshold) . As described further with reference to Figure 10 below, the first lower threshold is closer to zero than the second lower threshold . If MinPulse < IstLowerThreshold, the algorithm 110 moves to step 126 :

otherwise, the algorithm 1 10 moves to step 124.

At step 124, the duty cycle of all of the PWM pulses is increased . The algorithm 110 then terminates at step 128.

At step 126, the duty cycle of all of the PWM pulses is reduced . The

algorithm 110 then terminates at step 128.

The algorithm 110 seeks to modify all of the PWM pulses by the same amount to ensure that the minimum switching period is not violated . In addition, the algorithm 1 10 seeks to ensure that minimum distortion is introduced into the PWM signals. Thus, the distortion provided to the load 6 is minimised . Figure 10 shows details of thresholds used in the algorithm of Figure 9.

Figure 10 shows a time period, indicated generally by the reference numeral 130, of a single PWM pulse. The pulse has a start 131 , an end 132 and a centre point 133. Assuming that the pulse is symmetrical, the PWM pulse (unless it is a unity or zero pulse) will have a transition between the start 131 and the centre point 133.

The first and second upper thresholds of the algorithm 110 are indicated by points 134 and 135 of the time period 130 respectively. The first and second lower thresholds of the algorithm 1 10 are indicated by points 136 and 137 of the time period 130 respectively.

The second upper threshold (time period 135) is at time M inPulse after the start point 131. The second lower threshold (time period 137) is at time MinPulse away from the centre point 133. If a pulse transition occurs between the time periods 135 and 137, then the minimum switching period of the inverter 12 is complied with. If a pulse transition occurs either before the time period 135 or after the time period 137, then the minimum

switching period of the inverter 12 is violated and corrective action is required .

The first upper threshold (time period 134) is at a time MinPulse/2 after the start point 131. The first lower threshold (time period 136) is at a time MinPulse/2 before the centre point 133.

In the algorithm 110 described above, if the duty cycle of a PWM pulse is above the first upper threshold (detected at step 1 18 of the algorithm 1 10), this means that the transition in the pulse occurs between the start point 131 and the time period 134. In this case, the duty cycle is close to unity. In response to this determination, the duty cycle of all pulses is increased (step 124) . In this case, the duty cycle of the longest pulse is increased to unity, and the duty cycles of the other pulses are increased by the same amount.

If the duty cycle of any of the PWM pulses is below the first lower threshold (detected at step 122), such that the transition in the pulse occurs between the time 136 and the centre point 133, then the duty cycle is close to zero. In response to this determination, the duty cycle of all pulses is decreased (step 126) . In this case, the duty cycle of the shortest pulse is reduced to zero, and the duty cycles of the other pulses are reduced by the same amount.

If the transition of any of the PWM pulses is between the first and second upper thresholds (i .e. between the time periods 134 and 135), then that pulse violates the minimum switching time of the inverter 12, but not by much . In response to this determination, the duty cycle of all pulses is decreased (step 126) . This prevents the minimum switching time from being violated, but does not introduce significant distortion . For example, the duty cycle of the longest pulse may be reduced to the second upper threshold and the duty cycles of the other pulses reduced by the same amounts.

If the transition of any of the PWM pulses is between the first lower threshold and a second lower threshold (i .e. between the time periods 136 and 137), then that pulse violates the minimum switching time of the inverter 12, but not by much . In response to this determination, the duty cycle of all pulses is increased (step 124) . Again, this prevents the minimum switching time from being violated, but does not introduce significant distortion . For example, the duty cycle of the shortest pulse may be increased to the second lower threshold and the duty cycles of the other pulses increased by the same amounts. In the exemplary pulses shown in Figure 10, it can be seen that the switching of the phase U and phase V pulses occurs between the time periods 135 and 137 and therefore, those pulses do not violate the minimum switching period . The switching of the phase W pulse occurs after the first lower threshold 136. Accordingly, the algorithm 1 10 would determine (at step 126) that the duty cycle of all of the pulses should be reduced . The duty cycle of the pulse W would therefore be reduced to zero and the duty cycle of the other pulses reduced by the same amount.

The embodiments of the invention described above are provided by way of example only. The skilled person will be aware of many modifications, changes and substitutions that could be made without departing from the scope of the present invention. The claims of the present invention are intended to cover all such modifications, changes and substitutions as fall within the spirit and scope of the invention .

Claims

CLAIMS :

1. A method comprising determining whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold, and, if so, adjusting the duty cycle of said pulse accordingly and adjusting the duty cycles of the other pulses in the plurality by the same amount.

2. A method as claimed in claim 1 , further comprising determining whether the duty cycle of a longest pulse of a plurality of pulse width modulation pulses of the multi-phase inverter is above the upper threshold and, if so, adjusting the duty cycle of said longest pulse accordingly and adjusting the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount.

3. A method as claimed in claim 2, wherein adjusting the duty cycle of the longest pulse comprises increasing the duty cycle of said longest pulse.

4. A method as claimed in any preceding claim, further comprising determining whether a duty cycle of a shortest pulse of the plurality of pulse width modulation pulses is below the lower threshold and, if so, adjusting the duty cycle of said shortest pulse accordingly and adjusting the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount.

5. A method as claimed in claim 4, wherein adjusting the duty cycle of the shortest pulse comprises reducing the duty cycle of said shortest pulse.

6. A method as claimed in any preceding claim, further comprising reducing the duty cycle of each of the plurality of pulse width modulation pulses of the multi-phase inverter in the event that one of the duty cycles is above a second upper threshold and below a first upper threshold.

7. A method as claimed in any preceding claim, further comprising increasing the duty cycle of each of the plurality of pulse width modulation pulses in the event that one of the duty cycles is above a first lower threshold and below a second lower threshold.

8. A method as claimed in any preceding claim, further comprising determining the duty cycle of one or more of the plurality of pulse width modulation pulses of the multi-phase inverter.

9. A method as claimed in any preceding claim, further comprising ordering the plurality of pulse width modulation pulses in order to identify the pulse with the longest duty cycle and/or the pulse with the shortest duty cycle.

10. A method as claimed in claim 9, further comprising determining whether it is more likely that the pulse with the longest duty cycle is above the upper threshold or the pulse with the shortest duty cycle is below the lower threshold.

11. A controller configured to determine whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold, and, if so, to adjust the duty cycle of said pulse accordingly and to adjust the duty cycles of the other pulses in the plurality by the same amount.

12. A controller as claimed in claim 11 , further configured to determine whether the duty cycle of a longest pulse of a plurality of pulse width modulation pulses of the multi-phase inverter is above the upper threshold and, if so, to adjust the duty cycle of said longest pulse accordingly and to adjust the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount.

13. A controller as claimed in claim 1 1 or claim 12, further configured to determine whether a duty cycle of a shortest pulse of the plurality of pulse width modulation pulses is below the lower threshold and, if so, to adjust the duty cycle of said shortest pulse accordingly and to adjust the duty cycles of each of the other pulse width modulation pulses in the plurality by the same amount.

14. A pulse width modulation signal generation system of a multi-phase inverter system comprising :

means for determining whether the duty cycle of a pulse of a plurality of pulse width modulation pulses of a multi-phase inverter is above an upper threshold and/or below a lower threshold ;

means for adjusting the duty cycle of said pulse accordingly in the event that the duty cycle of a pulse of the plurality of pulse width modulation pulses is above the upper threshold and/or below the lower threshold ; and means for adjusting the duty cycles of the other pulses in the plurality by the same amount.