WO2017033069A1

WO2017033069A1 - Distributed modulation system and method for power electronic applications

Info

Publication number: WO2017033069A1
Application number: PCT/IB2016/054226
Authority: WO
Inventors: Simon DELALAY; Matthias LAMBERT; Nicolas CHERIX
Original assignee: Imperix Sa
Priority date: 2015-08-24
Filing date: 2016-07-15
Publication date: 2017-03-02
Also published as: CH713045B1; DE112016003849T5

Abstract

Endnode (30) for a distributed modulation system for power electronic applications, comprising: - at least a transceiver for receiving control data from a control master (10) via at least one data transmission channel (201) embedding a reference clock signal (RefCLK) and comprising at least one set of modulation parameters, - at least one a clock recovery module, arranged for recovering a recovered clock signal (rCLK) from the data transmission channel, - a modulator (302) arranged for generating modulation signals (401) based on the set of modulation parameters and on at least one periodic carrier generated by using the recovered clock signal (rCLK), - a supervisory module configured for mastering and adjusting an initial phase difference between the periodic carrier(s) and an interrupt signal based on the reference clock signal. The present invention concerns also a distributed modulation system for power electronic applications comprising this endnode and a relative method.

Description

Distributed modulation system and method for power electronic applications

Field of the invention

[0001] The present invention concerns an endnode for a distributed modulation system for power electronic applications, such a system and a method for such a system. Description of related art

[0001] Power converters, or power conversion systems, are widely used in order to convert AC or DC signals into AC or DC signals with different amplitude or frequency for example.

[0002] Modern power converters comprise two parts. On one side, a power stage acts as (a) controllable valve(s) in order to shape the power signal(s) and regulate the corresponding power flow(s). The power stage usually comprises power semiconductor switches, such as IGBTs, IGCTs, GTOs, thyristors, etc. On the other side, a control stage generates control signals for these switches in order to shape the output power signal(s) as desired.

[0003] Modern power converters generally make use of modulation techniques such as for example pulse width modulation (PWM) in order to combine good harmonic performance and good conversion efficiency.

[0004] The modulation is achieved by means of a modulator. In the context of the present invention, a modulator is a functional block generating one or more modulation signals based on one or more carriers and a set of modulation parameters. Generally, the modulation signal is a digital signal and the carrier is a periodic analog signal approximated by the value of a digital counter based on a clock signal. In the following, the expression "carrier (or signal) generated based on a clock signal" indicates that the carrier (or the signal) is generated by using a digital counter based on this clock signal.

[0005] A modulator can perform different modulations, for example a pulse width modulation, a pulse frequency modulation, a space vector modulation or may use optimized pulse patterns to transform its inputs into its outputs.

[0006] In the case of a pulse width modulator, the carrier is a periodic waveform, e.g. a saw-tooth or a triangle waveform generated based on a clock signal, and the main modulation parameter a threshold. If the value of the carrier is higher than the threshold, the modulation signal is in a high state, otherwise it is in a low state.

[0007] The modulation signals are in general used for controlling one or more power semiconductor switches of the power stage, e.g. for

determining the switching instants of those switches. [0008] Modular power conversion systems that comprise a power circuit with multiple Power Electronic Building Blocks (PEBBs) are well known. Systems comprising between 1 and 2Ό00 blocks, or more, are for example known. The use of a modular construction allows to easily scale the ratings and performance of power converters by paralleling or stacking different PEBBs. Besides, modular converters are easier and more cost-effective to develop and maintain, and are also more reliable thanks to possible redundancies.

[0009] Examples of modular power converters are given by US5642275A, DE10103031A1 or US20100156188A1. [0010] For a non-modular power conversion system, the overall system may be assimilated to a unique PEBB.

[0011] A known drawback of modular power conversion systems is the difficult operation and coordination of the multiple PEBBs, among which the modulation signals must be synchronized by suitable techniques. This is particularly challenging when the modulators are located inside the PEBBs and when the latter are physically separated or distributed geographically, such as in large facilities. [0012] In practice, the synchronization of multiple modulation signals generated by a plurality of modulators located inside distinct PEBBs implies two types of issues:

- first type of issue: synchronize the operation of the modulators; this implies that it must be possible to adjust and master the relative phases and frequencies of the corresponding modulation signals;

- second type of issue: preserve the temporal integrity of the modulation signals between the modulator(s) and the power switches.

[0013] WO14207436A1 and W013102779 are examples of post- modulation synchronization systems regarding the above-mentioned second type of issue.

[0014] The present invention deals with the first type of issue.

[0015] Various concerns are related to the synchronization of the modulation signals, corresponding to different requirements in terms of temporal accuracy. In the context of the present invention, the expression "temporal accuracy" indicates the accuracy with which the phase difference between two signals can be controlled, e.g. mastered and adjusted. This "temporal accuracy" can be also referred to as "timing jitter" or simply "jitter".

[0016] In particular, it is possible to distinguish three different types of requirements for temporal accuracies in a distributed modulation system:

- Type A: when PEBBs, or groups of PEBBS, are operated as distinct converters using low pulse numbers, for instance as paralleled six- or twelve-pulse converters, the necessary accuracy of the synchronization is related to a small fraction of the AC power signal. For instance, assuming a 50 Hz AC signal, this typically results in requirements in the order of 10 us to 1 ms.

- Type B: when PEBBs or groups of PEBBS are constituting a converter with higher pulse numbers, such as for instance PWM-operated converters, the necessary accuracy of the synchronization between the converters is related to a small fraction of the switching frequency. For instance, assuming an apparent switching frequency of 2 kHz, this typically results in requirements in the order of 500 ns to 10 us. These concerns are also applicable between the switching cells constituting multilevel converters.

- Type C: when power semiconductor switches must be directly operated in series or in parallel, the necessary accuracy of the synchronization is related to a small fraction of the switching transition time (from OFF to ON state, or vice-versa). For instance, an accuracy of 50 ns or better is necessary to operate parallel- or series-connected switches without much additional measures. [0017] The "temporal accuracy" required in a distributed modulation system for power applications must therefore be better than 1 ms, and often in the order of magnitude from a few tens to a few hundreds of nano-seconds.

[0018] The most obvious approach to synchronize the operation of multiple modulators is to distribute a common clocking signal to each of them using a dedicated electrical or optical line. In any case, this signal corresponds to an extra-wire which must be added to the communication channel that already exists between the modulators.

[0019] This approach is employed for example in DE102013106006, where the frequency of the distributed clock signal is similar to that of the AC power signal, hence achieving a synchronization of type A described here above.

[0020] Alternatively, a clock signal with a frequency similar to that of the switching frequency can be carried to the PEBB controllers.

Synchronization of type B here above can hence be achieved. [0021] The number of signals that must be produced by the control stage increases with the number of PEBBs. Therefore, in large systems, if extra synchronization signals must be present, this involves a prohibitive number of wires to the PEBBs. [0022] Instead of distributing a common clock signal, the

synchronization may be achieved through a communication channel, combined with a suitable synchronization protocol. PTP over Ethernet is an example of such a synchronization protocol and communication channel, respectively. [0023] In large systems with a high number of PEBBs, the

synchronization protocol requires a significant amount of data to be transmitted continuously, hence reducing the available bandwidth for more useful information exchanges (payload).

[0024] Alternatively, more specialized techniques can be set up. For instance, EP2800262 describes a control stage for commanding N power converters. The invention is however limited to a synchronization of type B here above, and the generation of phase-shifted carriers, shifted by 360/N degrees.

[0025] That said, in all the above cases, the slave circuits (i.e. the PEBBs and their modulators) possess their own individual clocking resources (oscillators, crystals, etc.) and are therefore clocked on separated time bases. Consequently, they inherently belong to separated clock domains and constitute a set of plesiochronous systems.

[0026] In the context of the present invention, the expression "the circuits belong to separated clock domains" designates that those circuits do not share a common time basis. As a consequence, their clocks are drifting, since their frequencies are not strictly equal. In order for two clocks to belong to the same clock domain, they must either be generated from the same source or the clocks have a constant phase relationship and a low relative jitter. [0027] As clock drift phenomena are unavoidable between systems that belong to separated clock domains, a periodic or constant

resynchronization is mandatory between modulators that belong to separated clock domains. [0028] In plesiochronous systems, the more accurate is the desired synchronization, the more frequent the synchronization protocol must be run or the less the different clock domains must drift between each other. This implies either very precise and expensive clocking resources, or intense re-synchronization efforts. [0029] Therefore, none of those prior art solutions is adapted to modern modular power conversion systems comprising a large number of power electronic building blocks and high requirements with respect to the temporal accuracy of the synchronization.

[0030] Moreover, none of those prior art solutions guaranties a temporal accuracy of 50 ns or better, which is necessary to operate parallel- or series-connected switches without much additional measures.

[0031] EP24081 10 describes a power conversion device, and more particularly inverters and their controllers. Power is transmitted from an AC source to a motor via a plurality of parallel individual drives, each drive comprising an inverter. Optical fibers or conductors link a control circuit to the inverters. A periodic synchronisation pulse is transmitted to the power layer circuitry of each of the parallel inverters to synchronize the operation and data transfer for each of the parallel inverters. The document recognizes that drifts or differences in pulse frequencies from local oscillators in the processing circuitry of the power layer circuitry can cause, over time, a loss of synchronicity between synchronization pulses and then errors. Therefore, data for synchronization are embedded in the data provided along the optical fibers or conductors linking the control circuit to the drives. This data allows for clock data recovery at the power layer inside the inverters. Based on the clock data recovery at the power layer, the power layer circuitry of each inverter periodically corrects the drifts of its local oscillator by adding or subtracting a clock cycle.

Brief summary of the invention

[0032] It is therefore an aim of the present invention to propose a distributed modulation system and method in which the modulated signals can be controlled with a high temporal accuracy, for example an accuracy of 50 ns or better.

[0033] Another aim is to propose a distributed modulation system and method in which no dedicated line carrying a synchronization signal is necessary.

[0034] Another aim is to propose a distributed modulation system and method in which the synchronization consumes less data communication bandwidth than the known solutions.

[0035] Another aim is to propose a distributed modulation system and method that offers a complete flexibility in the configuration of the carrier frequencies and relative phases among the distributed modulators.

[0036] According to the invention, these aims are achieved by means of an endnode for a distributed modulation system for power electronic applications, comprising:

- at least a transceiver configured for receiving control data from a control master via at least one data transmission channel embedding a reference clock signal generated by the control master, the control data comprising at least one set of modulation parameters, the control master being configured for generating an interrupt signal based on the reference clock signal,

- a clock recovery module configured for recovering a recovered clock signal from the data transmission channel,

- a modulator configured for generating at least one periodic carrier based on said recovered clock signal, and for generating modulation signals based on the set of modulation parameters and on said at least one periodic carrier,

- a supervisory module configured for mastering and adjusting an initial phase difference between said at least one periodic carrier and said interrupt signal.

[0037] In the context of the present invention, the term "endnode" designates a circuit belonging to the control stage of a power converter, and configured to communicate with the power stage of such a converter, e.g. with a PEBB. In a preferred embodiment, the endnode is physically separated from a PEBB. In another embodiment, an endnode and a PEBB can be integrated in the same circuit or assembly.

[0038] The modulation signals from the endnode are configured for determining the temporal instants of some operations: in a preferred embodiment, they are used for determining the switching instants of power switches of a PEBB connected to the endnode.

[0039] However, in other embodiments wherein the endnode is not connected to a PEBB, the modulation signals can be used for determining temporal instants of some measurements, e.g. the sampling instants of analog-to-digital converters, in the so constituted control infrastructure. [0040] As the generation of the carrier is directly based on the recovered clock signal, the clock signal driving the modulator is syntonous with the reference clock signal of the master control. Therefore, if at least two endnodes according to the invention are present in the distributed modulation system, each of the clock signals driving their modulators is syntonous with the reference clock signal of the control master, so that the clock signals driving the modulators are also syntonous between each other.

[0041] In order for two clocks to be syntonous (i.e. have exactly the same frequency), they must belong to the same clock domain. [0042] In one preferred embodiment, the endnode according to the invention comprises an electric path directly connecting the clock recovery module with the modulator, so that the modulator directly uses the recovered clock signal for generating the carriers. [0043] In one embodiment, the clock recovery module belongs to a PHY circuit. In the context of the present invention, the expression "PHY circuit" designates a circuit implementing physical layer functions (layer 1) according to the OSI model.

[0044] In one embodiment, the endnode according to the invention further comprises a clock cleaning circuit. This clock cleaning circuit can be integrated within the clock recovery module or can be a discrete device.

[0045] In an embodiment, the PHY circuit is associated with a MAC circuit configured to receive the control data including a set of modulation parameters from the PHY circuit, as will be discussed. [0046] In one embodiment, the mastering and adjusting the initial phase difference between the at least one periodic carrier and the interrupt signal is based on the Precision Time Protocol, as defined by the standard IEEE1588.

[0047] The supervisory circuit is arranged for controlling these phase differences with a temporal accuracy of 50 ns or better.

[0048] Two or more endnodes according to the invention therefore: - have their modulators driven by clocks that are syntonous between each other and also syntonous to the reference clock signal of the control master;

- possess a difference of phase between the carriers of their modulators that can be mastered and adjusted. [0049] In the context of the present invention, two periodic signals derived from syntonous clocks and having an adjustable and controlled phase difference are said to be "perfectly synchronous".

[0050] Therefore, in the case of one endnode according to the invention, the carriers of the modulators and the interrupt signal of the control master are "perfectly synchronous".

[0051] If more than one endnode according to the invention are present, the carriers of the modulators of the endnodes are "perfectly synchronous" as each carrier and the interrupt signal of the control master are "perfectly synchronous".

[0052] In one embodiment, the modulator of the endnode according to the invention further comprises a pre-scaling module so as to reduce the frequency of the recovered clock signal by dividing the frequency of the recovered clock signal by an integer number, ranging e.g. from 1 to 10. In other words, each carrier signal may be generated by a counter that is based on an integer sub-multiple of the recovered clock.

[0053] The use of a clock recovery module in each endnode enables using a clock that is recovered from the data transmission network, what allows circumventing the effects of clock drift between the endnodes and between the endnodes and the control master, and therefore allows the distributed modulators to belong to the same clock domain and actually use a common time basis, defined by the reference clock generated by the control master.

[0054] As a consequence, the distributed modulators may be

synchronized only once, typically during the system start-up, by mastering and adjusting the initial phase difference between the carriers and the interrupt signal, i.e. the phase difference between the carriers and the interrupt signal during the system start-up. Therefore, practically no data bandwidth is consumed by the synchronization mechanisms during runtime. [0055] As a consequence, the accuracy of the obtained synchronization can be equal or better than 50 ns and allows for synchronizations of type C described above.

[0056] As a consequence, the clock signal being embedded in the data transmission network, the synchronization does not require dedicated lines. Therefore, the number of lines that are required is reduced.

[0057] In the context of the application, the term "embedding" means integrating as an inherent part. Therefore, a clock signal which can be recovered from the transitions in a data transmission channel is said to be embedded into that data transmission channel. The same holds for a set of data transmission channels, i.e. a data transmission network.

[0058] According to an independent aspect of the invention, at least one signal transmitted from the transceiver of the endnode according to the invention to the control master via the data transmission network may be clocked on a clock signal that is different from the recovered clock signal.

[0059] At least one special network switch may be arranged in the data transmission network formed by one or more data transmission channels between at least one control master and at least one endnode. The modulation parameters as well as other data may be routed through this special network switch. This facilitates the connection of the different endnodes in the system.

[0060] In case a special network switch is present in the data

transmission network, that special switch must convey the embedded reference clock signal sourced by the control master, at least for the data transiting from the control master to the endnodes. Besides, some

processing of the data packets such as for example a special aggregation and disaggregation may be necessary in order to reduce their size and hence reduce the minimum data transmission delays in the network. [0061] In one preferred embodiment, the number of PHY circuits in each endnode depends on the number of control masters to which the endnode must be connected. In such a case, the endnode can comprise a multiplexer configured for multiplexing the signals from the PHY circuits. [0062] In one embodiment of the invention, at least two control masters may be used, hence disseminating at least two different reference clock signals into at least two distinct data transmission networks. In this case, the supervisory module is also configured responsible for selecting only one recovered clock signal, the selection being performed according to some fall-back or fault-tolerance criteria related to redundant mode operation.

[0063] In this case, each endnode must possess at least two clock recovery circuits to extract the at least two clocks and select one of them to drive the modulator. This allows using a multiplexer to swap from one control master to another for redundancy purposes. When at least two control masters, and hence reference clocks, are used, all endnodes must utilize the same reference clock recovered from the same network.

Otherwise, a perfect synchronization of the carriers cannot be achieved.

[0064] In one embodiment, the endnode according to the invention further comprises a MAC circuit configured to receive the modulation parameters and other control data from the PHY circuit. In the context of the present invention, a "MAC circuit" is a circuit implementing the media access control of the OSI model.

[0065] Therefore, in one embodiment, the supervisory circuit of the endnode is configured also to observe the recovered clock signals and data outputs of the MAC circuits so as to detect defects in the primary network and swap to a secondary network by means of the multiplexer. This multiplexer may also be acting at a different point of the data path, such as for instance between the PHY and MAC circuits.

[0066] In one embodiment, the endnode according to the invention further comprises a DMA circuit configured to receive the modulation parameters and other control data from the MAC circuit. In the context of the present invention, a "DMA circuit" is a circuit implementing the layers 3 to 7 of the OSI model.

[0067] The present invention also concerns a distributed modulation system for power electronic applications, comprising:

- at least one control master comprising

- a timebase generator configured for generating a reference clock signal,

- at least one supervisory controller configured for generating at least one set of modulation parameters,

- at least one endnode according to the invention,

- at least one data transmission channel connecting the at least one endnode with at least one control master.

[0068] Advantageously, the clock signal driving the modulator, i.e. the clock serving as a time base to the modulator, is the recovered reference clock signal of the control master.

[0069] In one preferred embodiment, the system comprises at least two endnodes, the clock signal for generating the carriers in each endnode being the recovered clock signal, which is syntonous with the reference clock signal.

[0070] In one preferred embodiment, the system comprises at least one power electronic building block connected to at least one endnode, the modulation signal(s) being configured for determining the switching instants of power switches of a PEBB connected to this endnode. [0071] In one preferred embodiment, at least one PEBB is constituting or is part of a multilevel converter.

[0072] In one preferred embodiment, the data transmission channels are based on fibre-optical links capable of more than one Gigabit per second of raw data bandwidth. [0073] In one preferred embodiment, the data transmission channels are Ethernet-type channels.

[0074] In one preferred embodiment, the system comprises two or more control masters, each control master generating a reference clock signal (RefCLK_A, RefCLK_B).

[0075] The present invention concerns also a method for a distributed modulation system for power electronic applications, comprising the following steps:

- generating a reference clock signal by using a timebase generator of at least one control master, each control master being configured to generate one reference clock signal;

- generating an interrupt signal based on the reference clock signal;

- generating at least one set of modulation parameters by using at least one supervisory controller of the control master;

- transmitting this set of modulation parameters through at least one data transmission channel that embeds the reference clock signal to an endnode comprising a clock recovery module and a modulator;

- recovering the reference clock signal from the data transmission channel by using the clock recovery module;

- receiving the at least one set of modulation parameters from the control master signal;

- generating at least one periodic carrier based on the recovered clock signal;

- mastering and adjusting an initial phase difference between the at least one periodic carrier and the interrupt signal by a supervisory module;

- generating modulation signals based on the periodic carriers and the set of modulation parameters; the modulation signals being configured for determining the temporal instants of some operations, e.g. for determining the switching instants of power switches of a PEBB connected to the endnode. [0076] In an embodiment, the initial synchronization of the carriers is achieved by means of an algorithm based on the Precision Time Protocol (PTP), as defined by the standard IEEE1588.

Brief Description of the Drawings [0077] The invention will be better understood with the aid of the description of an embodiment given by way of example and illustrated by the figures, in which:

Fig. 1 schematically illustrates a distributed modulation system.

Fig. 2 schematically illustrates an endnode. Detailed Description of possible embodiments of the Invention

[0078] Figure 1 schematically illustrates an example of a modular power converter 2 using a distributed modulation system. This example comprises two control masters 10, multiple data transmission channels 201 , some special network switches 20 and a plurality of endnodes 30, some of which are connected to power electronic building blocks 40 (PEBBs). The purpose of this system is to convert one or a plurality of power signals into one or a plurality of power signals with different frequency, phase or amplitude. The number of endnodes and PEBBs in the system might be comprised between 1 and 200 or more. [0079] For example, the power conversion system might establish one or a plurality of DC-to-AC, DC-to-DC, AC-to-DC or AC-to-AC converters, or any combination thereof.

[0080] Some of the components of the power conversion system may be implemented as modular building blocks, for example mounted in one or a plurality of racks and cabinets. Different components may be mounted in different rooms or locations. [0081] The different endnodes may be independent units and may by arranged at physically distant locations, such as for example throughout large wind or solar farms.

[0082] The control masters 10 comprise one or a plurality of supervising controllers 100. The supervising controller 100 generates commands for the endnodes 30, including at least one set of modulation parameters for the distributed modulators. The supervising controller also generates other parameters, commands, control data and signals for controlling and configuring the endnodes 30. The supervising controller further receives data from the endnodes 30, such as measure and feedback data, and adapt the control in response to this feedback.

[0083] The control master 10 further comprises a timebase generator

101 for generating a reference clock signal RefCLK. The timebase generator may be a standalone circuit, or be embedded as part of one of the supervising controllers.

[0084] The control master 10 further comprises an interrupt generator

102 for generating an interrupt signal transmitted to the supervising controllers 100. This signal serves to determine at which instants some processing and control routines must be executed. It is generated based on the reference clock signal RefCLK.

[0085] The control masters 10 may be for example based on suitably programmed and adapted "BoomBox" units as provided by the applicant. When applicable, several "BoomBox" units may also be stacked, hence constituting the multiple supervising controllers 100 of a given control master 10.

[0086] At least two networks A, B may be built around at least two control masters 10 in order to provide redundancy. In fact, the so- constituted secondary network B is used as a fall-back system in case of defective operation of the primary network A. Accordingly, at least two networks disseminating two different reference clocks RefCLK_A and RefCLK_B are hence implemented.

[0087] The supervising controller 100 comprises a network interface, for example a Gigabit Ethernet interface, and sends at least one set of modulation parameters as well as other control data as packets over the data transmission channels 201. Its network interfaces are syntonized to the reference clock signal RefCLK and therefore send data packets that are directly clocked with this reference clock signal. The clock signal RefCLK is thus embedded into the data transmission channels 201. [0088] A plurality of supervising controllers 100 may be used in a given control master 10 for adding redundancy, for increasing the bandwidth and the number of commands which can be generated during a given unit of time, or for increasing the number of data transmission channels which can be handled. [0089] The special network switches 20 are responsible for conveying control data between the supervising controllers 100 and the endnodes 30, and vice-versa. To do so while guaranteeing low transmission delays, the special network switches 20 may aggregate and disaggregate data packets in order to circumvent some limitations such as for example related to minimum packet length.

[0090] Furthermore, the special network switches 20 guarantee the dissemination of the reference clock RefCLK across the entire network. To do so, they must repeat the embedded clock received from the control master 10 on the ports connecting to the endnodes 30. On the other hand, they do not need to recover any clock coming from the endnodes 30, nor to reuse it to transmit data back to the control master.

[0091] The endnodes 30 will be described in more details in relation to Figure 2. The purpose of these circuits 30 is to receive the modulation parameters and other control data from the supervising controllers 100, to conduct the modulation e.g. in order to control the corresponding power switches 40, and to transfer back some other control data to their supervising controller 100.

[0092] In some cases, the endnodes 30 may also be responsible for carrying some of the control tasks that are otherwise handled by the supervisory controllers 100, hence relieving the latter from some of their duties.

[0093] The modulation parameters that are received might be typical parameters for a pulse width modulation strategy such a frequency, duty cycle, phase shift, blanking time, etc. or any other kind of modulation parameters. They can for instance also refer to optimized pulse patterns that are locally stored in look-up tables.

[0094] The power electronic building blocks 40 receive the modulation signals on modulation channels 401 as well as other input/output signals on I/O channels 402 generated by the endnodes 30 and are responsible to actually convert and deliver the power signals (not shown). Each PEBB 40 in this example comprises at least one power semiconductor switch. In one preferred embodiment, each PEBB 40 comprises a plurality of power semiconductor switches.

[0095] In general, one endnode 30 is physically attached to one power electronic building block 40. However, other configurations are also possible such as for instance using some endnodes 30 that may not be connected to a PEBB 40, but that only use their distributed modulators as clocking and synchronization resources, for instance in order to guarantee the synchronism of some measurements with the operation of the power switches.

[0096] In some cases, the endnode 30 and the PEBB 40 may be physically distant.

[0097] Each PEBB 40 comprises one or a plurality of power

semiconductor switches, such as without restriction IGBTs, IGCTs, GTOs, thyristors, etc. The shape of the output power signal is determined by the switching instants of those components, which are determined by the modulation signals sent by the distributed modulators over the modulation channels 401. [0098] Depending on the organization of the system and on the modulation parameters sent by the supervising controllers, the system may realize a variety of functions, including for example a pulse width modulated multilevel power conversion system.

[0099] Figure 2 schematically illustrates an example of an endnode 30. The illustrated circuit includes the connectivity to two data transmission channels 201 , each involving a PHY circuit 300 and a MAC circuit 301. It also comprises a modulator 302, a DMA circuit 303 as well as other peripherals 306. Besides, a supervisory module 304 and a multiplexor 305 are also present for selecting which recovered clock and data transmission channel should be used. In the illustrated embodiment, all circuits are integrated into a single chip, for example into an ASIC or FPGA. Other combinations are possible.

[00100] The PHY circuits 300 interface between the medium-dependent analog domain of the data transmission channels 201 and the digital domain of link-layer packet signalling. They encode and decode the data that are transmitted and received and implement the hardware send and receive function of data packets.

[00101] In one embodiment, the physical medium 201 is a Gigabit Ethernet (GbE) optical fibre cable. In this case, the endnode 30 may comprise a transceiver, such as an SFP transceiver, to convert the serial electrical signals to serial optical signals and vice versa.

[00102] The PHY circuit 300 includes a clock recovery module (not illustrated) so as to recover the reference clock from the data transiting on the data transmission channel and provide it to an rCLK output. In one embodiment, the clock recovery module may include a clock cleaning circuit, involving for instance a PLL.

[00103] The PHY circuit 300 may be integrated as a single PHY chip with clock recovery functionalities, or as a combination of a PHY chip and a separate clock recovery module.

[00104] The PHY circuit 300 may deliver other signals, including

functionalities related to the Precision Time Protocol (PTP) as defined by the standard IEEE1588.

[00105] The MAC circuit 301 receives data from the PHY circuit 300, detects packet boundaries, assembles bits into packets, validates them and undertakes some processing tasks.

[00106] The modulator 302 receives the recovered clock signal rCLK from the PHY circuit and data from the MAC circuit 301. Data received from the MAC circuit include the modulation parameters and other configuration data.

[00107] The modulation parameters can be used to determine the switching instants of the power switches, and thus determine the shape of the output signals of the power converter. For example, the modulation parameters determine the pulse widths in a pulse width modulation scheme.

[00108] In one preferred embodiment, the modulation parameters are updated frequently, such as for example with a refreshing rate of 0.05 kHz to 100 kHz in order to produce useful modulation signals.

[00109] In an embodiment, a DMA circuit 303 is used to processes the control data received from and sent to the MAC circuit 301. It typically implements the control layers 3 to 7 according to the OSI model. This circuit may also be responsible for ascertaining the temporal integrity of the data, such as evaluating the timestamps of each data packet against a given temporal validity.

[00110] The supervisory module 304 is responsible for the initial synchronization of the carriers present in the modulator 302 with the interrupt signal generated by the interrupt generator 102. To this end, it observes the value(s) of counters based on the recovered clock signal(s) and produces a synchronization strobe (SYNC sur la Fig. 2) for the modulator 302 and other peripherals 306. These counters may be provided by either the PHY 300 or the MAC circuit 301. [00111] This initial synchronization is always achieved during the initialization procedure of the endnode 30. It may also be achieved periodically if necessary.

[00112] In an embodiment, when redundant networks are used, the supervisory module 304 also observes the recovered clock signals as well as the data signals so as to evaluate the integrity of a given network. When necessary, the supervisory module 304 triggers the multiplexer 305 so as to switch from one network to another.

[00113] When present, the other peripherals 306 contain the necessary circuits to handle the rest of the input/output connectivity of the endnode 30 as well as its other processing tasks. This block is related to additional I/O signals and can also communicate with the supervising controllers 100 by the same means as for the modulators 302.

Reference numbers used in the Figures

1 Control stage

2 Power stage

10 Control master

20 Special network switch

30 Endnode

40 PEBB

100 Supervising controller

101 Timebase generator

102 Interrupt generator

201 Data transmission channel

300 PHY circuit

301 MAC circuit

302 Modulator

303 DMA circuit

304 Supervisory module

305 Multiplexer

306 Other peripherals

401 Modulation channels

402 Additional I/O channels

Claims

1. Endnode (30) for a distributed modulation system for power electronic applications, comprising:

- at least a transceiver for receiving control data from a control master (10) via at least one data transmission channel (201) embedding a reference clock signal (RefCLK) generated by said control master (10), said control data comprising at least one set of modulation parameters, said control master (10) being configured for generating an interrupt signal based on said reference clock signal (RefCLK),

- at least one a clock recovery module, arranged for recovering a recovered clock signal (rCLK) from said data transmission channel,

- a modulator (302) arranged for generating at least one periodic carrier by using said recovered clock signal (rCLK), and for generating modulation signals (401) based on said set of modulation parameters and on said at least one periodic carrier,

- a supervisory module configured for mastering and adjusting an initial phase difference between the at least one periodic carrier and said interrupt signal,

said modulation signals being configured for determining temporal instants of some operations, e.g. for determining the switching instants of at least one power switch of a PEBB (40) connected to said endnode.

2. Endnode according to claim 1 , comprising an electric path directly connecting the clock recovery module with said modulator (302), so that said modulator (302) directly uses said recovered clock signal (rCLK) for generating said periodic carriers.

3. Endnode according to one of claims 1 or 2, wherein said recovered clock signal (rCLK) is syntonous with said reference clock signal (RefCLK).

4. Endnode according to one of the previous claims, wherein said supervisory module is arranged for controlling said phase difference with an accuracy of 50 ns or better.

5. Endnode according to one of the previous claims, comprising at least one PHY circuit (300) comprising said at least one clock recovery module.

6. Endnode according to the previous claim, the number of said PHY circuits (300) depending on the number of control masters (10) which said endnode (30) is meant to be connected to.

7. Endnode according to one of claims 5 to 6, further comprising at least one MAC circuit (301) configured to receive the control data including a set of modulation parameters from the PHY circuit(s) (300).

8. Endnode according to the previous claim, comprising at least two PHY circuits (300) and/or at least two MAC circuits (301) and a multiplexer (305) configured for multiplexing signals from said PHY circuits (300) and/or from said MAC circuits, the supervisory module (304) being configured for selecting the utilized PHY and/or MAC circuits.

9. Endnode according to one of claims 7 to 8, comprising a DMA circuit (303) configured to receive the modulation parameters and other control data from the MAC circuit.

10. A distributed modulation system for power electronic applications, comprising:

- at least one control master (10) comprising

- a timebase generator (101) configured for generating a reference clock signal (RefCLK),

- at least one supervisory controller (100) configured for generating at least one set of modulation parameters,

- at least one interrupt generator (102) configured for generating an interrupt signal,

- at least one endnode (30) according to one of the claims 1 to 9,

- at least one data transmission channel (201) connecting the at least one endnode (30) with at least one control master (10).

1 1. The system according to the previous claim, further

comprising at least one power electronic building block (40) connected to at least one endnode (30), said power electronic building block (40) comprising at least one power switch, said modulation signals (401) being configured for determining of the switching instants of the at least one power switch.

12. The system according to the previous claim, wherein at least one PEBB (40) is constituting or is part of a multilevel converter.

13. The system according to one of the claims 10 to 12, wherein the data transmission channel (201) are based on fibre-optical links.

14. The system according to the previous claim, wherein the data transmission channel (201) is an Ethernet-type channel.

15. The system according to one of the claims 10 to 14, wherein at least one transceiver of at least one endnode (30) is configured for using a clock that is different from said recovered clock signal (rCLK) to transmit data back to the control master (10).

16. The system according to one of the claims 10 to 15,

comprising two or more control masters (10), each control master (10) generating a reference clock signal (RefCLK_A, RefCLK_B), the supervisory module (304) of said endnode (30) further being configured for selecting only one recovered clock signal (rCLK), the selection being performed according to fault-tolerance criteria.

17. The system according to one of the claims 10 to 16,

comprising at least one network switch (20) configured for conveying control data between the supervising controller(s) (100) and the endnode(s) 30.

18. A method for a distributed modulation system for power electronic applications, comprising the following steps: - generating a reference clock signal (RefCLK) by using a timebase generator (101) of a control master (10);

- generating an interrupt signal based on the reference clock signal by using an interrupt generator (102) of said control master;

- generating at least one set of modulation parameters by using at least one supervisory controller (100) of the control master;

- transmitting this set of modulation parameters through at least one data transmission channel (201) that embeds the reference clock signal (RefCLK) to an endnode (30) comprising a clock recovery module and a modulator (302);

- generating at least one periodic carrier based on the recovered clock signal;

- mastering and adjusting an initial phase difference between the at least one periodic carrier and the interrupt signal by a supervisory module (304);

- generating modulation signals based on the periodic carriers and the set of modulation parameters, the modulation signals being configured for determining the temporal instants of some operations, e.g. for determining the switching instants of at least one power switch of a PEBB connected to the endnode.