WO2014111595A1

WO2014111595A1 - A multilevel converter with hybrid full-bridge cells

Info

Publication number: WO2014111595A1
Application number: PCT/EP2014/051142
Authority: WO
Inventors: Alireza NAMI; Frans Dijkhuizen; Jiaqi Liang; Liwei Wang; Tomas Jonsson
Original assignee: Abb Technology Ltd
Priority date: 2013-01-21
Filing date: 2014-01-21
Publication date: 2014-07-24

Abstract

A multilevel converter (10) converting between AC and DC comprises a phase arm with a number of cells between a DC pole (P1and an AC terminal (AC1), the cells comprise at least one hybrid full bridge cell (HFBA) including a first cell connection terminal for coupling to the DC pole,a second cell connection terminal for coupling to the AC terminal,an energy storage element (C) having a positive and a negative end, a first group of series connected semiconducting units (S1, S2) in parallel with the energy storage element (C), where a junction between these forms one cell connection terminal, and a second group of series connected semiconducting units in parallel with the energy storage element (C) and comprising a third semiconducting unit (S3) and a fourth semiconducting unit consisting of a number of unidirectional conducting elements comprising at least one unidirectional conducting element(D), where a junction between these forms a further cell connection terminal.

Description

A MULTILEVEL CONVERTER WITH HYBRID FULL-BRIDGE CELLS

FIELD OF INVENTION The present invention generally relates to multilevel converters. More particularly the present invention relates to a multilevel converter configured to convert between alternating current and direct current.

BACKGROUND

Multilevel converters are of interest to use in a number of different power transmission environments. They may for instance be used as voltage source

converters in direct current power transmission systems such as high voltage direct current (HVDC) and

alternating current power transmission systems, such as flexible alternating current transmission system

(FACTS) . They may also be used as reactive compensation circuits such as Static VAR compensators.

In order to reduce harmonic distortion in the output of power electronic converters, where the output voltages can assume several discrete levels, so called

multilevel converters have been proposed. In

particular, converters where a number of cascaded converter cells, each comprising a number of switching units and an energy storage unit in the form of a DC capacitor have been proposed.

Examples of such converters can be found in

Marquardt, ' ew Concept for high voltage-Modular multilevel converter', IEEE 2004, A. Lesnicar, R.

Marquardt, "A new modular voltage source inverter topology", EPE 2003, WO 2010/149200 and WO 2011/124260. Converter elements in such a converter may for instance be of the half-bridge, full-bridge or clamped double cell type.

A half-bridge connection in upper and lower arms provides unipolar cell voltage contributions and offers the simplest structure of the chain link converter. This type is described by Marquardt, ' ew Concept for high voltage-Modular multilevel converter' , IEEE 2004 and A. Lesnicar, R. Marquardt, "A new modular voltage source inverter topology", EPE 2003.

However, there is a problem with the half-bridge topology in that the fault current blocking ability in the case of a DC fault, such as a DC pole-to-pole or a DC pole-to-ground fault, is limited.

One way to address this is through the use of full- bridge cells. This is described in WO 2011/012174.

Series connection of full-bridge cells offers four quadrant power flows through the energy storage element of the cell capacitor as well as DC fault voltage blocking capability by imposing a reverse voltage.

However, the use of full-bridge cells doubles the number of components compared with a half-bridge cell.

One way to reduce the number of components combined with a retained fault current limiting ability is through mixing the cells of the half- and full-bridge type. Half of the cells may then be full-bridge cells used for imposing the reverse voltage due to the rating of the cascaded converter cells. This is for instance described in WO 2011/042050. The mixing of cells reduces the number of components further while

retaining a good fault current limitation ability.

It is also possible to use a hybrid of the full bridge cell. A hybrid cell is described in WO 2011/124258. Here one of the switches in each of two groups of switches has been replaced by a diode. This cell is able to provide voltage contributions with two

different polarities. However, this type of cell only allows two quadrant operation. Furthermore, it is only able to be used with one current conduction direction.

However there is still room for improvement with regard to component reduction combined with fault current limitation .

SUMMARY OF THE INVENTION

The present invention is directed towards reducing the number of components in a voltage source converter combined with providing sufficient fault current limitation .

This object is according to a first aspect achieved through a multilevel converter configured to convert between alternating current and direct current and comprising

at least one phase arm with a number of cells between a DC pole and a first AC terminal, the cells comprising at least one hybrid full-bridge cell for fault current handling operation,

said hybrid full-bridge cell comprising

a first cell connection terminal for coupling to the DC pole,

a second cell connection terminal for coupling to the AC terminal,

an energy storage element having a positive and a negative end,

a first group of series connected semiconducting units, which group is connected in parallel with the energy storage element and where the semiconducting units of the first group comprises first and second switching elements with first and second anti-parallel

unidirectional conducting elements, where a junction between the first and second semiconducting unit forms one cell connection terminal,

a second group of series connected semiconducting units, which group is connected in parallel with the energy storage element as well as with the first group and where all the semiconducting units of the second group are connected in series and the second group comprises a third semiconducting unit having a third switching element with anti-parallel unidirectional conducting element and a fourth semiconducting unit consisting of at least one unidirectional conducting element, where a junction between the first and second semiconducting unit forms a further cell connection terminal .

Another object is to enable injection of reactive power into an AC network connected via the AC terminals of the multilevel converter according to the first aspect. This object is according to a second aspect achieved through the multilevel converter comprising a control unit configured to control, when there is a pole fault on a phase leg in which said phase arm is connected, a phase arm current to zero when there is a negative phase arm voltage during injection of reactive power through the first AC terminal. This object is according to the second aspect also achieved through a method of controlling a phase arm of a phase leg in a voltage source converter according to the first aspect, the method comprising

controlling, when there is a pole fault on a pole of a phase leg in which said phase arm is connected, a phase arm current to zero when there is a negative phase arm voltage during injection of reactive power through the first AC terminal. The phase arm of the first aspect may be a first phase arm in a phase leg between a first pole and a first AC terminal, which phase leg may further comprise a second phase arm between the first AC terminal and ground. Yet another object is to enable a reduction of the converter voltage rating required for a phase arm in order to handle AC phase faults.

This object is according to a third aspect achieved through the energy storage elements of all the

converter cells of the second phase arm being

configured to be bypassed in case of a phase fault on the AC side of the multilevel converter. This object is according to the third aspect also achieved through a method for reducing the voltage rating required for a phase arm comprising controlling the energy storage elements of all the converter cells of the second phase arm to be bypassed in case of a phase fault on the AC side of the multilevel converter.

The first aspect has a number of advantages. It

provides equal fault limiting capability as similar conventional converter structures with a reduced number of components. The hybrid full-bridge cells can also be used with dual current conduction directions. This is combined with a modular cell structure with low

complexity and low costs. Another advantage is that the number of control signals needed for controlling the cell are reduced.

The second aspect has the advantage of allowing

reactive power control to be performed in addition to the DC fault current blocking ability.

The third aspect also has a number of advantages in addition to having fault current blocking capability. It reduces the overvoltage experienced by the first phase arm in case of AC faults. Thereby the converter can be made considerably smaller while still allowing the AC phase faults be handled safely. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will in the following be

described with reference being made to the accompanying drawings, where fig. 1 schematically shows a cell-based voltage source converter connected between two poles,

fig. 2 schematically shows the structure of a first type of hybrid full-bridge cell,

fig. 3 schematically shows the structure of a first type of half-bridge cell,

fig. 4 schematically shows the structure of a second type of hybrid full-bridge cell,

fig. 5 schematically shows the structure of a second type of half-bridge cell,

fig. 6 schematically shows a first realization of a voltage source converter phase leg employing hybrid full-bridge cells of the first and second type and half-bridge cells of the first and second type, fig. 7 schematically shows a fault current path through an upper phase arm of the converter of fig. 6 in case of a first pole-to-ground fault occurring with a positive AC voltage,

fig. 8 schematically shows a fault current path through the upper phase arm of the converter of fig. 6 in case of the first pole-to-ground fault occurring with a negative AC voltage,

fig. 9 schematically shows a fault current path through a lower phase arm of the converter of fig. 6 in case of a second pole-to-ground fault occurring with a negative AC voltage, fig. 10 schematically shows a fault current path through the lower phase arm of the converter of fig. 6 in case of the second pole-to-ground fault occurring with a positive AC voltage,

fig. 11 schematically shows the structure of a third type of hybrid full-bridge cell,

fig. 12 schematically shows the structure of a fourth type of hybrid full-bridge cell,

fig. 13 shows various voltages and currents when injecting reactive power to an AC system connected to the converter during a pole fault,

fig. 14 schematically shows a control unit of the converter,

fig. 15 schematically shows a PQ control element of the control unit,

fig. 16 schematically shows a circulating current generating element of the control unit,

fig.17 schematically shows a circulating current control element of the control unit,

fig. 18 shows an equivalent circuit for the converter in fig. 1 with blocked switches during an AC phase fault in the connected AC system,

fig. 19 shows an alternative converter configuration for reducing the required converter voltage rating, which converter is realized as an asymmetric monopole converter,

fig. 20 schematically shows a variation of the hybrid full-bridge cell for use in reducing the required converter voltage rating,

fig. 21 shows an asymmetric monopole converter

employing another variation of the hybrid full-bridge cell , fig. 22 shows a variation of the alternative asymmetric monopole converter configuration employing regular full-bridge cells instead of hybrid-full bridge cells, fig. 23 shows the converter configuration from fig. 22 realized as a symmetrical bipole converter,

fig. 24 shows another variation of the alternative asymmetric monopole converter configuration employing asymmetric monopole mixed cells,

fig. 25 shows the converter structure from fig. 21 but with regular full-bridge cells comprising the bypass switch from fig. 20,

fig. 26 shows the converter structure from fig. 25, but with a bypass switch connected between cell connection terminals ,

fig. 27 shows the converter structure from fig. 25 where the bypass switch is realized as an IGCT, and fig. 28 shows a further converter structure based on clamped double cells with the bypass switch realized as an IGCT.

DETAILED DESCRIPTION OF THE INVENTION

In the following, a detailed description of preferred embodiments of the invention will be given.

Fig. 1 shows one variation of a multilevel converter in the form of a cell based voltage source converter 10. The converter operates to convert between alternating current (AC) and direct current (DC) . The converter 10 in fig. 1 comprises a three-phase bridge made up of a number of phase legs. There are in this case three phase legs. It should however be realized that as an alternative there may be for instance only two phase legs. There is thus a first phase leg PL1, a second phase leg PL2 and a third phase leg PL3. The phase legs are more particularly connected between two DC poles, a first DC pole PI and a second DC pole P2 and the mid points of the phase legs are connected to corresponding alternating current terminals ACA1, ACB1, ACC1. The current la output on the AC terminal ACA1 is also indicated. A phase leg is in this example divided into two halves, a first upper half and a second lower half, where such a half is also termed a phase arm.

The first DC pole PI furthermore has a first potential Vp that may be positive, while the second DC pole has a second potential Vn that may be negative. The first pole PI may therefore also be termed a positive pole, while the second pole P2 may be termed negative pole. These poles may furthermore be part of a DC power transmission system such as a High Voltage Direct

Current (HVDC) power transmission system. The AC terminals AC1, AC2, AC3 may in turn be connected to an AC system, such as a flexible alternating current transmission system (FACTS) , for instance via a

transformer. A phase arm between the first pole PI and a first AC terminal ACA1, ACB1 and ACC1 may be termed a first phase arm or an upper phase arm, while a phase arm between the second pole P2 and a first AC terminal may be termed a second phase arm or a lower phase arm.

As mentioned above, the voltage source converter of fig. 1 is only one example of a multilevel converter where the invention may be used. It is for instance possible to provide the three phase legs in series with each other between the two poles, where these then make up a first set of phase legs. It is then possible to provide a second set of series-connected phase legs in parallel with the first set. In this case the midpoints of the phase legs of the first set forms primary AC terminals and the midpoints of the phase legs of the second set forms secondary AC terminals for the three phases .

The voltage source converter may furthermore be

connected in an asymmetric monopole configuration, in a symmetric monopole configuration or in a symmetric bipole configuration. In an asymmetric monopole

configuration the second pole P2 is in fact no pole but ground, in a symmetric monopole system a mid point of a phase leg between the first and second poles is

grounded, while in a symmetric bipole configuration there would be a third and a fourth phase arm in the phase leg, where the second and third phase arms would be connected to ground, the first phase arm connected between the positive voltage and the second phase arm and the fourth phase arm connected between a negative voltage of the second pole P2 and the third phase arm. A first AC terminal would in the symmetric bipole configuration be provided between the first and second phase arms, while a second AC terminal would be

provided between the third and fourth phase arms.

The phase arms of the voltage source converter 10 in the example in fig. 1 comprise cells. A cell is a unit that may be switched for providing a voltage

contribution to the voltage on the corresponding AC terminal. A cell then comprises one or more energy storage elements, for instance in the form of capacitors, and the cell may be switched to provide a voltage contribution corresponding to the voltage of the energy storage element or a zero voltage

contribution. If more than one energy storage element is included in a cell it is possible with even further voltage contributions.

The cells are with advantage connected in series or in cascade in a phase arm.

In the example given in fig. 1 there are five series- connected or cascaded cells in each phase arm. Thus the upper phase arm of the first phase leg PL1 includes five cells Clpl, C2pl, C3pl, C4pl and C5pl, while the lower phase arm of the first phase leg PL1 includes five cells Clnl, C2nl, C3nl, C4nl and C5nl . The indicia p is here used to indicate that an upper phase arm is connected to a positive pole, while the indicia n is used to indicate that the lower phase arm is connected to a negative pole. Across the cells of the upper phase arm there is a first phase arm voltage Vap and through the upper phase arm there runs a first phase arm current lap, where a denotes the phase and p that the phase arm is connected to a positive pole. Because of this the upper phase arm may also be considered to be a positive phase arm. Across the cells of the lower phase arm there is a second phase arm voltage Van and through the lower phase arm there runs a second phase arm current Ian, where a denotes the phase and n that that the phase arm is connected to a negative pole. The lower phase arm may therefore also be considered to be a negative phase arm. The upper phase arm is

furthermore joined to the AC terminal ACA1 via a first or upper arm reactor Laarml, while the lower phase arm is joined to the same AC terminal ACA1 via a second or lower arm reactor Laarm2. In a similar fashion the upper phase arm of the second phase leg PL2 includes five cells Clp2, C2p2, C3p2, C4p2 and C5p2 while the lower phase arm of the second phase leg PL2 includes five cells Cln2, C2n2, C3n2, C4n2 and C5n2. Finally the upper phase arm of the third phase leg PL3 includes five cells Clp3, C2p3, C3p3, C4p3 and C5p3 while the lower phase arm of the third phase leg PL3 includes five cells Cln3, C2n3, C3n3, C4n3 and C5n3. The upper phase arms are furthermore joined to the corresponding AC terminals ACBl and ACCl via corresponding first or upper arm reactors Lbarml and Lcarml, respectively, while the lower phase arms are joined to the same AC terminal ACBl and ACCl via corresponding second or lower arm reactors Lbarm2 and Lcarm2, respectively.

The number of cells provided in fig. 1 is only an example. It therefore has to be stressed that the number of cells in a phase arm may vary. It is often favorable to have many more cells in each phase arm, especially in HVDC applications. A phase arm may for instance comprise hundreds of cells. There may however also be fewer.

Control of each cell in a phase arm is normally done through providing the cell with a control signal directed towards controlling the contribution of that cell to meeting a reference voltage. The reference voltage may be provided for obtaining a waveform on the AC terminal of a phase leg, for instance a sine wave. In order to control the cells there is therefore a control unit 12.

The control unit 12 is provided for controlling all the phase arms of the converter. However, in order to simplify the figure only the control of the upper phase arm of the first phase leg PL is indicated in fig. 1.

The other phase arms are controlled in a similar manner in order to form output waveforms on the three AC terminals AC1, AC2 and AC3.

The control unit 12 may furthermore be used for some dedicated control with regard to handling of reactive power injection into the AC system or with regard to operation at AC phase faults. These two situations will be described in more detail later.

There are a number of different cell types that can be used in the converter, such as full-bridge cells, half- bridge cells and clamped double cells.

A first aspect of the invention is based on the use of hybrid full-bridge cells. A hybrid full-bridge cell is in the context discussed here defined as a full-bridge cell where one bridge unit comprising at least one switching element anti-parallel unidirectional

conducting element pair is replaced by at least one unidirectional conducting element. A hybrid full-bridge cell in the definition used here is in one specific example thus a full-bridge where one of the switches is replaced by a diode. Thereby the cell can furthermore be termed an asymmetric full-bridge cell or an

asymmetric hybrid full-bridge cell.

Fig. 2 shows a first type of hybrid full-bridge cell HFBA that is to be provided in the upper phase arm of the first phase leg.

The cell HFBA is thus a hybrid full-bridge converter cell and includes an energy storage element, here in the form of a capacitor C, which is connected in parallel with a first group of semiconducting units SUl and SU2. The energy storage element C provides a voltage Udm, and therefore has a positive and negative end, where the positive end has a higher potential than the negative end. The semiconducting units SUl and SU2 in the first group are connected in series with each other. The first group here includes two semiconducting units SUl and SU2 (shown as dashed boxes) . These two semiconducting units SUl and SU2 are here provided as two series-connected switches SI and S2, where each switch may be realized in the form of a switching element that may be an IGBT (Insulated Gate Bipolar Transistor) transistor together with an anti-parallel unidirectional conducting element. In fig. 2 the first semiconducting unit SUl is therefore provided as a first switch SI having a first transistor Tl with a first anti-parallel diode Dl . The first diode Dl is connected between the emitter and collector of the transistor Tl and has a direction of conductivity from the emitter to the collector as well as towards the positive end of the energy storage element C. The second semiconducting unit SU2 is provided as a second switch S2 having a second transistor T2 with a second anti-parallel diode D2. The second diode D2 is

connected in the same way in relation to the energy storage element C as the first diode Dl, i.e. conducts current towards the positive end of the energy storage element C. The first semiconducting unit SU1 is

furthermore connected to the positive end of the energy storage element C, while the second semiconducting unit SU2 is connected to the negative end of the energy storage element C.

There is also a second group of series-connected semiconducting units SU3 and SU4. This second group of semiconducting units is here connected in parallel with the first group as well as with the energy storage element C. The second group includes a third

semiconducting unit SU3 and a fourth semiconducting unit SU4. The third semiconducting unit SU3 is provided as a third switch S3, here provided through a third transistor T3 with anti-parallel third diode D3.

However the fourth semiconducting unit SU4 is not a switch. It only comprises one type of semiconducting element, a unidirectional conduction element, a diode D. The fourth semiconducting unit SU4 thus consists of unidirectional conducting elements, where the number of such elements is at least one. This second group of semiconducting units is thus provided in a further branch in parallel with the capacitor C. The fourth semiconductor unit SU4 is furthermore connected to the positive end of the energy storage element C, while the third semiconducting unit SU3 is connected to the negative end of the energy storage element C. Both the diodes D3 and D furthermore have a direction of current conduction towards the positive end of the energy storage element C. The semiconducting units in the second group are thus connected in series with each other. The second group furthermore consists of or only comprises these series-connected semiconducting units. Furthermore, there is no other semiconducting unit connected in parallel with the fourth semiconducting unit .

This first type of hybrid full-bridge cell HFBA

comprises a first cell connection terminal TEFBAl and a second cell connection terminal TEFBA2, each providing a connection for the cell to the upper phase arm of the first phase leg of the voltage source converter. In this first type of hybrid full-bridge cell the first cell connection terminal TEFBAl more particularly provides a connection from the upper phase arm to the junction between the first and the second

semiconducting units SU1 and SU2, while the second cell connection terminal TEFBA2 provides a connection between the upper phase arm and a connection point between the third and fourth semiconducting units SU3 and SU4. The junction between the first and second semiconducting units SU1 and SU2 thus provides one cell connection terminal TEFBAl, while the junction between the third and fourth semiconducting units SU3 and SU4 provides a further cell connection terminal TEFBA2. These connection terminals TEFBAl and TEFBA2 thus provide points where the cell HFBA can be connected to the upper phase arm of the first phase leg. The first cell connection terminal TEFBAl thereby joins the upper phase arm with the connection point or junction between two of the series-connected switches of the first group, here the first and second switches, while the second cell connection terminal TEFBA2 joins the upper phase arm with a connection point between two of the series connected semiconducting units of the second group, here between the third switch and the sole diode D. The first cell connection terminal TEFBA1

furthermore faces the first pole and thereby couples the cell to the first pole, while the second cell connection terminal TEFBA2 faces the AC terminal of the phase leg and thereby couples the cell to the AC terminal. Thereby the further diode D also couples the second cell connection terminal TEFBA2 to the positive end of the energy storage element.

The expression couple or coupling is intended to indicate that more components, such as more cells and inductors, may be connected between the pole and the cell, while the expression connect or connecting is intended to indicate a direct connection between two components such as two cells. There is thus no

component in-between two components that are connected to each other.

Fig. 3 schematically shows a first type of half-bridge converter cell HBA that may be used in the upper phase arm of the first phase leg. Also this cell includes an energy storage element, here in the form of a capacitor C, which is connected in parallel with a group of switches. Also this energy storage element C provides a voltage Udm, and thus also has a positive and negative end, where the positive end has a higher potential than the negative end. The switches in this group are connected in series with each other. The group here includes a fourth and a fifth switch S4 and S5 (shown as dashed boxes), where each switch S4, S5 may be realized in the form of a switching element that may be an IGBT (Insulated Gate Bipolar Transistor) transistor together with an anti-parallel unidirectional

conduction element, which may be a diode. In fig. 3 there is therefore a fourth switch S4 having a fourth transistor T4 with a fourth anti-parallel diode D4, where the diode D4 has a direction of current

conduction towards the positive end of the energy storage element C and a fifth switch S5 connected in series with the fourth switch S4 and having a fifth transistor T5 with anti-parallel diode D5, where the diode D5 has the same direction of current conduction as the fourth diode D4. The fourth switch S4 is connected to the positive end of the energy storage element C, while the fifth switch S5 is connected to the negative end of the energy storage element C.

This first type of half-bridge cell HBA also comprises a first cell connection terminal TEHBA1 and a second cell connection terminal TEHBA2, each providing a connection for the cell to the upper phase arm of the first phase leg of the voltage source converter. In this first type of cell the first cell connection terminal TEHBA1 more particularly provides a connection from the upper phase arm to the junction between the fourth switch S4 and the capacitor C, while the second connection terminal TEHBA2 provides a connection from the upper phase arm to the junction between the fourth and the fifth switches S4 and S5. These cell connection terminals thus provide points where the cell can be connected to the upper phase arm. The second cell connection terminal TEHBA2 thus joins the phase arm with the connection point or junction between two of the series-connected switches of the first group, here the fourth and fifth switches S4 and S5, while the first cell connection terminal TEHBA1 joins the upper phase arm with a connection point between the fourth switch S4 and the positive end of the capacitor C. Also here the first cell connection terminal TEHBA1 faces the first pole, while the second cell connection terminal TEHBA2 faces the AC terminal of the phase leg.

Fig. 4 shows a second type of hybrid full-bridge cell HFBB that may be provided in the lower phase arm of the first phase leg.

The cell HFBB is thus a hybrid full-bridge converter cell and also includes an energy storage element, here in the form of a capacitor C, which is connected in parallel with a first group of semiconducting units. Also this energy storage element C provides a voltage Udm, and therefore has a positive and negative end, where the positive end has a higher potential than the negative end. The first group also here includes two series-connected semiconducting units SU1 and SU2

(shown as dashed boxes) in the form of switches SI and S2. In fig. 4 there is a first switch SI having a first transistor Tl with a first anti-parallel diode Dl, where the diode Dl has a direction of current

conduction towards the positive end of the energy storage element C. There is also a second switch comprising a second transistor T2 with anti-parallel second diode D2 and having the same current conduction as the first diode Dl . The first semiconducting unit SU1 is also here connected to the positive end of the energy storage element C, while the second

semiconducting unit SU2 is connected to the negative end of the energy storage element C. There is in this case also a second group of

semiconducting units connected in series with each other. This second group of semiconducting units is here connected in parallel with the first group as well as with the energy storage element C. The second group also here consists of a third semiconducting unit SU3 and a fourth semiconducting unit SU4, where the third semiconducting unit SU3 is provided through a third switch S3 comprising at least one third transistor T3 with anti-parallel third diode D3 and the fourth semiconducting unit SU4 is provided using only

unidirectional conduction elements, in this example a diode D. The fourth semiconducting unit SU4 thereby consists of a number of unidirectional conducting elements, comprising at least one element. The second group of semiconducting units is thus provided in a further branch in parallel with the capacitor C. The fourth semiconductor unit SU4 is in this case connected to the negative end of the energy storage element C, while the third semiconducting unit SU3 is connected to the positive end of the energy storage element C. The current conducting direction of both diodes D3 and D is towards the positive end of the energy storage element C. This second type of hybrid full-bridge cell HFBB comprises a first cell connection terminal TEFBB1 and a second cell connection terminal TEFBB2, each providing a connection for the cell to the lower phase arm of the voltage source converter, i.e. the lower phase arm of the first phase leg. Just as in the first type of hybrid full-bridge cell, the first cell connection terminal TEFBB1 provides a connection from the lower phase arm to the junction between the first and the second semiconducting units SU1 and SU2, while the second cell connection terminal TEFBB2 provides a connection between the lower phase arm and the

connection point between the third and fourth

semiconducting units SU3 and SU4. The junction between the first and the second semiconducting units SU1 and SU2 thus provide a cell connection terminal and the junction between the third and fourth semiconducting units SU3 and SU4 provide a further cell connection terminal. In this case the first cell connection terminal TEFBB1 furthermore faces the second pole and thereby couples the cell to the second pole, while the second cell connection terminal TEFBB2 faces the AC terminal of the phase leg. The second cell connection terminals thereby couples the cell to the AC terminal of the phase leg, while the at least one unidirectional conducting element couples the second cell connection terminal to the negative end of energy storage element C.

Fig. 5 shows a corresponding second type of half-bridge cell HBB for connection in the lower phase arm of the first phase leg. It comprises a group of switches comprising a fourth and fifth switch S4 and S5

connected in the same way as the fourth and fifth switches of the first type of half-bridge cell.

However, in this second type of half-bridge cell the first cell connection terminal TEHBB1 provides a connection from the lower phase arm to the junction between the fourth and the fifth switches S4 and S5, while the second cell connection terminal TEHBB2 provides a connection from the lower phase arm to the junction between the fifth switch S5 and the negative end of the capacitor C. Also in this case the first cell connection terminal TEHBB1 faces the second pole, while the second cell connection terminal TEHBB2 faces the AC terminal of the phase leg.

Fig. 6 schematically shows a phase leg where the upper phase arm comprises the first type of hybrid full bridge cells and the first type of half-bridge cells, while the lower phase arm comprises the second type of hybrid full bridge cells and the second type of half- bridge cells connected in the above described way.

The number of hybrid full-bridge cells in the upper phase arm may be between 20 and 100% of all the cells in the upper phase arm, may advantageously be between

20 and 50% and may as an example be 50%, while the rest of the cells in the upper phase arm are half-bridge cells. The same distribution may be provided in the lower phase arm.

In normal operation of the converter cells, the first type of hybrid full-bridge cell and the first type of half-bridge cell of the upper arm of the phase leg shown in fig. 6 are operated according to the switching table below, table 1. In the table the switching states of the first, second and third switches SI, S2 and S3 of the first type of hybrid full bridge cell are shown together with the switching states of the fourth and fifth switches S4 and S5 of the first type of half- bridge cell. Furthermore, in the table the two cells are considered as a pair together providing a voltage Vout . The table therefore shows the combination of switching states causing a voltage contribution that lowers the first pole voltage +DC. There is thus a voltage contribution -2Udm that lowers the pole voltage by the voltage across both cells, a voltage

contribution -Udm that lowers the pole voltage by the voltage across a single cell and a zero voltage

contribution. In the table also the direction of the phase arm current lap, i.e. the current through the upper phase arm, is indicated. It can thus be seen that the hybrid full-bridge cell can be used for dual current directions through the phase arm. As can be seen in the table, the switching states are also independent of the current direction in the phase arm.

TABLE 1

In a similar manner the switching states of the

switches of the second type of hybrid full bridge cell and the second type of half-bridge cell of the lower phase arm of the phase leg shown in fig. 6 are operated according to the switching table below, table 2. In the table the switching states of the first, second and third switches SI, S2 and S3 of the second type of hybrid full-bridge cell are shown together with the switching states of the fourth and fifth switches S4 and S5 of the second type of half-bridge cell. Also here the two cells are considered as a pair together providing a voltage Vout . The table thus shows the combination of switching states causing a voltage contribution that raises the second pole voltage -DC. There is thus a voltage contribution +2Udm that raises the pole voltage by the voltage across both cells, a voltage contribution +Udm that raises the pole voltage by the voltage across a single cell and a zero voltage contribution. In the table also the direction of the phase arm current Ian, i.e. the current through the lower phase arm, is indicated. As can be seen also here the switching states are independent of the current direction in the phase arm.

TABLE 2 In the hybrid full-bridge cell, the second branch of semiconducting units, i.e. the branch comprising the third and the fourth semiconducting units, here the branch with the third switch S3 and the diode D, is redundant in normal operation. This can be seen through the third switch S3 always being turned on. This means that the third switch S3 does in normal operation always provide a current path between the AC terminal of the phase leg and the corresponding pole. It can also be seen that therefore there is no needed for any switching element in parallel with the diode D of the fourth semiconducting unit of the full-bridge cells.

The reason for using full-bridge cells is ordinarily not for improving the normal operation, but to be able to limit and sometimes also block fault currents in case of a DC pole fault, such as a pole-to-pole fault or a pole-to-ground fault. When there is a pole-to- ground fault the voltage at the AC terminal of a phase leg can be considered as forming an AC voltage source VAC feeding the phase leg with an AC voltage. When such a fault occurs, the switching elements of all the switches may be opened by the control unit of the converter. The switching element of the third switch S3 may more particularly be open, at least in the negative half period of the AC voltage for the first type of hybrid full-bridge cell HFBA and at least in the positive half period of the AC voltage for the second type of hybrid full-bridge cell HFBB .

Fig. 7 shows the fault current through the upper phase arm of fig. 6 in case of a positive pole-to-ground fault at a positive half period of the AC voltage cycle of the AC voltage source VAC and fig. 8 shows the fault current through the upper phase arm of fig. 6 in case of a positive pole-to-ground fault at a negative half period of the AC voltage cycle of the AC voltage source VAC .

As can be seen in fig. 7, the fault current will, in the positive half-period of the AC voltage source VAC, run from the AC voltage source VAC, through the fourth switch S4, through the diode D, through the hybrid cell capacitor and through the diode of the second switch S2 to the first pole. It can also be seen that since the first pole has a positive potential during normal operation, the diode D is together with the second switch S2 connected in a branch between the first and the second cell connection terminals of the hybrid cell that couples the negative end of the hybrid cell energy storage unit to the first pole. It can in this way be seen that the diode D couples an end of the hybrid cell energy storage unit to a pole, which end has a polarity that is opposite to the polarity of the pole in normal operation .

As can be seen in fig. 8, the fault current will, in the negative half-period of the AC voltage source VAC, flow from the first pole, through the first switch SI, through the hybrid cell capacitor, through the diode of the third switch S3, through the half-bridge cell capacitor and through the diode of the fifth switch S5 to the AC voltage source VAC. It can here be seen that the switching element of the third switch S3 is needed in order for the current to pass through the hybrid cell capacitor in the situation depicted in fig. 7. However, there is no need for a switching element in parallel with the diode D for obtaining the same result in the situation in fig. 8. As can be seen there is in both cases, i.e. for both current directions, inserted a cell voltage that limits the fault current. It can also be seen that when the fault current is positive, i.e. runs from the first pole towards the AC terminal, then the voltages of both cells are inserted in the path and thereby limit the fault current. It can also be seen that the diode D functions to couple the energy storage element of the hybrid full bridge cell HFBA between the first and the second cell connection terminals of the hybrid full bridge cell HFBA with a polarity that counteracts negative currents in the phase arm. This means that when the diode D is conducting, the negative end of the hybrid full-bridge cell capacitor faces the first pole PI and the positive end faces the AC terminal AC1.

A similar situation is at hand if there is a negative pole-to-ground fault.

Fig. 9 shows the fault current through the lower phase arm of fig. 6 in case of a negative pole-to-ground fault at the negative half period of the AC voltage cycle of the AC voltage source VAC and fig. 10 shows the fault current through the lower phase arm of fig. 6 in case of a negative pole-to-ground fault at the positive half period of the AC voltage cycle of the AC voltage source VAC. As can be seen in fig. 9, the fault current will, in the negative half-period of the voltage source VAC, flow from the second pole, through the diode of the first switch SI, through the hybrid cell capacitor, through the diode D and through the diode of the fifth switch S5 to the AC voltage source VAC. It can also be seen that since the second pole has a negative

potential during normal operation, the diode D is together with the first switch SI provided in a branch between the first and the second cell connection terminals of the hybrid cell that couples the positive end of the hybrid cell energy storage unit to the second pole. It can in this way be seen that the diode D couples an end of the hybrid cell energy storage unit to a pole, which end has a polarity that is opposite to the polarity of the pole in normal operation.

As can be seen in fig. 10, the fault current will, in the positive half-period of the AC voltage source VAC, run from the AC voltage source VAC, through the fourth switch S4, through the half-bridge cell capacitor, through the diode of the third switch S3, through the hybrid cell capacitor and through the diode of the second switch S2 to the second pole. It can also here be seen that the switching element of the third switch S3 is needed in order for the current to pass through the hybrid cell capacitor in the situation depicted in fig. 9. However, there is no need for a switching element in parallel with the diode D for obtaining the same result in the situation in fig. 10.

As can be seen there is in both cases inserted a cell voltage that limits the fault current. It can also be seen that when the fault current is positive, i.e. runs from the second pole to the AC source, then the

voltages of both cells are inserted in the path and thereby limit the fault current. It can also in this case be seen that the diode D functions to couple the energy storage element of the hybrid full bridge cell HFBB between the first and the second cell connection terminals of the hybrid full bridge cell HFBB with a polarity that counteracts negative currents in the phase arm. This means that when the diode D is

conducting the positive end of the hybrid full-bridge cell capacitor faces the second pole P2 and the

negative end faces the AC terminal ACA1.

If enough such hybrid cells are provided in a phase arm, the fault current because of a pole-to-ground fault of the corresponding pole may be completely blocked .

It can thus be seen that as compared with a

conventional topology that mixes half-bridge cells with conventional full-bridge cells, the same fault limiting or fault blocking ability is obtained, however using less components together with dual current directions through the hybrid cells in normal operation.

Furthermore the complexity of the structure is also kept low, which directly affects the cost, loss and modularity of the total converter design.

There is thus provided an alternative mixed cell configuration for DC fault current limitation or DC fault current blocking in cascaded converters used in HVDC, FACTS and other similar applications. The

structure thus offers a lower number of components compared to other cell configurations with similar features (DC voltage blocking and fault blocking capability) . This structure operates in the same way as normal cascaded two level half-bridge cells (CTL) while one of the active switches, the third switch, of the hybrid cell is always ON and generate either 2Udm, Udm, 0 voltage levels, according to different switching states. However, in case of a DC fault, this third switch is turned OFF to provide an opposite voltage polarity according to the fault position in upper or lower arm. This results in the DC fault being blocked or limited.

The cell structure comprises 5 transistor antiparallel diode pairs and only one extra diode which can save one active switch compared to a converter configuration where there is a mix of half-bridge cells and

conventional full-bridge cells.

It should be realized that the hybrid cell structures used both in the upper and lower phase arms may be varied .

A third type of hybrid cell structure HFBC that may be used in the upper phase arm is schematically shown in fig. 11. This type differs from the structure of the first type through the fourth semiconducting unit SU4 with the diode D being connected to the negative end of the cell capacitor C and the third semiconducting unit SU3 being connected to the positive end of the cell capacitor C. The first cell connection terminal TEFBC1 is further provided at the junction between the third and fourth semiconducting units SU3 and SU4, while the second cell connection terminal TEFBC2 is provided between the first and second semiconducting units SU1 and SU2. In this type of cell the first cell connection terminal TEFBC1 is a further cell connection terminal coupling the cell HFBC to the first pole and the at least one unidirectional conducting element couples the first cell connection terminal TEFBC1 to the negative end of the energy storage element C.

A fourth type of hybrid cell structure HFBD that may be used in the lower phase arm is schematically shown in fig. 12. This differs from the structure of the second type through the fourth semiconducting unit SU4 with the diode D being connected to the positive end of the cell capacitor C and the third semiconducting unit SU3 being connected to the negative end of the cell capacitor C. The first cell connection terminal TEFBD1 is further provided at the junction between the third and fourth semiconducting units SU3 and SU4, while the second cell connection terminal TEFBD2 is provided between the first and second semiconducting units SU1 and SU2. In this type of cell the first cell connection terminal TEFBD1, which is here a further cell

connection terminal, couples the cell to the second pole and the at least one unidirectional conducting element D couples the first cell connection terminal TEFBD1 to the positive end of the energy storage element C.

The third type of hybrid cell may replace the first type in the upper arm. The third type may also be combined with the first type. There may thus be cells of both the first and the third type of hybrid cell in the upper phase arm. In a similar manner, the fourth type of hybrid cell may replace the second type in the lower arm. It may also be combined with the second type. There may thus be cells of both the second and the fourth type of hybrid cells in the lower phase arm.

There are a number of further variations that are possible apart form those already mentioned. It is possible that only one of the phase arms comprises hybrid full-bride cells. This may be of interest if pole-to-ground faults of one of the poles are extremely rare. This may be the case if one of the poles is an overhead line while the other is provided through a cable. All cells of a phase arm may also be hybrid cells .

The distribution between the hybrid full-bridge cells and the half-bridge cells may furthermore vary. The percentage of hybrid-full bridge cells in a phase arm may for instance vary between 20 and 100%. As an alternative it may vary between 20 and 50%. 50% is normally the percentage required for full fault current blocking ability. A higher percentage may be wanted if redundancy is an issue, while a lower may be used if only fault current limitation is desired. The other cells, i.e. the cells that are not hybrid full-bridge cells, are furthermore not necessarily half-bridge cells. They can also be full-bridge cells or clamped double-cells. It is furthermore possible with a

different distribution of hybrid full-bridge cells in the two phase arms. The hybrid full-bridge cells may furthermore be provided in other types of converters than the ones shown, such as in converters that employ full bridge-cells combined with director switches, which director switches operate at a fundamental frequency for selectively connecting an AC terminal to a waveform produced by cells in a phase arm.

The above described mixture of hybrid full-bridge cells with half-bridge cells also provides the following further advantages:

• It provides a fault tolerant cell structure that can be used for any kind of cascaded converter.

• It lowers the number of components compared to existing cell structures used for DC fault blocking · On the basis of required voltage rating, the same number of devices is provided in the conduction path as when there is a mix of half-bridge and conventional full-bridge cells

• The number of gate drive circuits required are reduced compared to when there is a mix of half-bridge cells and conventional full-bridge cells

• It provides a modular and easily implemented cell design structure

• It allows the possibility to form a mixture of connections of hybrid full-bridge cells and half-bridge cells and series-connection of hybrid full-bridge cells

• It provides a DC fault voltage blocking capability

• It provides a cost effective structure

• It provides a compact structure

· It provides the possibility to reduce the cost for cascaded topologies

• It provides the possibility to reduce the loss of cascaded topologies. When there are pole faults on one or more poles of the converter, it may additionally be of interest to inject reactive power into the AC system via the AC terminals, such as the first AC terminal ACAl of the first phase leg PL1. If for instance there is a pole to ground fault on the first pole PI, then the lower phase arm may be used for such injection, while the cells in the upper phase arm are being blocked. In the case of a pole to ground fault on the second pole P2, then the cells of the upper phase arm may be used for injecting reactive power, while the cells in the lower phase arm are being blocked. In both cases the hybrid full-bridge cells that are used to inject reactive power may be operated as half-bridge cells.

In case there is a pole-to-pole fault all the cells in the phase leg, i.e. in both the upper and lower phase arms, may need to be used for injecting reactive power.

If the hybrid full bridge cell is to be used for such reactive power injection, there is a problem that needs to be handled.

The hybrid full bridge cell has three-quadrant

operation. If for instance the first type of hybrid- full bridge cell shown in fig. 2 is used in the upper phase arm, this cell cannot be operated when there is a negative voltage and a negative current in the upper phase arm. Likewise the second type shown in fig. 4 cannot be operated when there is a negative voltage and a negative current in the lower phase arm. This

situation therefore has to be avoided.

A second aspect of the invention is concerned with this problem. Fig. 13 shows a number of voltage and current curves associated with the first phase leg, which curves indicate a way in which the above-mentioned situation is handled for a pole-to-pole ground fault, i.e. when both poles are connected to ground.

Fig. 13a shows the output voltage Va at the first AC terminal ACA1 of the first phase leg, the voltage Vdp at the first pole PI, the voltage -Vdn at the second pole P2 and the current la output via the AC terminal ACA1.

Fig. 13b shows a circulating current lacir of the upper phase arm, Fig. 13c shows the upper phase arm current lap and fig. 13d shows the lower phase arm current Ian.

In case of a pole-to-pole fault the voltages of the poles drop for instance all the way to ground. In this situation the upper phase arm voltage Vap will have an area when it is below zero. This area is indicated between times tl and t2 in fig. 13a in relation to the output voltage Vas . Likewise the lower phase arm voltage Van will have an area when it is below zero, which is between times t3 and t4. Also this area is indicated in fig. 13a in relation to the output voltage Vas.

As mentioned earlier the upper phase arm current lap cannot be negative when the upper phase arm voltage Vap is negative, because then the hybrid full bridge cells of the phase arm cannot be operated for reactive power injection. For the same reason the lower phase arm current Ian cannot be negative when the lower phase arm voltage Van is negative.

This is according to the second aspect of the invention solved through the control unit controlling the upper phase arm current lap to be zero when the upper phase arm voltage Vap is negative, i.e. between tl and t2, and controlling the lower phase arm current Ian to be zero when the lower phase arm voltage Van is negative, i.e. between t3 and t4, during the injection of

reactive power through the AC terminal to the AC system. This control allows the hybrid full bridge cells to be controlled for contributing to the reactive power injection.

The phase arm currents may more particularly be

controlled to be zero in the above mentioned intervals through the provision of the circulating current lacir, i.e. a current that circulates through the phase leg PL1. A circulating current is a current that circulates between the phase legs. Furthermore, it does not contribute to either the DC current on the poles PI and P2 or the AC current output via the AC terminal ACA1. This circulating current is set to be half the negative output current la, i.e. to -1/2 la, in the time

interval tl - t2, which results in the upper arm phase current being zero in this time interval and the lower phase arm current being equal to 2*Ia in the same interval tl - t2. In the interval between t3 and t4, the circulating current is controlled to be + l/2*Ia, which leads to the upper phase arm current being equal to 2*Ia, while the lower phase arm current is zero. The operation is more particularly the following.

When a pole-to-pole fault occurs, the voltage of both poles drop partially or fully depending on the fault impedance, i.e. Vdp = Vdn = 0~Vfault and Vfault < Ud, where the normal value of Vdp = Vdn = Ud for a

symmetric monopole system. In an asymmetric monopole system Vdp = 2Ud, while Vdn = 0 in an. The switches in both upper and lower arms are then blocked shortly after the fault. The fault current is then reduced to zero or an acceptable value, before the switches are restarted to support reactive power at the ac side.

The circulating current is then controlled so that neither phase arm current goes below zero when the corresponding phase arm voltage is below zero, which is done using a circulating current injection method, where the desired circulating current waveform is illustrated in Figure 13 (b) .

During the time period tl - t2 when the upper-arm voltage Vap for the first phase leg PL is negative, i.e., Vap = Vdp - Va < 0, the circulating current in the first phase leg PL1, Iacir = -½ la. As a result, during this period, the upper arm current lap is zero and the lower arm current Inp is equal to la, as illustrated in Figure 13 (c) and (d) . The same

operation is then applied to the time period t3 - t4 when the lower-arm voltage is negative.

As can be seen in fig. 14, the control unit 12

comprises a PQ control element 14 a circulating current reference generating element 16, a circulating current control element 18 and an AC fault handling element 20 The control unit is with advantage implemented through using a computer with computer program code comprising computer program instructions providing the above- mentioned elements.

How the control of the circulating current may be implemented will now be described also with reference to fig. 14, 15, 16 and 17, where fig. 14 shows a block schematic of some of the elements of the control unit 12, fig. 15 shows a block schematic of a PQ control element 14 of the control unit, fig. 16 shows a block schematic of a general circulating current reference generating element 16 of the control unit and fig. 17 shows a block schematic of a circulating current control element 18 for controlling the circulating current Iacir of the first phase leg PL1.

To control the circulating current to follow the desired waveform, which is an ac signal, a feed forward PI controller is used. The circulating current dynamics in the first phase leg PL1 can be described by

where F_ffldr = (Κ_φ + V_dn - V_ap - V„)l 2 _{(1 }}

/ =(I +1 ) / ^

^' acir ap am '

Here Larm is the phase arm inductance, Iacir is the circulating current in the phase leg, Vacir the voltage driving the circulating current and Rarm is the

resistance of the phase arm. Similar dynamics can be expressed for other phase legs. The reference (desired) values for the circulating currents and their time derivatives may be generated from the voltage and current references used in a PQ control loop, as illustrated in Figure. 15.

The PQ control element 14 comprises a first PI control block 22 to which a desired change in active power ΔΡ is provided. The first PI control block 22 performs proportional and integrating processing of the active power ΔΡ in order to obtain a reference or desired active current control value Id*, which is also the desired DC current. The first PI control block 22 provides the desired active current control value Id* to a first subtracting block 24, where the actual active current Id is subtracted from the desired active current Id* and the result is provided to a first current controller 26, which in a known way provides a desired active voltage value Vd* . In a similar manner, there is a second PI control block 28 to which the desired change in reactive power AQ is provided. The second PI control block 28 performs proportional and/or integrating processing of the reactive power AQ in order to obtain a desired reactive current control value Iq*, which is also a part of the desired output AC current la. The second PI control block 28 provides the desired reactive current control value Iq* to a second subtracting block 30, where the actual reactive current Iq is subtracted from the desired reactive current Iq* and the result is provided to a second current controller 32, which in a known way provides a desired reactive voltage value Vq* .

The desired current and voltage values Id*, Iq*, Vd*, Vq* are then combined for providing inputs to the general circulating current reference generating element 16. The inputs are more particularly a desired current Idq*, a desired voltage Vdq*, a phase 9dq and the voltages Vdp and Vdn, where the outputs are a desired circulating current Icir_abc* and a desired time derivate of the circulating current

d/dt (Icirabc*) .

The output values obtained from the generating element 16 are common for the three phases and may be separated into three different currents and time derivatives, one for each phase.

The control element 18 for controlling the circulating current of the first phase leg is schematically shown in fig. 17. It comprises a third subtracting block 34, which receives the desired circulating current in the first phase leg Iacir* and a value of the actual circulating current Iacir, The third subtracting block 34 subtracts the actual value Iacir from the desired value Iacir* and provides the result of the subtraction to a third PI control block 36, which performs a PI operation, i.e. proportional and/or integrating control on the result of the subtraction for providing a first control voltage value. The result of the PI operation, i.e. the first control voltage value, is provided to an adding block 38, which also receives a processed derivative of the desired circulating current, where the processed derivative involves a multiplication of the derivative with the arm inductance Larm. The processed derivative of the circulating current is thus a control term Larm* (d/dtIacir) that is dependent on the derivative of the circulating current and added to the first control voltage value. The adding block 38 adds the processed derivative to the first control voltage value. The sum of the processed derivative and the first control voltage value is then provided as the desired circulating current driving voltage Vacir* .

As an alternative it is possible to omit the adding block 38, in which case the first control voltage value will be the desired circulating current driving

voltage.

As can be seen the circulating current control loop for the first phase leg PL1 shown in fig. 17 is obtained based on the circulating current dynamics in equation (1) .

Corresponding circulating control loops can be obtained in a similar manner for the other phase legs. Here it may furthermore be mentioned that the feed-forward term Larm dlacir*/dt is added to improve the PI controller regulation performance on the ac reference signals.

The described second aspect has a number of advantages. It allows DC fault current blocking with mixed

asymmetric-full-bridge half-bridge cells together with reactive power control of mixed asymmetric-full-bridge half-bridge cells during DC faults. It also provides circulating current injection for converters employing asymmetric-full-bridge cells.

Another problem that may exist is that the voltage rating of a converter with the above-mentioned mixture of cells needs to be high in order to handle phase faults .

The equivalent circuit of a blocked asymmetric monopole converter with three phase legs during an AC phase ground fault is shown in fig. 18. In this figure each phase leg is realized as the phase leg shown in fig. 6 for an asymmetric monopole converter. This means that in relation to the converter in fig. 6 the "second pole" is no pole, but actually ground. The voltage -Vdn in fig. 6 is thus actually ground.

The equivalent circuit in fig. 18 represents the situation when there is an internal phase-to-ground fault, after which blocking of all cell switches has been made. An internal phase-to-ground-fault is not a fault in the connected AC system but an Ac fault in the environment of the converter, such as in an AC busbar provided in a converter station.

As can be seen in the equivalent circuit in fig. 18, the upper phase arm of each phase leg comprises a first capacitive branch BR1 in series with a diode with a direction of current towards the first pole PI. This branch BR1 comprises the sum of the capacitances of the hybrid full bridge cell capacitors in the upper phase arm. There is also a second capacitive branch BR2 in series with a diode having a conduction direction away from the first pole. The second capacitive branch BR2 comprises the sum of capacitances of the hybrid full bridge cell capacitors in series with the sum of the capacitances of the half-bridge cell capacitors in the upper phase arm. The first and second capacitive branches BR1 and BR2 are connected in parallel with each other. In a similar manner there is a third capacitive branch BR3 in series with a diode with a direction of current away from ground. This branch BR3 comprises the sum of the capacitances of the hybrid full bridge cell capacitors in the lower phase arm. There is also a fourth capacitive branch BR4 in series with a diode with a conduction direction towards ground. The fourth capacitive branch BR4 comprises the sum of capacitances of the hybrid full bridge cell capacitors in series with the sum of the capacitances of the half-bridge cell capacitors in the lower phase arm. The third and fourth capacitive branches BR3 and BR4 are connected in parallel with each other.

In case of a ground fault on one of the phases, this phase fault grounds the midpoint of the corresponding phase leg. The two other phase leg midpoints may then be seen as connected to AC voltage sources VAC1 and VAC2 via source impedances, which are typically transformers. These voltages have, because of the transformer, been raised with a value of V3 as compared with before the fault. This means that the peak voltage of the healthy phases after the converter transformer becomes ±1.732 Ud. At the negative peak of VAC = -1.732 Ud, this will charge the lower arm hybrid full-bridge capacitors from Ud to 1.732 Ud (73% overvoltage), and charge the upper arm (both half and full bridge) capacitors from 2Ud to 3.732 Ud (87% overvoltage). There is thus a considerable overvoltage that has to be handled by the converter,

In asymmetric monopole and symmetric bipole system configurations, the upper converter arm thus faces an over voltage rating of almost 80%-90% when there is an AC converter internal fault. This overvoltage exceeds the typical blocking voltage of an IGBT.

This situation would typically have to be handled through redundancy, i.e. through using additional cells that are only used for voltage rating purposes.

The size of the converter will thus have to be

unnecessarily large in order to handle the overvoltages caused by this type of fault.

It can be seen that if the third capacitive branch BR3 is short-circuited, then the overvoltage of the upper or first phase arm would be drastically limited.

This insight may be used for providing a different converter design in which the energy storage elements of all the converter cells of the lower or second phase arm are configured to be bypassed in case of a phase fault on the AC side of the multilevel converter. A third aspect of the invention is directed towards this. One first way in which the above-mentioned short- circuiting may be obtained is through only connecting unipolar cells in a phase arm that stretches between an AC terminal and ground. Thereby the cells with two voltage contribution polarities are all connected in a branch between a pole and an AC terminal. This

situation is schematically shown in fig. 19 for a converter with a asymmetric monopole structure. As can be seen only half-bridge cells are connected in the lower or second phase arm, while all the hybrid full bridge cells that have dual polarity voltage

contributing abilities are connected in the upper phase arm. In this way the cell capacitors in the lower or second phase arm are automatically bypassed as the cell switches are blocked during the AC fault. It should here be realized that it is possible that also half- bridge cells may be connected in the upper or first phase arm as long as the required pole fault current limiting ability is retained.

The operation of this converter is the following. When a converter station internal phase-to-ground fault occurs, all the cell switches are blocked by the control unit. At the negative peak of VAC (-1.732 Ud) , the low arm diode conducts with high surge current. This is the same case as a normal half-bridge

converter. The surge current creates voltage drops across the source impedance. If it is assumed that Lac, i.e. the inductance associated with the AC source VAC1 or VAC2 is approximately equal to Larm, then the midpoint voltage between the upper and lower arms is approximately -0.866 Ud. This charges the upper arm (both half and full bridges) capacitors from 2 Ud to 2.866 Ud (43% overvoltage) . This overvoltage level is the same as for a normal half-bridge converter, and will be further reduced if the source impedance Lac is higher than the arm impedance Larm.

It can thus be seen that the overvoltage handled by the upper phase arm is considerably reduced.

Another way in which the bypass may be obtained is through providing a bypass switch in the dual polarity cells in the lower phase arm, which dual polarity cells are here the above described hybrid full bridge cells. The lower phase arm thus comprises at least some hybrid full-bridge cells, where all are provided with a bypass switch that can be controlled to bypass the cell

capacitor. As is indicated in fig. 18, full-bridge cells in the lower arm can charge up to the line voltage in a negative cycle and cause the over voltage in the upper arm of the converter. In order to avoid the lower arm charging, this variation of the third aspect proposes a bypassing of the full-bridge capacitors.

A bypass switch may be provided as a thyristor switch TH and placed in the third semiconducting unit SU3 in parallel with the third switch T3 in the fourth type of hybrid cell HFBD. It may thus be a part of a switch used in the control of the cell voltage contribution made by the cell. This variation of the fourth type of hybrid cell HFBD is schematically shown in fig. 20.

The thyristor switch TH furthermore has a current conduction direction that is the opposite of the current conduction direction of the semiconducting unit diode D3. The cells of the third type HFBC placed in the upper phase arm will then lack such a bypass switch. This type of bypassing may also reduce the current rating of the diodes in addition to lowering the voltage rating of the upper phase arm.

When using a bypass switch, this will have to be controlled . The AC fault handling element 20 of the control unit 12 is therefore configured to switch on the bypass switch TH of all full-bridge cells in the second or lower phase arm when an AC fault is detected. This detection may be the detection of an AC fault on another phase than the phase the phase leg in question is connected to. The detection may as an alternative be a detection of an AC fault on any of the phases. The closing of the bypass switches TH will lead to the short-circuiting of the above-mentioned third capacitive branch BR3 and thereby the phase arm inductance is grounded. This will in turn lead to a lowering of the rating of the upper phase arm.

The bypass switch is not necessarily connected in parallel with the third switch T3 of the third

semiconducting unit SU3, but may instead be connected between the two cell connection terminals TEFBD1 and TEFBD2 with a current conduction direction towards the AC phase terminal of the phase leg.

As yet another alternative of a bypass switch as a part of a switch used in the control of the cell voltage contribution it is possible that the third semiconducting unit SU3 is an Integrated Gate- Commutated Thyristor (IGCT) with anti-parallel diode instead of an IGBT with anti-parallel diode. An

asymmetric monopole converter with this realization is schematically shown in fig. 21. In case of a fault on an AC phase, the IGCT is then switched on (while the other switches are blocked) and thereby the full-bridge capacitor is bypassed. The surge current capability of IGCT is 10 times higher than that of IGBT. The IGCT also has a stable short circuit failure behavior.

The examples above of the third aspect were all related to asymmetric monopole converters. However, the above described teachings of the third aspect may all be used also in symmetric bipole converters. In a phase leg of such a converter configuration there is a first phase arm corresponding to the above-mentioned upper phase arm and a second phase arm corresponding to the above- mentioned lower phase arm connected in series between a first pole and ground, where the first AC terminal is provided between these two phase arms. However in addition to these phase arms there is a third phase arm between ground and a second AC terminal and a fourth phase arm between the second AC terminal and a second pole. In this case the third phase arm will be

configured in the same way as the second phase arm, i.e. configured so that all the cell capacitors of the third phase arm are bypassed in case of a phase to ground fault either through only comprising half-bridge cells or through full-bridge cells with bypass

switches, while the fourth phase arm, just as the first phase arm, comprises hybrid full-bride cells all set to insert the cell capacitor during the same types of faults .

It should furthermore be realized that the full bridge cells for which the various bypass solutions are applied is not limited to the described hybrid full bridge cells, but can be used also for regular full- bridge cells as well as other dual polarity cells, such as so-called clamped double cells or asymmetric

monopole mixed cells. The concept may thus be used for any type of cell having a bipolar voltage contribution using at least one energy storage element.

Fig. 22 shows an example of an asymmetric monopole converter with regular full-bridge cells, where all the full bridge cells are provided in the first phase arm, i.e., between the first pole and the first AC terminal, and all half-bridge cells are provided in the second phase arm, i.e. between the first AC terminal and ground.

Fig. 23 shows a similar structure for a symmetric bipole converter. This has the same structure as that in fig. 22 but mirrored around a ground potential. This means that an upper half of the converter comprising the first and second phase arms is the same as that shown in fig. 22. The lower half then comprises the third and fourth phase arms, where all the half-bridge cells are connected in the third phase arm and all the full bridge cells are provided in the fourth phase arm. Each phase leg also comprises two AC terminals ACAl, ACA2, ACB1, ACB2, ACC1 and ACC2. Fig. 24 shows a variation of the asymmetric monopole converter of fig. 22, where the full-bridge cells are replaced by asymmetric monopole mixed cells. Similar variations of the bypass switch is shown in fig. 25 and 26 for a full-bridge cell, where fig. 25 has the thyristor bypass switch as a part of a

semiconducting unit, and fig. 26 has a bypass switch connected between the cell connection terminals.

Fig. 27 shows an IGCT bypass switch solution in a full- bridge cell and fig. 28 the same type of switch in a clamped double cell. In the clamped double cell the IGCT is provided as a part of an interconnecting switch interconnecting two cell halves, where each cell half is made up of a half-bridge.

The third aspect has a number of advantages. It reduces the cost by having 50% full-bridge cells in converter phase instead of 100% FB arms for DC current fault blocking capability within the converter arm. It avoids the extra rating and thus cost reduction of converter by minimizing the AC fault phase to ground over rating (from 80% to 40%) . It minimizes converter loss by reducing the over voltage rating. At the same time it enables the provision of full DC fault blocking

capability without DC breaker and avoids an extra rating of diodes. The multilevel voltage source converter according to the generalized third aspect may also be exemplified as A multilevel converter configured to convert between alternating current (AC) and direct current (DC) and comprising :

a phase leg having a first and a second phase arm, said first phase arm being connected between a first pole and a first AC terminal and the second phase arm being connected between the first AC terminal and ground, said phase leg comprising cells of a first type having a unipolar voltage contribution and cells of a second type having a bipolar voltage contribution, where each cell comprises at least one energy storage element for providing said voltage contribution,

wherein the first phase arm comprises cells of the second type and the energy storage elements of all the converter cells of the second phase arm are configured to be bypassed in case of a phase fault on the AC side of the multilevel converter.

The multilevel converter according to the previous example, wherein all cells of the second phase arm are cells of the first type, the energy storage elements of which are automatically bypassed as the semiconducting switches are blocking during such AC side faults. The multilevel converter according to any previous example, wherein at least some of the cells of the second phase arm are cells of the second type, each comprising a bypass switch TH controllable to bypass the corresponding energy storage element.

The multilevel converter according to the previous example, wherein the bypass switch is provided as a part of a switch used in control of the voltage

contribution by the cell.

The multilevel converter according to the example preceding the previous example, wherein the bypass switch is connected between cell connection terminals used for connecting the cell to the phase arm.

The multilevel converter according to any previous example, the phase leg further comprising a third phase arm between a second AC terminal and ground and a fourth phase arm between the second AC terminal and a second pole, wherein the fourth phase arm comprises at least one cell of the second type and the energy storage elements of all the converter cells of the third phase arm are configured to be bypassed in case of a phase fault on the AC side of the multilevel converter . The control of the multilevel converter according to the third aspect may also be exemplified as:

A method for reducing the voltage rating required for a phase arm in a voltage source converter configured to convert between alternating current (AC) and direct current (DC) , the multilevel converter comprising a phase leg having a first and a second phase arm, said first phase arm being connected between a first pole and a first AC terminal and the second phase arm being connected between the first AC terminal ACA1 and ground, said phase leg also comprising cells of a first type having a unipolar voltage contribution and cells of a second type having a bipolar voltage contribution, where each cell comprises at least one energy storage element for providing said voltage contribution, where the method comprises controlling the energy storage elements of all the converter cells of the second type in the second phase arm to be bypassed in case of a phase fault on the AC side of the multilevel converter .

The method according to the previous example, wherein all the cells of the second type in the second phase arm comprise a bypass switch TH and the controlling comprises activating the bypass switches to bypass corresponding energy storage elements when the phase fault occurs on the AC side of the multilevel

converter.

The method according to the previous example, wherein at least one bypass switch is provided as a part of a switch used in control of the voltage contribution by a corresponding cell.

The method according to the any of the last two

examples, wherein at least one bypass switch is connected between cell connection terminals used for connecting a corresponding cell to the phase arm.

The method according to any previous method example, the phase leg further comprising a third phase arm between a second AC terminal and ground and a fourth phase arm between the second AC terminal and a second pole, the method further comprising controlling the energy storage elements of all the converter cells of the second type in the third phase arm to be bypassed in case of a phase fault on the AC side of the

multilevel converter.

The method according to any previous method example, wherein the fault occurs on another phase than the phase to which the first AC terminal is connected.

From the foregoing discussion it is evident that the present invention can be varied in a multitude of ways It shall consequently be realized that the present invention is only to be limited by the following claims .

Claims

1. A multilevel converter (10) configured to convert between alternating current (AC) and direct current (DC) and comprising

at least one phase arm with a number of cells between a DC pole (PI; P2) and a first AC terminal (ACA1), said cells comprising at least one hybrid full bridge cell (HFBA; HFBB, HFBC; HFBD) for fault current handling operation,

said hybrid full-bridge cell comprising

a first cell connection terminal for coupling to the DC pole,

a second cell connection terminal for coupling to the AC terminal,

an energy storage element (C) having a positive and a negative end

a first group of series connected semiconducting units, which group is connected in parallel with the energy storage element (C) and where the semiconducting units (SU1, SU2) of the first group comprises first and second switching elements (Tl, T2) with first and second anti-parallel unidirectional conducting elements (Dl, D2), where a junction between the first and second semiconducting unit forms one cell connection terminal (TEFBA1; TEFBB1; TEFBC2; TEFBD2),

a second group of semiconducting units, which group is connected in parallel with the energy storage element (C) as well as with the first group and where all the semiconducting units of the second group are connected in series and the second group comprises a third semiconducting unit (SU3) having a third switching element (T3) with anti-parallel unidirectional conducting element (D3) and a fourth semiconducting unit (SU4) consisting of at least one unidirectional conducting element (D) , where a junction between the first and second semiconducting unit forms a further cell connection terminal (TEFBA2; TEFBB2; TEFBC1;

TEFBD1) .

2. The multilevel converter according to claim 1, wherein the third switching element (T3) of the third semiconducting unit (SU3) in the second group is always configured to be on in normal operation of the

converter .

3. The multilevel converter according to claim 1 or 2, wherein all switching elements of the hybrid full- bridge cell are configured to be turned off if a fault current due to a DC pole fault runs through the phase arm.

4. The multilevel converter according to any previous claim, wherein the direction of conduction of the unidirectional conducting elements of the hybrid full- bridge cell is toward the positive end of the energy storage element.

5. The multilevel converter according to any previous claim, wherein the fourth semiconducting unit couples the energy storage element between the first and the second cell connection terminal with a polarity that counteracts negative currents in the phase arm.

6. The multilevel converter according to any previous claim, further comprising a control unit (12) configured to control, when there is a pole fault on a phase leg in which said phase arm is connected, a phase arm current (lap, Ian) to zero when there is a negative phase arm voltage (Vap, Van) during injection of reactive power through the first AC terminal.

7. The multilevel converter according to claim 6, wherein the control involves controlling a circulating current (Iacir) of the phase leg.

8. The multilevel converter according to claim 7, wherein the control unit comprises a circulating current control element (18) configured to provide a circulating current driving voltage (Vacir*).

9. The multilevel converter according to claim 8, wherein the circulating current control element (18) comprises a a subtracting block (34) configured to subtract the actual circulating current from the desired circulating current and supply the results to a proportional and/or integrating control block (34) configured to perform proportional and/or integrating control on said results for obtaining a first control voltage value used in obtaining the circulating current driving voltage.

10. The multilevel converter according to claim 9, further comprising an adding block (38) configured to add a control term to the first control voltage value for obtaining the circulating current driving voltage, where the control term is dependent on the time

derivative of the circulating current.

11. The multilevel converter according to any previous claim, wherein said phase arm with hybrid full-bridge cell (HFBA; HFBC) is provided in a first phase arm between a first pole (PI) and a first AC terminal (ACA1) .

12. The multilevel converter according to any previous claim 11, further comprising a second phase arm between the first AC terminal and ground, wherein the energy storage elements of all the converter cells of the second phase arm are configured to be bypassed in case of a phase fault on the AC side of the multilevel converter .

13. The multilevel converter according to claim 12, wherein all cells of the second phase arm are half- bridge cells, the energy storage elements of which are automatically bypassed as the semiconducting switches are blocking during such AC side faults.

14. The multilevel converter according to claim 12 or

13. wherein at least some of the cells of the second phase arm are hybrid full-bridge cells (HFBD) , each comprising a bypass switch (TH) controllable to bypass the corresponding energy storage element.

15. The multilevel converter according to claim 14, wherein the bypass switch is provided as a part of the third semiconducting unit (SU3) .

16. The multilevel converter according to claim 14, wherein the bypass switch is connected between cell connection terminals (TEFBD1, TEFBD2) .

17. The multilevel converter according to any of claims 12 - 16, the phase leg further comprising a third phase arm between a second AC terminal (ACA2) and ground and a fourth phase arm between the second AC terminal

(ACA2) and a second pole, wherein the fourth phase arm comprises at least one hybrid full-bridge cell and the energy storage elements of all the converter cells of the third phase arm are configured to be bypassed in case of a phase fault on the AC side of the multilevel converter .

18. A method of controlling a phase arm of a phase leg in a voltage source converter converting between alternating current (AC) and direct current (DC) and comprising at least one phase arm with a number of cells according to any of claims 1 - 5, the method comprising

controlling, when there is a pole fault on a pole of a phase leg in which said phase arm is connected, a phase arm current (lap, Ian) to zero when there is a negative phase arm voltage (Vap, Van) during injection of reactive power through the first AC terminal (ACA1) .

19. The method according to claim 18, wherein the controlling comprises controlling a circulating current (Iacir) of the phase leg.

20. The method according to claim 19, wherein the controlling comprises providing a circulating current driving voltage (Vacir*) based on a control loop for the circulating current.

21. The method according to claim 20, wherein the controlling comprises applying a proportional and/or integrating control on the difference between the desired and actual circulating current (Iacir*. Iacir) for obtaining a first control voltage value used in obtaining the circulating current driving voltage.

22. The method according to claim 21, wherein the control comprises adding a control term to the first control voltage value for obtaining the circulating current driving voltage, where the control term is dependent on the time derivative of the circulating current .

23. A method for reducing the voltage rating required for a phase arm in a voltage source converter

configured to convert between alternating current (AC) and direct current (DC) and comprising a first phase arm between a first pole (PI) and a first AC terminal (ACA1) with a number of cells according to any of claims 1 - 5 and a second phase arm between the first AC terminal and ground, where at least some of the cells of the second phase arm are hybrid full-bridge cells

where the method comprises controlling the energy storage elements of all the hybrid full-bridge cells of the second phase arm to be bypassed in case of a phase fault on the AC side of the multilevel converter.

24. The method according to claim 23, wherein all the hybrid full-bridge cells of the second phase arm comprise a bypass switch (TH) and the controlling comprises activating the bypass switches to bypass corresponding energy storage elements when the phase fault occurs on the AC side of the multilevel converter .

25. The method according to claim 23 or 24, where the fault occurs on another phase than the phase to which the first AC terminal is connected.