WO2013019240A1

WO2013019240A1 - Semiconductor driver circuit for high inverter effeciency in solar application

Info

Publication number: WO2013019240A1
Application number: PCT/US2011/046595
Authority: WO
Inventors: Madhuwanti Joshi; Bruce Modick; Johan ENSLIN
Original assignee: Petra Solar, Inc.
Priority date: 2011-08-04
Filing date: 2011-08-04
Publication date: 2013-02-07

Abstract

A method and system for semiconductor gate driver with high efficiency may be provided. The gate driver is operated with two or more power supplies or a single variable power supply. First, an output power value may be received. Then a controller may generate a signal which may be transmitted in response to the received output power value. The controller output may be configured to: i) cause a first supply voltage input to be supplied when the output power value is within a first predetermined range; and ii) cause a second supply voltage input to be supplied when the output power value is within a second predetermined range.

Description

SEMICONDUCTOR DRIVER CIRCUIT FOR HIGH INVERTER EFFICIENCY IN SOLAR APPLICATION

This application is being filed on 04 August 201 1, as a PCT International Patent application in the name of Petra Solar, Inc., a U.S. national corporation, applicant for the designation of all countries except the U.S., and Madhuwanti Joshi, a citizen of the U.S., Bruce Modick, a citizen of the U.S., and Johan Enslin, a citizen of the Netherlands, applicants for the designation of the U.S. only.

BACKGROUND [001] With the growing initiative for clean energy, solar energy is becoming an important power generation element. In a solar power plant, energy from the Sun is converted into a direct current (DC) voltage by photovoltaic cells and then converted to a grid compatible alternating current (AC) voltage by a DC to AC voltage converter or inverter. This inverter may either be a string inverter, which takes input from many panels or a micro-inverter, which takes input from a single panel.

SUMMARY

[002] A method and system for controlling a semiconductor gate driver supply voltage in relation to the output power may be provided. First, an output power value may be received. Then a control input may be transmitted to the gate driver in response to the received output power value. The control input may be configured to: i) connect a first supply voltage to the gate driver when the output power value is within a first predetermined range; and ii) connect a second supply voltage input to be supplied when the output power value is within a second predetermined range.

[003] Both the foregoing general description and the following detailed description are examples and explanatory only, and should not be considered to restrict the invention's scope, as described and claimed. Further, features and/or variations may be provided in addition to those set forth herein. For example, embodiments of the invention may be directed to various feature combinations and sub-combinations described in the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[004] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate various embodiments of the present invention. In the drawings:

[005] FIG. 1 shows a prior art circuit;

[006] FIG. 2 shows another prior art circuit;

[007] FIG. 3 shows a normalized gate drive and conduction losses vs. power;

[008] FIG. 4 shows a modified gate driver circuit;

[009] FIG. 5 shows a gate driver circuit for semiconductor switching in a half bridge configuration;

[010] FIG. 6 shows resultant semiconductor losses using the inputs of table

1;

[011] FIG. 7 shows a comparison of overall losses;

[012] FIG. 8 shows a controller; and

[013] FIG. 9 shows another controller configuration.

DETAILED DESCRIPTION

[014] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the following description to refer to the same or similar elements. While embodiments of the invention may be described, modifications, adaptations, and other implementations are possible. For example, substitutions, additions, or modifications may be made to the elements illustrated in the drawings, and the methods described herein may be modified by substituting, reordering, or adding stages to the disclosed methods. Accordingly, the following detailed description does not limit the invention. Instead, the proper scope of the invention is defined by the appended claims.

[015] A conventional solar inverter comprises a DC voltage followed by a high frequency switching circuit, a transformer, a rectifier, and either a low frequency or a second high frequency switching circuit connected in cascade. The high frequency switching stage comprises semiconductors like MOSFETs, BJTs, IGBTs and their driving circuits. High efficiency is a desirable trait for solar inverters. As solar power varies with Sun conditions, inverters are faced with the challenge of converting DC input power from the solar panels to AC power at the highest possible efficiency at various input voltages and the power levels.

Achieving high efficiency at one operating point may be easy because all the circuit elements in the inverter can be optimized around that one operating point. But to have high efficiency for the inverter over its entire operating range of power and voltage is a difficult task.

[016] Inverter losses can be divided into two categories. The first inverter loss category may comprise power independent losses that may be constant losses (e.g. the losses independent of the output power.) The second inverter loss category may comprise power dependent losses that may be variable losses (e.g. losses varying with the output power.) Power independent losses, for example, may be gate drive losses, control circuit losses, or core losses in the transformer. Power dependent losses, for example, may be semiconductor conduction losses, copper losses in the transformer, etc. To achieve high average inverter efficiency at various power levels, power independent losses may be kept to a minimum level.

Reductions in these power independent losses may increase the average efficiency of the inverter significantly. Embodiments of the invention may focus on processes that may reduce power independent losses comprising gate drive losses, for example.

[017] FIG. 1 shows a solar inverter configuration with a conventional gate drive circuit for a single switching semiconductor device. The semiconductors are switched by two circuits. The first circuit is the controller that senses the input and output power, current, and voltage and based on that, gives a control signal 105 to the driver circuit. In the driver, control signal 105 goes through a logic level adjuster circuit (e.g. similar to a Schmitt trigger). Then it goes through a level shift circuit. Control signal 105 further goes through a logic circuit block and then to a driver/buffer circuit. The driver may have P channel and N channel MOSFETs connected in series as shown in FIG. 1. Most of the drivers have an under voltage detection (UV detect) circuit 110. Under voltage detection (UV detect) circuit 110 senses the supply voltage of the driver and sends a signal to the logic circuit to force the gate signal in to a tristate or low level logic state. [018] FIG. 2 shows another solar inverter configuration with conventional gate drive circuit that drives two MOSFETs connected in half bridge configuration. Similar to Fig. 1, it has two control signals from the controller that as inputs to the two gate driver circuits. It also has an additional bootstrap circuit for floating the ground of the top gate driver with respect to the bottom gate driver.

Semiconductor Loss Analysis for Conventional Systems

[019] The losses in the semiconductor may depend on a gate driver circuit. The total losses in the semiconductor may be given by equation 1 below.

Total ser i onductor losses = Conduction losses -f switching losses + gate drive losses (1)

The processes described below with respect to embodiments of the invention do not affect switching losses. So for this discussion the switching losses have been ignored.

[020] The conduction losses may be given by equation 2 below. Conduction lass = Current² x On state resistance of the device

(2)

The on state resistance may depend on the gate drive voltage. For lowest on state resistance of the device, the gate drive voltage may need to be above a certain threshold voltage. Most of the manufacturers specify operating gate drive voltage for the minimum on state resistance. However with a high gate drive voltage, the gate drive circuit losses increase. The gate drive losses are given by equation 3. Gate drive losses = Gate charge x driver voltage x switching f requency

(3)

The gate charge is further dependent on the driver voltage and the input capacitance of the device.

The overall gate drive loss equation then becomes as follows:

Gate drive losses = overall input capacitance at the gate x (gate drive voltage)²

(4)

It is clear from equation 4 that the gate drive losses are dependent on gate drive voltage. [021] FIG. 3 shows the normalized gate drive and conduction losses vs. power for a typical semiconductor in a solar inverter. From FIG. 3, it is apparent that at low power output, the gate drive losses are significant. In the prior art gate driver, as only one supply voltage is used, it can not be optimized for high power or low power and as a result the driver circuit is very lossy at some of the power levels. Embodiments of the invention may use a scheme of varying the gate driver power supply in relation to the output power or output current and/or output voltage. In the simplest case, the gate driver may be operated by two supplies.

[022] FIG. 4 shows a solar inverter configuration with a modified gate driver circuit 400 consistent with embodiments of the invention. As shown in FIG. 4, modified gate driver circuit 400 has a first supply voltage input 405 (e.g. V_cci), a second supply voltage input 410 (e.g. V_cc2), and a control signal input 415. Control signal input 415 may give an input to a first switch 420 and a second switch 425 to select an appropriate supply voltage (e.g. V_cci or V_cc2) for modified gate driver circuit 400. Control signal input 415 may be dependent on an output power 430 of modified gate driver circuit 400. Control signal input 415 may be supplied from a control circuit (e.g. a controller 800 described below) sensing output power 430 of modified gate driver circuit 400. Control input 415 may also give input to an undervoltage detection circuit. Based on control input 415, the under- voltage circuit may select an appropriate under-voltage lockout threshold levels.

[023] FIG. 5 shows another inverter configuration with modified driver circuit 500 for two devices switching in a half bridge configuration. Similar to modified gate driver circuit 400, modified driver circuit 500 includes an approach for the gate driver circuit for semiconductors switching in half bridge configuration. A converter may have two power supplies available having the same ground as the gate driver circuit. If more than two power supplies are available, then this approach can be modified to use more power supplies.

Semiconductor Loss Analysis Using the Modified Driver Circuit

[024] A sample loss analysis may be implemented using the modified gate driver scheme of FIG. 4 and/or FIG. 5 using equations 1 to 3. Table 1 shows the logic levels used for the sample analysis and comparison. 5

Table 1

The resultant semiconductor losses using the inputs of Table 1 are shown in FIG. 6. All the values shown in FIG. 6 are normalized with their maximum values. FIG. 7 shows a comparison of the overall losses using conventional systems and the modified gate driver consistent with embodiments of the present invention. In this analysis only two thresholds of output power namely 0 to 50% and 50% to 100% have been considered. Also, the thresholds of output power may be any range and are not limited to 0 to 50% and 50% to 100% and may be, for example, 0% to 30% and 30% to 80%. Based on efficiency requirements, more than two thresholds may also be used comprising various corresponding ranges. If the gate driver is operated with a time variable supply, then the control input may dynamically adjust the gate driver supply voltage depending on the output power. This approach is shown in FIG. 8 with a controller 800. The controller gives one input to modify the threshold voltage of the undervoltage lockout circuit and another input to change the reference voltage of the gate driver power supply.

[025] The controller 800 takes the input from either the output power or the output current and/or output voltage of the solar inverter. Based on the efficiency requirements of the inverters, the threshold limits for changing the supply voltage can be predetermined. Those limits are also input to the controller. The controller then compares the two inputs and generates one or multiple control signals to modify the gate driver power supply and also to change the threshold voltage for the undervoltage lockout limit. In its simplest form, controller 800 may be implemented by an operational amplifier and/or some discrete elements like resistor, capacitor, bipolar transistors, MOSFETs, IGBTs and diodes.

[026] FIG. 9 shows one of the possible controller configurations. As shown in FIG. 9, controller 800 may include a processing unit 810 and a memory unit 815. Memory unit 815 may include a selecting software module 820 and a selecting database 825. While executing on processing unit 805, selecting software module 820 may perform processes for providing control input 415 based upon output power 430 as described above. For example, as illustrated in Table 1, controller 800 may receive output power 430 at a level between 0% and 50% of a maximum value of output power 430. Consequently, controller 800 may supply control input 415 configured to cause first switch 420 to be closed and for second switch 425 to be opened in order to supply V_cci to modified gate driver circuit 400. Similarly, controller 800 may receive output power 430 at a level between 50% and 100% of the maximum value of output power 430. Consequently, controller 800 may supply control input 415 configured to cause first switch 420 to be open and for second switch 425 to be closed in order to supply V_cc2 to modified gate driver circuit 400. V_cc2 may be greater than V_CC]. While the above example shows two supply voltages and two ranges, any number of supply voltages and ranges may be used.

[027] Controller 800 ("the processor") may also be implemented using a mobile device, a personal computer, a network computer, a mainframe, or other similar microcomputer-based device. The processor may comprise any computer operating environment, such as hand-held devices, multiprocessor systems, microprocessor-based or programmable sender electronic devices, minicomputers, mainframe computers, and the like. The processor may also be practiced in distributed computing environments where tasks are performed by remote processing devices. Furthermore, the processor may comprise, for example, a mobile terminal, such as a smart phone, a cellular telephone, a cellular telephone utilizing Wireless Application Protocol (WAP) or unlicensed mobile access (UMA), personal digital assistant (PDA), intelligent pager, portable computer, a hand held computer, a conventional telephone, or a Wireless Fidelity (Wi-Fi) access point. The aforementioned systems and devices are examples and the processor may comprise other systems or devices.

[028] Controller 800 may communicate over a network. The network may comprise, for example, a local area network (LAN) or a wide area network (WAN). Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets, and the Internet. When a LAN is used as the network, a network interface located at any of the processors may be used to interconnect any of the processors. When the network is implemented in a WAN networking environment, such as the Internet, the processors may typically include an internal or external modem (not shown) or other means for establishing communications over the WAN. Further, in utilizing the network, data sent over the network may be encrypted to insure data security by using known encryption/decryption techniques.

[029] In addition to utilizing a wire line communications system as the network, a wireless communications system, or a combination of wire line and wireless may be utilized as the network in order to, for example, exchange web pages via the Internet, exchange e-mails via the Internet, or for utilizing other communications channels. Wireless can be defined as radio transmission via the airwaves. However, it may be appreciated that various other communication techniques can be used to provide wireless transmission, including infrared line of sight, cellular, microwave, satellite, packet radio, and spread spectrum radio. The processors in the wireless environment can be any mobile terminal, such as the mobile terminals described above. Wireless data may include, but is not limited to, paging, text messaging, e-mail, Internet access and other specialized data applications specifically excluding or including voice transmission. For example, the processors may communicate across a wireless interface such as, for example, a cellular interface (e.g., general packet radio system (GPRS), enhanced data rates for global evolution (EDGE), global system for mobile communications (GSM)), a wireless local area network interface (e.g., WLAN, IEEE 802), a bluetooth interface, another RF communication interface, and/or an optical interface.

[030] Embodiments of the invention may be practiced in an electrical circuit comprising discrete electronic elements, packaged or integrated electronic chips containing logic gates, a circuit utilizing a microprocessor, or on a single chip containing electronic elements or microprocessors. Embodiments of the invention may also be practiced using other technologies capable of performing logical operations such as, for example, AND, OR, and NOT, including but not limited to mechanical, optical, fluidic, and quantum technologies. In addition, embodiments of the invention may be practiced within a general purpose computer or in any other circuits or systems.

[031 ] Embodiments of the invention, for example, may be implemented as a computer process (method), a computing system, or as an article of manufacture, such as a computer program product or computer readable media. The computer program product may be a computer storage media readable by a computer system and encoding a computer program of instructions for executing a computer process. The computer program product may also be a propagated signal on a carrier readable by a computing system and encoding a computer program of instructions for executing a computer process. Accordingly, the present invention may be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). In other words, embodiments of the present invention may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. A computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[032] The computer-usable or computer-readable medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific computer-readable medium examples (a non-exhaustive list), the computer- readable medium may include the following: an electrical connection having one or more wires, a portable computer diskette, a random access memory (RAM), a readonly memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CD-ROM). Note that the computer-usable or computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

[033] Embodiments of the present invention, for example, are described above with reference to block diagrams and/or operational illustrations of methods, systems, and computer program products according to embodiments of the invention. The functions/acts noted in the blocks may occur out of the order as shown in any flowchart. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

[034] Embodiments of the invention may be practiced via a system-on-a- chip (SOC) where each or many of the components illustrated in FIG. 4, FIG. 5, FIG. 8, and FIG. 9 may be integrated onto a single integrated circuit. Such an SOC device may include one or more processing units, graphics units, communications units, system virtualization units and various application functionality all of which may be integrated (or "burned") onto the chip substrate as a single integrated circuit. When operating via an SOC, the functionality described herein with respect to embodiments of the invention, may be performed via application-specific logic integrated with other components on the single integrated circuit (chip).

[035] While the specification includes examples, the invention's scope is indicated by the following claims. Furthermore, while the specification has been described in language specific to structural features and/or methodological acts, the claims are not limited to the features or acts described above. Rather, the specific features and acts described above are disclosed as example for embodiments of the invention.

Claims

WHAT IS CLAIMED IS:

1. A method for reducing power independent losses, the method comprising:

receiving an output power value; and

transmitting a control input in response to the received output power value, the control input being configured to;

cause a first supply voltage input to be supplied when the output power value is within a first predetermined range, and

cause a second supply voltage input to be supplied when the output power value is within a second predetermined range.

2. The method of claim 1, wherein reducing the power independent losses comprises reducing gate drive losses.

3. The method of claim 1 , wherein transmitting the control input comprises transmitting the control input wherein the first supply voltage input is less than the second supply voltage input.

4. The method of claim 1, wherein transmitting the control input comprises transmitting the control input wherein the first predetermined range is less than the second predetermined range.

5. The method of claim 1, wherein transmitting the control input comprises transmitting the control input to a semiconductor driver circuit for a single device.

6. The method of claim 1, wherein transmitting the control input comprises transmitting the control input to a semiconductor driver circuit for two devices connected in a half bridge configuration.

7. The method of claim 1, wherein transmitting the control input comprises transmitting the control input wherein the first predetermined range comprises between 0% and 50% of the received output power value.

8. The method of claim 1, wherein transmitting the control input comprises transmitting the control input wherein the second predetermined range comprises between 50% and 100% of the received output power value.

9. A system for reducing power independent losses in a solar inverter, the system comprising:

a gate driver circuit having at least two power supplies;

a switching network comprising at least two switches;

an undervoltage detection circuit having a controllable threshold voltage; and a controller configured to;

receive input from output power of the solar inverter, and control the power supply of the gate driver and the threshold voltage of the undervoltage detection circuit.

10. The system of claim 9, wherein the controller comprises a processing unit coupled with a memory storage.

11. The system of claim 9, wherein the controller comprises one of the following: an analog device, a logic device, and a discrete semiconductor switch.

12. The system of claim 9, wherein the controller is operative to transmit a control input to a semiconductor driver circuit for a single device.

13. The system of claim 9, wherein the controller is operative to transmit a control input to a semiconductor driver circuit for two devices connected in a half bridge configuration.

14. The system of claim 9, wherein the controller may be implemented as a part of the gate driver circuit or it may be implemented separately.

15. The system of claim 9, wherein the controller comprises an integrated circuit.

*

16. The system of claim 9, wherein the gate driver has at least two supplies.

17. The system of claim 9, wherein the gate driver has a single supply voltage that varies with time and is controlled by the controller.

18. The system of claim 9, wherein the gate driver has a switching network with at least one switch to select the appropriate power supply.

19. The system of claim 9, wherein the gate driver has at least one control inputs to control the switching network and the threshold voltage of the undervoltage detection circuit.

20. The system of claim 9, wherein the gate driver has an undervoltage detection circuit having controllable threshold voltage.

21. The system of claim 9, wherein the system comprises a system-on-a- chip (SOC).

22. A method for reducing power independent losses in a solar inverter, the method comprising using a controller to vary a supply voltage supplied to a gate driver of a solid state device relative to an output power level of the solar inverter.

23. The method of claim 22, wherein using the controller to vary the supply voltage supplied to the gate driver of the solid state device comprises using the controller to vary the supply voltage supplied to the gate driver of the solid state device comprising a MOSFET.

24. The method of claim 22, further comprising the controller changing a threshold value of an undervoltage lockout circuit in relation with the output power level of the solar inverter.