WO2012169720A1

WO2012169720A1 - Graphene transistor and method for manufacturing same

Info

Publication number: WO2012169720A1
Application number: PCT/KR2012/001434
Authority: WO
Inventors: 안성진
Original assignee: 금오공과대학교 산학협력단
Priority date: 2011-06-08
Filing date: 2012-02-24
Publication date: 2012-12-13
Also published as: KR20120136118A; KR101245353B1

Abstract

Provided is a graphene transistor. The graphene transistor includes: a graphene active layer disposed on an insulation substrate; a gate electrode disposed on the graphene active layer; and an oxide graphene layer disposed between the gate electrode and the graphene active layer. The oxide graphene layer has a top surface that is coplanar to the graphene active layer.

Description

Graphene transistor and its manufacturing method

The present invention relates to a graphene transistor, and more particularly, to a transistor using graphene as an active layer and an insulating film and a method of manufacturing the same. The present invention is a basic research project carried out with the support of the Korea Research Foundation as a fund of the Korean government (Ministry of Education, Science and Technology) in 2011. Assignment number 2011-0014415.

With the development of the IT industry, silicon-based electronics have made remarkable progress over the last half century. However, recently, as optical lithography-based electronic device technology gradually reaches saturation in density and processing speed, there is a need for development of a material having an excellent charge mobility than conventional silicon. Graphene refers to a carbon allotrope in which carbon is arranged in a honeycomb form sp ² bonds on a two-dimensional plane. Graphene is very structurally and chemically stable and has a charge mobility about 100 times higher than that of silicon. In addition, graphene has high transparency and excellent thermal / mechanical properties. Various studies are being conducted to use the excellent properties of such graphene.

One object of the present invention is to provide a transistor using graphene. Another object of the present invention is to provide a method of manufacturing a transistor that can be used as a gate insulating film by oxidizing graphene.

A graphene transistor is provided for solving the above technical problems. The graphene transistor includes a graphene active layer on an insulating substrate, a gate electrode on the graphene active layer, and a graphene oxide layer between the gate electrode and the graphene active layer, wherein an upper surface of the graphene oxide layer is formed of the graphene active layer. Coplanar with the top surface.

In one embodiment, the graphene oxide layer may be provided in the upper portion of the graphene active layer.

In example embodiments, the graphene active layer may include a channel region between the graphene oxide layer and the insulating substrate and source / drain regions provided at both sides of the channel region. The thickness of the channel region may be thinner than the thickness of the source / drain regions.

Provided is a method of manufacturing a graphene transistor for solving the above technical problems. The method may include forming a graphene active layer on an insulating substrate, oxidizing a portion of the upper portion of the graphene active layer to form a graphene oxide layer, and forming a gate electrode on the graphene oxide layer. have.

In one embodiment, the thickness of the graphene oxide layer may be formed thinner than the thickness of the graphene active layer.

In example embodiments, the forming of the graphene oxide layer may include forming a first mask layer covering the first region of the graphene active layer and oxidizing an upper portion of the second region exposed by the first mask layer. And the first mask layer may be removed. The graphene oxide may be limited to the upper portion of the second region, and the lower portion of the second region may not be oxidized.

In example embodiments, the method may further include forming source / drain electrodes on the second region, and the source / drain electrodes may be simultaneously formed with the gate electrode.

In one embodiment, forming the graphene active layer on the insulating substrate includes forming the graphene active layer on a growth substrate, and transferring the graphene active layer onto the insulating substrate. can do.

In example embodiments, the forming of the graphene active layer on the growth substrate may be performed by at least one of chemical vapor deposition, epitaxy synthesis, and exfoliation.

In one embodiment, reducing the first region of the graphene oxide layer to form a graphene active layer, forming a gate electrode on the second region of the graphene oxide layer is not formed, and The method may include forming source / drain electrodes on the graphene active layer.

In one embodiment, the graphene active layer may be formed thinner than the thickness of the graphene oxide layer.

In example embodiments, the graphene active layer may be spaced apart from the gate electrode by the second region.

In one embodiment, forming the graphene active layer includes growing the graphene oxide layer on a growth substrate, reducing top and sidewalls of the graphene oxide layer, and insulating the reduced graphene oxide layer. Transferring onto a substrate, wherein the transfer process may be performed such that the top surface of the graphene oxide layer is in contact with the top surface of the insulating substrate. At least a portion of the lower portion of the graphene oxide layer in contact with the growth substrate may not be reduced.

In one embodiment, further comprising providing the graphene oxide layer on an insulating substrate, wherein forming the graphene active layer is to form a second mask layer on the graphene oxide layer and the insulating substrate, and It may include performing a reduction process on the graphene oxide layer exposed by the second mask layer.

In example embodiments, an upper portion of the graphene oxide layer in contact with the second mask layer may not be reduced, and a lower portion of the graphene oxide layer in contact with the insulating substrate in a region under the second mask may be reduced.

According to an embodiment of the present invention, a transistor capable of high-speed operation by a relatively high mobility and conductivity of the graphene active layer can be formed, and a relatively simple process by oxidizing a portion of the graphene active layer as a gate insulating film By the graphene transistor can be formed.

1 is a perspective view of a graphene transistor according to embodiments of the present invention.

2 to 5 are cross-sectional views illustrating a method of manufacturing a graphene transistor according to an embodiment of the present invention.

6 to 9 are plan views and cross-sectional views illustrating a method of manufacturing a graphene transistor according to another exemplary embodiment of the present invention.

10 to 12 are cross-sectional views illustrating a method of manufacturing a graphene transistor according to still another embodiment of the present invention.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, in the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. Also, in various embodiments herein, the terms first, second, third, etc. are used to describe various regions, films (or layers), etc., but these regions, films are defined by these terms. It should not be. These terms are only used to distinguish any given region or film (or layer) from other regions or films (or layers). Thus, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

Referring to FIG. 1, a graphene transistor 10 including a graphene layer is provided. The graphene transistor 10 includes a graphene active layer 110, a gate electrode 151 on the graphene active layer 110, and a gate insulating layer 120 between the graphene active layer 110 and the gate electrode 151. ) May be included. The graphene active layer 110 may be an active layer of the graphene transistor 10. In the present specification, as well as monolayer graphene, a graphene may refer to a stack of a few monolayer graphene (few monolayers). For example, the small number may be 6 or less. This definition applies equally to graphene oxide.

The graphene active layer 110 may include a source region S and a drain region D in which relatively many layers are stacked. For example, the source and drain regions S and D may have a structure in which single layer graphene is stacked in about 4 to 6 layers. Graphene exhibits various electrical properties depending on the number and shape of the stacked layers. As an example, in the case of graphene stacked about four or more layers such as the source drain regions S and D, the graphene layer may have an electrical property close to a metal. That is, the source and drain regions S and D may be conductive like the doped semiconductor material.

The graphene active layer 110 may further include a channel region C between the source region S and the drain region D. FIG. The channel region C may have a structure in which a relatively small number of single layer graphene is stacked as compared with the source and drain regions S and D. FIG. For example, the channel region C may have a structure in which about 1 to 3 single layer graphenes are stacked. Graphene may have a relatively close semiconductor property when the number of stacked layers is small. That is, the channel region C may be used as a channel of the graphene transistor 10 between the source and drain regions S and D, and according to the voltage applied to the gate electrode 151. And the drain regions S and D may or may not be electrically connected to each other.

The band gap of the channel region C may be adjusted by various methods. For example, the channel region C may be a fluorine-treated graphene layer. In another embodiment, the band gap of the channel region C may be adjusted by adsorbing water molecules under the channel region C. According to another embodiment, the width of the channel region C in the x direction may be relatively smaller than that of the source and drain regions S and D, unlike shown.

The gate insulating layer 120 may be a graphene oxide layer. An upper surface of the gate insulating layer 120 may form a coplanar with an upper surface of the graphene active layer 110. The gate insulating layer 120 may be provided in an upper portion of the graphene active layer 110. The gate insulating layer 120 may be formed by oxidizing a portion of the upper portion of the graphene active layer 110 as described below in the manufacturing method. Accordingly, the top surface of the gate insulating layer 120 may be coplanar with the top surfaces of the source and drain regions S and D, and the gate insulating layer 120 may be provided in an upper portion of the graphene active layer 110. Can be.

Source and

drain electrodes

141 and 142 may be provided on the source and drain regions S and D, respectively. The source and drain

electrodes

141 and 142 and the gate electrode 151 may be formed of the same material. For example, the source and drain

electrodes

141 and 142 and the gate electrode 151 may include at least one of metal or conductive metal nitride. Although omitted for simplicity, the graphene transistor 10 may be formed on a substrate (not shown), and the graphene active layer 110 and the gate insulating layer 120 may be covered by an insulating layer.

2 to 5 are cross-sectional views illustrating a method for manufacturing a graphene transistor according to an embodiment of the present invention.

Referring to FIG. 2, the graphene active layer 110 may be formed on the insulating substrate 100. The graphene active layer 110 may be formed by various methods. The insulating substrate 100 may be a quartz substrate, a glass substrate, or a silicon substrate having a silicon oxide layer formed thereon.

For example, the graphene active layer 110 may be formed by chemical vapor deposition (CVD). For example, a metal catalyst layer may be deposited on a growth substrate (not shown), and a carbon source gas may be supplied to absorb or deposit carbon atoms on the metal catalyst layer. Thereafter, the graphene layer may be formed by crystallizing carbon atoms on the metal catalyst layer through a cooling process. For example, the metal catalyst layer may be formed of nickel and / or copper, and the source gas may be methane and / or hydrogen mixed gas. The graphene layer formed as described above may be moved onto the insulation substrate 100 or may be formed from the metal catalyst layer by forming a metal catalyst layer on the insulation substrate 100. The thickness of the graphene active layer 110 may be adjusted by adjusting the type and thickness of the metal catalyst layer, the concentration of the reaction gas, and the like.

In another embodiment, the graphene active layer 110 may be formed by an epitaxy synthesis method using silicon carbide (SiC). That is, graphene may be grown by heating the silicon carbide layer at a high temperature to move carbon contained in the crystal to the surface. In another embodiment, the graphene active layer 110 may be formed by mechanical peeling or chemical peeling.

A mask layer may be formed on the resultant on which the graphene active layer 110 is formed. The mask layer may be the first resist layer 130. The first resist layer 130 may be a photoresist or an electron beam (e-beam) resist.

Referring to FIG. 3, a first resist pattern 131 may be formed from the first resist layer 130 by a lithography process. The lithographic process may be photolithography or electron beam lithography. The first resist pattern 131 may expose a portion of the top surface of the graphene active layer 110. For example, the first resist pattern 131 may be formed in consideration of the shape of the graphene oxide layer to be described below.

An upper portion of the graphene active layer 110 exposed by the first resist pattern 131 may be oxidized to form a gate insulating layer 120. The gate insulating layer 120 may be a graphene oxide layer. The gate insulating layer 120 may be formed to be limited to an upper portion of the graphene active layer 110. For example, when the graphene active layer 110 includes about 4 to 5 mono graphene layers, about 2-3 layers of the mono graphene layers are oxidized to form a gate insulating layer 120. And the mono graphene layers below it may not be oxidized. The selective oxidation of the graphene active layer 110 may be performed by various methods of dry / wet. For example, after the insulating substrate 100 having the graphene active layer 110 is placed in sulfuric acid, potassium permanganate is gradually added, and the temperature is increased to 35 ° C., followed by Teflon coated. A bar magnet can be placed and stirred for about 2 hours. Thereafter, a sufficient amount of water may be added, and hydrogen peroxide may be added until no gas is generated to form the gate insulating layer 120. The gate insulating layer 120 may be dried for about 12 hours or more under room temperature-vacuum. When the graphene active layer 110 is wet-oxidized as described above, the formation thickness of the gate insulating layer 120 may be controlled by adjusting the exposure time to the oxidizing liquid. Alternatively, the gate insulating film may be formed by various known methods.

The shape of the gate insulating layer 120 may be variously modified according to the oxidation process. For example, the width of the gate insulating layer 120 may be wider than the lower portion as shown.

Referring to FIG. 4, after forming the gate insulating layer 120, the first resist pattern 131 may be removed. A second resist pattern 132 for forming electrodes may be formed on the graphene active layer 110 and the gate insulating layer 120. The second resist pattern 132 may be a resist pattern for forming source / drain regions and a gate electrode to be described below. The second resist pattern 132 may be formed in consideration of shapes of the gate electrode and the source / drain electrodes to be described below.

Referring to FIG. 5, a gate electrode 151 may be formed on the gate insulating layer 120, and source /

drain electrodes

141 and 142 may be formed on the graphene active layer 110. The gate electrode 151 and the source /

drain electrodes

141 and 142 may be formed using the second resist pattern 132. For example, after the conductive layer is formed on the resultant product on which the second resist pattern 132 is formed, the gate electrode 151 and the source / drain electrodes 141 may be formed by performing a life-off process. 142 may be formed. In another embodiment, the gate electrode 151 and the source /

drain electrodes

141 and 142 may be formed by an attaching process using a conductive adhesive layer.

The graphene active layer 110 under the source electrode 141 may be used as a source region S of a graphene transistor, and the graphene active layer 110 under the drain electrode 142 may be a drain region of a transistor. (D) can be used. A lower portion of the graphene active layer 110 spaced apart from the gate electrode 151 by the gate insulating layer 120 may be used as the channel region C of the graphene transistor.

6 to 9 are plan views and cross-sectional views illustrating a method of manufacturing a graphene transistor according to another exemplary embodiment of the present invention. For simplicity, a detailed description of the same configuration may be omitted.

6 and 7, a graphene oxide layer 115 may be formed on the growth substrate 105. FIG. 7 is a cross-sectional view taken along line AA ′ of FIG. 6. For example, the graphene oxide layer 115 may be formed on the growth substrate 105 by the above-described chemical vapor deposition and oxidation process. The growth substrate 105 may be a metal substrate. In another embodiment, the graphene oxide layer 115 may be formed wet. For example, graphite is added to sulfuric acid, potassium permanganate is slowly added, the temperature is increased to 35 ° C, and teflon-coated bar magnets are stirred for about 2 hours. . Thereafter, a sufficient amount of water is added and hydrogen peroxide is added until no gas is generated. Thereafter, the graphite oxide is filtered through a glass filter, and then dried at room temperature and under vacuum for at least about 12 hours. The dried graphite oxide is added to an appropriate amount of water according to the intended use, and the graphite oxide is peeled off by ultrasonication to form graphene oxide sheets. The longer the sonication time, the smaller the size of the formed graphene oxide sheets. Alternatively, in order to control the size of the graphene oxide sheets may be slowly peeled off by stirring with a Teflon coated bar magnet. Alternatively, the graphene oxide sheets may be formed by various known methods. The graphene sheets may be amorphous in various forms depending on the form of the graphite oxide, the method of ultrasonication, and the stirring method.

The graphene oxide layer 115 formed as described above may be deposited on the growth substrate 105 by various methods. For example, the graphene oxide layer 115 may be spin coated, Langmuir-Blodgett method or layer-by-layer method (LBL), deep coating, spray coating. ), Or drop coating may be applied on the growth substrate 105 by at least one method.

A mask pattern 161 may be formed to cover both edges of the graphene oxide layer 115 facing each other. The mask pattern 161 may prevent the both edges of the graphene oxide layer 115 from being reduced in a reduction process to be described below.

Referring to FIG. 8, a portion of the graphene oxide layer 115 may be reduced to form the graphene active layer 110. For example, the reduction of the graphene oxide layer 115 is performed using a reducing agent including at least one of various reducing materials such as hydrazine, phenyl hydrazine, sodium hydride, and potassium hydroxide (KOH). Can be. The reduction process may be performed inward from the top and side surfaces of the graphene oxide layer 115 exposed to the outside. A central portion of the graphene oxide layer 115 that is not exposed to the outside may be maintained in the graphene oxide state without being reduced to become the gate insulating layer 120. Such partial reduction of the graphene oxide layer 115 may be achieved by controlling the time for exposing the graphene oxide layer 115 to the reducing agent.

Referring to FIG. 9, the graphene active layer 110 and the gate insulating layer 120 formed on the growth substrate 105 may be transferred onto the insulating substrate 100. The transfer process may be performed through an adhesive layer (not shown) on the insulating substrate 100. For example, an upper surface of the growth substrate 105 on which the graphene active layer 110 and the gate insulating layer 120 are formed is attached onto the insulating substrate 100 using an adhesive layer, and then the growth substrate 105 is formed. Can be removed. The graphene active layer 110 and the gate insulating layer 120 transferred onto the insulating substrate 100 may be substantially the same as the shape shown in FIG. 3. That is, the gate insulating layer 120 may be provided on the graphene active layer 110 to be exposed to the outside, and a graphene active layer to be used as a channel region may be provided below the gate insulating layer 120. Hereinafter, the electrode forming process is the same as described with reference to FIGS. 4 and 5.

10 to 12 are cross-sectional views illustrating a method of manufacturing a graphene transistor according to still another embodiment of the present invention. For the sake of simplicity, descriptions of overlapping configurations will be omitted.

Referring to FIG. 10, a graphene oxide layer 115 may be formed on the insulating substrate 100. The graphene oxide layer 115 may be formed directly on the insulating substrate 100 or may be formed on the insulating substrate 100 using a growth substrate (not shown) as described above. The first resist layer 130 may be formed on the resultant on which the graphene oxide layer 115 is formed.

11 and 12, a first resist pattern 131 exposing a portion of the graphene oxide layer 115 may be formed. The first resist pattern 131 may be formed by various lithography processes using the first resist layer 130. A portion of the graphene oxide layer 115 may be reduced using the first resist layer 130 to form the graphene active layer 110. Reduction of the graphene oxide layer 115 may be performed using a reducing agent including at least one of hydrazine, phenyl hydrazine, sodium hydride, and potassium hydroxide (KOH). The reducing agent may gradually reduce the graphene oxide layer 115 exposed by the first resist pattern 131 from top to bottom. During the reduction process, an upper portion of the graphene oxide layer 115 covered by the first resist pattern 131 may be maintained without being reduced to become the gate insulating layer 120. The arrow shown in FIG. 13 is a movement path of the reducing agent, the reducing agent moves from the top to the bottom of the graphene oxide layer 115, and along the boundary between the graphene oxide layer 115 and the insulating substrate 100. Can be moved. Therefore, the upper portion of the graphene oxide layer 115 spaced apart from the interface between the graphene oxide layer 115 and the insulating substrate 100 may not be reduced. Hereinafter, the process of forming the electrodes after the removal of the first resist pattern 131 may be performed as described with reference to FIGS. 4 and 5.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims

Graphene active layer on an insulating substrate;

A gate electrode on the graphene active layer; And

A graphene oxide layer between the gate electrode and the graphene active layer,

A graphene transistor having a top surface of the graphene oxide layer coplanar with a top surface of the graphene active layer.
The method of claim 1,

The graphene oxide layer is a graphene transistor provided in the upper portion of the graphene active layer.
The method of claim 1,

The graphene active layer is:

A channel region between the graphene oxide layer and the insulating substrate; And

Graphene transistor comprising source / drain regions provided on both sides of the channel region.
The method of claim 3, wherein

And the thickness of the channel region is thinner than the thickness of the source / drain regions.
The method of claim 4, wherein

And the channel region is composed of 1 to 3 mono graphene layers, and the source / drain regions are composed of 4 to 6 mono graphene layers.
The method of claim 3, wherein

And graphing the source / drain electrodes on the top surfaces of the source / drain regions, respectively.
The method of claim 1,

The insulating substrate is a graphene transistor, a glass substrate, or a silicon substrate insulated by an oxide film.
Forming a graphene active layer on the insulating substrate;

Oxidizing a portion of the upper portion of the graphene active layer to form a graphene oxide layer; And

A method of manufacturing a graphene transistor comprising forming a gate electrode on the graphene oxide layer.
The method of claim 8,

The thickness of the graphene oxide layer is a graphene transistor manufacturing method is formed thinner than the thickness of the graphene active layer.
The method of claim 8,

Forming the graphene oxide layer is:

Forming a first mask layer covering a first region of the graphene active layer;

Oxidizing an upper portion of the second region exposed by the first mask layer; And

The method of manufacturing a graphene transistor comprising removing the first mask layer.
The method of claim 10,

The graphene oxide is limited to the upper portion of the second region is formed, the lower portion of the second region is a method of manufacturing a transistor.
The method of claim 10,

Forming source / drain electrodes on the second region,

The source / drain electrodes are formed simultaneously with the gate electrode.
The method of claim 8,

Forming the graphene active layer on the insulating substrate is:

Forming the graphene active layer on a growth substrate; And

And transferring the graphene active layer onto the insulating substrate.
The method of claim 13,

Forming the graphene active layer on the growth substrate is performed by at least one of chemical vapor deposition, epitaxy synthesis, and exfoliation.
Reducing the first region of the graphene oxide layer to form a graphene active layer;

Forming a gate electrode on a second region of the graphene oxide layer on which the graphene active layer is not formed; And

Forming a source / drain electrodes on the graphene active layer.
The method of claim 15,

The graphene active layer is a method of manufacturing a graphene transistor is formed thinner than the thickness of the graphene oxide layer.
The method of claim 15,

And the graphene active layer is spaced apart from the gate electrode by the second region.
The method of claim 15,

Forming the graphene active layer is:

Growing the graphene oxide layer on a growth substrate;

Reducing the top and sidewalls of the graphene oxide layer; And

Transferring the reduced graphene oxide layer onto an insulating substrate,

The transfer process is a graphene transistor manufacturing method is performed so that the upper surface of the graphene oxide layer is in contact with the upper surface of the insulating substrate.
The method of claim 18,

At least a portion of the lower portion of the graphene oxide layer in contact with the growth substrate is not reduced.
The method of claim 15,

Providing the graphene oxide layer on an insulating substrate,

Forming the graphene active layer is:

Forming a second mask layer on the graphene oxide layer and the insulating substrate; And

A method of manufacturing a graphene transistor comprising performing a reduction process on the graphene oxide layer exposed by the second mask layer.
The method of claim 20,

The upper portion of the graphene oxide layer in contact with the second mask layer is not reduced, the lower portion of the graphene oxide layer in contact with the insulating substrate of the region under the second mask is reduced.
The method of claim 20,

The reduction process is a graphene transistor manufacturing method using a reducing agent comprising at least one of hydrazine (hydrazine), phenyl hydrazine (phenyl hydrazine), sodium hydride, and potassium hydroxide (KOH).