WO2011160644A2

WO2011160644A2 - Method of pwm switching for parallel converters

Info

Publication number: WO2011160644A2
Application number: PCT/DK2011/050233
Authority: WO
Inventors: Michael Adam Zagrodnik
Original assignee: Vestas Wind Systems A/S
Priority date: 2010-06-24
Filing date: 2011-06-23
Publication date: 2011-12-29
Also published as: WO2011160644A3

Abstract

The present invention relates to a method of PWM switching for control for a converter having a plurality of parallel converter legs per phase and a converter having a plurality of parallel converter legs in each phase. The plurality of converter legs may assume a set of possible different switching states, wherein the converter may be exposed to a cyclic load. Furthermore, the present invention relates to a converter having a plurality of parallel converter legs in each phase, wherein the converter includes a control block for identifying different switching states.

Description

METHOD OF PWM SWITCHING FOR PARALLEL CONVERTERS

TECHNICAL FIELD

The invention relates to a method of PWM switching enabling control of a converter having a plurality of parallel converter legs per phase. In particular, the invention relates to a wind turbine plant and a method for generating PWM switching signals for control of a converter. The converter may control a generator, motor or interface to the utility grid.

BACKGROUND OF THE INVENTION

Converters including a plurality of parallel converter legs for each phase are known in the art.

An example of such a converter is disclosed in US2008/0031024.

US2008/0031024 relates to method in connection with a network converter, the network converter comprising two or more network converter modules connectable in parallel with one another, and control means for controlling the network converter modules. Each network converter module comprises a network filter and a capacitor for a direct voltage intermediate circuit. The network converter modules are controlled by first control means determining a quantity relating to the network converter or its use to produce a power signal, preventing or allowing use of one or more network converter modules in order to reconfigure the network converter during operation of the network converter in response to the power signal. Once the numbers of modules to be included for conversion is decided, conventional interleaved converter switching takes place during which the converter legs for respective phase a cyclically connected and disconnected for control of respective phase.

The technology disclosed in US2008/0031024 enables adaptation of the circuit design to various load condition by allowing a selection of how many three phase converter modules should be in operation in a set of parallel three phase converter modules at a given time.

Even if the technology suggested in US2008/0031024 may provide more robust converters being adaptable to varying load conditions, there still is a need to provide further improvements the technology. Hence, an object of the invention is to further improve control methods for a converter including a plurality of converter legs for each phase.

BRIEF DESCRIPTION OF THE INVENTION The object of the invention is achieved by a method as defined in claim 1 . More specifically a method to generate PWM gating signals for control for a converter having a plurality of parallel converter legs is proposed. The plurality of converter legs may assume a set of possible different switching states. The different switching states includes all possible combinations of switching states connecting the converter legs to either a positive DC rail or a negative DC rail. The different possible switching states include subsets of redundant switching states. These are different switching states that have the same number of legs connected to a positive rail of a DC link, that is redundant switching states are constituted by switching states having different configurations, which different configurations all have the same number of legs connected to a positive rail of the DC link The selection of switching state for each phase is responsible for generating the output voltage of the converter which is presented to the cyclic load.

The cyclic load may typically be in the range 45 to 65 Hz.

The switching frequency would typically be in the range 2kHz to 8 kHz.

The switching may preferably take place at a high switching rate having a switching frequency considerably greater than the base frequency of the cyclic load. At each switching interval, the switching state among the redundant switching states which is most suitable is selected, By most suitable is intended the switching state having the lowest inductor current and/or the switching state which is most appropriate for enabling a balanced inductor current. Appropriate selection of the combination of switching states considering all phases enables the control of common mode voltage.

By appropriate selection of the redundant switching states the balancing of inductor currents is enabled. This will be explained in more detail below. The parallel converter topology when combined with the presented control method increases reliability of the converter. In the event of a failure in one of the converter legs the converter may continue to be operated with the faulty converter leg removed from the circuit. The output capacity of the converter is reduced under such mode of operation. Furthermore accurate reproduction of reference voltage waveforms with low distortion is enabled as a result of a densely populated vector space resulting from the multitude of possible switching states. High order multi-level performance is achieved. The presence of a plurality of redundant switching states also enables current balancing between the inductors of the different legs. In effect the loading of converter components is evenly balanced.

The present invention preferably makes use of Nearest Three Vector Space Vector Pulse Width Modulation (NTV-SVM) for the control of converters having multiple parallel converter legs per phase. Other forms of modulation such as Sinusoidal-PWM may be applied.

The method is particularly valuable in the control of parallel converters of high order including for example 6, 10, 20 or more converter legs per phase. The same method may however also be applied to control lower order converters such as with 2, 3 and 4 converter legs per phase.

Each converter leg of each phase in the converter includes a pair of semiconductor switches such as bipolar transistors. A free wheeling diode is connected in inverse parallel with each transistor device. In said pair of bipolar transistors the collector of a first bipolar transistor is connected to a positive rail of a DC link, an emitter of the first bipolar transistor is connected to an inductor. Furthermore an emitter of a second bipolar transistor is connected to a negative rail of a DC link, and a collector of the second bipolar transistor is connected to the same inductor. The inductors of each converter leg are in turn combined at a common terminal point, this constituting the output terminal of the particular converter phase. The configuration enables individual switching of said inductors to either the negative rail or to the positive rail depending on the state of said first and second transistors.

The term bipolar transistors is understand to include IGBT devices.

Optionally the method includes the step of selecting the switching states such that the resultant voltage VnN is restricted to a narrow band say between 0.4^*Vdc - 0.6^*Vdc, where Vdc is the potential difference between the positive and negative rails of the DC link. By restricting the voltage VnN to a narrow band centered around 0.5^*Vdc, the common mode voltage is reduced.

Optionally the plurality of parallel converter legs is constituted by an even number of legs per phase. For this topology it is possible to select switching states for all phases such that the resultant voltage VnN is equal to 0.5^*Vdc. In this manner the common mode voltage is essentially eliminated. Optionally switching between said redundant switching states during a switching interval is performed so as to balance the inductor currents in the converter legs of each phase. The converter legs with the smallest

instantaneous currents are switched to the positive dc rail. In another embodiment, the converter legs with the largest instantaneous currents are switched to the negative rail of the dc-link.

The number of inductors per phase so switched is described by the numbers Pa, Pb and Pc consistent with the active vector in effect. Through active current balancing, the current loading is equally distributed between the inductors and converter legs. Heating of components is uniform and magnetic saturation of the inductor is prevented. In an embodiment, the converter legs with the largest instantaneous current are switched to the negative dc rail to achieve the same effect.

The possible switching states may be identified by the generation of a vector space defining all possible switching states. The vector space includes all possible switching states. In the following description a three-phase converter system is described however systems with other numbers of phases may be considered. Each converter phase includes a plurality of parallel converter legs. The vector space identifies all possible switching combinations of the converter legs connected to the positive DC link for each phase. The vector space will include a number of redundant switching states which will include switching combinations having the same number of converter legs connected to the positive link for each phase.

Alternatively, all possible combinations of the number of converter legs connected to the negative DC link may also be identified. Since a leg is either connected to the positive rail or to the negative rail and since the vector space includes all possible combinations, the vector space is identical regardless of whether the reference to a negative or a positive DC link is made.

Optionally the method includes the step of reducing the vector space to include only switching states having a voltage VnN equal to 0.5^*Vdc. This enables elimination of common mode voltage since only switching states fulfilling this requirement may be selected for switching.

In the method a voltage reference vector defining a desired output of the converter is communicated to the PWM Controller. The reference voltage vector will have an end point pointing to a triangle within said vector space. The reference vector identifies three active vectors representing the corners of said triangle. The switching times for said active vectors may be calculated in order to approximate said voltage reference vector with said active vectors. For reference vectors of small magnitude a zero vector may be used.

In the method, a selection between the redundant switching states of the switching states may be made for each active vector, to use the redundant switching states which best contribute to the active balancing of the inductor currents.

Optionally the converter includes a plurality of parallel converter legs per phase. The method according to the invention will consider the entire converter at one time. It is fundamentally different from converter systems composed of parallel combinations of three-phase converter modules which are in turn controlled by interleaved switching. In the method according to the invention, the switching states for all the phases will be present in the vector space and redundant states for all branches will be considered. For converters having a plurality of converter legs per phase, steps for determining for each phase the number of legs connected to one of the DC links and selecting between redundant states having for each phase said number of legs connected to said one of the DC links may be performed. The method of the invention is particularly contemplated for control of wind turbine generators and for the control of converters interfaced to the utility grid. Both constitute the said cyclic load. The method according to the invention may base the control of the converter on operations transforming a converter topology into Thevenin equivalent sources having an equivalent impedance Leq, where equivalent voltage sources for respective phase and a common mode voltage source are expressed in terms of potential between the DC links, total number of legs in the braches, and number of legs connected to one of the DC links for each branch.

The use of Thevenin equivalents fundamentally reduces the complexity of the control routines and enables use of the number of switches connected to either the negative or the positive DC link for easy determination of the common mode voltage. Hence, the recasting of the parallel converter into the form of Thevenin equivalent sources enables the response of the complex converter to be described in terms of simple mathematical expressions of Pa, Pb, Pc, Vdc and Nlegs. Further the dynamic characteristics of the converter may be reduced to an equivalent series impedance Leq. The value of Leq is constant and is independent of the switching state.

The benefit here is that modeling and control of the converter is simplified. A further advantage allowing simplification of the control algorithm can be achieved by conceptually shifting the equivalent series inductance (Leq) from the converter to the load side. The benefit here is that both the PWM algorithm and load-control algorithms are simplified. For load-control purposes the equivalent inductance is considered together with the leakage inductance of the load. In other words, the parameter value of the load leakage inductance is increased to account for the converter but the overall form of the model remains fundamentally unchanged.

The method according to the invention enables control of high order parallel converters resulting is low harmonic distortion of the output, balanced loading of semiconductor and magnetic components as well as low common mode current. The desirable performance characteristics of multi-level converters are obtained whilst using only one dc-link. The problems associated with capacitor balancing common with other forms of multi-level converter are avoided.

The invention also relates to a converter having a plurality of parallel converter legs per converter phase. The PWM Controller includes a control block for identifying the nearest three active vectors consistent with the reference voltage vector and the degree of common mode voltage control. The control block identifies the different switching states, said different switching states being described by the numbers of converter legs switched to the positive rail for each phase. Furthermore a control block for selecting among redundant switching states so as to control the inductor currents. Embodiments of the converter are disclosed in the independent claims.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments of the invention will be described in further detail below, in connection with appended drawings, where

Fig. 1 shows a first converter architecture at which the method according to the invention may be used to control a cyclic load, in particular a wind turbine generator or converter interfaced to the utility grid;

Fig. 2 shows a second converter architecture at which the method according to the invention may be used to control a cyclic load, in particular a wind turbine generator or a converter interfaced to the utility grid;

Fig. 3 shows a schematic equivalent circuit generated describing a switching state with Pa, Pb and Pc legs to a positive DC link; Fig. 4 shows an equivalent circuit of the circuit presented in Fig. 3 with three Thevenin equivalent sources; Fig. 5 shows the circuit of Fig. 4 where the load of the converter and the leakage inductance of the generator load per phase is replaced by a modified load;

Fig. 6 shows a vector space for a converter with 3 phases having 4 converter legs per phase;

Fig. 7 shows a vector space for a converter with 3 phases having 6 converter legs per phase; Fig. 8 shows a vector space for a converter with 3 phases having 10 converter legs per phase;

Fig. 9 shows a conventional voltage source converter with a PWM controller for a converter with 3 converter legs;

Fig. 10 shows a voltage source converter which operates according to the invention;

Fig. 1 1 shows a vector space with 4 active vectors Vi, V₂, V₃ and V₄;

Fig. 12 shows a vector-space, for a three phase converter with 10 converter legs per phase (Nlegs=10) but restricted to using only vectors having voltage VnN=0.5^*Vdc;

Fig. 13 shows a vector space for a three phase converter with 10 converter legs per phase (Nlegs=10), with a distribution of switching states for

VnN=0.40^*Vdc to VnN=0.60^*Vdc; Fig.14 shows phase-A current waveforms for each of the 6 converter legs per phase (Nlegs=6); and

Fig. 15 shows a flow chart diagram of a switching controller.

DETAILED DESCRIPTION

Figure 1 shows a converter topology suitable for use in connection with a method according the invention. Converter includes a common DC link. A set of N converter modules Mi ....M_N, each including a set n converter legs {Legn,

Leg₂i, Leg..i, Leg_ni, Legi_N, Leg_2N, Leg.._N, Leg_nN}, where n is the number of output phases.

Each converter leg {Legn, Leg₂i, Leg..i, Leg_ni , Legi_N, Leg_2N, Leg.._N,

Leg_nN}, includes a pair of bipolar transistors 3, 5. In said pair of bipolar transistors 3, 5 a collector 7 of a first bipolar transistor 3 is connected to a positive rail 9 of the DC link 1 , an emitter 1 1 of the first bipolar transistor 3 is connected to an inductor 13. Furthermore an emitter 15 of a second bipolar transistor 5 is connected to a negative rail 17 of the DC link 1 , and a collector 19 of the second bipolar transistor 5 is connected to the inductor 13. The configuration enables control of each said legs to connect the series inductors L, individually to either the negative rail 17 or to said positive rail 9 depending on the state of said first and second bipolar transistors 3, 5.

Here the phase(k) output being formed by the parallel connection of N converter legs {Legki, Legk₂, L_k3, - - - L_kN}, each through a separate series inductor L 13.

In figure 2 a similar topology is shown. The difference is that in the

embodiment shown in figure 2, each module handles a separate phase.

Hence in figure 2 the converter includes a set of n converter modules Mi ....M_n. The number of converter modules n corresponds to the number of phases. Each converter module(k) including a number N of parallel converter legs respective converter legs L_ki, L_k2, L_k3, L_kN. The difference between the topology of the converter shown in figure 1 and in figure 2 merely resides in the grouping of converter legs. Still both

embodiments include a plurality of parallel converter legs per output phase, wherein said plurality of converter legs may assume a set of possible different switching states. The provision of a plurality of converter legs Leg , where i denotes the phase number and j denotes the number of the converter leg for a specific phase, enables selection of redundant switching states for enabling for instance load balance and common mode voltage control.

Below, embodiments of a control method for switching of the parallel converter legs are disclosed in further detail.

The proposed method, has the following benefits:

1 ) Accurate reproduction of reference voltage waveforms with low distortion due to multi-level output capability.

2) Controlled current flow in each inductor L (avoidance of magnetic saturation).

3) Control of common mode voltage.

4) Increased reliability through redundancy, meaning that if certain converter legs fail then the faulty legs can be switched out from the circuit and the converter can be placed back into operation with a reduced number of legs.

5) Load sharing where multiple converter legs share the load current equally.

At any instant in time, one bipolar transistor of each converter leg is ON and the other is OFF (exception to this may be during the brief instant of commutation/turn off). The transistor is preferably an insulated-gate bipolar transistor (IGBT).

Therefore at any instant in time; Phase-A has Pa number of switches connected to the +ve rail of the dc-link and Nlegs-Pa number of switches connected to the -ve rail of the dc-link. Phase-B has Pb number of switches connected to the +ve rail of the dc-link and Nlegs-Pb number of switches connected to the -ve rail of the dc-link. Phase-C has Pc number of switches connected to the +ve rail of the dc-link and Nlegs-Pc number of switches connected to the -ve rail of the dc-link.

Nlegs is the total number of converter legs for each phase.

Pa is the number of Phase-A converter legs switched to the +ve rail.

Pb is the number of Phase-B converter legs switched to the +ve rail.

Pc is the number of Phase-C converter legs switched to the +ve rail.

A schematic equivalent circuit generated describing this switching state is shown in figure 3.

The switching state of the converter can therefore be described in terms of Pa, Pb and Pc.

Using the negative rail of the dc-link as reference voltage VN, the converter can be recast as three Thevenin equivalent sources. Figure 4 shows an equivalent circuit to the circuit presented in figure 3 with three Thevenin equivalent sources. Additionally the phases of the load have been added together with the leakage inductance Z per phase of the load. The equivalent voltage source for Phase-A is VaN = Vdc^*Pa/Nlegs and this is in series with an inductance of L/Nlegs.

The equivalent voltage source for Phase-B is VbN = Vdc^*Pb/Nlegs and this is in series with an inductance of L/Nlegs.

The equivalent voltage source for Phase-C is VcN = Vdc^*Pc/Nlegs and this is in series with an inductance of L/Nlegs.

Note that the equivalent series inductance (Leq) can be expressed as Leq=L/Nlegs and is independent of the switching state Pa, Pb or Pc. The voltage VnN = Vdc^*(Pa+Pb+Pc)/(3^*Nlegs)

Van = VaN + VNn = (V_dc/3Niegs) ^* (2P_a - P_b - P_c)

Vbn = VbN + VNn = (V_dc/3Niegs) ^* (2P_b - P_c - Pa)

Vcn = VcN + VNn = (V_dc/3Niegs) ^* (2P_C - P_a - P_b)

Figure 5 shows the circuit of figure 4 where the load of the converter and the leakage inductance of the generator load per phase are replaced by a modified load. The Leq is considered to be part of the load inductance. For example, in generator control Leq is be added to the per phase leakage inductance of the machine.

Zload' = Zload + Leq. Figure 5 also shows an equivalent circuit for the common mode voltage.

In order to enable further analyses of the circuits for efficient control of the space vector diagrams of the possible switching states of the converter are retrieved. The space vector diagrams are retrieved in a conventional manner.

When presented in terms of space vectors, the vector space becomes densely populated for large N|_egs.

In figure 6 a vector space for a converter with 3 phases having 4 converter legs per phase is shown.

In figure 7 a vector space for a converter with 3 phases having 6 converter legs per phase is shown. In figure 8 a vector space for a converter with 3 phases having 10 converter legs per phase is shown. The performance for large Nlegs is therefore equivalent (in terms of vector space) to a high order multilevel converter. This enables a sinusoidal voltage waveform to be generated with little distortion. The selection of appropriate switching states, the balancing of inductor currents and the reduction or elimination of common mode voltage is greatly simplified by the representation of the converter in terms of Thevenin equivalent sources. For each phase, the equivalent voltage source with respect to the negative dc-link rail is directly proportional to the number of phase legs switched to the positive dc-link rail.

VaN = (Vdc^*Pa)/Nlegs. Where Pa is the number of Phase-A legs switched to the positive rail of the dc-link.

The Thevenin equivalent series inductance is the same for all phases and is irrespective of Pa, Pb and Pc.

This equivalent series inductance is Leq = L/Nlegs. The Leq is conveniently considered to be part of the load leakage inductance. For example, in motor control Leq would be added to the per phase leakage inductance of the machine.

Zload' = Zload + Leq. Pa may take on any value such that Pa = {01 1 1 21 31 ... | Nlegs}. The same choice is available for the selection of Pb and Pc.

For a converter with three phases there are (Nlegs + 1 )³ possible Switching States (combinations of Pa, Pb and Pc). In other words the selection space increases exponentially (cubed power) with the number of converter legs Nlegs. Not all Switching States form distinct active vectors. Certain switching states yield the same active vector; therefore there are fewer distinct active vectors than switching states. For example, in conventional 2 level converters there is only one converter leg per phase. Nleg = 1 . There 8 possible switching states 000, 001 , 010, 01 1 , 100, 101 , 1 10 and 1 1 1 . However there are two equivalent 'zero' states being 000 and 1 1 1 . There are therefore 7 distinct active vectors.

Nlegs Combinations of Distinct Active

Pa, Pb and Pc Vectors

1 8 7

2 27 19

3 64 37

4 125 61

5 216 91

6 343 127

7 512 169

8 729 217

9 1000 271

0 1331 331

1 1728 397

2 2197 469

3 2744 547

4 3375 631

5 4096 721

In figure 9 a conventional voltage source converter (3 phase, 2 level) with a SV-PWM controller is shown. This converter will have one converter leg per phase. The Load Controller 20 receives reference and control signals from a superior controller. The reference command may be a rotor speed command, a power command and so forth. The Load Controller additionally receives feedback signals from the load. For a motor load the feedback signals may include rotor speed, phase currents and so forth. On the basis of the reference commands and the received feedback, the Load Controller calculates and issues a reference voltage vector Vs, which is used as an input to a conventional PWM Controller 22 performing SV-PWM switching of the converter legs in the Converter power circuit 24.

Figure 10 shows a voltage source converter (3 phase, 3 converter legs per phase, Nlegs=3) which operates according to the invention. A Load Controller 26 receives reference and control signals from a superior controller. The Load Controller additionally receives feedback from the load. For a motor load the feedback signals may include rotor speed, phase currents and so forth. On the basis of the reference commands and the received feedback, the Load Controller calculates and issues a reference voltage vector Vs. The PWM Controller 28 generates the required gating signals to drive the Converter power circuit 30. The method of PWM switching is based on; the reference command voltage, the measured currents in each converter leg, the measured dc-link voltage and the Mode Selection command for control of common mode voltage.

It should be noted that the Load Controller 26 and the PWM Controller 28 have distinct functions.

The Load Controller 26 is responsible for calculating the desired voltages which are to be applied to the terminals of the load, so as to control the load in some specified manner. The specified manner is that intended to achieve the reference command issued the superior controller. For example, the load may be a generator of a wind turbine plant. The reference command may be a specified real power P^*. The control method may be a closed loop control based on generator flux estimation and torque control.

The method of load-control (open loop, closed loop, flux-based, rotating frame, sensorless etc) is the responsibility of the Load Controller 26. The Load Controller 26 is also required to calculate and output a voltage reference signal (Vs) to the PWM Controller. The PWM Controller in turn acts upon this reference signal and generates the gating signals for the power circuits of the Converter. In the above discussions the reference voltage is described as a vector Vs. The same reference voltage may also be expressed as scalar voltages for the individual phases Va, Vb and Vc.

The Load Controller 26 may assume that the voltage source applied to the load terminals is ideal and infinitely variable. This requirement is satisfied by combining the equivalent series inductance of the converter into the dynamic electrical model of the load. In other words, the non-ideal performance of the converter is incorporated into the model of the load. The electrical model of the load is modified to account for the non-ideal converter. The terminals of the 'modified load' are in effect shifted back to an imaginary location embedded within the Converter power circuit.

The PWM Controller 28 is responsible for receiving the voltage reference signal Vs and generating the required gating signals to drive the

semiconductor switches of the Converter. The PWM Controller 28 may also take on responsibility for both balancing the currents in each converter leg and controlling common mode voltages. The PWM Controller 28 is

distinguished from a conventional PWM controller in these respects. A general objective of Space Vector Pulse Width Modulation (SV-PWM) is to drive the converter outputs such that over the switching period the a time- weighted average of active vectors and zero vectors approximates the voltage reference vector. In 2-level converters with one converter leg per phase, there are 6 active vectors and 2 zero vectors. Although there are numerous variations of SVM proposed in the literature a commonly used sequence is as follows:

Voi→ Vi → V₂ → Vo2→ V₂→ Vi→ Voi

where: Voi and V02 are the two zero vectors and

Vi and V₂ are two active vectors.

With the proposed PWM control method there are a great number of active vectors to select from, especially when Nlegs is large.

In general, each reference vector points to a specific triangle within the vector space. The reference vector can be approximated by switching between the three active vectors (Vi,V₂ and V₃) which make up the corners of this triangle. This is known in the art as to as Nearest Three Vector - Space Vector

Modulation (NTV-SVM). If during the subsequent switching period the same three active vectors are selected then the switching sequence is reversed, such as: Vi→ V₂ → V₃ → V₃→ V₂ → Vi.

The zero-vectors need not be used except when the reference vector is of small magnitude.

In figure 1 1 is shown a vector space with 4 active vectors Vi, V₂, V₃ and V₄. For the 4 active vectors in figure 1 1 , the following analyses may be made:

It is observer that the vectors Vi, V₂, V₃ and V₄ can be formed from a number of switching combinations. For example, there are 7 different ways to form the vector V₂. Each combination is identical in terms of Van, Vbn and Vcn

however the voltage VnN with respect to the negative rail of the dc-link is different.

To reduce the common-mode current circulation, the common-mode voltage is reduced. In other words, a particular combination of Pa, Pb and Pc is chosen such that VnN is approximately equal to the value 0.5^*Vdc.

V,

Pa Pb Pc VnN VaN VbN VcN Van Vbn Vcn Re[Vs] lm[Vs] mag[Vs]

6 3 2 0.37 0.60 0.30 0.20 0.23 -0.07 -0.17 0.35 0.09 0.36

5 2 1 0.27 0.50 0.20 0.10 0.23 -0.07 -0.17 0.35 0.09 0.36

7 4 3 0.47 0.70 0.40 0.30 0.23 -0.07 -0.17 0.35 0.09 0.36

8 5 4 0.57 0.80 0.50 0.40 0.23 -0.07 -0.17 0.35 0.09 0.36

9 6 5 0.67 0.90 0.60 0.50 0.23 -0.07 -0.17 0.35 0.09 0.36

10 7 6 0.77 1.00 0.70 0.60 0.23 -0.07 -0.17 0.35 0.09 0.36 4 1 0 0.17 0.40 0.10 0.00 0.23 -0.07 -0.17 0.35 0.09 0.36

v₂

Pa Pb Pc VnN VaN VbN VcN Van Vbn Vcn Re[Vs] lm[Vs] mag[Vs]

6 4 2 0.40 0.60 0.40 0.20 0.20 0.00 -0.20 0.30 0.17 0.35

7 5 3 0.50 0.70 0.50 0.30 0.20 0.00 -0.20 0.30 0.17 0.35

5 3 1 0.30 0.50 0.30 0.10 0.20 0.00 -0.20 0.30 0.17 0.35

10 8 6 0.80 1.00 0.80 0.60 0.20 0.00 -0.20 0.30 0.17 0.35

8 6 4 0.60 0.80 0.60 0.40 0.20 0.00 -0.20 0.30 0.17 0.35

9 7 5 0.70 0.90 0.70 0.50 0.20 0.00 -0.20 0.30 0.17 0.35

4 2 0 0.20 0.40 0.20 0.00 0.20 0.00 -0.20 0.30 0.17 0.35 v₃

Pa Pb Pc VnN VaN VbN VcN Van Vbn Vcn Re[Vs] lm[Vs] mag[Vs]

7 4 2 0.43 0.70 0.40 0.20 0.27 -0.03 -0.23 0.40 0.17 0.44

6 3 1 0.33 0.60 0.30 0.10 0.27 -0.03 -0.23 0.40 0.17 0.44

9 6 4 0.63 0.90 0.60 0.40 0.27 -0.03 -0.23 0.40 0.17 0.44

10 7 5 0.73 1.00 0.70 0.50 0.27 -0.03 -0.23 0.40 0.17 0.44

5 2 0 0.23 0.50 0.20 0.00 0.27 -0.03 -0.23 0.40 0.17 0.44

8 5 3 0.53 0.80 0.50 0.30 0.27 -0.03 -0.23 0.40 0.17 0.44 v₄

Pa Pb Pc VnN VaN VbN VcN Van Vbn Vcn Re[Vs] lm[Vs] mag[Vs]

7 3 2 0.40 0.70 0.30 0.20 0.30 -0.10 -0.20 0.45 0.09 0.46

5 1 0 0.20 0.50 0.10 0.00 0.30 -0.10 -0.20 0.45 0.09 0.46

6 2 1 0.30 0.60 0.20 0.10 0.30 -0.10 -0.20 0.45 0.09 0.46

9 5 4 0.60 0.90 0.50 0.40 0.30 -0.10 -0.20 0.45 0.09 0.46

10 6 5 0.70 1.00 0.60 0.50 0.30 -0.10 -0.20 0.45 0.09 0.46

8 4 3 0.50 0.80 0.40 0.30 0.30 -0.10 -0.20 0.45 0.09 0.46

For the triangle defined by Vi, V₂ and V₃ together with the underlined

switching states, the variation in VnN is reduced to +/- 0.03^*Vdc.

V1 Pa=7, Pb=4, Pc=3, VnN=0.47

V2 Pa=7, Pb=5, Pc=3, VnN=0.50

V3 Pa=8, Pb=5, Pc=3, VnN=0.53

A principle for control of the common mode voltage will be presented below. The NTV-SVM scheme Vs identifies the triangle and the vectors (Vi, V₂, V₃) which define this triangle. Each vector Vi, V₂ and V₃ may be constructed by different switching combinations however each combination is not equivalent in terms of common mode voltage. It is therefore possible to select among the combinations available those that minimize the common mode voltage. For strict control of common mode current there should be no variation in common mode voltage per switching period. This implies that Vi, V₂ and V₃ must be selected such that VnN=0.5^*Vdc. With standard NTV-SVM the nearest three vectors cannot be constructed so as to have identical VnN. It is however possible to re-map the vector-space, using only with vectors having voltage VnN=0.5^*Vdc. Such a chart is shown in figure 12 for Nlegs=10 and VnN = 0.5^*Vdc. In this example it is seen that both Vi and V₄ can be formed in such a way as to have VnN=0.5^*Vdc.

Therefore by applying only this restricted set of active vectors it is possible to perform NTV-SVM with VnN=0.5Vdc for all instances.

The optimal common mode voltage is obtained when VnN = 0.5^*Vdc where Vdc is the voltage of the dc-link. In this case the dc-link is balanced around earth potential as is the neutral point of balanced loads. Common mode currents, circulating through stray/filter capacitances through ground, are minimized. The reduction in Vcm is however at the expense harmonic distortion. The reason for this is that the number of selectable active-vectors is reduced and the triangle size is increased. Restricting the set of active vectors has the same effect as reducing the number of converter legs.

For a converter with an even number of legs, the effective number of legs after re-mapping the active vectors is half of the original number..

If Nlegs is an odd number then VnN = 0.5^*Vdc is not obtainable with any switching-state. So for an odd number of converter-legs it is not possible to eliminate the common-mode voltage by this method.

A significant observation is that while the common-mode voltage may be reduced as explained above, the maximum magnitude of the voltage output is also reduced. For Nlegs=10 the maximum modulation index is reduced to 0.75 [equal to (V3/2)²] when VnN is restricted to 0.5^*Vdc. This is

demonstrated in figure 12.

If the control strategy is to reduce (rather than eliminate) the common mode voltages, then it is possible to re-construct the space vector diagram permitting only vectors within an acceptable band centered at VnN=0.5^*Vdc. For example the distribution of switching states with VnN=0.40^*Vdc to VnN=0.60^*Vdc are shown in figure 13 for Nlegs=10.

In this example it is seen that by relaxing the control of common-mode voltages (for example by allowing a range of +/- 0.1 ^*Vdc) then the full density of switching states is restored. Further the maximum modulation index is increased to m=0.854. This is demonstrated in figure 13.

It is evident that there is a trade off between common mode voltage control and the combination of harmonic distortion and the maximum output voltage.

To summarize; there are two different operating modes for common mode control.

1 ) Common Mode Elimination.

- only effective if Nlegs is an even number.

- only switching states and active vectors with VnN=0.5^*Vdc are considered for selection.

- the modulation index is limited to m=0.75. Above this modulation the requirement that VnN=0.5^*Vdc can not be maintained.

- the output distortion is increased because the available vector space is less densely populated..

2) Common Mode Reduction.

- the available vector space is restricted to switching states having a voltage VnN bounded within set limits around the value 0.5^*Vdc.

- Nlegs may be even or odd.

- the maximum modulation index increases as the control on common mode voltage is relaxed. - for a given modulation index m, a greater number of legs per phase (Nlegs) will result in lower common mode voltage.

The performance in each mode is different and the decision to operate in either mode is taken by a superior controller. The selection of either mode depends on the output voltage magnitude required, the importance of reducing the common mode voltage and the concern over harmonic distortion. A principle for balancing the inductor currents in the converter legs of each phase will be presented below.

The voltage reference signal V_s and the degree of common mode voltage control (described above) fully describe the required switching state in terms of combinations of the number of switches required to be connected to the positive dc-link rail, that is Pa, Pb and Pc.

It is irrelevant which Phase-A switches are connected to the positive dc-link rail so long as their total number is equal to Pa. The same applies for Phase- B and Phase-C.

Therefore different combinations of Phase-A switches may be switched to the positive dc-link rail without changing the state of the converter. In other words there is redundancy of equivalent states.

This redundancy is exploited to balance the current flow in each converter leg. Central to this circuit topology is the apparent 'shorting-out' the converter legs within the same phase group. If not controlled it is possible that large currents will circulate through both the inductor L and the switching devices. A method described as 'redundancy cycling' is used to control and balance the inductor currents.

This is to provide even loading of the switches and avoiding saturation of the inductor L.

The problem remains then to determine which converter legs are to be switched. The method is explained by way of example where we assume Nlegs = 10. With Pa = 0 there is no choice except to switch all 10 phase 'A' legs to the negative DC rail. With Pa = 10 there again is no option except to switch all phase 'A' legs to the positive DC rail.

Note that when Pa = 0 or Pa = 10 there is no possibility to regulate the currents in the individual converter-legs. However all legs are switched identically and the current change in each leg (over the switching interval) should be the same for all. The relative change is zero (barring component tolerance mismatch).

With Pa = 1 there are 10 valid options. Any one of the phase 'A' legs may be switched to the positive DC rail. However with the foresight that the circulating current in this leg will increase quickly, it is apparent that the best choice is to select the phase 'A' converter leg where the current is the least.

With Pa = 2 there are 45 valid options. However, in order to balance the phase 'A' currents, the legs with the two smallest currents are selected. Similarly with Pa = 3 there are 36 valid options, however the legs with the three smallest currents are selected for switching.

The same decision process is applied when Pa = 4, 5,6,7,8 and 9.

The overall result is that magnitude of the phase 'A' currents in each converter leg will change in a saw-tooth manner however the relative magnitude of the currents in legs of each phase will remain approximately the same (ie. the currents are balanced). The summation (the average) of these currents (the phase output) will be relatively smooth and much like a sinusoid.

This behaviour is clearly seen in the accompanying circuit simulations. In figure 14 a converter with Nlegs=6 is shown. The phase legs with the least current are successively switched to the positive DC rail. The number of legs switched at one time depends on the applicable Pa. Figure 14 shows phase 'A' current waveforms for each of the 6 converter legs for phase 'A' (Nlegs=6). The leg currents are characteristically of a saw-tooth shape due to active balancing. As figure 14 depicts a fixed frequency switching converter, where the legs are switched at regular time intervals, the switching instants are clearly visible. The legs with the smallest currents are regularly switched to the positive dc-rail. On occasion only one leg is switched, on other occasions two or more legs are switched. Once switched, the currents tend to increase. The net effect is that the entire group keeps together with individual currents tracking the same mean value.

The ripple size of individual legs is a function of the inductance and the switching frequency. When the currents are combined, the resultant load current will have both an average value and a high frequency ripple component. The high frequency ripple will depend on how the individual ripples are correlated. If the ripples are perfectly correlated, then the ripple current should have the same proportion in both the individual legs and after they are combined as the load current. However, the ripples are not perfectly correlated. Some currents rise while others fall. The ripples do not add together but tend to cancel each other. There will consequently be a reduction in the ripple as a proportion of the fundamental.

In figure 15 a flow chart diagram of a switching controller is shown. An overriding Superior Controller 32 generates a control reference signal to the Load Controller 26 and a mode signal determining the degree of common mode voltage control to the PWM Controller 28. The mode signal can include information whether common mode voltage control should take place or not and of the specific accepted deviation of VnN from 0,5^*Vdc that is accepted for the different switching states. The load controller 26 provides a voltage reference vector V_s as an input to the PWM Controller 28. In a nearest three vector selection control block 34, the nearest 3 active vectors Vi, V₂ and V₃ which define the triangle at which the voltage reference vector points are identified. A switching time (t1 ,t2,t3) for assuming each respective vector is calculated. The switching times are calculated to minimize the error in representation of the reference vector by the active vectors Vi, V₂ and V₃ in accordance with well known principles.

Further, in a switching state identification control block 36, the different switching states which generate the active vectors are identified. These switching states can be described by the numbers Pa, Pb, Pc of legs that are connected to the positive DC link for the respective phase. The switching state control block 36 may also reduce the set of switching states in the vector space to include only switching states having (VnN=0.5^*Vdc) no common mode voltage or (0.5^*Vdc - V_bound < VnN < 0.5^*Vdc + V_bound) a common mode voltage bounded by V_b0Und-

In a balancing of phase leg current control block 38 it is determined which of a redundant set of switching states, all fulfilling the requirement of the selected numbers Pa, Pb, Pc have the smallest currents in the inductors.

The nearest three vector selection control block 34, the switching state identification control block 36 and the balancing of phase leg current control block 38 may all be integrated in a PWM Controller 28. An output from the PWM Controller is the gate signals enabling the switching of the BIPOLAR transistors in the converter legs to assume the desired switching states. The actual physical switching is performed in the Converter 40 power circuit, which may for example have the appearance as disclosed in figure 1 or 2. The Converter 40 is connected to a load 42, which preferably is constituted by a generator or utility grid interface of a wind turbine.

A first feedback signal from the Converter representing the phase leg currents and the dc-link voltage is fed back to the PWM Controller. A second feedback signal from the load representing phase currents and other load parameters is feed back to the Load Controller 26.

It is apparent that the method as described by the flow chart in figure 15 enables a control method including the steps of:

- providing a voltage reference vector V_s;

- identifying nearest vectors Vi, V₂ and V₃ which define a triangle in a vector space at which the voltage reference vector points;

- calculating switching times t1 , t2 and t3, to represent said reference vector by said nearest three vectors;

- identifying different switching states which generate the active vectors, said different switching states being described by the numbers of converter legs in a converter having a plurality of parallel converter legs for each phase;

- selecting among redundant switching states having the same number of legs connected to a positive DC link of the converter.

In particular the method may comprise the substeps of: - selecting the redundant switching states which have the smallest

inductor current, and/or

- reducing the vector space to include only switching states having a voltage VnN within set bounds about 0.5^*Vdc or to include only switching states having VnN equal to 0.5^*Vdc.

Regarding different steps of the analyses and calculations performed to form a basis for the method according to the invention the following may be noted:

The previously described Thevenin transformation is performed in order to facilitate the analyses by simplification of the circuit and to reduce calculation complexity. The Thevenin transformation does not take place in real time calculation. The deternnination of the vector spaces is based on real time calculations. Nlegs is known and constant. However, Vdc may vary in time and the acceptable bounds on VnN may change during operation, therefore the vector space may need to be calculated in real time. Optionally, the reference vector could be expressed in terms of Vdc in order to facilitate the use of look-up tables for a real time determination of vector spaces.

The identification of the nearest three vectors is performed in real-time and may be facilitated by use of precompiled look up tables.

The identification of the possible switching states is performed in real time and may be performed by the use of a pre-compiled look up table.

The determination of the "best" redundant state from a set of redundant states requires the measurement of instantaneous inductor currents, and is hence based on a real time decision.

Claims

1 ) Method for generating PWM signals for a converter having a plurality of parallel converter legs (Leg ) for a converter phase, wherein said plurality of converter legs may assume a set of possible different switching states, the method comprising the step of exposing said converter to a cyclic load (42), characterized by providing subsets of redundant switching states in said set of possible different switching states, said subsets of redundant switching states including different switching states having an equal number of legs connected to a positive rail (9) of a DC link (1 ), and by selection of one or more of said redundant switching states for switching during a load cycle of said cyclic load.

2) Method according to claim 1 , characterized in that each converter leg (Legy) including a pair of bipolar transistors (3, 5), wherein in said pair of bipolar transistors a collector (7) of a first bipolar transistor (3) is connected to a positive rail (9) of a DC link (1 ), an emitter (1 1 ) of the first bipolar transistor (3) is connected to an inductor (13), an emitter

(15) of a second bipolar transistor (5) is connected to a negative rail (17) of a DC link (1 ), and a collector (19) of the second bipolar transistor (5) is connected to said inductor (13), enabling control of each said legs to either connect said inductor to said negative rail or to said positive rail depending on the state of said first and second bipolar transistors.

3) Method according to claim 1 or 2, characterized by in said set of

redundant switching states selecting switching states having a voltage VnN in between 0.4 - 0.6 Vdc where Vdc is the potential difference between the positive and negative rails (9; 17) of the DC link (1 ) and where VnN is the potential difference between the neutral point of the load and the negative rail of the dc-link.

4) Method according to claim 3, characterized in that said plurality of parallel converter legs (Leg ) is constituted by an even number of legs, wherein only switching states having a voltage VnN equal to 0.5^*Vdc are selected.

5) Method according to any of the preceding claims, characterized in that switching between said redundant switching states during a load cycle of said cyclic load is performed by successively selecting the switching states where the converter legs with the smallest currents are switched to the positive rail of the dc-link.

6) Method according to any of claims 1 - 5, characterized in that a vector space defining all possible switching states is generated.

7) Method according to claim 6, characterized by reducing said vector space to include only switching states having a voltage VnN equal to 0,5^*Vdc where VnN is the potential difference between the neutral point of the load and the negative rail of the dc-link

8) Method according to claim 6, characterized by reducing said vector space to include only switching states having a voltage VnN within defined bounds centered around 0.5^*Vdc.

9) Method according to any of claims 6 - 8, characterized by obtaining a voltage reference vector defining a desired output of the converter, said reference voltage vector pointing to a triangle within said vector space, identifying three active vectors representing the corners of said triangle, and calculating switching times for said active vectors in order to approximate said voltage reference vector with said active vectors. 10) Method according to claim 9, characterized in that for each active vector selecting the redundant switching states where the converter legs having the smallest currents are switched to the positive rail of the dc-link.

1 1 ) Method according to any of the preceding claims, characterized in that switching between said redundant switching states during a load cycle of said cyclic load is performed by successively selecting the switching states where the converter legs with the largest currents are switched to the negative rail of the dc-link.

12) Method according to any of the preceding claims, characterized in that said converter includes a plurality of phase outputs, wherein each separate phase output includes a plurality of parallel converter legs.

13) Method according to claim 1 1 , characterized by determining for each phase a number of legs connected to one of the rails of the DC link and selecting between redundant states having for each phase said number of legs connected to said one of the rails of the DC link .

14) Method according to any of the preceding claims, characterized in that said cyclic load is a wind turbine generator or an interface to the utility grid. 15) Method according to any of the preceding claims, characterized by transforming a converter topology into Thevenin equivalent sources having an equivalent impedance Leq, where equivalent voltage sources for respective phase and a common mode voltage source are expressed in terms of potential between the DC links, total number of legs in the braches, and number of legs connected to one of the DC links for each branch. 16) A converter having a plurality of parallel converter legs (Legy) in each phase, characterized in that said converter includes a control block 36 for identifying different switching states, said different switching states being described by the numbers of converter legs in a converter having a plurality of parallel converter legs for each phase; and a control block 38 for selecting among redundant switching states having the same number of legs connected to a positive DC link of the converter.

17) A converter according to claim 15, characterized in that said converter further includes a Load Controller 26 for providing a voltage reference vector V_s; a control block 34 being arranged to identify nearest vectors Vi, V₂ and V₃ which define a triangle in a vector space at which the voltage reference V_s vector points, said control block 34 additionally calculating switching times t1 , t2, t3 to represent said reference vector Vs by said nearest three vectors Vi, V₂, V₃.

18) A converter according to claim 16, characterized in that a switching state control block 36 is arranged to select the redundant switching states which connect the converter legs with the smallest inductor currents to the positive rail of the dc-link or the largest inductor currents to the negative rail of the dc-link.

19) A converter according to claim 16 or 17, characterized in that a

switching state control block is arranged to reduce a vector space including possible switching states to include only switching states having a voltage VnN equal to 0.5^*Vdc where VnN is the potential difference between the neutral point of the load and the negative rail of the dc-link , or a voltage VnN within defined bounds centered around 0.5^*Vdc.