WO2011027489A1

WO2011027489A1 - System clock monitoring device and motor control system

Info

Publication number: WO2011027489A1
Application number: PCT/JP2010/002885
Authority: WO
Inventors: 木元勝斗; 藤阪孝誠; 今村勝幸
Original assignee: パナソニック株式会社
Priority date: 2009-09-01
Filing date: 2010-04-21
Publication date: 2011-03-10

Abstract

A comparison unit compares an expected value with a count result at an end of a monitoring period of a counter for counting the number of pulses of a system clock for each monitoring period. If the comparison result shows a mismatch between the count result and the expected value, the comparison unit outputs an anomaly detection signal. The frequency modification unit modifies the frequency of the system clock according to a frequency modification request signal. A frequency modification determination unit, upon confirmation of receipt of the frequency modification request signal and modification of the system clock frequency, outputs an expected value modification instruction signal for instructing modification of the expected value to a value corresponding to the system clock frequency after modification. The condition adjustment unit controls each unit so that a mismatch between the count value and the expected value does not occur immediately after receipt of the frequency modification request signal.

Description

System clock monitoring device and motor control system

The present invention relates to a system clock monitoring apparatus that is mounted on a system driven by a system clock and monitors a system clock frequency abnormality using a clock of a system different from the system clock as a monitoring clock. The present invention also relates to a motor control system equipped with such a system clock monitoring device.

As a system clock monitoring device, a monitoring clock that is different from the system clock that drives the system is prepared, and the number of pulses of the system clock is counted within a certain period (monitoring period) specified by this monitoring clock. Is known that compares the expected value (the number of pulses corresponding to normal operation) to determine the frequency anomaly of the system clock (see, for example, Patent Document 1).

FIG. 14 is a configuration diagram of a system clock monitoring device in the above-described prior art. The CPU and peripheral circuit 18 operate using the system clock CK11 as a clock source. The monitoring clock CK12 is a clock of a different system from the system clock CK11. The count unit 12 is supplied with a system clock CK11 and a monitoring clock CK12, and the counting unit 12 counts the number of pulses PN11 of the system clock CK11 for each monitoring period defined by the monitoring clock CK12. The comparison unit 16 compares the count result output from the count unit 12 (referred to as the pulse number PN11 of the system clock CK11) with the expected value Ex11 read from the storage unit 13, and if they do not match, the abnormality detection signal Sa (frequency) Is output to the CPU and peripheral circuit 18. The CPU and the peripheral circuit 18 that have received the abnormality detection signal Sa execute a predetermined safe operation.

15 and 16 are timing charts showing the monitoring operation of the system clock monitoring device of FIG. The monitoring operation involves counting the number of pulses of the system clock CK11 and comparing the expected value. First, the normal system clock monitoring operation will be described with reference to FIG. Here, the case of the expected value Ex11 (= 9) will be described as an example. When the monitoring operation is turned on, pulses of the system clock CK11 are counted in one cycle period of the monitoring clock CK12. This pulse number PN11 is compared with the expected value Ex11. During normal operation, the number of pulses PN11 is the same as the expected value Ex11 (PN11 = Ex11 = 9), so the abnormality detection signal Sa is not output and normal operation continues.

Next, the operation at the time of abnormality will be described with reference to FIG. It is assumed that the frequency of the system clock CK11 is unexpectedly decreased due to some cause in the middle of the monitoring cycle (timing t21). Furthermore, it is assumed that the frequency of the system clock CK11 is also decreased five times within one cycle of the monitoring clock CK12. Since the number of pulses PN11 (= 5) does not match the expected value Ex11 (= 9) (PN11 ≠ Ex11), the abnormality detection signal Sa is output for the frequency of the system clock CK11. In response to the abnormality detection signal Sa, the CPU and the peripheral circuit 18 stop or wait for the system to be in a safe state.

JP-A-4-326410

In the above prior art, the system clock frequency change is monitored during system operation to detect a frequency abnormality. However, even when the system clock frequency is changed during normal operation on the system, such as when changing the operation mode or shifting to the low-consumption mode, the above-mentioned conventional technique is used to change the frequency of the system clock. It is determined that the frequency is abnormal. Anomaly detection is not desired because it is a change in the frequency of the system clock during normal operation on the system. Nevertheless, since the abnormality detection occurs, it is necessary to temporarily stop the clock monitoring function. However, once the clock monitoring function is stopped when the clock is set or the mode is changed, the clock frequency abnormality cannot be monitored, and the safety of the system is lowered.

Therefore, when a request to change the frequency of the system clock is generated, a configuration in which the expected value is automatically changed according to the request can be considered. By adopting such a configuration, even after the frequency change, the number of pulses will match the expected value, so even if the frequency is changed during normal operation on the system, an abnormal detection signal is unexpectedly output. Such inconvenience is avoided.

It is considered that the expected value should be changed as well as changing the system clock frequency in this way. However, in the comparison unit that compares the number of pulses and the expected value, there may be a difference between the timing when the number of pulses after the frequency change is recognized and the timing when the expected value after the change is recognized. In such a case, the expected value changes in time, and the comparison result in the comparison unit becomes inconsistent, and an abnormality detection signal is unexpectedly output.

The present invention was created in view of such circumstances, and its main purpose is to increase the clock monitoring accuracy and improve the safety of the system.

(1) The present invention solves the above-described problems by including the following configuration. The present invention is a count unit, a comparison unit, a frequency change unit, and a frequency change determination unit having the following functions. The count unit sets a monitoring cycle based on a monitoring clock of a system different from the system clock, and then counts the number of pulses of the system clock for each monitoring cycle.

The comparison unit compares the count result of the count unit at the end of the monitoring period with an expected value, and if the comparison result indicates a mismatch between the count result and the expected value, an abnormality detection indicating an abnormality in the frequency of the system clock Output a signal. The abnormality detection signal is used for ensuring the safety of the system.

The frequency changing unit generates the system clock based on a system clock source, and changes the frequency of the system clock according to a frequency change request signal.

The frequency change determination unit confirms the reception of the frequency change request signal by the frequency change unit and the change of the system clock frequency by the frequency change unit based on the received frequency change request signal. An expected value change instruction signal for instructing the change of the expected value to a value corresponding to the frequency is output.

The expected value changing unit changes the expected value according to the expected value change instruction signal.

The condition adjustment unit controls the count unit, the comparison unit, the frequency change unit, or the expected value change unit so that no mismatch occurs between the count result and the expected value immediately after receiving the frequency change request signal.

The condition adjustment unit makes a difference between the timing at which the number of pulses after the frequency change is recognized and the timing at which the expected value after the change is recognized. This avoids the inconvenience that an abnormality detection signal is output. The condition adjusting unit adjusts the operating conditions so that there is no discrepancy between the number of pulses and the expected value immediately after receiving the frequency change request signal of the system clock. In other words, when the frequency change request signal is received, “the frequency change unit immediately changes the frequency of the system clock” and “the frequency change determination unit immediately outputs an expected value change instruction signal” and “the comparison unit has a monitoring cycle. By adjusting one of the series of operating conditions of `` Compare the number of system clock pulses after frequency change at the end with the expected value after change '' to `` Set the number of pulses immediately after the frequency change request and the expected value '' It is configured so that “a mismatch does not occur” does not occur. The condition adjustment unit cancels the condition adjustment processing when the monitoring cycle at the time of reception of the frequency change request signal ends and shifts to the next monitoring cycle.

According to the present invention, even if a situation occurs where there is a deviation between the timing of the change in the number of pulses and the timing of the expected value change, a situation where an abnormality detection signal is output in the mismatch determination due to the deviation, This can be avoided by the operation of the condition adjustment unit.

According to the present invention, when the condition adjustment unit is provided and the system clock frequency change request signal resulting from the change of the operation mode or the transition to the low consumption mode is received, the number of pulses immediately after that and the expected value are obtained. Since the operating conditions are adjusted so that mismatch does not occur, it is possible to avoid a situation where the comparator makes a mismatch determination and outputs an abnormality detection signal due to a timing difference between the change in the number of pulses and the expected value change. Can do. Thereby, it is not necessary to substantially stop the clock monitoring function, and it is possible to continuously ensure the safety of the system.

FIG. 1 is a diagram showing a basic configuration of a system clock monitoring apparatus according to each embodiment of the present invention. FIG. 2 is a configuration diagram of a system in which the system clock monitoring apparatus according to Embodiment 1 of the present invention is mounted. FIG. 3 is a timing chart during normal operation of the system clock monitoring apparatus according to the first embodiment of the present invention. FIG. 4 is a configuration diagram of a system in which the system clock monitoring apparatus according to the second embodiment of the present invention is mounted. FIG. 5 is a timing chart during normal operation of the system clock monitoring apparatus according to the second embodiment of the present invention. FIG. 6 is a timing chart when an abnormality is detected in the system clock monitoring apparatus according to the second embodiment of the present invention. FIG. 7 is a configuration diagram of a system in which the system clock monitoring apparatus according to the third embodiment of the present invention is mounted. FIG. 8 is a timing chart during normal operation of the system clock monitoring apparatus according to the third embodiment of the present invention. FIG. 9 is a configuration diagram of a system in which the system clock monitoring apparatus according to the fourth embodiment of the present invention is mounted. FIG. 10 is a timing chart during normal operation of the system clock monitoring apparatus according to the fourth embodiment of the present invention. FIG. 11 is a configuration diagram of a motor control system according to the fifth embodiment of the present invention. FIG. 12 is a timing chart during normal operation of the motor control terminal of the inverter control microcomputer according to the fifth embodiment of the present invention. FIG. 13 is a timing chart when an abnormality is detected in the motor control terminal of the inverter control microcomputer according to the fifth embodiment of the present invention. FIG. 14 is a block diagram of a system clock monitoring device in the prior art. FIG. 15 is a timing chart at the time of normal operation of the system clock monitoring device in the prior art. FIG. 16 is a timing chart when an abnormality is detected in the system clock monitoring device in the prior art.

The following are some of the aspects of the condition relaxation described in the above section [Means for Solving the Problems].

The function of the condition adjustment unit is “to adjust the operating conditions so that there is no discrepancy between the number of pulses immediately after that and the expected value when there is a request to change the frequency of the system clock”.

(A) In the monitoring cycle when the frequency change request signal S1 is received, the frequency of the system clock is not changed even though the frequency change request signal is received, and the next monitoring cycle (the time when the frequency change request signal is received) The system clock frequency change and expected value change are not made until the monitoring period next to the monitoring period in FIG. In this way, “there is no mismatch between the number of pulses and the expected value” can be realized in the monitoring cycle at the time when the frequency change request signal S1 is received.

(B) In the monitoring cycle at the time when the frequency change request signal S1 is received, by stopping the comparison of the number of pulses and the expected value by the comparison unit, “no mismatch between the number of pulses and the expected value does not occur” This can be realized in the monitoring cycle at the time when the frequency change request signal S1 is received.

(C) In the monitoring cycle when the frequency change request signal S1 is received, if the expected value is adjusted to match the number of pulses of the system clock after the frequency change, “the number of pulses does not match the expected value. It can be realized in the monitoring cycle at the time when the frequency change request signal S1 is received. In this case, if there is a margin in the expected value without causing a discrepancy, the discrepancy between the number of pulses and the expected value will occur even if the degree of system clock frequency abnormality is large. It is easy to realize that there is nothing.

(D) Similar to (c) above, the expected value is adjusted to the number of pulses of the system clock after the frequency change. However, the expected value is not limited to a single value. Good.

Hereafter, details will be explained in order.

(A) Condition relaxation by effective postponement of system clock frequency change request In the configuration of (1) above, when the condition adjustment unit receives the system clock frequency change request signal, There is an aspect in which the frequency change process is postponed based on the frequency change request signal until the end of the monitoring period, and the frequency change of the system clock is executed at or near the end of the monitoring period.

In other words, in the configuration of (1) above,
The condition adjusting unit includes the counting unit and the frequency changing unit,
The count unit is configured to output a frequency change permission signal to the frequency change unit when detecting the end of the monitoring period based on the count of the monitoring clock,
When the frequency change unit receives the frequency change request signal, the frequency change unit holds the frequency change of the system clock until the frequency change enable signal is input, and receives the frequency change enable signal and performs a system clock frequency change process. It is configured to be effective.

If the frequency of the system clock is changed immediately, the count result (number of pulses) at the end of the monitoring cycle has changed from the previous value. On the other hand, the expected value has not been changed. In this case, there is a possibility that a mismatch occurs between the count result and the expected value, and then an abnormality detection signal is unexpectedly output.

Even if the frequency change unit receives the frequency change request signal, the frequency change unit temporarily postpones the frequency change process based on the request until the end of the monitoring cycle. When the condition adjustment process of effective postponement of the frequency change request process is performed, the number of pulses in the monitoring period is the same as that before the request. Then, in the comparison unit, the determination of coincidence is continued in the comparison between the number of pulses performed at the end of the monitoring period and the expected value, and no abnormality detection signal is unexpectedly output. The frequency change request process is activated at the end of the monitoring cycle, and the frequency of the system clock is changed. The frequency change determination unit that has confirmed this outputs an expected value change instruction signal to the expected value change unit. Changes the expected value given to the comparator to an expected value corresponding to the system clock frequency after the frequency change. The change in the frequency of the system clock is performed at the beginning of the subsequent monitoring cycle, and the expected value is also changed at the beginning of the subsequent monitoring cycle. Even if there is a slight difference in timing between these two changes, there is no problem at the end of the monitoring cycle when the count result is compared with the expected value, and the system clock count result after the frequency change matches the expected value. To do.

Note that the postponement until the end of the monitoring cycle is a point here, but for checking the end of the monitoring cycle, it is preferable to make the count unit for inputting the monitoring clock function. The detection of the end of the monitoring period by the count unit is transmitted to the frequency change unit as a frequency change permission signal, and the frequency change process based on the frequency change request signal that the frequency change unit that has received the frequency change permission signal has suspended until then. It should be effective.

According to the above configuration, when a system clock frequency change request signal is issued in the middle of the system clock monitoring cycle, the clock monitoring function does not need to be substantially stopped and the system safety is continuously secured. It becomes possible to do.

(B) Condition relaxation by stop of comparison processing In the configuration of (1), when the condition adjustment unit receives the frequency change request signal, the condition adjustment unit stops comparing the count result and the expected value by the comparison unit. There is an aspect in which the current monitoring cycle in the counting unit is terminated and immediately shifted to the next monitoring cycle.

In other words, in the configuration of (1) above,
The condition adjustment unit includes the count unit and the comparison unit,
The counting unit is configured to immediately end the monitoring cycle when receiving a frequency change request signal and immediately shift to the next monitoring cycle,
The comparison unit temporarily stops the comparison between the count result and the expected value in the monitoring period when the frequency change request signal is received, and restarts the comparison when the next monitoring period is started. It is configured.

比較 In the monitoring cycle when the frequency change request signal is received, the comparison process at the end of the cycle is stopped. That is, the monitoring cycle is terminated immediately after receiving the frequency change request signal, and the process immediately shifts to the next monitoring cycle. The system clock frequency can be changed without delay. The frequency change is the initial period of the monitoring period next to the monitoring period when the frequency change request signal is received. In the next monitoring cycle in which the frequency is changed, the expected value is also changed at the initial stage. Since the comparison process between the number of pulses and the expected value is stopped in the monitoring period when the frequency change request signal is received, there is no mismatch and, naturally, no abnormality detection signal is output. In the monitoring period next to the monitoring period when the frequency change request signal is received, the number of pulses counted increases with time. If the operation is normal, the number of pulses matches the expected value after the change at the end of the cycle, and no abnormality detection signal is output.If the operation is abnormal, the number of pulses at the end of the cycle is An anomaly detection signal is output because it does not match the expected value after the change.

According to the above configuration, when the frequency change request signal of the system clock is received, the frequency of the system clock is immediately changed. Therefore, after ensuring the quick response of the frequency change process to the frequency change request signal, The system clock frequency can be continuously monitored even immediately after the system clock is changed to ensure the safety of the system.

(C) Condition relaxation by expanding expected value range In the configuration of (1) above, the condition adjustment unit is an expected value before change before receiving a frequency change request signal as the expected value in the monitoring period when receiving a frequency change request signal. And an expected value range in which one of the post-change expected values corresponding to the post-change frequency instructed by the frequency change request signal is an upper limit value and the other is a lower limit value, and the frequency change request signal is received. There is a mode in which the expected value is changed to the changed expected value when the monitoring period is shifted to the next monitoring period.

In other words, in the configuration of (1) above, the condition adjustment unit includes the expected value change unit and the comparison unit,
The expected value changing unit corresponds to the expected value in the monitoring period when receiving an expected value change instruction signal, the expected value before change before receiving the frequency change request signal, and the changed frequency instructed by the frequency change request signal. After setting the expected value range in which one of the expected values after change is an upper limit value and the other is a lower limit value, the expected value is transferred to the monitoring cycle next to the monitoring cycle when the frequency change request signal is received. Is changed to the expected value after the change,
In the monitoring period when the frequency change request signal is received, the comparison unit compares the count result of the count unit at the end of the monitoring period with the expected value range, and in the comparison result, the count result is within the expected value range. If it is out of range, the abnormality detection signal is output.

When receiving the frequency change request signal, the frequency change unit immediately accepts the request signal and immediately changes the frequency of the system clock. Since the frequency of the system clock is changed, the number of pulses in the monitoring period is different from the previous number of pulses. Adjustment may be made so that the expected value matches the number of pulses, but it is difficult to grasp how much the number of pulses changes. Therefore, the expected value is changed with a certain width. Assuming that the expected value corresponding to the frequency related to the frequency change request signal is the expected value after change, the newly set expected value has a range from the expected value before change to the expected value after change. This is the expected value range. The magnitude relationship between the expected value before change and the expected value after change depends on the situation at that time. When the frequency is increased, the range is [expected value before change to expected value after change], and when the frequency is decreased, the range is [expected value after change to expected value before change].

If conditions are relaxed by expanding the expected value range, the number of pulses will fall within the expected value range with the range from the expected value before the change to the expected value after the change at the end of the monitoring period. The count result obtained by counting the system clocks coincides with the expected value. If it is out of the expected value range, an abnormality detection signal is output.

The comparison of the number of pulses to the expected value range is only for the monitoring period at the time when the frequency change request signal S1 is received, and the expected value changing unit is expected when the period shifts to the next monitoring period. Change the value to the expected value after the change.

As described above, when a frequency change request signal resulting from a change in operating mode or transition to a low-consumption mode is received, the system clock frequency is continuously monitored without stopping the clock monitoring function. Is possible. In addition, when the frequency change request signal is received, the frequency of the system clock is immediately changed, so that it is possible to ensure quick response of the frequency change signal to the frequency change request signal. Furthermore, even if there is a temporary frequency fluctuation (fluctuation) when switching to the system clock frequency immediately after the frequency change and fluctuations may occur in the count result of the number of pulses at the end of the monitoring period, Since the expected value range is set, the output of the abnormality detection signal due to the mismatch determination is prevented, and the safety of the system can be ensured. Incidentally, the substantial system clock monitoring in the case of (b) is slightly delayed in the next monitoring cycle. On the other hand, in the case of (c), immediate system clock monitoring in the monitoring cycle at the time when the frequency change request signal S1 is received is realized.

(D) Condition relaxation by adjustment of expected value for temporary alignment In the configuration of (1) above, the condition adjusting unit uses the expected value in the monitoring period when receiving the frequency change request signal as the frequency change request. After setting the value calculated based on the count result of the counting unit at the time of receiving the signal, and when shifting to the monitoring cycle next to the monitoring cycle at the time of receiving the frequency change request signal, the expected value is changed to the frequency change request. There is an aspect in which it is configured to change the value according to the signal.

Adjusting the expected value so that it matches the number of pulses corresponding to the timing at which the frequency change request signal was received means that when the system clock frequency change request signal is received, the number of pulses immediately after that and the expected value Is an example of adjusting the operation condition so that no mismatch occurs.

In other words, in the configuration of (1) above,
The condition adjustment unit includes the count unit and the expected value change unit,
The counting unit is configured to end the monitoring cycle and immediately shift to the next monitoring cycle when receiving the frequency change request signal,
When the expected value change unit receives the expected value change instruction signal, the expected value in the monitoring period at the time of receiving the frequency change request signal is used as a count result of the count unit at the time when the frequency change request signal is received. After setting to a value calculated on the basis of the frequency change request signal, the expected value is changed to a value corresponding to the frequency change request signal when the monitoring period is shifted to the next monitoring period. Yes.

If the timing (phase) of the frequency change request signal is known in the monitoring cycle when the frequency change request signal is received, the number of pulses can be determined. The matching is performed so as to match the number of pulses, and the expected value is temporarily adjusted. In other words, the expected value, which is a comparison standard and must be kept at a constant value, is adjusted to the number of pulses that change from the expected value. By such a condition adjustment process of adjusting the expected value temporarily, the number of pulses is matched with the expected value (that is, a mismatch between the number of pulses immediately after receiving the frequency change request signal and the expected value may occur. Avoid output of abnormality detection signals.

According to the above configuration, the frequency of the system clock can be continuously continued without stopping the clock monitoring function even when a frequency change request signal resulting from a change in the operation mode or transition to the low power consumption mode is received. Monitoring becomes possible. In addition, when the frequency change request signal is received, the frequency of the system clock is changed immediately. Therefore, it is possible to ensure the safety of the system while ensuring quick response of the frequency change to the frequency change request signal. It becomes possible. Further, more accurate system clock monitoring can be performed as compared with the case of temporarily stopping the comparison in the case of (b) and the case of expanding the expected value of (c). Incidentally, the period of substantial system clock monitoring in the case of (b) is the next monitoring period, and in the case of (c), it is the monitoring period when the frequency change request signal S1 is received. There is a little accuracy. On the other hand, in the case of (d), in addition to instantaneous switching of the system clock frequency, immediate system clock monitoring in the monitoring cycle at the time when the frequency change request signal S1 is received is realized.

Furthermore, the motor control system according to the present invention includes:
A motor,
An inverter circuit having a switching element for controlling the supply current of the motor;
The system clock monitoring device according to claim 1, wherein the switching element is controlled so that the motor is in a safe state when a clock frequency abnormality occurs.
Is provided.

In this specification, each component of the frequency changing unit, the counting unit, the frequency change determining unit, the expected value changing unit, the comparing unit, and the condition adjusting unit is configured by hardware, and each step or routine in software You may comprise. Or you may comprise by the combination of hardware and software.

Hereinafter, a plurality of embodiments of a system clock monitoring apparatus according to the present invention will be described in detail with reference to the drawings.

[Basic configuration of each embodiment]
First, a basic configuration common to the embodiments will be described. FIG. 1 is a basic configuration diagram of a system clock monitoring apparatus which is common to the embodiments of the present invention. This system clock monitoring device includes a frequency changing unit 1, a counting unit 2, a frequency change determining unit 4, an expected value changing unit 5, a comparing unit 6, and a condition adjusting unit 7.

The frequency changing unit 1 generates the system clock CK1 from the system clock source CS, and changes the frequency of the system clock CK1 according to the frequency change request signal S1. The count unit 2 is supplied with a system clock CK1 and a monitoring clock CK2 of a system different from the system clock CK1. The counting unit 2 counts the number of pulses PN of the system clock CK1 in the monitoring period T1 based on the monitoring clock CK2. The frequency change determination unit 4 outputs an expected value change instruction signal S2 when it is confirmed that the frequency change request signal S1 is present and the frequency change unit 1 has changed the frequency of the system clock CK1. The expected value changing unit 5 changes the expected value Ex to an expected value corresponding to the changed frequency based on the reception of the expected value change instruction signal S2 from the frequency change determining unit 4. The comparison unit 6 compares the count result (the number of pulses PN of the system clock CK1) supplied from the count unit 2 with the expected value Ex supplied from the expected value changing unit 5 and the comparison result. If they do not match, an active abnormality detection signal Sa (indicating frequency abnormality) is output. When the condition adjustment unit 7 receives the frequency change request signal S1 of the system clock CK1, the condition adjustment unit 7 adjusts the operating condition so that there is no mismatch between the number of pulses PN immediately after that and the expected value Ex.

The expected value changing unit 5 determines the expected value Ex given to the comparing unit 6 as follows:
Obtained from an external storage device in which a correspondence table between the frequency of the system clock CK1 and the expected value is stored,
-Obtained from a built-in memory in which a correspondence table having the same configuration as the correspondence table is stored.
Configured as follows.

Hereinafter, the operation of the system clock monitoring apparatus of this embodiment will be described.

(Normal operation)
The count unit 2 and the comparison unit 6 function during normal operation without the system clock frequency change request signal S1, and the frequency change determination unit 4, the expected value change unit 5, and the condition adjustment unit 7 are substantially suspended. State. The frequency changing unit 1 generates a system clock CK1 having a basic operating frequency based on the system clock source CS. The count unit 2 receives a system clock CK1 and a monitoring clock CK2. The count unit 2 counts the number of pulses of the system clock CK1 every monitoring period T1 defined by the monitoring clock CK2. The comparison unit 6 compares the count result of the count unit 2 (the count result of the number of pulses in the monitoring period T, hereinafter referred to as the pulse number PN) and the expected value Ex every monitoring period T1. Since both coincide with each other during normal operation, the abnormality detection signal Sa (indicating presence or absence of frequency abnormality) output from the count unit 2 remains inactive. When a frequency abnormality occurs in the system clock CK1 and the pulse number PN increases or decreases from its normal value, the pulse number PN does not match the expected value Ex. Upon detecting this, the comparison unit 6 activates the abnormality detection signal Sa and outputs it to a CPU and peripheral circuits (not shown). The CPU or peripheral circuit that has received the active abnormality detection signal Sa performs a predetermined safe operation.

(When changing the system clock frequency)
When a frequency change request for the system clock is generated due to a change in the operation mode, a shift to a low consumption mode, or the like, and the frequency change request S1 becomes active, the frequency change determination unit 4, the expected value change unit 5, and The condition adjustment unit 7 shifts to an operating state.

When the condition adjustment unit 7 receives the frequency change request signal S1, the condition adjustment unit 7 becomes active, and in the monitoring period T1 _x when the frequency change request signal S1 of the system clock is received, the frequency change unit 1 or the count unit 2 or The operating condition is adjusted by controlling the frequency change discriminating unit 4, the expected value changing unit 5 or the comparing unit 6. Specifically, the operating conditions of each unit are adjusted so that there is no discrepancy between the number of pulses PN immediately after the frequency change request signal S1 and the expected value Ex. When the monitoring period T1 _x ends and the process proceeds to the next monitoring period T1 _{x + 1} , the condition adjustment unit 7 cancels the operation condition adjustment process.

There are a plurality of configurations for performing the operation condition adjustment processing, and each of the plurality of configurations is the first to fourth embodiments of the present invention.

(Embodiment 1)
FIG. 2 is a configuration diagram of the system 100 in which the system clock monitoring device that performs the operation condition adjustment processing of the first embodiment is mounted. The present embodiment corresponds to the condition adjustment unit 7 in FIG. 1 realized by the cooperation of the counting unit 2 and the frequency changing unit 1. That is, it corresponds to the above (a) [condition relaxation by effective postponement of the frequency change request signal of the system clock]. In FIG. 2, the same reference numerals as those in FIG.

The system 100 includes a storage unit 3 in addition to the configuration of FIG. The storage unit 3 stores an expected value Ex for the number of pulses PN of the system clock CK1. In the storage unit 3, there are a plurality of patterns for the frequency transition of the system clock CK 1, and expected values Ex corresponding to these transition patterns exist. The storage unit 3 holds the plurality of expected values Ex in the form of a table, and the storage unit 3 switches the expected value Ex to be output based on the control from the expected value change unit 5.

The system 100 further includes a CPU and a peripheral circuit 8. When the expected value change unit 5 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the expected value change unit 5 newly reads the expected value Ex corresponding to the frequency of the system clock CK1 after the change from the storage unit 3, and the old expected value The value Ex is updated with the new expected value Ex. After that, the updated expected value Ex is output to the comparison unit 6. The CPU and peripheral circuit 8 are driven using the system clock CK1 output from the frequency changing unit 1 as a clock source.

The CPU and the peripheral circuit 8 output a frequency change request signal S1 to the frequency change unit 1 when receiving an instruction to change the frequency of the system clock CK1 due to a change in the operation mode or a shift to the low consumption mode. The CPU and peripheral circuit 8 also provides the frequency change request signal S1 to the frequency change determination unit 4 and the count unit 2. The frequency changing unit 1 generates the system clock CK1 based on the system clock source CS, and supplies the generated system clock CK1 to the CPU and the peripheral circuit 8.

When the frequency change unit 1 receives the frequency change request signal S1 from the CPU and the peripheral circuit 8,
-Until the active frequency change permission signal S3 is supplied from the count unit 2, the frequency change of the system clock CK1 is suspended (postponed),
When the active frequency change permission signal S3 is received, the frequency change of the system clock CK1 is made effective.
It is configured as follows.

When receiving the frequency change request signal S1 from the CPU and the peripheral circuit 8, the count unit 2 is configured to output an active frequency change permission signal S3 to the frequency change unit 1 in synchronization with the end detection of the monitoring period T1. ing. Note that the end of the monitoring cycle T1 is detected based on the count of the monitoring clock CK2.

The comparison unit 6 outputs an active abnormality detection signal Sa to the CPU and the peripheral circuit 8 when detecting a frequency abnormality of the system clock CK1 based on the comparison between the pulse number PN and the expected value Ex.

The storage unit 3 may be configured with an internal memory, an external memory, or an external recording medium. Other configurations are the same as the basic configuration common to the above-described embodiments (FIG. 1), and thus the description thereof is omitted.

By having the above configuration,
A frequency change request signal S1 is supplied,
The count unit 2 detects the end of the monitoring cycle T1 in the monitoring clock CK2 by counting the clock CK2.
When the two conditions are satisfied, the frequency changing process of the system clock CK1 by the frequency changing unit 1 is performed.

Next, the operation of the system clock monitoring apparatus of the first embodiment configured as described above will be described with reference to the timing chart of FIG. In the following description, the frequency change request signal resulting from the change of the operation mode, the shift to the low consumption mode, or the like at the timing t1 within the monitoring cycle T1 set based on the monitoring clock CK2 input from the count unit 2 It is assumed that S1 is output from the CPU and peripheral circuit 8.

The frequency change request signal S1 is supplied to the frequency change unit 1, the count unit 2, and the frequency change determination unit 4. Even when the frequency changing unit 1 receives the frequency change request signal S1, the frequency changing unit 1 does not immediately change the frequency of the system clock CK1. This is because the frequency change permission signal S3 is not active. Even when the count unit 2 receives the frequency change request signal S1, it does not immediately output the active frequency change permission signal S3, but after receiving the frequency change request signal S1, the monitoring cycle T1 has further reached its end. The count unit 2 outputs an active frequency change permission signal S3 only after detecting this. In the monitoring period T1 when the frequency change request signal S1 is input, the number of pulses PN of the system clock CK1 counted by the count unit 2 is sequentially incremented as time elapses. When the end of the monitoring period T1 is reached, the comparison unit 2 compares the pulse number PN with the expected value Ex. Here, the number of pulses PN = 9 and the expected value Ex = 9, which are the same, and the active abnormality detection signal Sa is not output.

When the end of the monitoring cycle T1 is reached, the count unit 2 outputs an active frequency change permission signal S3 to the frequency change unit 1. The frequency changing unit 1 that has received the frequency change request signal S1 at the timing t1 activates the frequency changing function when receiving the active frequency change permission signal S3. That is, simultaneously with the transition to the next monitoring cycle of the monitoring cycle at the time when the frequency change request signal S1 is received (timing t2), the frequency changing unit 1 changes the frequency of the system clock CK1 by the frequency change request signal S1. Change to frequency. Simultaneously with the transition to the next monitoring cycle, the pulse number PN is reset and returned to 0, and the count unit 2 starts counting up again.

When the frequency of the system clock CK1 is changed after shifting to the next monitoring cycle, this is confirmed by the frequency change determination unit 4. When the frequency change determination unit 4 confirms the frequency change of the system clock CK1, it outputs an expected value change instruction signal S2. The expected value changing unit 5 that has received the expected value change instruction signal S2 searches the storage unit 3 according to the information indicated by the expected value change instruction signal S2 immediately after the timing t2, reads the corresponding new expected value Ex, This is given to the comparison unit 6. Here, the description will be continued on the assumption that the update value is set to the expected value Ex = 4.

As the time elapses, the pulse number PN of the system clock CK1 counted by the counting unit 2 is incremented as 0 → 1 → 2 → 3, and the number of pulses reaches the end of the monitoring period (next monitoring period). PN = 4. This is compared with the expected value Ex = 4 in the comparison unit 6. In this case, since both match, the comparison unit 6 does not output an active abnormality detection signal Sa. Such a determination is based on the following state assumption. That is, in this situation, the comparison results agree with each other, although the frequency of the system clock CK1 has changed, but this frequency change is within the design assumption due to the change of the operation mode or the shift to the low consumption mode. It is not an abnormal frequency change. Based on this situation assumption, the comparison unit 6 does not output an active abnormality detection signal Sa.

As described above, in the monitoring period T1 when the active frequency change request signal S1 is received, the frequency change process of the system clock CK1 is postponed until the timing t2 is reached in the period from the timing t1 to the timing t2. Such a postponement of the frequency change is a postponement with a very short time length, and the frequency change is immediately implemented in the next monitoring period. For this reason, the temporary stop of the clock monitoring function does not substantially occur, and the safety of the system due to the temporary stop of the clock monitoring function does not occur.

In the operation example of FIG. 3, when a frequency abnormality occurs in the system clock CK1 in any of the monitoring periods T1 after the next monitoring period, the comparison unit 6 determines the number of pulses PN and the expected value at the end of the period in which the frequency abnormality has occurred. A mismatch with Ex = 4 is detected. In such a state, the comparison unit 6 outputs an abnormality detection signal Sa to the CPU and the peripheral circuit 8.

According to the present embodiment, when a system clock frequency change request is issued (receives the frequency change request signal S1) during the monitoring period T1 of the system clock CK1, the clock monitoring function is substantially stopped. There is no need, and the safety of the system can be ensured continuously.

In the first embodiment described above, the timing t2 at which the frequency of the system clock CK1 is actually changed is slightly delayed from the timing t1 at which the frequency change request signal S1 is received. The second embodiment described below further improves the responsiveness.

(Embodiment 2)
FIG. 4 is a configuration diagram of a system 200 in which a system clock monitoring device that performs the operation condition adjustment processing of the second embodiment is mounted. The present embodiment corresponds to the condition adjusting unit 7 in FIG. 1 realized by the cooperation of the counting unit 2 and the comparison unit 6. In other words, this corresponds to the above-mentioned [condition relaxation by stopping the comparison process] of (b). In FIG. 4, the same reference numerals as those in FIGS. 1 and 2 indicate the same components, and detailed description thereof will be omitted.

Unlike the system 100 (FIG. 2), the system 200 (FIG. 4) does not supply the frequency change request signal S1 from the CPU and the peripheral circuit 8 to the count unit 2. Further, the frequency change permission signal S3 is not supplied from the count unit 2 to the frequency change unit 1. Instead of supplying these signals, a frequency change request signal S1 is supplied from the CPU and peripheral circuit 8 to the comparison unit 6. The expected value change instruction signal S2 output from the frequency change determination unit 4 is supplied to the count unit 2 together with the expected value change unit 5. Upon receiving the expected value change instruction signal S2, the count unit 2 ends the monitoring cycle T1 at the time of receiving the frequency change request signal S1 immediately after receiving the request signal S1, and immediately shifts to the next monitoring cycle. It is configured.

When the comparison unit 6 receives the frequency change request signal S1 from the CPU and the peripheral circuit 8, the comparison unit 6 temporarily stops the comparison operation at the monitoring period T1 when the frequency change request signal S1 is received, and shifts to the next monitoring period. It is configured to return the comparison operation to active. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

Next, the operation of the system clock monitoring apparatus of the second embodiment configured as described above will be described with reference to the timing chart of FIG. FIG. 5 shows the operation during normal operation.

At the timing t3 of the monitoring cycle T1 generated by the monitoring clock CK2 input by the count unit 2, the CPU and the peripheral circuit 8 send the frequency change request signal S1 due to the change of the operation mode or the shift to the low consumption mode. Suppose that it outputs. The frequency change request signal S1 is supplied to the frequency change unit 1, the frequency change determination unit 4, and the comparison unit 6.

When the frequency change unit 1 receives the frequency change request signal S1, the frequency change unit 1 changes the frequency of the system clock CK1 to the frequency indicated by the frequency change request signal S1 at a timing t4 immediately after that. In this respect, unlike the first embodiment, the response is high. When the frequency of the system clock CK1 is changed, this is confirmed by the frequency change determination unit 4, and the frequency change determination unit 4 directs the active expected value change instruction signal S2 to the count unit 2 and the expected value change unit 5. Output.

Upon receiving the active expected value change instruction signal S2, the counting unit 2 ends the monitoring cycle T1 at the time of receiving the active expected value change instruction signal S2 immediately after receiving the signal S2, and immediately shifts to the next monitoring cycle. To do.

On the other hand, the comparison unit 6 that has received the frequency change request signal S1 from the CPU and the peripheral circuit 8 has the number of pulses PN and the expected value from the count unit 2 at the end of the monitoring period T1 that has been forcibly terminated (immediately before timing t4). The comparison process with the expected value Ex from the changing unit 5 is temporarily stopped. At this time, if the expected value Ex = 9 and the actually measured number of pulses PN = 5, they are inconsistent, but the comparison process is not performed as described above, so that an active abnormality detection signal Sa is output. Never happen.

Further, the expected value change unit 5 that has received the expected value change instruction signal S2 from the frequency change determination unit 4 searches the storage unit 3 according to the information superimposed on the expected value change instruction signal S2 immediately after the timing t4, and The new expected value Ex to be read is read out and given to the comparison unit 6. Here, after the expected value Ex = 4 is read from the storage unit 3, the expected value Ex of the comparison unit 5 is updated by the expected value Ex = 4.

As the time elapses, the pulse number PN of the system clock CK1 counted by the counting unit 2 is incremented as 0 → 1 → 2 → 3, and the number of pulses at the stage of reaching the end of the next monitoring cycle (timing t5) Is compared with the expected value Ex = 4 in the comparison unit 6. In the time chart of FIG. 5, since the number of pulses PN = 4 and they match, the comparison unit 5 does not output an active abnormality detection signal Sa. That is, at the timing t5, the frequency of the system clock CK1 changes immediately before, but this is an expected frequency fluctuation caused by a change in the operation mode, a shift to the low consumption mode, and the like, and not an abnormal fluctuation. In the present embodiment, by updating the expected value Ex at the timing t4, the comparison unit 5 can maintain the accuracy of the comparison operation after the timing t4 while continuing the comparison operation. As a result, the active abnormality detection signal Sa is not unnecessarily output after timing t4 (for example, timing t5).

As described above, the comparison operation in the comparison unit 6 is temporarily stopped only during the monitoring period T1 when the frequency change request signal S1 is supplied, and the comparison operation is immediately performed in the next monitoring period. Since the operation is resumed, the temporary stop of the clock monitoring function does not substantially occur, and the safety of the system does not deteriorate. In addition, when the frequency change request signal S1 of the system clock CK1 is received, the frequency of the system clock CK1 is immediately changed, so that quick response of frequency change to the frequency change request signal S1 can be ensured.

FIG. 6 shows an operation in the case where the system clock CK1 is abnormal in frequency and the system runs away in the second embodiment. In this case, it is assumed that a system runaway has occurred under the following conditions.
When a frequency abnormality has occurred in the system clock CK1 from the timing t6 preceding the timing t7,
At timing t7, the CPU and peripheral circuit 8 output the frequency change request signal S1 resulting from the change of the operation mode or the shift to the low consumption mode.

When the system runaway occurs under such conditions, the frequency change request signal S1 itself does not become normal. That is, the frequency changing unit 1 cannot correctly change the frequency of the system clock CK1 to the target frequency indicated by the change request signal S1. Therefore, the frequency change determination unit 4 does not output the expected value change instruction signal S2 to the count unit 2 and the expected value change unit 5 (timing t8). Since the expected value change instruction signal S2 is not output, the count unit 2 ends the monitoring cycle T1 at the time of receiving the frequency change request signal S1 immediately after receiving the frequency change request signal S1, unlike the case of FIG. Such control cannot be performed. Therefore, the count unit 2 continues to count the number of pulses PN of the system clock CK1 in which the frequency is abnormal until the end of the monitoring period T1. In FIG. 6, the number of pulses PN = 7 at timing t9, which is the end of the monitoring period T1. If there is no abnormality in the system clock CK1, the number of pulses PN at timing t9 is PN = 4 and should match the expected value Ex = 4. However, when the system clock CK1 has an abnormality, the expected value Ex = Does not match 4. In FIG. 6, (pulse number PN = 7) ≠ (expected value Ex = 4).

Further, since the expected value change instruction signal S2 is not output immediately after the timing t9, the expected value changing unit 5 does not change the expected value Ex = 4. As a result, the comparison processing in the comparison unit 6 performed at the end of the monitoring cycle T1 does not match, and an active abnormality detection signal Sa is output to the CPU and the peripheral circuit 8. The CPU and the peripheral circuit 8 that have received the active abnormality detection signal Sa execute a predetermined safe operation.

When the frequency change of the system clock CK1 is based on the system clock frequency change request signal S1 caused by the change of the operation mode or the transition to the low consumption mode, the abnormality of the system clock CK1 is not detected. Anomaly detection is reliably performed when the change is caused by runaway. Thus, in this embodiment, the monitoring accuracy of the frequency fluctuation of the system clock CK1 is maintained high while the responsiveness is maintained.

In the second embodiment, although the responsiveness is high, the comparison operation is temporarily stopped. The third embodiment which will be described next is designed to further improve the reliability.

(Embodiment 3)
FIG. 7 is a configuration diagram of a system 300 equipped with a system clock monitoring apparatus according to the third embodiment of the present invention.

The present embodiment corresponds to the condition adjustment unit 7 in FIG. 1 realized by the cooperation of the expected value change unit 5 and the comparison unit 6. That is, it corresponds to the above-mentioned (c) [Relaxing conditions by expanding the expected value range]. In FIG. 7, the same reference numerals as those in FIGS. 1 and 4 indicate the same components, and detailed description thereof will be omitted.

Unlike the second embodiment (FIG. 4), the CPU and the peripheral circuit 8 do not supply the frequency change request signal S1 to the comparison unit 6. Further, the frequency change determination unit 4 does not supply the expected value change instruction signal S2 to the count unit 2. Instead of supplying these signals, the frequency change determination unit 4 supplies the expected value change instruction signal S2 to the comparison unit 6. When the expected value change unit 5 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the expected value change unit 5 sets the expected value range Er as an expected value in the monitoring cycle T1 at the time when the frequency change request signal S1 is received. When the next monitoring cycle of the monitoring cycle T1 at the time when the change request signal S1 is received, the expected value range Er is changed to the expected value Ex2 in the next monitoring cycle. Specifically, in the monitoring cycle T1 when the frequency change request signal S1 is received, the expected value Ex2 after change and the expected value Ex1 before change corresponding to the frequency indicated by the frequency change request signal S1 are used as expected values. The expected value range Er (Ex1 to Ex2 or Ex2 to Ex1) is set, and when the frequency change request signal S1 is received and the process shifts to the next monitoring cycle of the monitoring cycle T1, the expected value range Er is further expected after the change. Change to value Ex2.

The counting unit 2 supplies the monitoring period T1 to the expected value changing unit 5 in order to notify the expected value changing unit 5 that it has shifted to the next monitoring cycle. When the comparison unit 6 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the comparison unit 6 counts the result of the count unit 2 (the pulse of the system clock CK1) at the end of the monitoring period T1 when the frequency change request signal S1 is received. The number PN) is compared with the expected value range Er. In this comparison, when it is detected that the number of pulses PN is out of the expected value range Er, the comparison unit 6 outputs an active abnormality detection signal Sa. The point of performing such a comparison operation is different from the second embodiment. Since other configurations are the same as those in the second embodiment, description thereof is omitted.

Next, the operation of the system clock monitoring apparatus of the third embodiment configured as described above will be described with reference to the timing chart of FIG. FIG. 8 shows the operation during normal operation. At timing t10 of the monitoring cycle T1 that the count unit 2 generates based on the monitoring clock CK2, the frequency change request signal S1 is sent from the CPU and the peripheral circuit 8 due to the change of the operation mode, the shift to the low consumption mode, or the like. Suppose that it is output. The frequency change request signal S1 is supplied to the frequency change unit 1 and the frequency change determination unit 4.

When the frequency change unit 1 receives the frequency change request signal S1, the frequency change unit 1 changes the frequency of the system clock CK1 to the frequency indicated by the frequency change request signal S1 (timing t11). When the frequency of the system clock CK1 is changed, the frequency change determination unit 4 detects this. When detecting the frequency change, the frequency change determination unit 4 supplies the expected value change instruction signal S2 to the expected value change unit 5 and the comparison unit 6.

The expected value change unit 5 that has received the expected value change instruction signal S2 from the frequency change determination unit 4 searches the storage unit 3 in accordance with the information indicated by the expected value change instruction signal S2, and reads and reads the corresponding new expected value Ex. Based on the new expected value Ex, the expected value range Er and the changed expected value Ex2 are set. Specifically, the expected value changing unit 5 sets the changed expected value Ex2 by updating the old expected value Ex with the read new expected value Ex. Further, the expected value before change (old expected value Ex) is set to the expected value Ex1 before change, and the expected value range Er including the changed expected value Ex2 and the expected value Ex1 before change (Ex1 to Ex2 or Ex2 to Ex1) Set.

The expected value changing unit 5 gives the expected value range Er to the comparing unit 6. The magnitude relationship between the pre-change expected value Ex1 and the post-change expected value Ex2 varies depending on the situation at that time. That is, when the frequency fluctuates upward, the expected value range Er becomes [Ex1 to Ex2], and when the frequency fluctuates downward, the expected value range Er becomes [Ex2 to Ex1]. Here, the expected value range Er≡ [4 to 9].

On the other hand, when the comparison unit 6 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the comparison unit 6 count results (number of pulses PN) at the end of the monitoring period T1 when the frequency change request signal S1 is received. ) Is compared with the expected value range Er. In this comparison, if it is determined that the number of pulses PN is outside the expected value range Er, the comparison unit 6 switches its operation state in the monitoring period T1 to the output operation state of the abnormality detection signal Sa.

After the timing t10 in the monitoring cycle T1, with the passage of time, the number of pulses PN of the system clock CK1 counted by the counting unit 2 is incremented as 5 → 6, and at the stage when the end of the monitoring cycle T1 is reached. The number PN = 7. The count result (number of pulses PN = 7) at the end of the monitoring period T1 is compared with the expected value range Er≡ [4 to 9] in the comparison unit 6. In this case, since the number of pulses PN = 7 is within the expected value range Er≡ [4 to 9], the comparison unit 6 does not output an active abnormality detection signal Sa. This is based on the following findings. That is, the frequency of the system clock CK1 fluctuated in the monitoring period T1, but this frequency fluctuation is an expected frequency fluctuation due to a change in the operation mode, a shift to the low consumption mode, and the like, and is not an abnormal frequency fluctuation. . Therefore, there is no need to output an active abnormality detection signal Sa.

When the above-described frequency fluctuation determination (determination that the fluctuation is within the assumption) is performed at the end of the monitoring period T1 and the process proceeds to the next monitoring period, the expected value changing unit 5 replaces the expected value range Er with the frequency The changed expected value Ex2 = 4 corresponding to the changed system clock frequency is provided to the comparison unit 6.

As described above, the present embodiment performs condition relaxation by expanding the expected value range. When the system clock frequency change request signal S1 due to the change of the operation mode, the transition to the low consumption mode, or the like is received, the frequency change of the system clock CK1 is postponed in the first embodiment. The comparison operation was paused. On the other hand, in the third embodiment, the frequency is changed immediately and the comparison process is performed at a predetermined timing. Therefore, in the third embodiment, the temporary stop of the clock monitoring function does not substantially occur, and the frequency of the system clock CK1 can be continuously monitored, and the safety of the system is ensured. In addition, when the frequency change request signal S1 of the system clock CK1 is received, the frequency of the system clock CK1 is immediately changed (see timings t10 and t11), so that the quick response of the frequency change process to the frequency change request signal S1. It is possible to ensure the safety of the system while ensuring the above.

In the operation example of FIG. 8, if a frequency abnormality occurs in the system clock CK1 in each monitoring period T1 after the next monitoring period, and the number of pulses PN does not coincide with the expected value Ex = 4 at the end of any period, The comparison unit 6 outputs an active abnormality detection signal Sa to the CPU and peripheral circuit 8.

In addition, regarding the expected value range Er (Ex1 to Ex2 or Ex2 to Ex1), instead of setting Ex1 to the expected value before change and Ex2 to the expected value after change, the range may be expanded a little more, or conversely The width may be narrowed. In the above example, instead of the expected value range Er≡ [4-9]
Er≡ [5-9] and Er≡ [6-9] may be set as the expected value range Er, and Er≡ [3-9] and Er≡ [2-9] may be set as the expected value range Er. That is, the expected value range Er may be adjusted as appropriate according to the operating environment.

In the third embodiment, the change to the expected value Ex = 4 after the frequency change is timing t12, which corresponds to the end of the monitoring cycle at the time when the frequency change request signal S1 is received. In the second embodiment, the monitoring cycle at the time of receiving the frequency change request signal S1 is shortened (the monitoring cycle at the time when the frequency change request signal S1 is received at the timing t4 in FIG. 5 ends), but the third embodiment Then, such a cycle shortening does not occur, and the change of the expected value Ex must be delayed correspondingly. In the fourth embodiment described below, the expected value Ex can be changed quickly.

(Embodiment 4)
FIG. 9 is a configuration diagram of a system 400 equipped with a system clock monitoring apparatus according to the fourth embodiment of the present invention. This embodiment corresponds to the condition adjustment unit 7 in FIG. 1 realized by the cooperation of the count unit 2 and the expected value change unit 5. That is, it corresponds to the above (d) [conditional relaxation by adjusting the expected value for temporary alignment]. In FIG. 9, the same reference numerals as those in FIGS. 1 and 4 indicate the same components, and detailed description thereof will be omitted.

Unlike the second embodiment (FIG. 4), the CPU and peripheral circuit 8 do not supply the frequency change request signal S1 to the comparison unit 6. Instead of this signal supply, the count unit 2 supplies the monitoring clock count value TN to the expected value changing unit 5. When the count unit 2 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the count unit 2 ends the monitoring cycle T1 at the time of reception immediately after reception, and immediately shifts to the next monitoring cycle. The count unit 2 includes a monitoring cycle counter that counts the monitoring clock CK2 as a clock source, and gives the monitoring clock count value TN by the monitoring cycle counter to the expected value changing unit 5.

When the expected value change unit 5 receives the expected value change instruction signal S2 from the frequency change determination unit 4, the expected value in the monitoring period T1 when the frequency change request signal S1 is received is the reception timing of the frequency change request signal S1. The expected value is adjusted to match the number of pulses PN corresponding to. That is, the expected value changing unit 5 calculates the expected value Ex by substituting the monitoring clock count value TN supplied from the counting unit 2 into the following arithmetic expression (1), and the expected value obtained by the calculation process Ex is given to the comparison unit 6.

When the frequency of the monitoring clock CK2 is twice the frequency of the system clock CK1, the arithmetic expression (1) is
Ex = {(TN + 1) / 2} -1 (1)
It becomes. Substituting TN = 3 into equation (1) yields Ex = {(3 + 1) / 2} -1 = 2-1 = 1. The arithmetic expression (1) has an expression structure considering that the initial values of the number of pulses PN of the system clock CK1 and the monitoring clock count value TN are zero.

It should be noted that the arithmetic expression (1) is further generalized as follows. That is, assuming that the frequency f2 of the monitoring clock CK2 is k times the frequency f1 of the system clock CK1 (k = f2 / f1), the equation (1) is
Ex = {(TN + 1) / k} −1 (1) ′
And then
Ex = {(TN + 1) / (f2 / f1)}-1 (1) ''
It becomes.

In this way, the expected value changing unit 5 adjusts the expected value Ex according to the number of pulses PN corresponding to the reception timing of the frequency change request signal S1. In the above example, the pulse number PN corresponding to the reception timing of the frequency change request signal S1 is PN = 1, but Ex = 1 is calculated so as to match this. As a result, the expected harmony Ex is adjusted so as to always coincide with the pulse number PN corresponding to the reception timing of the frequency change request signal S1 as a result of the scheduled harmonization by the arithmetic expression (1).

In addition, the expected value changing unit 5 changes the expected value Ex to an expected value corresponding to the frequency change request signal S1 at the time of transition to the next monitoring period of the monitoring period T1 when the frequency change request signal S1 is received. It is configured.

Next, the operation of the system clock monitoring apparatus according to the fourth embodiment will be described with reference to the timing chart of FIG. FIG. 10 shows the operation during normal operation. It is assumed that the CPU and the peripheral circuit 8 output the frequency change request signal S1 at the timing t13. Here, the timing t13 is an arbitrary timing included in the monitoring cycle T1 set by the counting unit 2 based on the monitoring clock CK2, and the frequency change request signal S1 is changed to an operation mode or a transition to a low consumption mode. It is assumed that the signal indicates a frequency change request based on an expected frequency variation caused by the above.

The frequency change request signal S1 is supplied to the frequency change unit 1 and the frequency change determination unit 4. When receiving the frequency change request signal S1, the frequency changing unit 1 changes the frequency of the system clock CK1 to the frequency indicated by the frequency change request signal S1 at timing t14. When the frequency of the system clock CK1 is changed, this is confirmed by the frequency change determination unit 4, and the frequency change determination unit 4 outputs the expected value change instruction signal S2 toward the count unit 2 and the expected value change unit 5. To do.

The count unit 2 that has received the expected value change instruction signal S2 outputs the monitoring clock count value TN by the monitoring period counter to the expected value change unit 5, and immediately thereafter clears the monitoring clock count value TN. Then, counting of a new monitoring cycle T1 is started.

On the other hand, the expected value changing unit 5 that has received the expected value change instruction signal S2 is expected in the monitoring cycle T2 in which the frequency of the system clock CK1 has been changed based on the monitoring clock count value TN supplied from the counting unit 2. The value Ex is calculated by calculation and given to the comparison unit 6.

As described above, since the expected value Ex is adjusted using the arithmetic expression (1) so that the expected value Ex matches the pulse number PN corresponding to the reception timing of the frequency change request signal S1, the comparison unit at this timing is adjusted. The comparison process of 6 (comparison process of the number of pulses PN and the expected value Ex) always matches, and the active abnormality detection signal Sa is not output.

In the next monitoring period positioned next to the monitoring period at the supply timing of the frequency change request signal S1, the expected value Ex is changed to an expected value corresponding to the frequency change request signal S1 of the system clock (Ex = 3). Thereby, in the comparison process between the pulse number PN and the expected value Ex in the next monitoring cycle, the pulse number PN and the expected value Ex always match. As a result, the active abnormality detection signal Sa is not output. Although the frequency of the system clock CK1 has changed, this is due to a change in the operation mode, a shift to the low consumption mode, or the like, so there is no need to output the active abnormality detection signal Sa.

In the operation example of FIG. 10, if a frequency abnormality occurs in the system clock CK1 in each monitoring period T1 after the next monitoring period, and the number of pulses PN at the end of the period does not coincide with the expected value Ex = 3, the comparison unit 6 Outputs an abnormality detection signal Sa to the CPU and peripheral circuit 8.

According to the present embodiment, the system clock frequency is continuously monitored even when the system clock frequency change request signal S1 resulting from the change of the operation mode or the shift to the low consumption mode is received. System security is ensured. In addition, when the system clock frequency change request signal S1 is received, the system clock frequency and the expected value are immediately changed, so that a quick response of the frequency change process and the expected value change process to the frequency change request signal S1. It is possible to ensure the safety of the system while ensuring the safety.

In each of the above-described embodiments, the expected value table is stored in the storage unit 3 and the expected value changing unit 5 reads out the corresponding expected value Ex from the storage unit 3. The change unit 5 may be configured to calculate the expected value Ex according to the frequency of the system clock after the frequency change by calculation. In this case, the expected value storage unit 3 is not required.

(Embodiment 5)
The present embodiment relates to a motor control system. FIG. 11 is a configuration diagram of a motor control system that is widely used in industrial and household appliances. The motor control system of FIG. 11 includes an AC power source 21, a converter circuit 22, an inverter circuit 23, a switching element (IGBT element) 24 constituting the inverter circuit 23, an inverter control microcomputer 25, and a three-phase motor 26. Is provided. IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor.

The inverter control microcomputer 25 is equipped with the system clock monitoring device A having any one of the configurations of the first to fourth embodiments, and controls the three-phase motor 26.

The converter circuit 22 converts the output of the AC power source 21 into a DC power source and supplies it to the inverter circuit 23. The inverter control microcomputer 25 controls the switching element 24 in the inverter circuit 23 by using six output terminals [U-phase output (U1, U2), V-phase output (V1, V2), W-phase output (W1, W2)]. Thus, the current control of the three-phase motor 26 is performed. Thereby, the rotation direction and rotation speed of the three-phase motor 26 are controlled.

FIG. 12 is a timing chart showing the operation of each output terminal of the inverter control microcomputer 25 in a normal state. The U-phase output (U1, U2), the V-phase output (V1, V2), and the W-phase output (W1, W2) each have a pair of outputs. These outputs operate so that both the + side and − side switching elements 24 are not active (the control signal is H). This is because if both the + side and − side switching elements 24 become active, a through current flows through the entire system and the system may be destroyed.

FIG. 13 is a timing chart showing the operation of each output terminal of the inverter control microcomputer 25 and the abnormality detection signal Sa at the time of abnormality. When an abnormality occurs in the instruction control of the inverter control microcomputer 25 due to an abnormality in the clock frequency, and there is a section in which both U-phase outputs (U1, U2) are active (timing t15), a through current is generated. However, when such an instruction control abnormality occurs, the system clock monitoring device A installed in the inverter control microcomputer 25 detects an abnormality in the frequency of the system clock CK0 and detects an abnormality in the CPU and the peripheral circuit 8. The signal Sa is output. When receiving the abnormality detection signal Sa, the CPU and the peripheral circuit 8 forcibly change the six output terminals of the inverter control microcomputer 25 to a safe state, thereby preventing the occurrence of a through current.

As described above, according to this embodiment, the system clock monitoring device can be used effectively in the inverter control system of the three-phase motor.

The system clock monitoring device of the present invention is widely useful in fields where safety of various semiconductor products is required because it can constantly monitor the system clock that is the backbone of the system.

DESCRIPTION OF SYMBOLS 1 Frequency change part 2 Count part 3 Memory | storage part 4 Frequency change discrimination | determination part 5 Expected value change part 6 Comparison part 7 Condition adjustment part 8 CPU and peripheral circuit 100,200,300,400 System A system clock monitor mounting Device CS System clock source CK1 System clock CK2 Monitoring clock Ex Expected value Ex1 Upper limit expected value Ex2 Lower limit expected value Er Expected value range PN number of pulses S1 Frequency change request signal S2 Expected value change instruction signal S3 Frequency change permission signal Sa Abnormality detection signal T1 monitoring cycle TN monitoring clock count value

Claims

After setting a monitoring cycle based on a monitoring clock of a system different from the system clock, a counting unit that counts the number of pulses of the system clock for each monitoring cycle;
The count result of the count unit at the end of the monitoring period is compared with an expected value, and if the comparison result indicates a mismatch between the count result and the expected value, an abnormality detection signal indicating an abnormality in the frequency of the system clock is output. A comparison unit;
Generating a system clock based on a system clock source, and changing a frequency of the system clock in response to a frequency change request signal; and
When the reception of the frequency change request signal by the frequency change unit and the change of the system clock frequency by the frequency change unit based on the received frequency change request signal are confirmed, the value corresponds to the system clock frequency after the change. A frequency change determination unit that outputs an expected value change instruction signal for instructing change of the expected value of
An expected value changing unit that changes the expected value in response to the expected value change instruction signal;
A condition adjustment unit that controls the count unit or the comparison unit, the frequency change unit, or the expected value change unit so that no mismatch occurs between the count result and the expected value immediately after receiving the frequency change request signal;
A system clock monitoring device comprising:
The condition adjusting unit is configured to postpone the change of the system clock frequency by the frequency changing unit based on the reception of the frequency change request signal to the end of the monitoring cycle at the time of receiving the frequency change request signal or a time close thereto. Being
The system clock monitoring device according to claim 1.
The condition adjusting unit includes the counting unit and the frequency changing unit,
The counting unit is configured to detect the monitoring period end based on the count of the monitoring clock, and to output a frequency change permission signal to the frequency changing unit when the monitoring period end is detected,
The frequency changing unit is configured to enable the system clock frequency changing process when receiving both the frequency change request signal and the frequency change permission signal.
The system clock monitoring device according to claim 1.
When the condition adjustment unit receives the frequency change request signal, the condition adjustment unit stops the comparison between the count result by the comparison unit and the expected value and immediately ends the current monitoring cycle in the count unit and immediately performs the next monitoring. Configured to transition to a period,
The system clock monitoring device according to claim 1.
The condition adjustment unit includes the count unit and the comparison unit,
The counting unit is configured to immediately end the monitoring cycle when receiving a frequency change request signal and immediately shift to the next monitoring cycle,
The comparison unit temporarily stops the comparison between the count result and the expected value in the monitoring period when the frequency change request signal is received, and restarts the comparison when the next monitoring period is started. It is configured,
The system clock monitoring device according to claim 1.
The condition adjustment unit, as the expected value in the monitoring period at the time of receiving a frequency change request signal, an expected value before change before receiving the frequency change request signal and a change corresponding to the changed frequency instructed by the frequency change request signal After setting an expected value range in which one of the post-expected values is an upper limit value and the other is a lower limit value, the expected value is changed when a transition is made to the monitoring cycle next to the monitoring cycle when the frequency change request signal is received. After configured to change to the expected value,
The system clock monitoring device according to claim 1.
The condition adjustment unit includes the expected value change unit and the comparison unit,
The expected value changing unit corresponds to the expected value in the monitoring period when receiving an expected value change instruction signal, the expected value before change before receiving the frequency change request signal, and the changed frequency instructed by the frequency change request signal. After setting the expected value range in which one of the expected values after change is an upper limit value and the other is a lower limit value, the expected value is transferred to the monitoring cycle next to the monitoring cycle when the frequency change request signal is received. Is configured to change to the expected value after
In the monitoring period when the frequency change request signal is received, the comparison unit compares the count result of the count unit at the end of the monitoring period with the expected value range, and in the comparison result, the count result is within the expected value range. It is configured to output the abnormality detection signal when indicating that it is out of range,
The system clock monitoring device according to claim 1.
The condition adjustment unit sets the expected value in the monitoring cycle at the time of receiving the frequency change request signal to a value calculated based on the count result of the count unit at the time of receiving the frequency change request signal. The expected value is changed to a value corresponding to the frequency change request signal when the frequency change request signal is received and the monitoring period is shifted to the next monitoring period.
The system clock monitoring device according to claim 1.
The condition adjustment unit includes the count unit and the expected value change unit,
The counting unit is configured to end the monitoring cycle and immediately shift to the next monitoring cycle when receiving the frequency change request signal,
When the expected value change unit receives the expected value change instruction signal, the expected value change unit receives the expected value in the monitoring period when the frequency change request signal is received, based on the count result of the count unit at the time when the frequency change request signal is received. The expected value is changed to a value corresponding to the frequency change request signal when the monitoring period is shifted to the next monitoring period when the frequency change request signal is received. ,
The system clock monitoring device according to claim 1.
A motor,
An inverter circuit having a switching element for controlling the supply current of the motor;
The system clock monitoring device according to claim 1, wherein the switching element is controlled so that the motor is in a safe state when a clock frequency abnormality occurs.
A motor control system comprising: