WO2010150322A1

WO2010150322A1 - Test method and test system for ac coupling input buffer, and semiconductor integrated circuit

Info

Publication number: WO2010150322A1
Application number: PCT/JP2009/002950
Authority: WO
Inventors: 小野田恭也; 紺本明彦
Original assignee: 富士通株式会社
Priority date: 2009-06-26
Filing date: 2009-06-26
Publication date: 2010-12-29

Abstract

A pulse generator (70) is provided on a test board (7) of a tester (8); high-frequency pulses are output to an AC coupling input buffer (30) of a semiconductor integrated circuit (1) mounted on the test board (7); and the output pulses of the AC coupling input buffer (30) are counted by a counter (5). The tester (8) measures the high frequency of the AC coupling input buffer from the count value of the counter (5).

Description

AC coupling input buffer test method, test system, and semiconductor integrated circuit

The present invention relates to an AC coupling input buffer test method, a test system, and a semiconductor integrated circuit.

In recent years, the speedup of IC (Integrated Circuit) and LSI (Large Scale Integrated circuit) devices has been remarkable. For this reason, the signal frequency between IC and LSI is also high, and it is important to test the high-frequency performance of input and output.

Usually, the high frequency performance of input / output depends on the frequency performance of an I / O (Input / Output) buffer in an interface circuit of an IC or LSI that is an AC (alternating current) coupling unit. For this reason, the frequency performance of the I / O buffer is tested.

FIG. 6 is an explanatory diagram of a conventional AC coupling I / O test method. As shown in FIG. 6, the LSI for measurement 120 is mounted on the tester board 100. Here, the LSI for measurement 120 shows only an interface circuit.

The LSI for measurement 120 includes an input buffer (AC coupling unit: receiver) 122, a test circuit 124, and a synchronization circuit 126. The input buffer 122 includes a pair of capacitive elements (capacitors) 122-1 connected to the pair of signal lines L1 and L2, respectively, and a differential amplifier 122-2 connected to the capacitor 122-1. The input buffer 122 receives a differential input signal from the pair of signal lines L1 and L2 and converts it into a DC pulse signal.

The synchronization circuit 126 outputs the pulse signal from the input buffer 122 to the internal circuit in synchronization with the internal circuit. On the other hand, the LSI tester 130 connected to the tester board 100 is a system for testing various performances of the LSI 110. The LSI tester 130 outputs a general control signal for testing the LSI 110 from the signal line L5 to the LSI 110.

The LSI tester 130 is a general-purpose tester, and the signal output from the channel has a limit of several hundred MHz. Therefore, a dedicated test circuit 124 is provided in the interface circuit of the LSI 120 in order to perform a test at a high frequency of the LSI 120. The dedicated test circuit 124 includes a loopback circuit 124-1 and a determination circuit.

In order to test the AC coupling unit of the LSI 120, the LSI tester 130 sends a control signal to the test circuit 124 via the signal line L3 and starts the operation of the test circuit 124. The loopback circuit 124-1 is configured with a driver and outputs a pulse signal from the high-frequency pulse generation circuit in the test circuit 124 to the input stage of the input buffer 122.

On the other hand, the determination circuit of the test circuit 124 determines the performance for the given high frequency from the output from the input buffer 122. Then, the determination circuit of the test circuit 124 outputs a determination signal to the LSI tester 130 via the signal line L4. In this way, the frequency dynamic range of the AC coupling unit is measured at a frequency higher than the limit frequency of the LSI tester 130.

Japanese Patent Laid-Open No. 09-113586 JP 2008-128759 A

However, as the speed of LSIs in recent years increases, a signal transmission rate (frequency) on the order of more than GHz is required. Since the signal output from the channel of the general-purpose LSI tester has a limit of several hundred MHz, such an LSI tester cannot send a signal to the AC coupling I / O having a transmission rate exceeding GHz. For this reason, it is difficult to test an AC coupling unit having such a transmission rate.

Also, the test pulse generation method from the Loopback circuit has a problem that the control for performing the test is complicated and it is difficult to create a test circuit and a test pattern.

Furthermore, since the diagnosis is made in a wide range including the driver 124-1 and the receiver 122, it is difficult to specify the failure location when there is a failure.

Therefore, an object of the present invention is to provide an AC coupling input buffer test method, a test system, and a semiconductor integrated circuit, which can easily perform an AC coupling input buffer test at a high frequency using a general-purpose LSI tester. There is.

To achieve this object, an AC coupling input buffer test method for testing the frequency characteristics of an AC coupling input buffer includes a pulse generator provided on a test board on which a semiconductor integrated device having the AC coupling input buffer is mounted. The step of inputting a pulse signal having a set frequency to the AC coupling input buffer, the step of counting the output pulses of the AC coupling input buffer to which the pulse signal has been inputted by a counter, and the pulse generation A tester reads a value of the counter after a set number of signals are input to the AC coupling input buffer; and the tester reads the value of the counter and the set number And the AC coupling input bar at the frequency. And a step of determining characteristics of the file.

In order to achieve this object, an AC coupling input buffer test system for testing frequency characteristics of an AC coupling input buffer includes a test board on which a semiconductor integrated device having the AC coupling input buffer is mounted, and the test. A pulse generator provided on the board for inputting a pulse signal having a set frequency to the AC coupling input buffer, and a counter value for counting output pulses of the AC coupling input buffer to which the pulse signal is input. After the pulse generator inputs a set number of signals to the AC coupling input buffer, it reads out, compares the read counter value with the set number, and A tester for determining characteristics of the AC coupling input buffer.

In order to achieve this object, the semiconductor integrated circuit is supplied with a pulse signal having a set frequency from an AC coupling input buffer and a pulse generator provided on the test board to the AC coupling input buffer. A counter for counting output pulses of the AC coupling input buffer to which the pulse signal is input, and a terminal for reading the value of the counter from the tester.

∙ Since the tester's test board is equipped with a pulse generator to output high frequency pulses, it is possible to measure the high frequency of the AC coupling input buffer. Further, since the signal is controlled from the channel of the tester, it is not necessary to consider the combination with the driver, and it is understood that if there is a circuit failure, it is a problem of the receiver itself. In addition, since it is not necessary to provide a loopback circuit and a determination circuit for the conventional test in the circuit under test, the number of elements of the semiconductor integrated circuit can be reduced.

1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. It is a block diagram of the test system of one embodiment of this invention. It is a wave form diagram of each part of the structure of FIG. FIG. 3 is a measurement process flow diagram of the first embodiment of the present invention. It is a measurement processing flowchart of the 2nd Embodiment of this invention. It is explanatory drawing of the measuring method of the conventional AC coupling input buffer.

Hereinafter, embodiments of the present invention will be described in the order of an IC to be measured, a test system, an embodiment of a measurement process, and other embodiments, but the present invention is not limited to this embodiment.

(IC to be measured)
FIG. 1 is a block diagram of an embodiment of an IC to be measured according to the present invention.
An example is Processor Unit).

As shown in FIG. 1, the IC under measurement 1 includes an arithmetic device 10 that executes arithmetic operations, an instruction control device 12 that analyzes instructions and controls each circuit (device), and an interface circuit connected to the instruction control device 12. Group 20. The IC 1 to be measured includes a memory interface circuit group 22 for connecting to an external memory, and a memory controller 16 connected to the memory interface circuit group 22 and controlling the cache memory 14.

This CPU analyzes the instruction received from the interface circuit group 20 by the instruction control device 12, sets the data in the cache memory 14 to the arithmetic device 10 based on the analysis result, and executes the arithmetic operation. The calculation result is stored in the cache memory 14.

Further, the instruction control device 12 instructs the memory controller 16 to access the external memory via the memory interface circuit group 22 based on the analysis result. The memory controller 16 accesses (reads or writes) the external memory via the memory interface circuit group 22, stores necessary data in the cache memory 14, or writes data in the cache memory 14 to the external memory.

The IC 1 to be measured further has a test control circuit 18. The test control circuit 18 tests the arithmetic device 10, the instruction control device 12, the interface circuit group 20, the memory interface circuit group 22, the cache memory 14, and the memory controller 16 according to instructions from the outside. Necessary instructions are output, and the test state is output to the outside.

Here, the interface circuit group 20 and the memory interface circuit group 30 are provided with as many input buffer units (AC coupling units) 30 as the number of connection lines. That is, the CPU 1 is connected to an external circuit or a memory via a connection line by the interface circuit group 20 and the memory interface circuit group 22, and the input buffer unit (receiver) 30 receives a signal such as a command or data from the signal line. Receive.

Note that the IC to be measured 1 is not limited to the CPU in FIG. 1, but may be another functional element (memory, bridge circuit, I / O controller, hub, etc.) connected to the connection line and having an input buffer.

(Test system)
FIG. 2 is a block diagram of an embodiment of the test system of the present invention, and FIG. 3 is a waveform diagram of each part of FIG. 2 that are the same as those shown in FIG. 1 are denoted by the same symbols.

As shown in FIG. 2, the IC 1 to be measured is mounted on the tester board 7 of the LSI tester 8. Here, the IC for measurement 1 shows only the input buffer unit 30 of the interface circuit 20 (22).

The input buffer unit 30 of the IC 1 to be measured has an input buffer (AC coupling unit: receiver) 2, a counter 5, and a synchronization circuit 6. The input buffer 2 includes a pair of capacitive elements (capacitors) 3 connected to the pair of signal lines L 10 and L 11, and a differential amplifier 4 connected to the capacitor 3.

The input buffer 2 receives the differential input signals (B and C in FIG. 3) from the pair of signal lines L10 and L11 and converts them into a DC pulse signal (D in FIG. 3). The synchronization circuit 6 outputs the pulse signal from the input buffer 2 to an internal circuit (for example, a memory controller or an instruction control device in FIG. 1) in synchronization with the internal circuit. The counter 5 counts pulse signals from the input buffer 2.

On the other hand, the LSI tester 8 connected to the tester board 7 is a system for testing various performances of the IC 1. The LSI tester 8 outputs a general control signal for testing the IC1 from the signal line L9 to the IC1 (the test control circuit 18).

This LSI tester 8 is a general-purpose tester, and the signal output from the channel is limited to several hundred MHz. Therefore, a pulse generator 70 and a frequency setting circuit 72 are provided on the tester board 7 in order to execute a test of the IC 1 at a high frequency. The frequency setting circuit 72 receives a set frequency signal given from the LSI tester 8 through the signal line L7, and sets the frequency of the generated pulse in the pulse generator 70.

The pulse generator 70 generates pulse signals B and C having frequencies set by the frequency setting circuit 72 in response to an enable signal A (see FIG. 3) given from the LSI tester 8 via the signal line L6. Output to. The count value of the counter 5 is read into the LSI tester 8 through the signal line L8.

As described above, the pulse generator 70 is arranged between the channel of the general-purpose LSI tester 8 and the AC coupling I / O 2 to be tested, and the test counter circuit 5 is connected to the output of the AC coupling I / O 2. Connecting. The pulse generator 70 is a self-oscillation type, and Output
When Enable (OE) A is asserted, a waveform with an arbitrary frequency is output.

During the test, OE (signal A) is asserted as shown in FIG. 3, the waveforms B and C are output from the pulse generator 70, and the generated waveforms are input to the AC coupling I / O2 to be measured. When the circuit of the AC coupling unit 2 is normal, a waveform having the same frequency as the input waveform is output from the output of the AC coupling I / O 2 and propagates to the clock input of the next-stage test counter circuit 5.

The counter 5 counts up with this clock. After the output of the pulse generator 70 is stopped by deasserting OE (signal A), the upper bits of the counter 5 are read. As a result, the LSI tester 8 determines whether the AC coupling I / O operation is good or bad.

With such a configuration, since the pulse generator 70 is used, a high-frequency pulse can be distributed, so that the AC coupling capacitor 3 can be passed. Further, since the frequency can be made variable by using the pulse generator 70, it is possible to investigate the operation limit of the IC.

Furthermore, since the signal is controlled from the channel of the LSI tester 8, there is no need to consider the combination with the driver. In addition, when there is a circuit failure, it is understood that this is a problem of the receiver 2 itself. In this case, it is assumed that the operation of the test counter 5 has been confirmed by another function test.

In addition, since there is no need to provide a loopback circuit and a judgment circuit for the conventional test in the IC1, the number of elements of the IC1 can be reduced.

(Measurement process)
FIG. 4 is a process flowchart of the first embodiment of the measurement process of the present invention, and shows the measurement process for discriminating between a good product and a defective product, which is executed by the LSI tester 8 of FIG.

(S10) A general control signal is sent from the LSI tester 8 to the IC 1 through the signal line L9, and all counters in the IC 1 are reset.

(S12) The frequency and number of pulses of the frequency setting circuit 72 are set by the control signal from the LSI tester 8 through the signal line L7.

(S14) The LSI tester 8 outputs the signal via the signal line L6.
Enable A is asserted and the pulse generator 70 is operated. The pulse generator 70 generates pulses B and C at a set frequency and outputs them to the signal lines L10 and L11. As a result, a pulse is applied to the input buffer 2 of the measured interface circuit 20 / memory interface circuit 30. When the input buffer 2 can receive a pulse, a counter clock signal D is generated from the input buffer 2. When the counter clock signal D is generated, the counter 5 counts up.

(S16) The pulse generator 70 generates the set number of pulses and stops. The LSI tester 8 reads the value of the counter 5 through the signal line L8.

(S18) The LSI tester 8 compares the read counter value with the value (number of pulses) previously set in the frequency setting circuit 72.

(S20) When the measured interface circuit 20 / memory interface circuit 30 can receive a pulse of this frequency, the values match, so the LSI tester 8 indicates that the comparison result indicates a match. This measured IC 1 is determined to be a non-defective product. On the other hand, if the measured interface circuit 20 / memory interface circuit 30 cannot receive the pulse of this frequency, the counter clock signal is not generated. When the counter clock signal is not generated, the counter 5 does not count up. For this reason, the LSI tester 8 determines that the IC 1 to be measured is a defective product when the comparison result does not indicate coincidence.

Thus, since the pulse generator 70 is provided on the tester board of the general-purpose tester and the high frequency pulse is output, the AC coupling capacitor 3 can be passed at a high frequency. In addition, since the signal is controlled from the channel of the LSI tester 8, it is not necessary to consider the combination with the driver. In addition, when there is a circuit failure, it is understood that this is a problem of the receiver 2 itself. In addition, since there is no need to provide a loopback circuit and a determination circuit for the conventional test in the IC1, the number of elements of the IC1 can be reduced.

FIG. 5 is a process flow diagram of the second embodiment of the measurement process of the present invention, which is executed by the LSI tester 8 of FIG. In this example, a measurement process for measuring the frequency limit performance of an IC is shown. In FIG. 5, the same components as those shown in FIG. 4 are indicated by the same symbols.

(S30) The LSI tester 8 executes S10 to S18 of FIG. That is, a general control signal is sent from the LSI tester 8 to the IC 1 through the signal line L9, and all counters in the IC 1 are reset (S10). The frequency and the number of pulses of the frequency setting circuit 72 are set by the control signal from the LSI tester 8 through the signal line L7 (S12). The LSI tester 8 outputs the signal via the signal line L6.
Enable A is asserted, the pulse generator 70 is operated, and pulses B and C having a set frequency are generated from the pulse generator 70 and output to the signal lines L10 and L11. The counter 5 counts up the counter clock signal D (S14). The LSI tester 8 reads the value of the counter 5 through the signal line L8 (S16). The LSI tester 8 compares the read counter value with the value (number of pulses) previously set in the frequency setting circuit 72.

(S32) The LSI tester 8 determines whether the comparison result indicates a match.

(S34) When the comparison results match, the LSI tester 8 updates the frequency set in the frequency setting circuit 72 to a frequency one step higher. Then, the LSI tester 8 determines whether the updated frequency exceeds the upper limit frequency of measurement. If the updated frequency exceeds the upper limit frequency of measurement, the LSI tester 8 determines that the upper limit frequency is the limit frequency of the IC and stores this. On the other hand, if the updated frequency does not exceed the upper limit frequency for measurement, the LSI tester 8 returns to step S30 (step S10 in FIG. 4).

(S36) If the comparison result does not match, the LSI tester 8 determines that the frequency set one time before the current measurement is the limit frequency of the IC, and stores this.

Thus, since the pulse generator 70 is provided on the test board and the high frequency pulse can be distributed, it is possible to pass through the AC coupling capacitor 3 and to measure at a high frequency. Further, since the frequency can be made variable by using the pulse generator 70, it is possible to investigate the operation limit of the IC.

Furthermore, since the signal is controlled from the channel of the LSI tester 8, there is no need to consider the combination with the driver. In addition, when there is a circuit failure, it is understood that this is a problem of the receiver 2 itself. In this case, it is assumed that the operation of the test counter 5 has been confirmed by another function test. In addition, since there is no need to provide a loopback circuit and a determination circuit for the conventional test in the IC1, the number of elements of the IC1 can be reduced.

(Other embodiments)
In the above description, the interface circuit has been described with an example of one input buffer. However, the present invention can be similarly applied even when a plurality of input buffers are provided. In this case, the pulse generator 70 of the test board may be provided with an output switching circuit for a plurality of input buffers, and the measurement of the plurality of input buffers may be executed sequentially. If a plurality of input buffers are provided, the counter 5 may be shared.

1 Semiconductor integrated circuit (IC)
2 AC coupling input buffer 3 Capacitor (capacitance element)
4 Differential Amplifier 5 Counter 6 Synchronous Circuit 7 Test Board 8 LSI Tester 20 (22) Interface Circuit 30 Input Buffer 70 Pulse Generator 72 Frequency Setting Circuit

Claims

An AC coupling input buffer test method for testing a frequency characteristic of an AC coupling input buffer, the method comprising:
A step of inputting a pulse signal having a set frequency to the AC coupling input buffer from a pulse generator provided on a test board on which the semiconductor integrated device having the AC coupling input buffer is mounted;
Counting the output pulses of the AC coupling input buffer to which the pulse signal is input with a counter;
After the pulse generator inputs a set number of signals to the AC coupling input buffer, the tester reads the value of the counter;
The tester comprises a step of comparing the read counter value with the set number to determine a characteristic of the AC coupling input buffer at the frequency. How to test the input buffer.
The determination step further includes:
The tester compares the read counter value with the set number, and updates the frequency set in the pulse generator to a frequency higher by a predetermined number when the comparison result is good. When,
The tester sets the updated frequency in the pulse generator, and executes the input step, the counting step, the reading step, and the determining step;
When the tester compares the read counter value with the set number and the comparison result is not good, the frequency before update is set as the frequency characteristic of the AC coupling input buffer. The method for testing an AC coupling input buffer according to claim 1, further comprising the step of:
The AC coupling input buffer includes a pair of capacitive elements respectively connected to a pair of signal lines, and a differential amplifier connected to the pair of capacitive elements. A method for testing the AC coupling input buffer.
The method of testing an AC coupling input buffer according to claim 1, wherein the determining step includes a step of determining whether the AC coupling input buffer is good or bad from the comparison result.
The test method for an AC coupling input buffer according to claim 1, wherein the semiconductor integrated device includes the AC coupling input buffer and the counter.
The tester resetting the counter;
The tester sets the frequency and number of pulses in the pulse generator;
The test method for an AC coupling input buffer according to claim 1, wherein the tester further includes a step of instructing the pulse generator to start operation.
An AC coupling input buffer test system for testing a frequency characteristic of an AC coupling input buffer, comprising:
A test board on which a semiconductor integrated device having the AC coupling input buffer is mounted;
A pulse generator provided on the test board and for inputting a pulse signal having a set frequency to the AC coupling input buffer;
The value of a counter that counts output pulses of the AC coupling input buffer to which the pulse signal is input is read after the pulse generator inputs a set number of signals to the AC coupling input buffer, A tester for comparing the value of the read counter with the set number to determine the characteristics of the AC coupling input buffer at the frequency; system.
The tester further comprises:
The read counter value is compared with the set number, and if the comparison result is good, the frequency set in the pulse generator is updated to a predetermined higher frequency, and the updated frequency Is set in the pulse generator, and the value of the read counter is compared with the set number, and if the comparison result is not good, the frequency before the update is determined as the AC coupling. 8. The AC coupling input buffer test system according to claim 7, wherein the frequency characteristic of the input buffer is determined.
9. The AC coupling input buffer includes a pair of capacitive elements respectively connected to a pair of signal lines, and a differential amplifier connected to the pair of capacitive elements. AC coupling input buffer test system.
The test system for an AC coupling input buffer according to claim 7, wherein the tester determines whether the AC coupling input buffer is good or bad from the comparison result.
The test system for an AC coupling input buffer according to claim 7, wherein the semiconductor integrated device includes the AC coupling input buffer and the counter.
8. The AC coupling input according to claim 7, wherein the tester resets the counter, sets the frequency and the number of pulses to the pulse generator, and instructs the pulse generator to start operation. Buffer test system.
An AC coupling input buffer;
When a pulse signal having a set frequency is input from the pulse generator provided on the test board to the AC coupling input buffer, the output pulses of the AC coupling input buffer to which the pulse signal is input are counted. Counter to
A semiconductor integrated circuit comprising: a terminal for reading the value of the counter from a tester.
The semiconductor integrated circuit according to claim 13, wherein the AC coupling input buffer includes a pair of capacitive elements respectively connected to a pair of signal lines, and a differential amplifier connected to the pair of capacitive elements. .
An interface circuit having the AC coupling input buffer and the counter;
The semiconductor integrated circuit according to claim 13, further comprising: a functional circuit that is connected to an external device via the interface circuit and transmits / receives data.