WO2010055706A1

WO2010055706A1 - Data processing device, data processing method, and program

Info

Publication number: WO2010055706A1
Application number: PCT/JP2009/059356
Authority: WO
Inventors: 賢悟西野
Original assignee: 日本電気株式会社
Priority date: 2008-11-14
Filing date: 2009-05-21
Publication date: 2010-05-20
Also published as: JPWO2010055706A1

Abstract

A data processing device which executes a calculation process based on a state includes: a control unit having a first state management unit for controlling a state transition; a second state management unit for controlling a state transition of a smaller scale than the state transition controlled by the first state management unit; and an auxiliary control unit which selects control of a state transition using the second state management unit or control of a state transition using only the first state management unit without using the second state management unit.

Description

Data processing apparatus, data processing method, and program

The present invention relates to a data processing apparatus that executes arithmetic processing according to a state.

Information processing apparatuses have a wider range of use, and are required to have more advanced arithmetic processing or the ability to process a large amount of data at high speed, such as images and moving images. In order to satisfy these requirements, a DSP (Digital Signal Processor) or ASIC (Application Specific Integrated Circuit) that performs specific operations and processing separately from the host processor is provided. A configuration is known in which the processing capability as an information processing apparatus is improved by reducing the processing load.

However, recent information processing apparatuses require compression / decompression processing and arithmetic processing of various standards for multimedia data such as images, moving images, sounds, music, etc., and via a network such as the Internet. It is necessary to use various protocols for communication processing for transmitting and receiving various data. Furthermore, since the safety of information transmitted and received on the network is a problem, the information processing apparatus also requires an encryption process for information security and a decryption process for decrypting the information. Therefore, if a large number of DSPs, ASICs, and the like are provided in accordance with these processes, the circuit scale and cost of the information processing apparatus become enormous.

Therefore, the information processing device is equipped with a data processing device consisting of a reconfigurable device such as an FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device) or DRP (Dynamically Reconfigurable Processor), and a program for the data processing device as required. There is a configuration that improves the throughput of the information processing apparatus by rewriting and executing the processing, and can cope with various processing requests while reducing the cost.

The reconfigurable device includes an internal memory for storing a program (object code) therein, and loads the object code stored in the external memory into the internal memory under the control of the CPU or the like, and internally stores it according to the loaded object code. A circuit is configured and processing is performed on the input data by the circuit.

The details of DRP are described in, for example, Patent Documents 1 to 6 and Non-Patent Document 1. The DRP is configured to include a calculation unit that executes calculation processing and a control unit that controls the operation of the calculation unit. The arithmetic unit includes a plurality of small arithmetic units and an interconnection unit that switches connection between them, and implements various processes by switching instruction codes for the arithmetic units and the interconnection unit.

By the way, there are various types of processing executed by DRP. For example, other data may be read from the memory during the processing and the processing may be continued using the data. DRP has an internal memory, but its storage capacity is often limited. Therefore, in the DRP processing, when referring to a table or data that requires a large storage capacity during the processing, it is necessary to access the memory in which the data is stored. The processing method for this is described in Patent Document 7 and Patent Document 8, for example.

In the data processing apparatus composed of the above-described reconstruction device or the like, processing is executed based on an object code composed of one or more pieces of configuration information generated according to data to be processed. In this case, the data processing apparatus adopts a method of executing the process while directly specifying the position where the configuration information is stored.

Here, the configuration information is an operation command for the arithmetic unit at a certain point in time, information indicating the connection relationship of the arithmetic units by the interconnection unit, and information indicating a relationship between the event signal and the corresponding configuration information to be selected next. The information necessary for constructing a virtual circuit in the data processing apparatus. The object code indicates a collection of configuration information necessary for executing a desired process.

In such a method, when a plurality of object codes are mounted on the data processing apparatus, if the storage positions of the configuration information included in each object code overlap, it is necessary to re-synthesize the object code so that they do not overlap.

If the number of configuration information that can be held by the data processing device exceeds the number of pieces of object code or large-scale object code installed in the data processing device, the data processing device stops the operation and holds the object It is necessary to execute a series of processes such as code replacement and restart. For this operation, an external processing device such as an MPU is required. In that case, in the conventional data processing apparatus, since the configuration information can be mounted only at the place determined at the time of synthesizing the object code, even if the configuration information is composed of the codes of the same function, It is necessary to prepare multiple pieces of configuration information consisting of codes. In addition, since the configuration information cannot be shared, the data processing apparatus has a problem that processing is slowed down due to unnecessary processing such as holding a plurality of the same configuration information or rewriting the same configuration information again.

In order to solve such a problem, the present applicant has already proposed a data processing apparatus that eliminates the restriction of the storage destination of the configuration information and enables the sharing of the configuration information (Japanese Patent Application No. 2006-103987: Hereinafter referred to as the prior application invention).

In the prior invention, in addition to the control unit, an auxiliary control unit that controls state transitions within a predetermined group having a smaller scale than the state transitions controlled by the control unit is provided. The auxiliary control unit controls the state transition in each group. And in such a configuration in which the control structure is hierarchized, the auxiliary control unit can control the state transition at a higher speed than the control unit, and as a result, it is possible to perform a higher speed process than the conventional data processing device. Yes.

However, when an object code is actually created from an application and the operation of the data processing apparatus based on the object code is verified, there are also applications in which state transition is often controlled by a control unit.

In this case, since the opportunity for switching the state transition control source from the auxiliary control unit to the control unit increases and the time required for the switching also increases, the processing time of the entire data processing apparatus is longer than the configuration without the auxiliary control unit. It may become. That is, in a data processing device with a hierarchized control structure, the processing time may be longer than a data processing device with a non-hierarchical control structure, depending on the application to be processed.

JP 2000-138579 A JP 2000-2224025 A JP 2000-232354 A JP 2000-232162 A Japanese Patent Laid-Open No. 2003-076668 JP 2003-099409 A JP 2005-222141 A JP 2005-222142 A

Therefore, an object of the present invention is to provide a data processing apparatus that can reduce the time required for processing.

In order to achieve the above object, a data processing apparatus of the present invention is a data processing apparatus that executes arithmetic processing according to a state,
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
Have

On the other hand, the data processing method of the present invention includes a control unit including a first state management unit that controls state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that can select control of state transition using only the first state management unit without using the state management unit of
A data processing method for generating an object code to be executed by a data processing apparatus having:
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Generating control configuration selection information for designating whether or not to use the second state management unit with better processing performance;
In this method, the control configuration selection information is added to the generated object code.

Further, the program of the present invention includes a control unit including a first state management unit that controls state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
A program for causing a computer to generate object code that causes a data processing apparatus to execute a desired process,
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Generating control configuration selection information for designating whether or not to use the second state management unit with better processing performance;
This is for causing the computer to execute processing for adding the control configuration selection information to the generated object code.

FIG. 1 is a block diagram illustrating the configuration of the data processing apparatus according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration example of an object code generation apparatus for generating an object code used in the data processing apparatus illustrated in FIG. FIG. 3 is a block diagram showing another configuration example of the object code generation device shown in FIG. FIG. 4 is a block diagram illustrating a configuration of the data processing apparatus according to the second embodiment. FIG. 5 is a block diagram showing a configuration example of an object code generation device for generating an object code used in the data processing device shown in FIG. FIG. 6 is a block diagram illustrating a configuration of a data processing device according to the third embodiment. FIG. 7 is a block diagram showing a configuration example of an object code generation device for generating an object code used in the data processing device shown in FIG. FIG. 8 is a block diagram showing the configuration of the data processing apparatus of the first embodiment. FIG. 9 is a schematic diagram showing an example of a state transition table used in the data processing apparatus shown in FIG. FIG. 10A is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 8. FIG. 10B is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing device illustrated in FIG. 8. FIG. 10C is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 8. FIG. 11 is a graph illustrating the effect of the data processing apparatus of the first embodiment. FIG. 12 is a block diagram showing the configuration of the data processing apparatus of the second embodiment. FIG. 13A is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 12. FIG. 13B is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 12. FIG. 13C is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 12. FIG. 14 is a block diagram showing the configuration of the data processing apparatus of the third embodiment. FIG. 15A is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 14. FIG. 15B is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 14. FIG. 15C is a schematic diagram illustrating an example of a processing path used for calculation of processing performance of the data processing apparatus illustrated in FIG. 14.

Next, the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the data processing apparatus according to the first embodiment.

As shown in FIG. 1, the data processing apparatus of the present embodiment has a configuration including a control unit 1 and a calculation unit 2.

The control unit 1 includes a state management unit 11, a configuration number conversion unit 12, a configuration information storage unit 13, and a configuration rewriting unit 15. The computing unit 2 includes an auxiliary control unit 23, a plurality of computing units 21, and an interconnection unit 22 for connecting the plurality of computing units 21.

The state management unit 11 prepares a state transition table prepared in advance based on a current operation state included in the configuration information, a candidate group of transition states (transition destination candidate group), and an event signal sent from the calculation unit 2. The logical number of the configuration information to be used in the next operation state is determined, and the logical number is notified to the configuration number conversion unit 12.

The logical number is information indicating the interrelationship of each configuration information included in the object code. The actual position of the configuration information stored in the configuration information storage unit 13 is specified by a real number.

The configuration number conversion unit 12 converts a logical number of configuration information notified from the state management unit 11 into a real number using a conversion table provided in advance, and the real number is converted into a state management unit 11 and an auxiliary control unit of the calculation unit 2. 23 to notify each.

The configuration rewriting unit 15 writes the configuration information in the configuration information storage unit 13, writes the state transition table in the state management unit 11, and writes the conversion table in the configuration number conversion unit 12 when the data processing apparatus is initially operated. The configuration rewriting unit 15 also writes the state transition table in the state management unit 231 provided in the auxiliary control unit 23 described later when the data processing apparatus is initially operated.

When the configuration information rewriting request is issued from the configuration number converting unit 12, the configuration information storage unit 13 rewrites the currently unnecessary configuration information to the configuration information specified at the time of the rewriting request. At this time, for the selection of unnecessary configuration information, a known method such as the Least Recently Used (LRU) method may be used. When the configuration rewriting unit 15 rewrites the configuration information stored in the configuration information storage unit 13, the configuration rewriting unit 15 updates the conversion table that is included in the configuration number conversion unit 12 and includes conversion information used for conversion processing from a logical number to a real number. .

The configuration rewriting unit 15 basically rewrites only one requested configuration information in response to the rewrite request from the configuration number converting unit 12, but also rewrites the configuration information used thereafter with the configuration information. Also good.

The computing unit 21 performs arithmetic processing according to the designated configuration information read from the configuration information storage unit 13 for each of a plurality of operating states that sequentially transition.

The interconnection unit 22 switches the connection relationship of the plurality of computing units 21 based on the configuration information read from the configuration information storage unit 13.

The auxiliary control unit 23 includes a state management unit 231 that controls state transitions in a predetermined group whose scale is smaller than the state transitions managed by the state management unit 11 of the control unit 1. When the event signal indicating the state transition exceeding the range that can be controlled by the state management unit 231 is notified from the computing unit 21, the auxiliary control unit 23 notifies the state management unit 11 of the control unit 1 of the event signal.

A clock having a predetermined frequency generated by a clock generator (not shown) is supplied to the control unit 1 and the calculation unit 2, and the control unit 1 and the calculation unit 2 operate using the clock.

Note that each component of the data processing apparatus shown in FIG. 1 does not have to be provided independently for each functional unit shown in FIG. 1, and any component may be included in another component, and any These components may be composed of a plurality of parts. For example, the configuration information storage unit 13 may be configured by a memory (not illustrated) provided in each of the computing unit 21 and the interconnection unit 22. Further, it is not necessary that all the components of the data processing apparatus shown in FIG. 1 are provided in one apparatus. For example, the configuration rewriting unit 15 may be realized by another device provided outside or an MPU.

As described above, the configuration information indicates a calculation command for the arithmetic unit at a certain point in time, information indicating the connection relationship between the arithmetic units by the interconnection unit, and a relationship between the event signal and the corresponding configuration information to be selected next. This is information necessary for constructing a virtual circuit in the data processing apparatus, including information and the like. The object code indicates a collection of configuration information necessary for executing a desired process.

The arithmetic unit 21 may be configured to include a so-called arithmetic arithmetic unit (ALU) or a combination of a plurality of types of arithmetic units and storage elements such as registers.

Note that the state management unit 11 may have any configuration as long as it can determine the next state to be transitioned based on the current state and the event signal. For example, the state management unit 11 may be configured to include a correspondence table indicating transition relationships between the states.

Further, the configuration number conversion unit 12 may have any configuration as long as the logical number of the configuration information designated by the state management unit 11 can be converted into a real number. For example, the configuration number conversion unit 12 includes a correspondence table showing a correspondence relationship between logical numbers and real numbers, or a function for converting logical numbers to real numbers based on relative values of logical numbers and real numbers. A configuration provided is conceivable. Here, the correspondence table, relative values, and the like necessary for the process for converting the logical number to the real number executed by the configuration number conversion unit 12 are collectively referred to as “conversion information”.

The auxiliary control unit 23 according to the present embodiment is either state transition control using the state management unit 231 or state transition control using only the state management unit 11 of the control unit 1 without using the state management unit 231. Select one. In such selection processing by the auxiliary control unit 23, for example, at the time of synthesizing the object code, control configuration selection information for designating any one of these controls is added to the object code. What is necessary is just to select whether the control part 23 uses the state management part 231 according to this control structure selection information.

FIG. 2 is a block diagram showing a configuration example of an object code generation device for generating an object code used in the data processing device shown in FIG.

As shown in FIG. 2, the object code generation device includes a synthesis tool 50 that generates an object code, the control configuration selection information added to the object code generated by the synthesis tool 50, and a data processing device that uses the object code. And a performance estimation tool 60 for estimating the processing performance.

The object code generation device can be realized by an LSI or DSP composed of a logic circuit or the like, or an information processing device (computer) that operates as the synthesis tool 50 and the performance estimation tool 60 according to a predetermined program.

For example, as illustrated in FIG. 3, the information processing device includes a processing device 70 that executes predetermined processing according to a program, an input device 80 for inputting commands and information to the processing device 70, and the processing device 70. And an output device 90 for monitoring the processing result.

The processing device 70 stores a CPU 71, a main storage device 72 that temporarily stores information necessary for the processing of the CPU 71, and a program for causing the CPU 71 to execute processing as the synthesis tool 50 and the performance estimation tool 60. A data storage device 74 for storing a recording medium 73, an operation description of an application for which an object code is to be created, constraint information to be described later, or a composited object code, a main storage device 72, a recording medium 73, and a data storage device 74, a memory control interface unit 75 that controls data transfer with 74, and an I / O interface unit 76 that is an interface device between the input device 80 and the output device 90, and these are connected via a bus 78 It is. The data storage device 74 does not need to be in the processing device 70 and may be provided independently from the processing device 70.

The processing device 70 realizes the function of the synthesis tool 50 and the function of the performance estimation tool 60 described later according to the program recorded in the recording medium 73. The recording medium 73 may be a magnetic disk, a semiconductor memory, an optical disk, or other recording medium.

The synthesizing tool 50 generates an object code including at least one piece of configuration information based on the behavioral description and the constraint information when the behavioral description and the constraint information of the application are input. The constraint information is information for designating constraint conditions during the operation of the data processing apparatus based on object codes, such as restrictions on resources to be used and priority performance.

The performance estimation tool 60 uses the object code, application operation additional information, and hardware information created by the synthesis tool 50 to estimate the performance during operation of the data processing apparatus by a known operation simulation method or branch probability calculation method. Then, based on the estimation result, it is determined whether to use the state management unit 231 of the auxiliary control unit 23, and control configuration selection information indicating the determination result is added to the object code.

The application operation additional information is information for improving the estimation accuracy by the performance estimation tool 60. When the processing performance of the data processing apparatus is estimated by the operation simulation method, for example, input data when an application is actually operated may be used as the application operation additional information. Further, when the processing performance of the data processing apparatus is estimated by the branch probability calculation method, for example, a value indicating the occurrence probability of a state transition requiring control of the state management unit 11 may be used as the application operation additional information.

The programs for realizing the synthesis tool 50 and the performance estimation tool 60 may be configured by a plurality of programs, respectively, or may be configured to realize the synthesis tool 50 and the performance estimation tool 60 by one program. .

According to the data processing apparatus of this embodiment, control configuration selection information is added to the object code, and whether to use the state management unit 231 of the auxiliary control unit 23 according to the control configuration selection information during operation is selected. By doing so, the process according to the object code can be executed with a control structure that can obtain better processing performance. Therefore, the time required for the processing of the data processing device can be reduced.

(Second embodiment)
FIG. 4 is a block diagram showing the configuration of the data processing apparatus according to the second embodiment.

In the data processing apparatus of the second embodiment, control configuration selection information for specifying whether or not to use the state management unit 231 of the auxiliary control unit 23 is added to each configuration information stored in the configuration information storage unit 13. Is done. The data processing apparatus according to the second embodiment includes two

clock generators

51 and 52, and supplies a clock to be supplied to the control unit 1 and the calculation unit 2 based on control configuration selection information added to the object code. select.

As shown in FIG. 4, the data processing apparatus according to the second embodiment has a configuration including a control unit 1 and a calculation unit 2 as in the first embodiment.

As in the first embodiment, the auxiliary control unit 23 of the present embodiment controls state transition using the state management unit 231 or only the state management unit 11 of the control unit 1 that does not use the state management unit 231. Select one of the state transition controls using. However, in the present embodiment, when synthesizing the object code, control configuration selection information for designating any one of these controls is added for each configuration information, and during operation by the data processing apparatus, the auxiliary control unit 23 Whether to use the state management unit 231 is selected according to the control configuration selection information for each configuration information.

The

clock generators

51 and 52 supply clocks having required frequencies to the control unit 1 and the calculation unit 2, respectively. The clock generated by the clock generator 51 is used when controlling the state transition using only the state management unit 11 of the control unit 1 without using the state management unit 231 of the auxiliary control unit 23. On the other hand, the clock generated by the clock generator 52 is used when controlling the state transition using the state management unit 231 of the auxiliary control unit 23.

The control unit 1 selects one of the two clocks generated by the

clock generators

51 and 52 based on the control configuration selection information added for each configuration information. The selected clock is supplied to the control unit 1 and the calculation unit 2 until the clock is selected based on the control configuration selection information added to the next transition configuration information.

In the present embodiment, an example is shown in which one of the two clocks is selected based on the control configuration selection information. However, any one of the two clocks along with the control configuration selection information is provided for each configuration information. The operating frequency information for designating one of them may be added, and the control unit 1 may select one of the two clocks based on the operating frequency information.

Generally, the state management unit 231 of the auxiliary control unit 23 can operate (control of state transition) with a clock having a higher frequency than the state management unit 11 of the control unit 1. In the first embodiment, a clock having a fixed frequency corresponding to the state transition by the state management unit 231 of the auxiliary control unit 23 is supplied to the data processing device, and the state management unit 11 of the control unit 1 performs two cycles of the clock. Alternatively, state transition is controlled by taking three cycles. For this reason, in the data processing apparatus according to the first embodiment, the delay of the state transition due to the control of the state management unit 11 of the control unit 1 becomes relatively large.

Therefore, in the second embodiment, the clock generator 51 generates a clock having a frequency lower than that of the clock generator 52, and the clock generated by the clock generator 51 is used only by the state management unit 11 of the control unit 1. Used when controlling state transitions.

At this time, if the frequency of the clock generated by the clock generator 51 is set so that the state management unit 11 of the control unit 1 can control the state transition in one cycle of the clock, the control of the state management unit 11 of the control unit 1 It is possible to reduce the delay of state transition due to.

Since other configurations and operations of the data processing apparatus are the same as those of the data processing apparatus shown in the first embodiment, the description thereof is omitted.

FIG. 5 is a block diagram showing a configuration example of an object code generation apparatus for generating an object code used in the data processing apparatus shown in FIG.

As illustrated in FIG. 5, the object code generation device according to the second embodiment includes a synthesis tool 50 that generates an object code, and the control configuration selection information in each configuration information of the object code generated by the synthesis tool 50. And a performance estimation tool 60 for estimating the processing performance of the data processing apparatus using the object code.

The synthesizing tool 50 generates an object code including at least one piece of configuration information based on the behavioral description and the constraint information when the behavioral description and the constraint information of the application are input.

The performance estimation tool 60 of the present embodiment uses the object code, application operation additional information, and hardware information created by the synthesis tool 50, and uses the known operation simulation method or branch probability calculation method when the data processing apparatus operates. Estimate performance. Then, based on the estimation result, it is determined whether to use the state management unit 231 of the auxiliary control unit 23, and control configuration selection information (and operating frequency information corresponding to the control structure) indicating the determination result is determined for each configuration information. Append to

Other configurations and operations of the object code generation device are the same as those of the object code generation device and the information processing device described in the first embodiment, and thus description thereof is omitted.

According to the data processing device of this embodiment, control configuration selection information is added for each configuration information, and the state management unit 231 of the auxiliary control unit 23 according to the control configuration selection information during operation of the data processing device by object code. By selecting whether or not to use and selecting a clock having a frequency according to the control structure, it is possible to execute processing at an operating frequency more optimal than that of the data processing apparatus of the first embodiment. Therefore, the time required for the processing of the data processing device can be reduced.

(Third embodiment)
FIG. 6 is a block diagram showing the configuration of the data processing apparatus according to the third embodiment.

In the data processing device of the third embodiment, the state management unit 231 of the auxiliary control unit 23 is provided for each piece of configuration information stored in the configuration information storage unit 13 as in the data processing device of the second embodiment. Control configuration selection information for specifying whether to use is added. The data processing apparatus according to the third embodiment includes the variable clock generator 7 that can change the frequency of the clock generated according to an instruction from the outside, and is added to each piece of configuration information. The frequency of the clock supplied to the control unit 1 and the calculation unit 2 is changed according to the operating frequency information specifying the frequency.

As shown in FIG. 6, the data processing apparatus according to the third embodiment has a configuration including a control unit 1 and a calculation unit 2 as in the first and second embodiments.

As in the first and second embodiments, the auxiliary control unit 23 according to this embodiment controls state transition using the state management unit 231 or does not use the state management unit 231. One of the state transition controls using only the unit 11 is selected. In the third embodiment, as in the second embodiment, control composition selection information for designating any one of these controls is added for each piece of composition information when synthesizing the object code. During operation by the apparatus, the auxiliary control unit 23 selects whether to use the state management unit 231 according to the control configuration selection information for each configuration information.

The variable clock generator 7 generates a clock having a required frequency to be supplied to the control unit 1 and the calculation unit 2, respectively. In the third embodiment, the frequency of the clock generated by the variable clock generator 7 is changed according to the operating frequency information added for each piece of configuration information. In general, the path length (calculation path) of a virtual circuit built in the calculation unit 2 according to the configuration information differs for each configuration information, and therefore the delay amount is not always uniform. Therefore, even if the control configuration selection information is the same configuration information, the operating frequency may be different.

In the data processing apparatus according to the present embodiment, the state transition control using the state management unit 231 or the state transition control using only the state management unit 11 of the control unit 1 without using the state management unit 231 is optimal. The operating frequency can be optimally set according to the path length of the virtual circuit constructed in the arithmetic unit 2 according to the configuration information, the delay amount thereof, etc. The time required can be reduced.

FIG. 7 is a block diagram showing a configuration example of an object code generation device for generating an object code used in the data processing device shown in FIG.

As illustrated in FIG. 7, the object code generation device according to the third embodiment includes the synthesis tool 50 that generates an object code, and the control configuration selection information in each configuration information of the object code generated by the synthesis tool 50. And a performance estimation tool 60 for estimating the processing performance of the data processing apparatus using the object code.

The performance estimation tool 60 of the present embodiment uses the object code, application operation additional information, and hardware information created by the synthesis tool 50, and uses the known operation simulation method or branch probability calculation method when the data processing apparatus operates. Estimate performance. Then, based on the estimation result, it is determined whether to use the state management unit 231 of the auxiliary control unit 23, and control configuration selection information indicating the determination result is added for each configuration information.

Further, in the control configuration selection information of the present embodiment, the operating frequency of the data processing device is changed according to whether or not the state management unit 231 of the auxiliary control unit 23 is used, and in the calculation unit 2 according to the configuration information. An optimum operating frequency is determined according to the path length of the virtual circuit to be constructed, its delay amount, etc., and operating frequency information indicating the frequency of the clock used in the data processing apparatus is added.

Other configurations and operations of the object code generation apparatus are the same as those of the object code generation apparatus and the information processing apparatus shown in the first embodiment and the second embodiment, and thus description thereof is omitted.

According to the data processing device of this embodiment, control configuration selection information is added for each configuration information, and the state management unit 231 of the auxiliary control unit 23 according to the control configuration selection information during operation of the data processing device by object code. Is used, and the frequency of the clock to be used is optimally changed in accordance with the operating frequency information, so that processing can be performed at a more optimal operating frequency than the data processing apparatus of the second embodiment. Can be executed. Therefore, the time required for the processing of the data processing device can be reduced.

Next, an embodiment of the data processing apparatus of the present invention will be described with reference to the drawings.

(First embodiment)
The first embodiment is an example in which the above-described first embodiment is applied to the data processing apparatus of the prior invention (Japanese Patent Application No. 2006-103987) shown in the background art.

FIG. 8 is a block diagram showing the configuration of an embodiment of the data processing apparatus of the present invention.

The data processing apparatus of the present embodiment is an example in which the data processing apparatus shown in FIG. 1 is realized by the above-described DRP (Dynamically Reconfigurable Processor).

As shown in FIG. 8, the data processing apparatus (DRP) of the present embodiment includes a state transition management unit (STC) 3 that becomes the control unit 1 shown in FIG. 1 and an auxiliary that becomes the calculation unit 2 shown in FIG. In this configuration, a calculation unit 4 including a control unit (MSTC) 43 and a plurality of processor elements (PE) 41 and an external memory 6 are provided. A clock having a predetermined frequency generated by a clock generator (not shown) is supplied to the state transition management unit (STC) 3, the calculation unit 4, and the external memory 6.

The state transition management unit (STC) 3 includes a state management unit 31, a configuration number conversion unit 32, a configuration rewrite unit 33, and a configuration designation register 34.

The state management unit 31 corresponds to the state management unit 11 shown in FIG. 1, the configuration number conversion unit 32 corresponds to the configuration number conversion unit 12 shown in FIG. 1, and the configuration rewriting unit 33 uses the configuration rewriting unit shown in FIG. It corresponds to the part 15. The configuration designation register 34 holds control configuration selection information that is information for designating whether or not to use the state management unit 431 corresponding to the state management unit 231 shown in FIG. 1 provided in the auxiliary control unit (MSTC) 43. To do.

The processor element (PE) 41 includes a register file (RFU), an ALU, a data processing arithmetic unit (DMU), a switch (SW), and a configuration information memory, and via the switch (SW) and wiring connected to the switch. Connected to each other.

In the data processing apparatus shown in FIG. 8, the plurality of processor elements 41 included in the calculation unit 4 are the calculator 21 shown in FIG. Note that the arithmetic unit is not limited to the processor element 41 and may be realized by a logic array, for example.

The auxiliary control unit (MSTC) 43 includes a state management unit 431 corresponding to the state management unit 231 illustrated in FIG. 1, and the state management unit 431 includes a plurality of internal state transitions within a logical number (the above group). Manage state transitions.

Further, the auxiliary control unit (MSTC) 43 uses the real number register 432 that holds the real number of the current configuration information, the internal state number register 433 that holds the internal state number, and the state management unit 431. A configuration designation register 434 that holds control configuration selection information, which is information for designating, and an event signal register 435 that holds an event signal that designates a large-scale state transition that cannot be controlled by the state management unit 431. The event signal register 435 temporarily holds an event signal that designates a large-scale state transition that cannot be controlled by the state management unit 431 before being sent to the state management unit 31.

The auxiliary control unit 43 determines the operation of various selectors used when selecting whether or not to use the state management unit 431 according to the value stored in the configuration designation register 434.

Similarly, the state transition management unit (STC) 3 determines the operation of various selectors used for selecting whether or not to use the state management unit 431 according to the value stored in the configuration designation register 34.

The state transition management unit (STC) 3 is sent from the state management unit 31 whether or not to cause the configuration number conversion unit 32 to send a stop signal for the group of processor elements 41 according to the value stored in the configuration designation register 34. Whether the internal state number is always written to the internal state number register 433 or whether the internal state number is written to the internal state number register 433 synchronously when the real number is written from the configuration number conversion unit 32 to the real number register 432 select.

In this embodiment, a memory (hereinafter referred to as a configuration information memory) included in each processor element 41 and the state transition management unit (STC) 3 serves as the configuration information storage unit 13. That is, the configuration information storage unit of the present embodiment is configured to be divided into memories provided in each processor element 41 and the state transition management unit (STC) 3.

Next, the operation of the data processing apparatus of this embodiment will be described.

In the following description, it is assumed that configuration information of logical numbers “0” and “1” is held in the instruction memory provided in the data processing device (DRP). At this time, an example of the state transition table provided in the state management unit 31 is shown in FIG. Here, the configuration information with the logical number “0” is written in the configuration information memory with the real number “0”, and the configuration information with the logical number “1” is written in the configuration information memory with the real number “1”. To do.

First, the operation of the data processing apparatus when using the state management unit 431 of the auxiliary control unit 43 will be described. Here, it is assumed that the state is changed according to the state transition table shown in FIG. 9, and the processing is started from the internal state number “1” (state 0-1) included in the configuration information of the logical number “0”. .

In the processing of the first cycle, the data processing apparatus first reads out the real number corresponding to the configuration information of the logical number “0” from the real number register 432 by the auxiliary control unit 43 and the internal state number “433” from the internal state number register 433. 1 ”is read out.

The auxiliary control unit 43 reads the configuration information from the configuration information memory using the real number read from the real number register 432 and the internal state number “1”, and notifies each processor element 41 of the calculation unit 4. Each processor element 41 determines its operation and switch connection relationship according to the configuration information notified from the auxiliary control unit 43. As a result, each processor element 41 executes a required calculation.

When the calculation result is notified as an event signal from the processor element 41, the state management unit 431 proceeds to control of the next state transition corresponding to the event signal based on the state transition table. Here, since the transition to the next state can be controlled by the state management unit 431, the state management unit 431 writes the next internal state number “2” in the internal state number register 433. At this stage, the first cycle process is completed.

FIG. 10A is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 10A, the processing path when the state management unit 431 controls the state transition is indicated by a thick arrow. That is, the thick arrow in FIG. 10A indicates that the internal state number register 433 is the starting point of processing, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the signal determines the next internal state, and shows the processing path until the internal state number indicating the internal state is written in the internal state number register 433.

In the processing of the second cycle, the data processing apparatus reads the real number corresponding to the configuration information of the logical number “0” from the real number register 432 by the auxiliary control unit 43 and the internal state number “2” from the internal state number register 433. "Is read out.

The auxiliary control unit 43 reads the configuration information from the configuration information memory using the real number read from the real number register 432 and the internal state number “2”, and notifies each processor element 41 of the calculation unit 4. Each processor element 41 determines its operation and switch connection relationship according to the configuration information notified from the auxiliary control unit 43. As a result, each processor element 41 executes a required calculation.

When the calculation result is notified as an event signal from the processor element 41, the state management unit 431 proceeds to control of the next state transition corresponding to the event signal based on the state transition table. Here, the transition to the next state cannot be controlled by the state management unit 431 because the logical number changes. Therefore, the state management unit 431 issues a WE cancel signal for stopping the operation of the processor elements 41 group. When the processor element 41 receives the WE cancel signal, it does not accept the update of the register contents. Further, when the processor element 41 receives the WE cancel signal, the data input operation from the external port is also stopped.

The auxiliary control unit 43 issues a WE cancel signal and stores the event signal in the event signal register 435 at the same time. At this stage, the process in the second cycle is completed.

In the process of the third cycle, the data processing device reads the event signal stored in the event signal register 435 by the state management unit 31 and based on the event signal and the real number “0” notified from the configuration number conversion unit 32. The logical number “1” of the next transition state is determined according to the state transition table, and the configuration number conversion unit 32 is notified of the logical number “1”. In addition, the state management unit 31 uses the real number “0” notified from the configuration number conversion unit 32 and the received event signal to start an internal state number that starts in the next transition state (hereinafter referred to as a start internal state number). ) Determine "1".

When the logical number “1” is notified from the state management unit 31, the configuration number converting unit 32 converts the logical number “1” into a real number using the conversion table. Here, since the configuration information of the logical number “1” is held in the configuration information memory, the configuration number conversion unit 32 succeeds in conversion from the logical number to the real number. The configuration number conversion unit 32 stores the obtained real number “1” in the real number register 432 and the state management unit 31. At this time, the configuration number conversion unit 32 transmits the start internal state number to the internal state number register 433.

FIG. 10B is a diagram showing a processing path of two cycles by the data processing apparatus described above. In FIG. 10B, the processing path when the state management unit 431 controls the state transition in the second cycle and the processing path when the state management unit 31 controls the state transition in the third cycle are indicated by thick arrows. . That is, the thick arrow shown in FIG. 10B starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the event signal tries to determine the next internal state, and the state management unit 431 that cannot determine the next internal state stores the event signal received in the event signal register 435; When an event signal is issued to the state management unit 31 via the event signal register 435, the state management unit 31 determines the logical number and internal state number of the next state, and the logical number is executed by the configuration number conversion unit 32. The second process is performed until the conversion result is notified to the real number register 432 and the internal state number register 433. It is shown the door.

In the processing of the fourth cycle, the data processing apparatus reads the real number corresponding to the configuration information of the logical number “1” from the real number register 432 by the state management unit 31 and the internal state number “1” from the internal state number register 433. "Is read out. Then, the WE cancel signal issued by the state management unit 431 is stopped, and the processor elements 41 are restarted.

In the process of the third cycle, when the configuration information of the next logical number “1” is not held in the configuration information memory, the configuration number conversion unit 32 fails to convert the logical number to the real number. In this case, the configuration number conversion unit 32 requests the configuration rewriting unit 33 to write the configuration information of the logical number “1” in the configuration information memory.

The configuration rewriting unit 33 rewrites the configuration information that is unnecessary at the present time with the configuration information of the logical number “1” among the configuration information stored in the configuration information storage unit 13. Since it takes a long time to rewrite the configuration information, the configuration number conversion unit 32 waits for an end notification indicating completion of the rewriting from the configuration rewriting unit 33.

When the rewriting of the configuration information memory is completed and the update of the conversion table included in the configuration number conversion unit 32 is completed, the configuration rewriting unit 33 transmits an end notification to the configuration number conversion unit 32. The configuration number conversion unit 32 converts the logical number “1” into a real number using the updated conversion table, and stores it in the real number register 432.

Next, the operation of the data processing apparatus when the state management unit 431 of the auxiliary control unit 43 is not used will be described.

When the auxiliary control unit 43 is not used, the event signal indicating the calculation result of the processor element 41 is directly notified to the state management unit 31 without passing through the state management unit 431 and the event signal register 435.

When receiving the event signal from the processor element 41, the state management unit 31 determines the logical number of the next transition state based on the current real number and the received event signal according to the state transition table, and the configuration number conversion unit 32 The real number “1” corresponding to the logical number obtained from the above is transmitted to the real number register 432 and the state management unit 31, and the start internal state number is stored in the internal state number register 433. The state management unit 31 executes the processing so far in one cycle.

That is, when the state transitions according to the state transition table shown in FIG. 9, the transition from the state 0-1 to the state 0-2 and the transition from the state 0-2 to the state 1-1 are respectively performed by the state transition management unit ( Control with STC) 3.

FIG. 10C is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 10C, the processing path when the state management unit 31 controls the state transition without using the auxiliary control unit 43 is indicated by a thick arrow. That is, the thick arrow in FIG. 10C starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 31 that has received the signal determines the next internal state, the configuration number conversion unit 32 converts the logical number notified from the state management unit 31 into a real number, and the result is the real number register 432 and the internal state. The processing path until notification to the number register 433 is shown.

Here, when the configuration information of the next logical number “1” is not stored in the configuration information memory, the configuration number conversion unit 32 fails to convert the logical number to the real number.

In this case, the configuration number conversion unit 32 requests the configuration rewriting unit 33 to write the configuration information of the logical number “1” to the configuration information memory, and causes the processor element 41 group to stop the operation until the rewriting is completed. A WE cancel signal is issued. The rewriting operation of the configuration information is the same as that in the case of using the auxiliary control unit 43 described above, and thus the description thereof is omitted here.

When the configuration number conversion unit 32 receives an end notification indicating completion of rewriting of the configuration information from the configuration rewriting unit 33, the configuration number conversion unit 32 converts the logical number notified from the state management unit 31 into a real number, and converts the result into a real number register 432 and Notify the internal state number register 433 and stop issuing the WE cancel signal.

Next, a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 2 will be described with reference to the drawings.

As described above, the object code synthesizing apparatus generates an object code of an application to be operated on the data processing apparatus by the synthesizing tool 50. Further, the object code synthesis apparatus estimates the processing performance of the data processing apparatus when the auxiliary control unit 43 is used or not used by the performance estimation tool 60, and uses the auxiliary control unit 43 based on the estimation result. The superiority or inferiority of the processing performance when not used is determined, and control configuration selection information indicating whether or not to use the auxiliary control unit 43 is added to the object code generated by the synthesis tool 50 according to the determination result.

Here, in the judgment of superiority or inferiority of the processing performance when the auxiliary control unit 43 is used or not used, the operation time per cycle of the data processing device, the case where the auxiliary control unit 43 is used and the case where it is not used are used. Use the required number of cycles.

First, how to calculate the operating time per cycle will be described.

When using the auxiliary control unit 43, the processing time of one cycle as a reference is the time required for processing the route indicated by the thick arrow in FIG. 10A. Using this value, the number of cycles required for control by the state transition management unit 3 is determined.

Specifically, the processing time required for control by the state transition management unit 3 shown in FIG. 10B is divided by the time required for the processing of the route shown in FIG. 10A, and the value raised to an integer is obtained. calculate. Next, by subtracting “1” from this value, the number of overhead cycles, which is the number of cycles required for control by the state transition management unit 3, is calculated.

On the other hand, when the auxiliary control unit 43 is not used, the time of one cycle as a reference is set as the time required for processing the route indicated by the thick arrow in FIG. 10C.

Next, a performance estimation method using the performance estimation tool 60 shown in FIG. 2 will be described.

When the required number of cycles is calculated by the operation simulation method described above, the number of cycles when the auxiliary control unit 43 is not used is the value of the number of cycles of the operation simulation itself.

Further, the number of cycles when the auxiliary control unit 43 is used is the product of the number of state transitions generated by the control of the state transition management unit 3 and the overhead when the state transitions by the control of the state transition management unit 3. It is calculated by adding the number of cycles for motion simulation.

On the other hand, when the performance of the data processing device is estimated by the branch probability calculation method, the required number of cycles is expressed as a ratio. For example, if the number of cycles when the auxiliary control unit 43 is not used is “1”, the number of cycles when the auxiliary control unit 43 is used is the occurrence probability of the state transition requiring the control of the state transition management unit 3. Calculation is performed by adding “1” to the product of the overhead value when the state transition management unit 3 controls the state transition.

Finally, the operation time per cycle and the required number of cycles are multiplied to determine the time required for processing of the data processing apparatus corresponding to the application (hereinafter referred to as operation required time).

The performance estimation tool 60 calculates the required operation time when the auxiliary control unit 43 is used and when not used, and determines a control structure (whether the auxiliary control unit 43 is used) that shortens the required operation time. Then, control configuration selection information indicating whether to use the auxiliary control unit 43 based on the determination result is added to the object code.

Note that, when the processing performance is estimated more precisely, it is desirable that the performance estimation tool 60 also considers the time required for rewriting configuration information during operation. In this case, since the number of rewrite cycles does not change, the opportunity to select a control structure that uses the auxiliary control unit 43 having a higher operating frequency increases.

Next, a specific example of a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 2 will be described.

Here, the required operation time by the processing path shown in FIG. 10A is 10 ns, the required operation time by the processing path shown in FIG. 10B is 16 ns, and the required operation time by the processing path shown in FIG. 10C is 13 ns. Assume that the probability of occurrence of a state transition requiring control of the unit 3 is 0.2.

As described above, when changing from the state transition controlled by the auxiliary control unit 43 to the state transition controlled by the state transition management unit 3, two cycles are required for the state transition control, so the number of overhead cycles is “1”. Become.

Here, if the number of cycles when the auxiliary control unit 43 is not used is “1”, the number of cycles when the auxiliary control unit 43 is used is (1 + 0.2 × 1) = 1.2.

Further, the operation time required for the data processing apparatus is 13 × 1 = 13 ns when the auxiliary control unit 43 is not used, and 10 × 1.2 = 12 ns when the auxiliary control unit 43 is used. That is, the operation required time is shorter when the auxiliary control unit 43 is used. In this case, the performance estimation tool 60 gives control configuration selection information for specifying the use of the auxiliary control unit 43 to the object code.

On the other hand, when the occurrence probability of the state transition requiring the control of the state transition management unit 3 is 0.4, the operation required time when the auxiliary control unit 43 is used is 10 × 1.4 = 14 ns. In this case, the operation required time is shorter when the auxiliary control unit 43 is not used. Therefore, the performance estimation tool 60 gives control configuration selection information for designating non-use of the auxiliary control unit 43 to the object code.

FIG. 11 is a graph in which the horizontal axis indicates the probability of occurrence of a state transition that requires the control of the state transition management unit 3, and the vertical axis indicates the required operation time.

FIG. 11 shows the required operation time when the auxiliary control unit 43 is used and the required operation time when the auxiliary control unit 43 is not used, with respect to the occurrence probability of the state transition that requires the control of the state transition management unit 3. The relationship with the required operation time when optimally selecting whether or not to use the auxiliary control unit 43 (the present invention) is shown.

In the above-mentioned prior application, since the process is executed only when either the auxiliary control unit 43 is used or not, depending on the object code, the required operation time may be long. On the other hand, in this embodiment, the performance estimation tool 60 estimates in advance the processing performance when the auxiliary control unit 43 is used and when not used, determines an optimal control structure, and sets control configuration selection information indicating the determination result. Since it is given to the object code, the data processing apparatus can execute the process with a control structure having a shorter operation required time. Therefore, the time required for the processing of the data processing device can be reduced.

(Second embodiment)
The second embodiment is an example in which the second embodiment described above is applied to the data processing apparatus of the prior invention (Japanese Patent Application No. 2006-103987) shown in the background art.

FIG. 12 is a block diagram showing the configuration of the data processing apparatus of the second embodiment.

The data processing apparatus according to the second embodiment has a configuration specifying table 36 instead of the configuration specifying register 34 shown in the first embodiment. Further, the data processing apparatus of the second embodiment includes two

clock generators

51 and 52.

As shown in FIG. 12, the data processing apparatus (DRP) of the present embodiment includes a state transition management unit (STC) 3 that becomes the control unit 1 shown in FIG. 4 and an auxiliary that becomes the calculation unit 2 shown in FIG. This is a configuration having a calculation unit 4 including a control unit (MSTC) 43 and a plurality of processor elements (PE) 41, two

clock generators

51 and 52, and an external memory 6. Of the clocks generated by the two

clock generators

51 and 52, the state transition management unit (STC) 3, the arithmetic unit 4, and the external memory 6 are based on the control configuration selection information stored in the configuration designation table 36. One of the clocks selected by the state transition management unit (STC) 3 is supplied.

The state transition management unit (STC) 3 includes a state management unit 31, a configuration number conversion unit 32, a configuration rewriting unit 33, and a configuration designation table 36.

The state management unit 31 corresponds to the state management unit 11 shown in FIG. 4, the configuration number conversion unit 32 corresponds to the configuration number conversion unit 12 shown in FIG. 4, and the configuration rewriting unit 33 uses the configuration rewriting unit shown in FIG. It corresponds to the part 15.

The configuration designation table 36 includes, for each configuration information, control configuration selection information that designates whether or not the state management unit 431 corresponding to the state management unit 231 illustrated in FIG. 4 provided in the auxiliary control unit (MSTC) 43 is used. Hold.

In the data processing apparatus shown in FIG. 12, the plurality of processor elements 41 included in the calculation unit 4 are the calculator 21 shown in FIG. Note that the computing unit 21 is not limited to the processor element 41 and may be realized by, for example, a logic array.

The auxiliary control unit (MSTC) 43 includes a state management unit 431 corresponding to the state management unit 231 illustrated in FIG. 4. The state management unit 431 includes a plurality of internal state transitions within a logical number (the above group). Manage state transitions.

Further, the auxiliary control unit (MSTC) 43 uses the real number register 432 that holds the real number of the current configuration information, the internal state number register 433 that holds the internal state number, and the state management unit 431. A configuration designation register 434 that holds control configuration selection information, which is information for designating, and an event signal register 435 that holds an event signal that designates a large-scale state transition that cannot be controlled by the state management unit 431. In the event signal register 435, an event signal that designates a large-scale state transition that cannot be controlled by the state management unit 431 is temporarily held before being sent to the state management unit 31.

The state transition management unit (STC) 3 reads the value (control configuration selection information) stored in the memory area of the configuration designation table 36 corresponding to the real number of the configuration information to be used, and based on the read value, the state transition management unit (STC) 3 The operation of various selectors used for selecting whether to use the management unit 431 is determined. At this time, the state transition management unit (STC) 3 stores the value read from the configuration designation table 36 in the configuration designation register 434.

The clock generator 51 generates a clock used in the data processing device when the control structure does not use the state management unit 431. On the other hand, the clock generator 52 generates a clock to be used in the data processing device when the control structure uses the state management unit 431.

The state transition management unit (STC) 3 selects a clock generated by the clock generator 51 or the clock generator 52 according to the value stored in the configuration designation table 36.

Further, the state transition management unit (STC) 3 is sent from the state management unit 31 whether or not to cause the configuration number conversion unit 32 to send a stop signal for the processor element 41 group according to the value stored in the configuration designation table 36. Whether the internal state number is always written to the internal state number register 433 or the internal state number is written to the internal state number register 433 synchronously when the real number is written from the configuration number conversion unit 32 to the real number register 432 Select.

The configuration information with logical number “0” is written in the configuration information memory with real number “0”, and the configuration information with logical number “1” is written in the configuration information memory with real number “1”. . Further, control configuration selection information for instructing use of the state management unit 431 is added to the configuration information of logical number 0, and control configuration selection information for instructing non-use of the state management unit 431 is added to configuration information of logical number 1. It shall be added.

First, the operation of the data processing apparatus when using the state management unit 431 of the auxiliary control unit 43 will be described. Here, as in the first embodiment, the state is changed according to the state transition table shown in FIG. 9, and the internal state number “1” (state 0-1) included in the configuration information of the logical number “0” is assumed. An example of starting the process from is shown.

The state transition management unit (STC) 3 first reads out the control configuration selection information added to the configuration information of the logical number “0” from the configuration designation table 36, and based on the control configuration selection information, the clock of the clock generator 52 is read out. Select. Thereafter, the state transition management unit (STC) 3 and the calculation unit 4 according to the present embodiment operate using the clock generated by the clock generator 52 until the next clock is selected. Until the state transition management unit (STC) 3 selects a clock based on the control configuration selection information, the state transition management unit (STC) 3 and the calculation unit 4 have the processing capability of the state transition management unit (STC) 3. It is assumed that the operation is performed with a clock having a preset frequency (in this case, a clock generated by the clock generator 51).

FIG. 13A is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 13A, the processing path when the state management unit 431 controls the state transition is indicated by a thick arrow. That is, the thick arrow in FIG. 13A starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the signal determines the next internal state, and shows the processing path until the internal state number indicating the internal state is written in the internal state number register 433.

When the operation result is notified from the processor element 41 as an event signal, the state management unit 431 proceeds to control of the next state transition corresponding to the event signal based on the state transition table. Here, since the transition to the next state cannot be controlled by the state management unit 431 because the logical number changes, the state management unit 431 issues a WE cancel signal for stopping the operation of the processor elements 41 group. When the processor element 41 receives the WE cancel signal, it does not accept the update of the register contents. Further, when the processor element 41 receives the WE cancel signal, the data input operation from the external port is also stopped.

In the processing of the third cycle, the data processing device reads the event signal stored in the event signal register 435 by the state management unit 31, and based on the real number “0” and the event signal notified from the configuration number conversion unit 32, The logical number “1” of the next transition state is determined according to the state transition table, and the logical number “1” is notified to the configuration number conversion unit 32. Further, the state management unit 31 is based on the real number “0” notified from the configuration number conversion unit 32 and the received event signal, and the internal state number (starting internal state number) “1” starting in the next transition state. To decide.

The state transition management unit (STC) 3 reads the control configuration selection information added to the configuration information corresponding to the real number “1” from the configuration designation table 36, and the state management unit 431 is used for the configuration information of the logical number “1”. It is detected that a control structure that is not used is used, and the clock of the clock generator 51 is selected based on the read control configuration selection information. In this case, the state transition management unit (STC) 3 and the calculation unit 4 operate using the clock generated by the clock generator 51 from the next cycle. In addition, the state management unit 31 writes information indicating a control structure that does not use the state management unit 431 in the configuration designation register 434.

FIG. 13B is a diagram showing a processing path of two cycles by the data processing apparatus described above. In FIG. 13B, the processing path when the state management unit 431 controls the state transition in the second cycle and the processing path when the state management unit 31 controls the state transition in the third cycle are indicated by thick arrows. . That is, the thick arrow shown in FIG. 13B starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the event signal tries to determine the next internal state, and the state management unit 431 that cannot determine the next internal state stores the event signal received in the event signal register 435; When an event signal is issued to the state management unit 31 via the event signal register 435, the state management unit 31 determines the logical number and internal state number of the next state, and the logical number is executed by the configuration number conversion unit 32. The second process is performed until the conversion result is notified to the real number register 432 and the internal state number register 433. It is shown the door.

Here, since a control structure that does not use the state management unit 431 is used, the event signal indicating the calculation result of the processor element 41 is directly notified to the state management unit 31 without passing through the state management unit 431 and the event signal register 435. The

FIG. 13C is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 13C, the processing path when the state management unit 31 controls the state transition without using the state management unit 431 of the auxiliary control unit 43 is indicated by a thick arrow. That is, the thick arrow in FIG. 13C indicates that the internal state number register 433 is the starting point of processing, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 31 that has received the signal determines the next internal state, the configuration number conversion unit 32 converts the logical number notified from the state management unit 31 into a real number, and the result is the real number register 432 and the internal state. The processing path until notification to the number register 433 is shown.

Next, a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 5 will be described with reference to the drawings.

As described above, the object code synthesizing apparatus generates an object code of an application to be operated on the data processing apparatus by the synthesizing tool 50. Further, the object code synthesis apparatus estimates the processing performance of the data processing apparatus when the state management unit 431 of the auxiliary control unit 43 is used and when not used by the performance estimation tool 60, and the auxiliary control unit 43 based on the estimation result. Control configuration selection information indicating whether or not to use the state management unit 431 of the auxiliary control unit 43 is determined according to the determination result. It is added to the object code generated by the synthesis tool 50.

Here, in order to determine the superiority or inferiority of the processing performance when the state management unit 431 of the auxiliary control unit 43 is used or not, the operation time per cycle of the data processing device and the state management unit of the auxiliary control unit 43 are determined. The number of cycles required when using 431 and when not using 431 are used.

First, how to calculate the operating time per cycle will be described.

When using the state management unit 431 of the auxiliary control unit 43, the processing time for one cycle as a reference is set as the time required for processing the route indicated by the thick arrow in FIG. 13A. Using this value, the number of cycles required for control by the state transition management unit 3 is determined.

Specifically, the processing time required for control by the state transition management unit 3 shown in FIG. 13B is divided by the time required for the processing of the route shown in FIG. 13A, and the value raised to an integer is obtained. calculate. Next, by subtracting “1” from this value, the number of overhead cycles, which is the number of cycles required for control by the state transition management unit 3, is calculated.

On the other hand, when the state management unit 431 of the auxiliary control unit 43 is not used, the time for one cycle as a reference is set as the time required for processing the path indicated by the thick arrow in FIG. 13C.

Next, a performance estimation method using the performance estimation tool 60 shown in FIG. 5 will be described.

When the required number of cycles is calculated by the operation simulation method described above, the number of cycles when the state management unit 431 of the auxiliary control unit 43 is not used is the value of the number of cycles of the operation simulation itself.

The number of cycles when the state management unit 431 of the auxiliary control unit 43 is used is the overhead when the state transition occurs under the control of the state transition management unit 3 and the number of state transitions generated by the control of the state transition management unit 3. Is calculated by adding the number of cycles of the operation simulation to the product.

On the other hand, when the performance of the data processing device is estimated by the branch probability calculation method, the required number of cycles is expressed as a ratio. For example, if the number of cycles when the state management unit 431 of the auxiliary control unit 43 is not used is “1”, the number of cycles when the state management unit 431 of the auxiliary control unit 43 is used is controlled by the state transition management unit 3. Is calculated by adding “1” to the product of the probability of occurrence of a state transition that requires and the overhead value when the state transition management unit 3 controls the state transition.

The performance estimation tool 60 calculates the required operation time when the state management unit 431 of the auxiliary control unit 43 is used and when not used, and a control structure that shortens the required operation time (the state management unit of the auxiliary control unit 43). Control configuration selection information having the determination result as a basic control structure is generated.

Here, considering the operation required time in units of configuration information, the performance of the data processing apparatus may be improved in a control structure that is not adopted as a basic control structure. For example, when a control structure that does not use the state management unit 431 of the auxiliary control unit 43 is adopted as the basic control structure, there is configuration information in which the process stays for a long time, such as a loop process. Moreover, when the control structure using the state management unit 431 of the auxiliary control unit 43 is adopted as the basic control structure, there is configuration information for repeating a plurality of states one after another, repeating a branch process according to a branch condition. When such configuration information exists in the object code, the synthesis tool 50 rewrites the control configuration selection information of the corresponding configuration information.

Next, a specific example of a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 5 will be described.

Here, the required operation time by the processing path shown in FIG. 13A is 10 ns, the required operation time by the processing path shown in FIG. 13B is 16 ns, and the required operation time by the processing path shown in FIG. 13C is 13 ns. Assume that the probability of occurrence of a state transition that requires control of the unit 3 is 0.4.

Here, if the number of cycles when the auxiliary control unit 43 is not used is “1”, the number of cycles when the auxiliary control unit 43 is used is (1 + 0.4 × 1) = 1.4.

The operation time required for the data processing apparatus is 13 × 1 = 13 ns when the state management unit 431 of the auxiliary control unit 43 is not used, and 10 × 1.4 = 14 ns when the auxiliary control unit 43 is used. Become. That is, the operation required time is shorter when the state management unit 431 of the auxiliary control unit 43 is not used. Therefore, the performance estimation tool 60 employs the non-use of the state management unit 431 of the auxiliary control unit 43 as a basic control structure.

Next, the performance estimation tool 60 needs to control the state transition management unit 3 for each state group belonging to each piece of configuration information (for example, configuration information having a plurality of states such as logical number 0 shown in FIG. 9). The occurrence probability of state transition is calculated. For the configuration information whose occurrence probability is smaller than 0.3, a control structure using the state management unit 431 of the auxiliary control unit 43 is adopted.

According to the present embodiment, the performance estimation tool 60 estimates the processing performance when the state management unit 431 of the auxiliary control unit 43 is used and when it is not used, determines the optimal control structure for each configuration information, and the determination result Is added to each object information, and operation frequency information for specifying an operation frequency in the control structure using the state management unit 431 of the auxiliary control unit 43 and the control structure not in use is added to the object code. Therefore, the data processing apparatus of this embodiment can select the clock according to the control structure. Therefore, the time required for the processing of the data processing device can be reduced.

(Third embodiment)
The third embodiment is an example in which the above-described third embodiment is applied to the data processing apparatus of the prior invention (Japanese Patent Application No. 2006-103987) shown in the background art.

FIG. 14 is a block diagram showing the configuration of the data processing apparatus of the third embodiment.

The data processing apparatus of the third embodiment is different from the second embodiment in that a variable clock generator 7 is provided instead of the two

clock generators

51 and 52 shown in FIG.

As shown in FIG. 14, the data processing apparatus (DRP) of the third embodiment is a state transition management unit (STC) 3 that is the control unit 1 shown in FIG. 6 and an arithmetic unit 2 shown in FIG. The operation unit 4 includes an auxiliary control unit (MSTC) 43 and a plurality of processor elements (PE) 41, a variable clock generator 7, and an external memory 6. A clock generated by the variable clock generator 7 is supplied to the state transition management unit (STC) 3, the arithmetic unit 4, and the external memory 6.

The state management unit 31 corresponds to the state management unit 11 shown in FIG. 6, the configuration number conversion unit 32 corresponds to the configuration number conversion unit 12 shown in FIG. 6, and the configuration rewriting unit 33 sets the configuration rewriting unit shown in FIG. It corresponds to the part 15. The configuration designation table 36 holds control configuration selection information that is information that designates whether or not to use the state management unit 431 corresponding to the state management unit 231 illustrated in FIG. 6 provided in the auxiliary control unit (MSTC) 43. To do.

In the data processing apparatus shown in FIG. 14, the plurality of processor elements 41 included in the calculation unit 4 are the calculator 21 shown in FIG. 6. Note that the arithmetic unit is not limited to the processor element 41 and may be realized by a logic array, for example.

The auxiliary control unit (MSTC) 43 includes a state management unit 431 corresponding to the state management unit 231 illustrated in FIG. 6, and the state management unit 431 includes a logical number (the above group) including a plurality of internal state transitions. Manage state transitions.

Further, the auxiliary control unit (MSTC) 43 uses the real number register 432 that holds the real number of the current configuration information, the internal state number register 433 that holds the internal state number, and the state management unit 431. A configuration designation register 434 that holds control configuration selection information, which is information for designating, and an event signal register 435 that holds an event signal that designates a large-scale state transition that cannot be controlled by the state management unit 431.

In the event signal register 435, an event signal designating a large-scale state transition that cannot be controlled by the state management unit 431 is temporarily held before being sent to the state management unit 31.

The state transition management unit (STC) 3 reads the value stored in the memory area of the configuration designation table 36 corresponding to the real number of the configuration information to be used, and uses the state management unit 431 based on the read value. The operation of various selectors used for selecting whether or not is determined. At this time, the state transition management unit (STC) 3 stores the value read from the configuration designation table 36 in the configuration designation register 434.

The variable clock generator 7 generates a clock having a required frequency and supplies it to the state transition management unit (STC) 3 and the calculation unit 4. The variable clock generator 7 can change the frequency of the clock to be generated according to the value (operation frequency information) read from the configuration designation table 36.

The state transition management unit (STC) 3 determines whether or not to cause the configuration number conversion unit 32 to send a stop signal for the processor element 41 group according to the value stored in the configuration designation table 36, and whether the internal state sent from the state management unit 31 Whether the state number is always written to the internal state number register 433 or whether the internal state number is written to the internal state number register 433 synchronously when the real number is written from the configuration number conversion unit 32 to the real number register 432 select.

The state transition management unit (STC) 3 first reads the operating frequency information added to the configuration information of the logical number “0” from the configuration designation table 36, and generates the clock generated by the variable clock generator 7 according to the operating frequency information. Set the frequency.

FIG. 15A is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 15A, the processing path when the state management unit 431 controls the state transition is indicated by a thick arrow. That is, the thick arrow in FIG. 15A starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the signal determines the next internal state, and shows the processing path until the internal state number indicating the internal state is written in the internal state number register 433.

The state transition management unit (STC) 3 reads the operating frequency information added to the configuration information corresponding to the real number “1” from the configuration designation table 36 and uses the state management unit 431 for the configuration information of the logical number “1”. It is detected that the control structure is not used, and the frequency of the clock generated by the variable clock generator 7 is changed according to the read operation frequency information. In this case, the state transition management unit (STC) 3 and the calculation unit 4 operate using the clock after the change from the next cycle. In addition, the state management unit 31 writes information indicating a control structure that does not use the state management unit 431 in the configuration designation register 434. Until the state transition management unit (STC) 3 selects a clock based on the control configuration selection information, the state transition management unit (STC) 3 and the calculation unit 4 have the processing capability of the state transition management unit (STC) 3. It is assumed that it is operating with a clock having a preset frequency.

FIG. 15B shows two cycles of processing paths by the data processing apparatus described above. In FIG. 15B, the processing path when the state management unit 431 controls the state transition in the second cycle and the processing path when the state management unit 31 controls the state transition in the third cycle are indicated by thick arrows. . That is, the thick arrow shown in FIG. 15B starts when the internal state number register 433 is the starting point of processing, and when a calculation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 431 that has received the event signal tries to determine the next internal state, and the state management unit 431 that cannot determine the next internal state stores the event signal received in the event signal register 435; When an event signal is issued to the state management unit 31 via the event signal register 435, the state management unit 31 determines the logical number and internal state number of the next state, and the logical number is executed by the configuration number conversion unit 32. The second process is performed until the conversion result is notified to the real number register 432 and the internal state number register 433. It is shown the door.

Here, since the state management unit 431 is not used, the event signal indicating the calculation result of the processor element 41 is directly notified to the state management unit 31 without passing through the state management unit 431 and the event signal register 435.

FIG. 15C is a diagram showing a processing path of one cycle by the data processing apparatus described above. In FIG. 15C, the processing path when the state management unit 31 controls the state transition without using the state management unit 431 of the auxiliary control unit 43 is indicated by a thick arrow. That is, the thick arrow in FIG. 15C starts from the internal state number register 433, and when an operation result by a circuit constructed by each processor element 41 based on the current configuration information is issued as an event signal, The state management unit 31 that has received the signal determines the next internal state, the configuration number conversion unit 32 converts the logical number notified from the state management unit 31 into a real number, and the result is the real number register 432 and the internal state. A processing path until notification to the number register 433 is shown.

Next, a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 7 will be described with reference to the drawings.

As described above, the object code synthesizing apparatus generates an object code of an application to be operated on the data processing apparatus by the synthesizing tool 50. Further, the object code synthesis device estimates the processing performance of the data processing device when the state management unit 431 of the auxiliary control unit 43 is used and when not used by the performance estimation tool 60, and the auxiliary control unit 43 based on the estimation result. Whether the state management unit 431 is used or not is determined as to whether the processing performance is superior or inferior. Then, control configuration selection information indicating whether or not to use the state management unit 431 of the auxiliary control unit 43 is added to the configuration information generated by the synthesis tool 50 according to the determination result.

First, how to calculate the operating time per cycle will be described.

When using the state management unit 431 of the auxiliary control unit 43, the processing time of one cycle as a reference is set as the time required for processing the route indicated by the thick arrow in FIG. 15A. Using this value, the number of cycles required for control by the state transition management unit 3 is determined.

Specifically, the processing time required for control by the state transition management unit 3 shown in FIG. 15B is divided by the time required for the processing of the route shown in FIG. 15A, and the value raised to an integer is obtained. calculate. Next, by subtracting “1” from this value, the number of overhead cycles, which is the number of cycles required for control by the state transition management unit 3, is calculated.

On the other hand, when the state management unit 431 of the auxiliary control unit 43 is not used, the time of one cycle as a reference is set as the time required for processing the path indicated by the thick arrow in FIG. 15C.

Next, a performance estimation method using the performance estimation tool 60 shown in FIG. 7 will be described.

Next, a specific example of a method for estimating the processing performance of the data processing apparatus by the object code synthesizing apparatus shown in FIG. 7 will be described.

Here, the required operation time by the processing path shown in FIG. 15A is 10 ns, the required operation time by the processing path shown in FIG. 15B is 16 ns, and the required operation time by the processing path shown in FIG. 15C is 13 ns. Assume that the probability of occurrence of a state transition that requires control of the unit 3 is 0.4.

The operation time required for the data processing apparatus is 13 × 1 = 13 ns when the state management unit 431 of the auxiliary control unit 43 is not used, and 10 × 1.4 = 14 ns when the auxiliary control unit 43 is used. Become. That is, the operation required time is shorter when the state management unit 431 of the auxiliary control unit 43 is not used. Therefore, the performance estimation tool 60 uses the non-use of the state management unit 431 of the auxiliary control unit 43 as a basic control structure.

Furthermore, the performance estimation tool 60 adds operating frequency information for each configuration information. As described above, since the path length (calculation path) of the virtual circuit constructed in the calculation unit 2 according to the configuration information differs for each configuration information, the delay amount is not always uniform. Therefore, even if the control configuration selection information is the same configuration information, the operating frequency may be different.

According to this embodiment, the performance estimation tool 60 estimates in advance the processing performance when the state management unit 431 of the auxiliary control unit 43 is used and when it is not used, and selects the control configuration indicating the optimal control structure for each configuration information In addition to adding information, operating frequency information indicating an operating frequency corresponding to the delay amount is added, and the data processing apparatus can operate by selecting a control structure and an operating frequency for each piece of control information according to the information. Therefore, as compared with the data processing device of the second embodiment, the arithmetic processing can be executed at a more optimal operating frequency, so that the time required for the processing of the data processing device can be further reduced.

As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to the said embodiment. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2008-292120 filed on Nov. 14, 2008 and Japanese Patent Application No. 2009-035543 filed on Feb. 18, 2009. Get everything here.

Claims

A data processing device that executes arithmetic processing according to a state,
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
A data processing apparatus.
The auxiliary controller is
Information for selecting control of state transition using the second state management unit, or control of state transition using only the first state management unit without using the second state management unit, 2. The data processing apparatus according to claim 1, wherein the data processing apparatus is read together with an object code for causing the data processing apparatus to execute a desired process.
The auxiliary controller is
Information for selecting control of state transition using the second state management unit, or control of state transition using only the first state management unit without using the second state management unit, Each piece of configuration information, which is information necessary for virtually configuring a circuit in the data processing device, is stored, and whether to use the second state management unit along with the switching of the configuration information is selected. The data processing apparatus according to claim 2.
The controller is
Information for selecting control of state transition using the second state management unit, or control of state transition using only the first state management unit without using the second state management unit, 4. The data processing apparatus according to claim 1, wherein the data processing apparatus is used for selecting or changing an operating frequency.
The controller is
Along with information for selecting state transition control using the second state management unit, or state transition control using only the first state management unit without using the second state management unit, The data processing apparatus according to claim 1, further comprising information for selecting or changing the operating frequency.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
An object code generation device that generates an object code for causing a data processing device to execute a desired process,
A synthesis tool for generating the object code;
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Each of the processing performances of the data processing device is calculated, and control configuration selection information for designating whether or not to use the second state management unit with better processing performance is generated, and the control configuration selection information is A performance estimation tool to be added to the object code generated by the synthesis tool;
An object code generation device having
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
An object code generation device that generates an object code for causing a data processing device to execute a desired process,
A synthesis tool for generating the object code;
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit The second state management in which the processing performance of the data processing device is calculated, and the processing performance is improved for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device. A performance estimation tool that generates control configuration selection information that specifies whether to use a unit, and adds the control configuration selection information to each configuration information included in the object code generated by the synthesis tool;
An object code generation device having
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
An object code generation device that generates an object code for causing a data processing device to execute a desired process,
A synthesis tool for generating the object code;
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit The processing performance of the data processing device is calculated for each state, and the second processing performance is better for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device. The control configuration selection information for specifying whether to use the state management unit and the operation frequency information for selecting or changing the operation frequency are generated, and the control configuration selection information and the operation frequency information are generated by the synthesis tool. A performance estimation tool to be added for each configuration information included in the object code;
An object code generation device having
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that can select control of state transition using only the first state management unit without using the state management unit of
A data processing method for generating an object code to be executed by a data processing apparatus having:
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Generating control configuration selection information for designating whether or not to use the second state management unit with better processing performance;
A data processing method for adding the control configuration selection information to a generated object code.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that can select control of state transition using only the first state management unit without using the state management unit of
A data processing method for generating an object code to be executed by a data processing apparatus having:
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Control for designating whether or not to use the second state management unit with better processing performance for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device Generate configuration selection information,
A data processing method for adding the control configuration selection information to each configuration information included in the generated object code.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that can select control of state transition using only the first state management unit without using the state management unit of
A data processing method for generating an object code to be executed by a data processing apparatus having:
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of the data processor for each state,
Control for designating whether or not to use the second state management unit with better processing performance for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device Generate configuration selection information and operating frequency information for selecting or changing the operating frequency,
A data processing method for adding the control configuration selection information and the operating frequency information for each configuration information included in the generated object code.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
A program for causing a computer to generate object code that causes a data processing apparatus to execute a desired process,
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Generating control configuration selection information for designating whether or not to use the second state management unit with better processing performance;
A program for causing a computer to execute processing for adding the control configuration selection information to a generated object code.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
A program for causing a computer to generate object code that causes a data processing apparatus to execute a desired process,
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of each data processor,
Control for designating whether or not to use the second state management unit with better processing performance for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device Generate configuration selection information,
A program for causing a computer to execute processing for adding the control configuration selection information to each configuration information included in the generated object code.
A control unit including a first state management unit for controlling state transition;
A second state management unit that controls a state transition that is smaller in scale than the state transition controlled by the first state management unit, and controls the state transition using the second state management unit, or the second An auxiliary control unit that selects control of state transition using only the first state management unit without using the state management unit of
A program for causing a computer to generate object code that causes a data processing apparatus to execute a desired process,
When the state transition is controlled using the second state management unit, and when the state transition is controlled using only the first state management unit without using the second state management unit Calculate the processing performance of the data processor for each state,
Control for designating whether or not to use the second state management unit with better processing performance for each piece of configuration information that is information necessary for virtually configuring a circuit in the data processing device Generate configuration selection information and operating frequency information for selecting or changing the operating frequency,
A program for causing a computer to execute processing for adding the control configuration selection information and the operating frequency information for each configuration information included in the generated object code.