WO2009136368A1

WO2009136368A1 - Charge pump dc-dc converter

Info

Publication number: WO2009136368A1
Application number: PCT/IB2009/051851
Authority: WO
Inventors: Robert Jan Fronen
Original assignee: Nxp B.V.
Priority date: 2008-05-09
Filing date: 2009-05-06
Publication date: 2009-11-12

Abstract

A capacitive voltage converter (700) comprises: an input node (404) for receiving an input voltage (Vin),- an output node (406) for supplying an output voltage (Vout); a reference node (408) for receiving a reference voltage; a plurality of capacitors (410, 412, 414, 416); and switching means (718, 728, 720, 732, 722, 736, 724, 738) configured for, in a first mode, connecting the capacitors (410, 412, 414, 416) in series between the input node (404) or the output node (406), on the one hand, and the reference node (408) on the other hand and, in a second mode, connecting the capacitors in parallel between the input node (404) and the output node (406).

Description

CHARGE PUMP DC-DC CONVERTER

FIELD OF THE INVENTION

The invention relates to an electronic circuit comprising a capacitive voltage converter.

BACKGROUND OF THE INVENTION

DC-to-DC voltage converters are typically used in battery-operated electronic devices that have several circuits requiring different voltage levels. Also, a DC-to-DC converter is used to stabilize voltage supplied to a circuit, e.g., a light emitting diode (LED) circuit. Battery voltage decreases over time as the stored power is drained in operational use, whereas the circuit needs a more-or-less constant voltage supply.

An example of a DC-to-DC converter is a switched-capacitor (SC) converter, also referred to as a "charge pump converter". An SC converter alternately connects multiple capacitors to the input in a first configuration (e.g., connected in series) for being charged and to the output in another configuration (e.g., connected in parallel) for being discharged.

Examples of an SC converter are given in, e.g., US patent 5,581,454; US patent 6,281,705; and US patent 6,657,875, all incorporated herein by reference.

SUMMARY OF THE INVENTION

The configurations of the SC converters known from above documents consecutively switch the capacitors in series between the input and ground in the primary cycles and in parallel between the output and ground in the secondary cycles.

The inventor has had the insight that the efficiency of the SC converter can be improved by means of using another configuration in the secondary cycles. This applies especially when the conversion factor between the input voltage and the output voltage lies between, e.g., 0.5 and 1.5.

The inventor therefore proposes an electronic device comprising an electronic circuit with a capacitive voltage converter. The converter comprises an input node for receiving an input voltage; an output node for supplying an output voltage; a reference node for receiving a reference voltage (also referred to as "ground"); a plurality of capacitors; and switching means. The switching means is configured for, in a first mode, connecting the capacitors in series between the input node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node.

The invention is based on the insight that the input voltage source at the input node delivers the current to the buffer capacitance at the output node, if the parallel configuration of the capacitors is connected between the input node and the output node. As a result, the capacitors themselves do not have to provide the majority of the electric energy to the buffer capacitance, as the energy is directly transferred from input to output. Charging and discharging of a capacitor dissipates power through Ohmic losses and electromagnetic radiation. As the voltage source supplies the charging current to the buffer capacitance, the amount of charge involved in charging and discharging the capacitors is limited. This, in turn, increases the efficiency of the converter.

Based on the same insight, another electronic device is proposed by the inventor .The device comprises an electronic circuit with a capacitive voltage converter. The converter comprises: an input node for receiving an input voltage; an output node for supplying an output voltage; a reference node for receiving a reference voltage; a plurality of capacitors; and switching means. The switching means is configured for, in a first mode, connecting the capacitors in series between the output node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node. The series configuration is now connected to the output node instead of to the input node in the embodiment first-mentioned. Both embodiments are variations on the same theme and provide a voltage conversion by a factor of (1 + n/k).

The switching means is preferably controlled so as to alternately implement the series configuration of the capacitors and the parallel configuration of the capacitors, using a certain controller that opens and closes the switches in different time slots with a certain frequency.

The invention also relates to a capacitive voltage converter configured for use in above devices. The invention further relates to a method of converting an input voltage at an input node to an output voltage at an output node, using a plurality of capacitors and a reference node. One embodiment of the method comprises: in a time slot connecting the capacitors in series between the input node and the reference node, and in another time slot connecting the capacitors in parallel between the input node and the output node. Another embodiment of the method comprises: in a time slot connecting the capacitors in series between the output node and the reference node, and in another time slot connecting the capacitors in parallel between the input node and the output node.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is explained in further detail, by way of example and with reference to the accompanying drawing, wherein:

Fig.1 is a circuit diagram illustrating the charging of a capacitor; Figs.2 and 3 give formulae explaining the operation of the circuit of Fig.l; Fig.4 is a diagram of a known capacitive voltage converter;

Fig.5 is a diagram for explaining operation of the known converter during the secondary stroke;

Fig.6 gives formulae for explaining operation of the known converter; Fig.7 is a circuit diagram of a converter in the invention; Fig.8 is a diagram for explaining operation of the converter in the invention during the secondary stroke;

Fig.9 gives formulae for explaining operation of the converter in the invention;

Figs. 10 and 11 are diagrams of a converter in the invention that uses the series and parallel configurations in a manner opposite to that of the converter of Fig.7; and

Fig.12 gives formulae explaining the converter of Figs.10 and 11.

Throughout the Figures, similar or corresponding features are indicated by same reference numerals.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Light emitting diodes (LEDs) are rapidly finding their way into homes, cars and mobile systems as a highly efficient and reliable replacement of incandescent, TL and other conventional lighting systems. For example, the high- brightness white LED is an LED system replacing the conventional Xenon flash. One of the drawbacks of an LED-based lighting system is that the LED requires a stabilized supply current at low forward voltage of a few volts with large spread per device and halfway in between normal battery voltages. Therefore, powering an LED from a Li- ion battery in a highly efficient manner requires a voltage converter that is capable of converting voltage up or down depending on: the charge-condition of the battery, the output current and the forward voltage of the LED. The invention relates, among other things, to a novel way of converting an input voltage to an output voltage only a small step up or down from the input voltage.

More generically, the invention relates to a capacitive converter. For mobile applications, a capacitive converter needs to be capable of generating an output voltage V_out by means of making small steps around the input voltage V_1n: V_out = (1 ± k/n) V_1n, wherein "n" is an integer taking the value of, e.g., 4, 5 or 6, and wherein "k" is an integer ranging from, e.g., 1 to 4. In a conventional approach the step V₀Ut = (1 - l/n)V_mis associated with high losses in the conversion. The inventor proposes a manner to make the small step down with lower losses and, therefore, with higher efficiency.

In order to address the efficiency issue, reference is made to Figs. 1, 2 and 3. Fig.l is a diagram of a simple circuit 100 for illustrating the operation of charging a capacitor in terms of energies. Circuit 100 comprises a constant voltage source 102 supplying a voltage V_1n. Source 102 is connected to a series arrangement of a resistor 104 (having a resistance value R) and a capacitor 106 (having a capacitance value C) via a switch 108. The initial condition is that switch 108 is not conducting, and that capacitor 106 is completely discharged. When switch 108 is conducting, source 102 supplies a current I(t) that decreases from a maximum value to zero when capacitor 106 is charged completely. The time-integral of current I(t) represents the charge Q(t) stored at capacitor 106. When charge Q(t) does not increase anymore, the final stage has been reached wherein current I(t) has decreased to zero and the voltage across capacitor 106 equals supply voltage V_1n.

The energy supplied by source 102 is then given by expression (202). The energy stored in capacitor 106 is given by expression (204). The energy dissipated in resistor 104 is given by expression (206). Current I as a function of time t is given by expression (208) with Io - V_in/R. Combining expression (208) with expression (206) gives expression (210). Accordingly, half of the energy supplied by source 102 in the process of charging capacitor 106 from completely empty to completely full is dissipated in resistor 104. Note that expressions (202) and (204) have been derived without mentioning resistor 104 at all. Accordingly, the discrepancy between the supplied energy from source 102 and the energy stored in capacitor 106 is independent of the resistance value of resistor 106. If the resistance is taken vanishingly small, then expressions (202) and (204) still apply. In that case, a very high current will flow for a very short time. The loss of energy, equal to the difference between expressions (202) and (204) may then be interpreted as owing to the generation of electromagnetic fields caused by the high values of the time derivative of the current. Expression (212) gives an expression for the efficiency η of the process of charging capacitor 106 from completely empty to completely full. Using expressions (202) and (204) the efficiency η of above scenario is given as 0.5.

In above example, the charging of capacitor 106 was from completely empty to completely full. Now consider the scenario wherein the capacitor is charged from a voltage (V_1n - ΔV) to V_1n. This scenario is explained with reference to the expressions in Fig.3. The energy supplied by source 102 is given by expression (302). The energy received by capacitor 106 is given by expression (304). The efficiency η is now given by expression (306). The efficiency η increases with a decreasing value of the quantity ΔV. Accordingly, it is advisable to keep the level of discharging of the capacitors, i.e., the magnitude of the quantity ΔV in an SC converter, as low as possible in order to maximize the efficiency.

Fig.4 is a diagram of an electronic device 400 comprising an electronic circuit with a known capacitive voltage converter 402. Converter 402 comprises an input node 404 for receiving an input voltage from voltage source 102; an output node 406 for supplying an output voltage; and a reference node 408 for receiving a reference voltage, here ground. Converter 402 further comprises a plurality of capacitors 410, 412, 414 and 416. In this example, capacitors 410-416 are assumed to have the same capacitance value. Converter 402 also comprises controllable switching means implemented by switches 418, 420, 422, 424, 426, 428, 430, 432, 434, 436 and 438. In a first phase, only switches 418, 426, 432 and 438 are conducting and the other switches are blocking. In the first phase, capacitors 410-416 are connected in series between input node 404 and reference node 408. In a second phase, only switches 420, 426, 432, 434 and 436 are conducting. In the second phase, capacitors 414 and 416 are connected in parallel between node 408 and a series connection of capacitors 410 and 412. In the second phase, the series connection of capacitors 410 and 412 is also connected to output node 406. In a third phase, only switches 422, 424, 428, 430, 434 and 436 are conducting. In the third phase, the first terminals of capacitors 410-416 are connected to each other and their second terminals are connected to node 408. Converter 400 further comprises a buffer capacitor 440 at output node 406. Buffer capacitor 440 has a capacitance value much larger than the capacitance value of any individual one of capacitors 410-416. This condition keeps the output voltage at node 406 substantially constant per cycle of the three phases, mentioned above, in operational use of converter 102.

In the first phase, also referred to as "the primary stroke", switches 418, 426, 432 and 438 are closed. Capacitors 410-416 are then connected in series and each is charged to a voltage of A V_1n. This follows from the fact that, when the currents have ceased to flow, there is no net electric charge present in an imaginary box enclosing the lower plate of capacitor 410 and the upper plate of capacitor 412. In the second phase (or: secondary stroke) switches 420, 426, 432, 434 and 436 are closed, making a circuit of two capacitors in parallel connected in series with the other two. A voltage of ³A V_1n is transferred to output 406. In the third phase, also referred to as the "equalization stroke", the differences in charge on the capacitors are equalized as a preparation for the next primary stroke. The equalization stroke connects capacitors 410, 412, 414 and 416 in parallel. This equalization stroke is needed because the charges at series capacitors 410 and 412 and the charges at parallel capacitors 414 and 416 are unequal at the end of the secondary phase. Without equalization, the voltages at a node interconnecting two of capacitors 410- 416 is floating and drifts to levels that are uncontrolled and that can potentially damage the capacitors. Also note that the use of the equalization phase increases the time needed to run a full operational cycle, thus lowering, in effect, the frequency of operation.

For the calculation of the dynamics of converter 402, reference is made to the circuit diagram of Fig. 5 and to the formulae of Fig. 6. It is easier to start with the secondary stroke first. It is assumed that capacitors 410-416 store equal charges and have been charged to a voltage of A V_1n at the start of the secondary stroke. It is further assumed that, for all practical purposes, output voltage V_out remains constant during operation. For convenience, it is further assumed that the time period to carry out the equalization stroke is much shorter than that of the primary and secondary strokes.

During the secondary stroke, capacitors 410-416 are discharged while displacing a charge Q according to expression (602) in Fig.6, wherein the quantity f is the frequency of the operational cycle of converter 402, and wherein the quantity ΔV is the voltage drop across connected capacitors 410-416 during discharge (also referred to as: "ripple voltage"). The ripple voltage is an important parameter. The ripple voltage is associated with the current I_out to output 408 according to expression (602), and hence with the output power E_out according to expression (604) and output voltage V₀Ut according to expression (606). The ripple voltage is also associated with the losses Ei_oss during the secondary stroke according to expression (608). Equation (606) indicates that converter 402 generates in principle a slightly lower output voltage V₀Ut than in the ideal case due to the finite value of C.

After the secondary stroke the charges and the voltages of capacitors 410-416 are unequal since capacitors 410 and 412 are discharged in series, resulting in a voltage drop ΔV_seπes ⁼ 2/5 ΔV and capacitors 414 and 416 are discharged in parallel resulting in a voltage drop ΔV_paraii_ei = 1/5 ΔV. During the equalization stroke, capacitors 410-416 are connected in parallel so as to balance the energy by means of forcing an equal voltage across them according to expression (610). A small amount of energy is lost in the equalization stroke as given by expression (612).

After the equalization capacitors 410-416 are primed for charging using the input voltage source in the primary stroke. Capacitors 410-416 are then connected in series between node 404 carrying a voltage V_1n and reference node 408. At the start of the primary stroke, capacitors 410-416 are charged to a voltage of V_1n - 6/5 ΔV. Capacitors 410-416 then store a total energy as given by expression (614). At the end of the primary stroke, capacitors 410-416 are each charged to a voltage of A V_1n. The energy stored in capacitors 410-416 at the end of the primary stroke is given by expression (616). The amount of energy extracted from the source providing input voltage V_1n is then given by expression (618). During the primary stroke, the losses associated with the energy transfer are given by expression (620). The total of energy losses during a complete cycle of duration 1/f can now be determined by summing the results of expressions (620), (612) and (608), giving expression (622). The efficiency of the conversion process, carried out by converter 402, is calculated using definition (624). Using expressions (618) and (622), the efficiency η can be expressed according to formula (626). Using formula (602) in order to express ripple voltage ΔV in terms of output current I_out, expression (626) can be converted to expression (628).

Fig.7 is a circuit diagram of an electronic device 700 comprising an electronic circuit with a capacitive voltage converter 702 according to the invention. Device 700 comprises, e.g., a battery-operated electronic device such as a mobile telephone, a mobile media player (e.g., a mobile MP3 player or a mobile video player, or a portable device equipped with an LED flash light. Converter 702 comprises an input node 404 for receiving an input voltage from a voltage source (not shown); an output node 406 for supplying an output voltage; and a node 408 for receiving a reference voltage, here ground. Converter 102 further comprises a plurality of capacitors 410, 412, 414 and 416. Converter 702 also comprises controllable switching means implemented by first switches 718, 720, 722 and 724, and second switches 726, 728, 730, 732, 734, 736 and 738. In a first mode, switches 718-724 are conducting and switches 726-738 are blocking. In the first mode, capacitors 410-416 are connected in series between input node 404 and node 408. In a second mode, switches 718-724 are blocking and switches 726-738 are conducting. In the second mode, capacitors 410-416 are connected in parallel between input node 404 and output node 406. The switching means is controlled so as to have capacitors 410-416 alternately in the series configuration and in the parallel configuration in cycles with a pre-determined duration. A buffer capacitor 440 at output node 406 has a capacitance value much larger than the capacitance value of any individual one of capacitors 410- 416. This condition keeps the output voltage at node 406 substantially constant per cycle in operational use of converter 702.

Device 700 operates as follows. Instead of the three phases discussed with reference to device 400 of Fig.4, device 700 operates with only two phases: the primary stroke and the secondary stroke. The primary stroke in device 700 is similar to the one discussed with regard to device 400. In the primary stroke, capacitors 410- 416 are charged each to a voltage of A V_1n. In the secondary stroke, a voltage of magnitude: V_1n minus the voltage across any of capacitors 410-416 is transferred to output 406, resulting in a voltage at node 406 of ³A V_1n. After the secondary stroke, the charges at capacitor s 410-416 are identical, thereby eliminating the need for an equalization stroke.

For the calculation of the dynamics of converter 702, reference is made to the circuit diagram of Fig.8, showing converter 502 during the secondary stroke, and to the formulae of Fig. 9. Again, it is easier to start the calculations with the secondary stroke under the same assumptions as with the calculations above for converter 402, namely, that capacitors 410-416 are charged equally to V_in/4 and that capacitance of buffer capacitor 440 is much larger than the capacitance of any of capacitors 410-416. The output voltage V_out = %Vin - ΔV can therefore be assumed as constant during the whole cycle time 1/f.

During the secondary stroke, the amount of charge displaced is given by expression (902). An interesting aspect of converter 702 is that the energy stored in capacitors 410-416 at the start of the conversion E_initiai, given by expression (904), is actually lower than the energy stored at the end of the secondary stroke E_end, given by expression (906). This implies that capacitors 410-416 are being charged during the secondary stroke. An explanation of this is that more energy is extracted from input voltage source 802 than is transferred to output 406 including losses and the energy stored at capacitors 410-416. The extracted energy E_1n is given by expression (908). Again the ripple voltage ΔV is the key factor determining the energy balance and the output voltage V_out similar to expressions (604), (606) and (608). For converter 702, the corresponding expressions are expressions (910), (912) and (914).

The equivalent circuit for the primary stroke in converter 702 of the invention looks identical to the equivalent circuit of converter 402. However, there is a very relevant difference in the initial conditions at the start of the primary cycle. At the start of the primary cycle, capacitors 410-416 are charged to a voltage ¹A V_1n + ΔV and they will be discharged to ¹A V_1n while recycling energy CΔVV_in back to supply voltage source 802. In other words, the current from source 802 to capacitors 410- 416, arranged in series during the primary stroke, has a negative polarity.

The energy loss during the secondary stroke is calculated by taking the difference of equations (904) and (906) and subtracting the recycled energy CΔVV_in. The result is given by expression (914). Using expression (624) for the efficiency η, and substituting expressions (902), (908) and (914), gives the efficiency η according to expression (916). In a practical embodiment of the capacitive converter in the invention, used for, e.g., mobile LED photo-flash applications, the following typical values of the parameters are chosen: C = I μF; f = 1 MHz; V_1n = 3.6 V; and I_load = 500 mA. As a result, the factor I_loaxl/(f C V_1n) occurring in expressions (916) and (628) has a value of 0.14. Expressions (628) and (916) allow comparing the efficiency of known converter 402 with the efficiency of converter 702 in the invention. With above parameter values, known converter 402 has an efficiency of 81% whereas the converter 702 in the invention has an efficiency of 97%.

This substantial improvement of the converter of the invention over the known converter is owed to a number of factors. In the invention, the major portion of the energy (3/4 to be exact) is directly transferred from source 802 to output 406 without ever be stored in an energy buffer, represented by capacitors 410-416. In the known converter, all energy is converted via intermediate storage in capacitors 410- 416. The storing of energy in capacitors 410-416 as well as the retraction of energy from capacitors 410-416 is accompanied by energy losses. As a result, the known converter has a lower efficiency. Further, the major portion of the energy that is stored in capacitors 410-416 in the converter of the invention is recycled back to voltage source 802 during the primary stroke. In addition, the ripple voltage ΔV for a certain current I_outand for a certain frequency f in the invention is lower by a factor of 10 than the ripple voltage ΔV in the known converter. As explained before, the ripple voltage ΔV is the determining factor in the energy balance and the energy losses.

The following differences between a converter according to the invention and the known converter are also noteworthy. Both converter 402 and converter 702 require the same number of switches of similar properties to be able to displace charge with sufficient speed within the cycle time. The output voltage in the converter of the invention is a closer approximation of the intended output voltage of V₀Ut = ³/4 V_1n = 2.7 V. In the calculation examples above, the output voltage in the known converter is lower by an amount of 625 mV (23%), whereas the output voltage in the converter of the invention is lower by an amount of 62.5 mV (i.e. 2.3%). For achieving an output voltage and efficiency in the known converter that comparable to those of the converter in the invention, capacitors 410-416 have to be given a capacitance with a value, higher by a factor often. This, however, gives rise to a sharp increase in the cost and the PCB footprint. The known converter needs a frequency that is 50% higher than that of the converter in the invention in order to accommodate the equalization stroke. The contribution of the equalization to the energy losses is minor. In above examples, the losses in the equalization stroke are an order of magnitude smaller than those in the primary and secondary strokes, respectively. Figs. 10 and 11 are circuit diagrams of another configuration 1000 of a converter in the invention operating in a first phase and in a second phase, respectively. In converter 702, capacitors 410-416 were connected in series to input node 404 in the primary stroke and were connected in parallel between input node 404 and output node 406 in the secondary stroke. In contrast, converter 1000 has capacitors connected in series to output node 406 in a first phase, and in parallel between input node 404 and output node 406 in a second phase.

Fig.12 gives formulae roughly explaining the operation of converter 1000 to first order, ignoring the ripple voltage. In the first phase, illustrated by Fig.10, the voltage across each of capacitors 410-416 is given by expression 1202. In the second phase, illustrated by Fig.11 , the relationship between input voltage V_1n and output voltage V_out is given by expression (1204). As a result, the output voltage V_out can be expressed as in formula (1206). Again, the result is that the output voltage differs from the input voltage by a factor (1 + n/k).

The invention has been explained by way of example, with regard to the drawing enclosed. It is clear to the person skilled in the art that various other configurations of connected capacitors can be used. These other configurations are then variations on the same theme of the invention. For example, the invention has been explained with respect to switching the capacitor configuration between a pure series arrangement and a pure parallel arrangement. It is clear that one or more additional capacitors can be connected in parallel to one or more capacitors of the series configuration, e.g., to cater for a larger capacitance value, and that one or more additional capacitors can be connected in series with one or more of the capacitors in the parallel configuration, e.g., to cater for a smaller capacitance value, without departing from the scope of the invention. Also, the invention can be used with another number of capacitors, e.g., 6 in order to achieve smaller output voltage steps of 1/6 with high efficiency.

Claims

CLAIMS:

1. An electronic device (700) comprising an electronic circuit with a capacitive voltage converter (702), wherein the converter comprises: an input node (404) for receiving an input voltage; an output node (406) for supplying an output voltage; - a reference node (408) for receiving a reference voltage; a plurality of capacitors (410-416); and switching means (418-438) configured for, in a first mode, connecting the capacitors in series between the input node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node.

2. A capacitive voltage converter (702) comprising: an input node (404) for receiving an input voltage; an output node (406) for supplying an output voltage; - a reference node (408) for receiving a reference voltage; a plurality of capacitors (410-416); and switching means (418-438) configured for, in a first mode, connecting the capacitors in series between the input node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node.

3. An electronic device comprising an electronic circuit with a capacitive voltage converter (1000), wherein the converter comprises: an input node (404) for receiving an input voltage; - an output node (406) for supplying an output voltage; a reference node (408) for receiving a reference voltage; a plurality of capacitors (410-416); and switching means (418-438) configured for, in a first mode, connecting the capacitors in series between the output node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node.

4. A capacitive voltage converter (1000) comprising: - an input node (404) for receiving an input voltage; an output node (406) for supplying an output voltage; a reference node (408) for receiving a reference voltage; a plurality of capacitors (410-416); and switching means (418-438) configured for, in a first mode, connecting the capacitors in series between the output node and the reference node and, in a second mode, connecting the capacitors in parallel between the input node and the output node.

5. A method of converting an input voltage at an input node (404) to an output voltage at an output node (406), using a plurality of capacitors (410-416) and a reference node (408), wherein the method comprises: in a time slot connecting the capacitors in series between the input node and the reference node, and in another time slot connecting the capacitors in parallel between the input node and the output node.

6. A method of converting an input voltage at an input node (404) to an output voltage at an output node (406), using a plurality of capacitors (410-416) and a reference node (408), wherein the method comprises: in a time slot connecting the capacitors in series between the output node and the reference node, and in another time slot connecting the capacitors in parallel between the input node and the output node.