WO2009132427A1 - Multi-level voltage inverter - Google Patents

Abstract

The number of output voltage levels available in PWM voltage source inverters can be increased by inserting a split-wound coupled inductor between the upper and lower switches in each inverter leg. Interleaved PWM control of both inverter leg switches produces 3-level PWM voltage waveforms at the centre tap of the coupled inductor winding, representing the inverter leg output terminal, with a PWM frequency twice the switching frequency. The winding leakage inductance is in series with the output terminal, with the main magnetizing inductance filtering the instantaneous PWM-cycle voltage differences between the upper and lower switches. Since PWM dead-time signal delays can be removed, higher device switching frequencies and higher fundamental output voltages are made possible. The proposed inverter topologies produce 5-level PWM voltage waveforms between two inverter leg terminals with a PWM frequency up to four times higher than the inverter switching frequency. This is achieved with half the number of switches used in known alternative schemes.

Description

MULTI-LEVEL VOLTAGE INVERTER

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of United States provisional 61/049,674 filed

May 1, 2008.

TECHNICAL FIELD

[0002] Voltage inverters.

BACKGROUND

[0003] Conventional pulse width modulated (PWM) H-bridge and 6-switch three phase inverter topologies are the preferred power converters in many industrial applications for either dc to ac, or ac to dc, power conversion. The output waveform contains high frequency voltage harmonics that have known negative side-effects including high frequency currents, high dv/dt stresses, common mode voltages, interactions with the cable impedance and load impedances, and increased stray losses in magnetic components such as electrical machines. Mitigation of these effects can be addressed by a wide range of approaches including multiple parallel inverters with ac filter inductors, Neutral-Point-Clamped (NPC) inverters and modular switching schemes. A number of competing design factors complicate the ideal design. The inverter designs presented here are intended to address one or more of the difficulties in conventional inverters.

SUMMARY

[0004] There is provided in one embodiment, an inverter comprising a positive rail, a negative rail and at least an inverter leg comprising a split inductor with center tap, the split inductor having a first inductor terminal connected through a first switch to the positive rail and through a first diode to the negative rail, the split inductor having a second inductor terminal connected through a second switch to the negative rail and through a second diode to the positive rail. The inverter configuration operates with a pwm controller connected to supply control voltage to the first switch and to the second switch. The pwm controller is configured to provide the first switch and second switch with switching states that include at least the following positions: a) first switch off and second switch on; b) first switch on and second switch off; and c) one or both of the states: cl) first switch on and second switch on, and c2) first switch off and second switch off.

[0005] In various other embodiments, the split inductor may comprise a split wound coupled inductor; the pwm controller may be configured to provide the first switch and second switch of the first inverter leg with switching states that include the states cl and c2; additional switches are provided in the inverter legs to connect to a dc center tap and provide additional voltage levels; parallel and/or serial connected diodes are provided on one or more of the inductor terminals to reduce voltage stress; the inverter leg is provided in combination with a second inverter leg as claimed in an H-bridge configuration; and N inverter legs are provided in parallel to provide N phase operation, where N is one or more and may be three. A method of operation is also presented.

[0006] These and other embodiments of the inverter are set out in the claims and description that follows and the accompanying drawings, which are incorporated here by reference.

BRIEF DESCRIPTION OF THE FIGURES

[0007] Embodiments will now be described with reference to the figures, in which like reference characters denote like elements, by way of example, and in which:

[0008] Fig. IA is an electrical schematic of a 2-switch inverter with coupled inductor;

[0009] Fig. IB shows the inverter of Fig. IA with an AC inductor;

[0010] Fig. 1C shows the inverter of Fig. IA with a dc link center tap;

[0011] Fig. 2 is an electrical schematic of two 2-switch inverters in an H-bridge configuration;

[0012] Fig. 3 is an electrical schematic of three 2-switch inverters in a configuration suitable for three phase operation; [0013] Fig. 4a shows a first exemplary coupled inductor useful for the embodiment of

Fig. 1;

[0014] Fig. 4b shows a second exemplary coupled inductor useful for the embodiment of

Fig. 1;

[0015] Figs. 5A-5E show the switching states of the inverter shown in Fig. 1;

[0016] Figs. 6A-6C show equivalent circuits of the inverter of Fig. 1, in which Fig. 6A shows a transformer equivalent model, Fig. 6B shows an output terminal model and Fig. 6C shows a circuit model between the switches;

[0017] Figs. 7A and 7B show exemplary two-level interleaved PWM controls signals to produce a three-level PWM output for the inverter of Fig. 1 and Fig. 7C shows open loop V/F control using interleaved modulation signals;

[0018] Figs. 8 A and 8B show experimental waveforms for the split- wound coupled inductor and inverter of Fig. 1, with Fig. 8 A showing 60 Hz fundamental cycle and Fig. 8b showing expanded waveforms;

[0019] Figs. 9A and 9B show experimental output comparing a standard 4-switch H- bridge inverter without a coupled inductor and an inverter according to Fig. 2;

[0020] Figs. 1OA and 1OB show experimental comparisons of the coupled inductor winding currents as a result of using different inductor sizes (see Table III for the inductor parameters);

[0021] Fig. 11 shows experimental waveforms for the proposed inverter of Fig. 2 illustrating the three-level PWM output voltage and a "raised cosine" winding current wave shape;

[0022] Fig. 12 shows experimental coupled inductor winding dc magnetizing current compared with the ac load current for the embodiment of Fig. 2;

[0023] Fig. 13A shows possible inductor cores for use in the embodiment of Fig. 3 including a three limb core and single limb cores;

[0024] Figs. 13B and 13C show additional possible cores for use in the embodiment of

Fig. 3;

[0025] Fig. 13D shows division of the fundamental components of the winding currents in a three-phase design; [0026] Fig. 13E shows DC flux cancellation in a 3 -limb core, left side showing dc current and magnetic core MMFs and right side showing the corresponding magnetic circuit; [0027] Fig. 14 shows simulated common mode voltage, V_CM, with upper and lower winding currents of phase A, and the common mode current I_CM under DPWMl with the three limb core of Fig. 13 A;

[0028] Fig. 15 shows experimental motor common-mode voltages obtained from standard inverter (upper) and a proposed inverter (lower);

[0029] Fig. 16 shows PWM line-line voltages of six-switch multi-level topology under

DPWMl for various modulation depths;

[0030] Fig. 17. Simulated high frequency current spectrum under SPWM with standard six-switch inverter (grey) and six-switch multi-level proposed inverter (black); [0031] Fig. 18 shows experimental phase-neutral voltage of 18,000 rpni induction machine with: six-switch (grey) and six-switch multi-level proposed inverter (black) under DPWMl, ni_A = 0.9;

[0032] Fig. 19 shows experimental line to line voltages of six-switch multi-level inverter using the three limb core (black) and standard six switch inverter (grey); [0033] Fig. 20 shows experimental phase currents of unloaded 18,000 rpni induction motor with standard six-switch inverter (top) and a six-switch multi-level inverter (SSML inverter) of Fig. 3 using a three limb core (bottom);

[0034] Fig. 21 shows experimental high frequency ripple of phase currents for multilevel six-switch using the three limb core (black) and standard six-switch (grey) inverter; [0035] Fig. 22 shows experimental high frequency FFT of 18,000 rpni phase currents for the six-switch multi-level using the three limb core (black) and six-switch (grey) inverter; [0036] Fig. 23 shows experimental line to line voltages of six-switch multi-level inverter using separate cores (black) and standard six switch inverter (grey);

[0037] Fig. 24 shows experimental phase currents of 18,000 rpni induction machine for multi-level six-switch inverter using separate cores (bottom) and standard six-switch (top); [0038] Fig. 25 shows high frequency phase current ripple on experimental 18,000 rpni induction motor for six-switch inverter using separate cores (grey) and six-switch multi-level inverter (black); [0039] Fig. 26 shows experimental high frequency FFT of 18,000 rpni phase currents for the six-switch multi-level using separate cores (black) and six-switch (grey) inverter;

[0040] Fig. 27 shows experimental common mode voltage of the split- wound inductor, current and coil currents for the six-switch multi-level inverter with the three limb core under

DPWMl;

[0041] Fig. 28 shows experimental demonstration of the effect of dead-time at 20 IcHz and the corresponding phase current for a fixed mechanical power;

[0042] Fig. 29 shows a 4-switch asymmetrical half-bridge with a dc link center tap using the inverter cell of Fig. 1;

[0043] Fig. 30 shows a first switch mode of the asymmetrical half bridge of Fig. 29;

[0044] Fig. 31 shows a second switch mode of the asymmetrical half bridge of Fig. 29;

[0045] Fig. 32 shows a 3-phase inverter using a coupled inductor 4-switch asymmetrical half bridge with a dc link center tap and minimal diode count using the configuration of Fig. 29 for the inverter legs; and

[0046] Fig. 33 shows a 3-phase inverter using a coupled inductor 4-switch asymmetrical half bridge with a dc link center tap and devices with reduced voltage stress using the configuration of Fig. 29 for the inverter legs.

DETAILED DESCRIPTION

[0047] Referring to Fig. IA, there is shown a basic inverter cell or inverter leg configuration 10 that is used in various embodiments discussed further below. The inverter 10 comprises a split inductor 11 (Lt) with center tap. The center tap divides the inductor 11 into a first inductor terminal 12 that is connected through a switch 13 to a positive rail P and through a diode 14 to a negative rail N and a second inductor terminal 15 connected through a switch 16 to the negative rail N and through a diode 17 to the positive rail P. A pulse width modulation (pwm) controller 18 is connected to supply control voltage to the switch 13 and to the switch 16. As explained in more detail below, the pwm controller 18 is configured to provide the switch 13 and switch 16 with switching states that include at least the following positions: a) switch 13 off and switch 16 on; b) switch 13 on and switch 16 off; and c) one or both of the states: cl) switch 13 on and switch 16 on, and c2) switch 13 off and switch 16 off.

[0048] In Fig. IB, the inverter leg 1OB is formed in the same manner as the inverter leg of Fig. IA, except that the center tap of the split inductor is shown connected to an AC inductor 19. This AC inductor 19 may be present in any of the inverter leg embodiments disclosed here, as for example the inverter legs shown in Figs. 2 and 3. The AC inductor 19 may also be provided on either the positive rail P or negative rail N on the AC side of the inverter, depending on which rail the voltage at the center tap on the split inductor 11 is referenced to. The embodiment of Fig. 1C shows an embodiment of an inverter leg 1OC with a dc link center tap O. The center tap O and the center tap A on the split inductor in the inverter leg 1OC produce a voltage VaO. The AC inductor 19, when used with the inverter of Fig. 1OC, may also be placed at the dc link center tap. Power may move both ways through any of the inverters shown. [0049] In Fig IA, IB and 1C, and the equivalent parts of the other embodiments disclosed here, the two inductor terminals of the inductor 11 may be provided by separate inductors or reactors, but are preferably symmetrical split-wound coupled inductors wound on a unitary core and preferably have characteristic responses to the flow of electrical energy through them that are as close as is practical to being identical. The dots in Fig. IA, IB and 1C and the other figures that show the split inductor show the coupling direction. Any suitable device that creates inductance may be used. Design parameters for the inductors are discussed in more detail below. The switches 13 and 16 and the diodes 14 and 17 are preferably solid state devices, and the entire device may be made as monolithic as is possible given the technology available. The controller 18 for the switches 13 and 16 may be any suitable controller now known or later developed for the provision of pwm control in a niulti -level inverter. The controller 18 may be a single module, or separate modules, one for each switch or group of switches, for example one module for upper switches and one module for lower switches, with the modules synchronized by a computing device. Although shown as connected to switches 13 and 16, the switches represented could be any of the switches disclosed in any of the inverter embodiments. [0050] The controller 18 is characterized by the switching voltages provided to the switches 13 and 16, and hence is adequately described by voltage graphs indicating the control voltages. A variety of switching modes may be used as disclosed for example in more detail below. The use of pwm control is driven by the desire to reduce harmonic distortion in the output. In cases where reduction of harmonic distortion is not required, there may be relaxation of the pwm requirement The center tap produces voltage va, which is shown in Fig. IA as vout. [0051] The inverter embodiments of Figs. IA, IB and 1C form a 2 switch asymmetric half-bridge. Fig. 2 shows two 2-switch asymmetric half-bridge inverters 20, 22 in an H-bridge configuration 24. Each inverter 20, 22 is formed according to the design of inverter 10. The controller 18 is not shown for the sake of simplicity. Fig. 3 shows a three phase inverter 30 using three asymmetric half-bridges 32, 34 and 36, each formed according to the design of inverter 10. The inverter power can also flow in both directions with a rapid power reversal possible. Hence, the proposed inverter staicture can be used in applications such as a variable speed drive or a utility PWM rectifier. The proposed inverter can consume or provide reactive power to an ac supply. Hence, the proposed inverter has no basic operational restrictions introduced by the use of the coupled inductors. Another way to look at the inverter leg is that there are parallel paths connecting the positive P and negative N rails, one path having a diode then a switch in order from the negative rail, and the other having a switch then a diode in order from the negative rail, with each of the terminals of a split inductor with center tap connected into a respective one of the paths between the respective diode and switch. [0052] In the example of Fig. IA, the center tap of the split inductor 11 may form an output terminal. The two windings of the inductor 11 are preferably closely coupled, with low leakage inductance, and may for example be wound as two coils 40, 42 on a standard three-limb magnetic core 44, as shown in Fig. 4A. The inductor 11 provides more than just protection against dc-rail short. It also allows interleaved PWM switching of the upper and lower switches 13, 16 and an extra output voltage level equal to one-half of the dc supply voltage. The inductor 11 may also be made as shown in Fig. 4A with layered windings 52, 54 wound on a core 56. These designs are exemplary and not restrictive. Any of various inductor designs may be used for the inductor 11.

[0053] An exemplary switching operation of the two-switch inverter 10 is described here.

The coupled inductor 11 and two-level interleaved PWM switching of the upper and lower switches 13, 16 are shown to produce three-level PWM output voltage waveforms with balanced winding currents. If the two switches 13, 16 in the proposed inverter 10 are controlled using standard two-level interleaved PWM techniques, then four switching states are possible (Figs. 5A-5E). Fig. 5A shows the basic switching cell and provides labels for currents and voltages established in the circuit in operation. In Fig. 5B, switch 13 SaU , and switch 16 SbL are ON: and va = vdc /2. In Fig. 5C, switch 13 SaU and switch 16 SaL are OFF: and va = vdc /2. In Fig. 5D switch 13 SaU is OFF, and switch 16 SaL is ON: and va = 0. In Fig. 5E, switch 13 SaU is ON and switch 16 SaL is OFF and va = vdc .

[0054] A simplified model for the inverter 10 includes a winding leakage inductance

L_(Lι in Fig. 6B), magnetizing inductance Lm, and an ideal transformer as shown in Figs. 6A- 6C. The equivalent circuits illustrate that the output terminal consists of three-level PWM voltages [see va ,with L_/2 in series, Fig. 6B] and a large magnetizing reactance in series between he switches [Fig. 6C].

[0055] An exemplary two-level interleaved PWM control scheme is illustrated in Fig.

7A, together with the three-level output voltage va . Vref is a sinusoidal reference voltage. VcL is a saw-toothed voltage generated in conventional manner that is compared with Vref voltage in a comparator to produce control voltage VaL which is applied to the lower switch 16. VcU is a saw-toothed voltage generated in conventional manner that is compared with Vref voltage in a comparator to produce control voltage VaU which is applied to the upper switch 13. The resulting output va of the inverter is shown at the bottom of Fig. 7A.

[0056] Thus, Fig. 7A summarizes a basic interleaved pwm controller where a reference signal "vref is used to change the average (= average over a pwm switching cycle..) output voltage of an inverter leg in a sinusoidal fashion, see va in Fig. 7A. An interleaved pwm controller can control the two switches in an inverter leg, see vaU and vaL in Fig. 8A, such that when the average output voltage is required to be above Vdc/2, the output voltage waveform interchanges between the states Vdc/2 and Vdc over a pwm cycle (see va in Fig. 7A when the reference waveform vref is positive). Similarly when the average output voltage is required to be less than Vdc/2 (see va in Fig. 7A when vref is less than zero) the pwm output voltage waveform switches between Vdc/2 and 0. An interleaved pwm controller produces both of these two situations and also allows an easy transfer between them. This ease of transfer is achieved by allowing the switching edges of the two voltage vaU and vaL in Fig. 8A (also corresponding to the switching edges of the two switches) to easily move past one another in the pwm cycle. vaU and vAL corresponds to the voltages supplied to either end of the inductor by the two switch network. There are many ways to achieve this interleaved pwn switching action, Fig. 7 A shows a basic option.

[0057] A further control is shown in Fig. 7B. In Fig. 7A, the modulation is sinusoidal pwm (SPWM) and in Fig. 7B it is discontinuous pwm (PDWM). Space vector pwm (SVPWM) may also be used. In order to achieve the third voltage state, the upper and lower switches 13, 16 must either be both off or both on at the same instant. In Fig. 7B, Tap corresponds to VaU, Tan corresponds to VaL and Van corresponds to va in Fig. 7A. Simple open loop V/F control can be used to demonstrate the ability of the six-switch multi-level topology as a high speed drive, Fig. 7C. In Fig. 7C, an input waveform Wref generates Vref using V/F module 70, and Vref is then modulated in modulator 72 to produce control signals Tau, Tbu, Tcu for the upper switches 13 of Fig. 3 and, with a suitable time shift Ts, control signals TaI, TbI, TcI for the lower switches 16 of Fig. 3.

[0058] There are many more possible switching states for the proposed three phase inverter. A suitable interleaved three phase PWM switching scheme is described here based upon lowering the winding high frequency current ripple. The PWM scheme described is generic and can be implemented using either open loop voltage control, such as for a variable frequency drive, or current control, such as for an active utility rectifier.

[0059] An experimental three phase inductor constaicted used a standard 3 limb magnetic core with 0.0185" laminations. This is not the optimum material and laminations, but was used as a proof of concept. The measured inductor parameters are L₁₁₁ = 4.7 niH, K_pn = 0.999, K_lunb = 0.425, R_n = 0.3Ω, where L₁₁₁ is the series self inductance of both phase windings (with phases o/c), R_n: is the series resistance of both phase windings, K_pn is the magnetic coupling between two windings on the same limb and K_lunb magnetic coupling between windings on different limbs.

[0060] When using interleaved PWM, an examination of the possible inverter switching states reveals the basic states summarized in Figs. 7D-7I (the winding centre tap connection is omitted for clarity). The resultant winding "effective" inductances for each switching state are given in Table I. [0061] The "effective" inductances are related to the current ramping rate for the winding current in each switching state, and their size determines the maximum high frequency peak- peak current ripple. The inductance values were confirmed using simulations and 60Hz ac excitation for the various states. The three phase inductor design and its characteristics under the influence of high frequency PWM voltages are exemplary and different designs may be used for different situations. The values given in Table I should be regarded as approximate, but prove sufficient to reasonably predict the winding high frequency current ripple. [0062] TABLE I: PHASE A EFFECTIVE COMBINED WINDING INDUCTANCE

[0063] Switching state (a) shown in Fig. 7D produces the lowest effective winding inductance and corresponds to all the inverter switches of a three phase inverter being either all on, or all off. This state occurs frequently when using standard sinusoidal interleaved PWM, including standard space vector PWM (SVPWM). However, this state can be easily avoided using discontinuous PWM (DWPM) control. A PWM scheme that avoids state (a) has one inverter leg tied high or low for 60 degrees, with the other two inverter legs controlled using a suitable PWM strategy so as to produce sinusoidally modulated ac output voltages between the inverter output terminals, Table II. In DPWM switching, at most two of the three inverter legs operate at a high frequency at any given time.

[0064] TABLE II: SUITABLE PWM SWITCHING STATES FOR A THREE PHASE INVERTER

[0065] Suitable modulating signals for open loop voltage control are illustrated in Figs.

7J and 7K for two amplitude modulation depths (ma = 1.15 and ma = 0.9). These signals can be used to generate interleaved PWM signals using a variety of techniques, including: comparison with triangular carrier signals and space vector techniques. Experimental testing proved that this modulating scheme is suitable for variable frequency constant voltage per hertz operation of an induction motor with no coupled inductor winding current control being necessary. [0066] Figs. 8A- 12 relate to single phase operation of an inverter leg having the basic design of Fig. 2. The experimental waveforms shown in Fig. 8 A produced by the PWM control of Fig. 7A show that high-quality three-level sinusoidally modulated PWM voltages are obtained at the output terminals (see /a and va ). The nature of the voltage waveform va illustrates that the leakage inductance between the windings of the inductor 11 is low. The inductor voltage vail L [Fig. 8B] illustrates that the PWM cycle inductor voltage is symmetrical with no dc component. This feature exists over the complete output voltage range; hence, no winding dc current drifts or core saturation is produced by the interleaved PWM control scheme. There is always a concern that dc and circulating currents are produced in parallel-connected inverters. Ideally, the parallel circuit paths have identical voltage drops and the natural variations in the device operating conditions can cause unbalanced currents. The device voltage drops in the proposed topology produce a net negative voltage drop across the inductor (equal to one switch and one diode voltage drop on average) that acts against dc current drifts or circulating currents. Experimental testing illustrated that the switch turn-OFF times can produce a positive inductor voltage drop, and hence, a dc current. However, practically, this can be overcome easily by introducing a small difference between the switching of the upper and lower switches to provide a small net negative inductor winding voltage drop, and hence, guarantee that no dc current builds up. It should be noted, however, that the inductor windings have a natural dc current component determined by the magnitude of the ac output current (see /all, /aL in Fig. 8A, 8B). [0067] The analysis presented in this section uses a per unit system to allow inductor sizes to be chosen based upon the current ripple: [0068] Ls = Lp. u. s Lbase, Pbase = Vs /base and Lbase = Vs /2πfsPbase.

(Eqtn 1)

[0069] A test condition is used to compare the inductor size and the high-frequency current ripple for the various inverter topologies: Vs = 120 V, fs = 60Hz, /s,pk = 10A, Δ/max = 5% peak-topeak (pk-pk), Vdc = 1.5 Vs , switching frequency fc = 10 kHz (note: Vs is the ac load voltage). In some applications, the inverter 1OC will be provided with an ac filter inductor shown for example as inductor 19 in Fig. 1OB. The maximum high-frequency pk-pk current ripple for the ac filter inductor Ls isΔ/max and can be sized relative to the 60 Hz pk-pk value of the ac output current /pp using Ris,Rf , and Rv:

[0070] Ris = /pp/Δ/max, Rf = fc fs and Rv = Vdc V2Vs . Eqtn (2)

[0071] Hence, for the test condition,Ris = 20,Rv = 1.06, andRf = 166.7. For the standard two-switch inverter leg, Δ/max occurs when the inverter output terminal has a 50% duty ratio with the voltage switching between +Vdc and -\/dc. The supply inductor Ls sees a PWM voltage that is a symmetrical square wave at the carrier frequency fc and magnitude \/dc: [0072] Δ/max = Vdc /2fcLs and Ris = 2/ppfcLs /Vdc . (Eqtn 3)

[0073] Equations (l)-(3) can be used to link Lsp.u. with Δ/max. Similar analysis can be conducted for a conventional two switch inverter with no coupled inductor, a conventional 4- switch H-bridge inverter with no coupled inductor and the topologies of Figs. 1C (2 switch coupled L and Fig. 2 (4 switch coupled L), with the results given in Table III. Table III Design Parameters for the AC Filter Inductor L_s

2-switcfl 4-switch 2 -switch 4-switch Inverter- 1 ,eg I l -bridge Coupled I , Coupled I , pu π^Ris^Rv 7C ^Ris^Ry π ^Ris^Rv π ^Ris^Rv

L 2 R_f 8 R_* 8 R₄, 32 R_f

R 25 R 25 R R

ΛI 50 π- ^■ π - ^■ π - 3.1 π - max pu pu pu R_fL_s R_fL_s R_fL_s R_fL_s

[0074] Hence, suitable inductors to meet the test conditions are as follows. 1) Two-switch inverter leg (Lp.u. S = (1.57)[(20 * 1.06)/ 166.7] = 0.2p.u.):With Lbase = 45 niH and Ls = 9mH, this inductor will have a 20% fundamental voltage drop at the rated current. 2) Four- switch standard H-bridgβ (Lp.u. s = 0.392[(20 x 1.06)/166.7] = 0.05 p.u.): With Lbase = 45 mH, Ls = 2.25 mH, this inductor will have a 5% fundamental voltage drop at the rated current. 3) Two-switch coupled inductor (Lp.u. S = 0.392[(20 x 1.06)/166.7] = 0.05 p.u.): Ls is the same as for the four switch H-bridge, 2.25 mH, with a 5%fundamental voltage drop across the inductor at rated current. 4) Four-switch coupled inductor (Lp.u. S = 0.1 [(20 x 1.06)/166.7] = 0.0127 p.u.): With Lbase = 45 mH and Ls = 0.57 mH, this inductor will have a 1.3% fundamental voltage drop at rated current and is four times smaller than required for the standard four-switch inductor.

[0075] For the 2-switch coupled inductor Lt of Fig. 1C, the maximum pk-pk high- frequency current ripple occurs when the inductor Lt sees a PWM symmetrical square-wave voltage of magnitude ±2 \/dc and frequency fc . For the 4 switch inverter of Fig. 2, the coupled inductor Lt has a maximum current ripple when it sees a PWM symmetrical square-wave voltage of magnitude ±Vόc and frequency fc Design parameters for the inductors are given in Table IV using the design parameter: [0076] RW = /pp/Δ/t,max . (Eqtn 4)

Table IV Design Parameters for the Coupled Inductor L_t

2-switch 4-switeh split dc rail H»bridge π ^Rit ^Rv

L π-

I, p ti R_f 2 R_f

R R

Δl 1007f 50 π - l,m fix p u

R_fL_t R

<%) ¹V I - ^Pt ^U [0077] A recommended minimum value for Rit in some embodiments should be 4 to avoid excessive core losses and discontinuous winding currents; 8 or higher value significantly lowers the core losses and results in the high-frequency current ripple, but significant Cu losses can then be experienced. The four-switch H-bridge under the test conditions: Rit = 4, Rv = 1.06, Rf = 166.7: Lt,p.u. = 0.04 p.u. = 1.8 mH.

[0078] Tables III and IV allow the designer to pick suitable exemplary inductors, in terms of millihenries, given a desired current ripple for a single phase inverter. When compared with some standard topologies, the coupled inductors reduce the ac filter inductor by a factor of 4. The high-frequency ripple in the ac filter inductor is twice the carrier frequency for the proposed two-switch topology (four times for the H-bridge) and the inductor losses are significantly reduced, as the inductor current ripple magnitude is much smaller. In general, the standard two-switch inverter has a very large relative current ripple, but using the coupled inductor an inverter produces a ripple current magnitude equal to the standard H-bridge. The four-switch H-bridge with a coupled inductor produces a current ripple magnitude comparable to when using two 4-switch H-bridges and a standard ac filter inductor. Inverters using the coupled inductors produce the same performance as standard inverters using twice the power electronics and lower the size of the ac inductors and their fundamental voltage drop. This increases the fundamental load voltage and lowers the load current. This has the effect of lowering the losses in the semiconductors and inductors.

[0079] Inductor design parameters are compared here for a singlephase four-switch H- bridge inverter using the following design criteria: Vs = 120 V, /s = 60Hz, /s = 7A, with fc = 20 kHz and Vdc = 200 V. Designs are considered for several maximum current ripple magnitudes: Δ/t,max = 1.5, 4, and 6 A (see Table V).

[0080] All values given for component values are applicable to specific embodiments and not intended to limit the generality of the overall design. Different applications will include different component values. A skilled person may select the component values according to the application. Table V Inductor Designs Using Low-Permeability Cores

[0081] Inductors used in Table V are: 1) Ls1 : standard H-bridge ac inductor; 2) Ls2 : ac inductor for the H-bridge of Fig. 2; 3) Ls3 : experimental ac inductor used for the H-bridge of Fig. 2; 4) Lta,b : H-bridge coupled inductors of Fig. 2 ( 1 : Δ/t,max = 1.5 A, 2: Δ/t,max = 4A, 3: Δ/t,max = 6A). The coupled inductor required for each winding current ripple can be compared with each other and the ac filter inductor Ls .

[0082] Several design guidelines were used. 1) Low-permeability cores with a distributed airgap were considered for all the ac inductors due to their slow saturation characteristics. The maximum permissible core saturation was set at 50%. 2) High-permeability ferrite cores with an airgap were not considered, as all inductors can be exposed to surge currents and have significant "dc flux" and energy storage.

[0083] 3) The wire size was chosen to have the minimum cross section suitable for the rnis current with no attempt to minimize the Cu losses. 4) The maximum ripple in the ac flux (Sac ) and manufacturer data was used to estimate the core losses. This produces a large overestimate in the predicted core losses but is useful for comparison purposes. Note that the designs for the ac filter inductors (Ls 1 and Ls2 in Table V) were chosen to give the same current ripple in both the bridge types, e.g., the standard H-bridge and the H-bridge of Fig. 2 (see Δ/max in Table V). For the experimental waveforms, a 1-iiiH inductor was used for both cases (Ls3 in Fig. 8) to compare the effect on the ac current ripple of using the proposed H-bridge rather than the standard H-bridge. TableV is a typical design table for the various inductors. For the coupled inductor Lt (see Table V), the winding ripple current cases of 4 and 1.5 A, the total weight, WtTotal, of the inductors used is less than the weight of the ac filter inductor required for the standard H-bridge. 1) Standard H-bridge: WtTotal = 2222 g. 2) Proposed H-bridge (Δ/t,max = 6 A): WtTotal = 650 + 2 * 265 = 1 170 g.

[0084] 3) Proposed H-bridge (Δ/t,max = 4 A): WtTotal = 650 + 2 x 402 = 1604 g.

[0085] 4) Proposed H-bridge (Δ/t,max = 1.5A): WtTotal = 650 + 2 x 1002 = 2652 g.

[0086] If the winding ripple current is made too small, e.g., Δ/t,max = 1.5 A, the total inductor weight required can be increased above that required for the standard inverters: if too large, Δ/t,max = 6A, excessive core losses can be experienced. These results illustrate that the proposed topology can halve the number of switches and can also be used to lower the combined inductor weight. This weight reduction is limited by the winding dc magnetizing current component and the inductor core losses. Magnetic cores with lower core loses should be considered rather than those used here. The main benefit of the proposed approach is to allow multilevel PWM switching using half the power electronics and suitable for applications using an inductive load such as a motor.

[0087] The experimental waveforms presented in this section used a general-purpose laboratory test inverter with the following inductors and load parameters. 1) Vs = 120 V; /s = 7 A, fs = 60 Hz, \/dc = 200 V, fc = 20 IcHz. 2) Standard H-bridge: ac filter inductor = Ls1 . 3) Proposed H-bridge: ac filter inductor = Ls3 . 4) Coupled inductor = Lt1 a,b, Lt2a,b . The same standard laminated iron ac filter inductor was used in all cases (Ls3 = 1 mH) to allow comparison of the ac load current ripple magnitude. The interleaved PWM signals were generated using a TI TMS320F2812 DSP. Since the proposed four-switch H-bridge produces five-level PWM voltage waveforms across its two output terminals compared with the three- level in the standard H-bridge, the output current ripple is reduced by 25% relative to the standard H-bridge (Figs. 9A and 9B).

[0088] Figs. 1OA and 1OB show experimental comparisons of the coupled inductor winding currents as a result of using different inductor sizes (see Table V for the inductor parameters), for Fig. 1OA: Lta,b = Lt2a,b and for Fig. 1OB: Lta,b = Lt1 a,b . [0089] In Fig. 11 experimental waveforms are shown for the proposed inverter leg illustrating the three-level PWM output voltage and a "raised cosine" winding current wave shape with Lta,b = Lt1 a,b (see Table V for the inductor parameters). In Fig. 12 experimental coupled inductor winding dc magnetizing current /cm is compared with the ac load current /a : Lta,b = Lt1 a,b (see Table V for the inductor parameters).

[0090] The magnitude of the coupled inductor winding current ripple does not affect the load current ripple or the quality of the PWM output voltage waveforms (Figs. 9A, 9B, 1OA and 10B). The coupled inductor winding currents have a magnetizing current /cm with a dc component equal to half the peak ac output current (Figs. 1OA, 1OB and 12) and a high- frequency current ripple determined by the inductor size. The three-level inverter leg output voltage waveform is shown in Fig. 11 with the middle voltage level sitting at one-half the dc-rail voltage. The coupled inductor magnetizing current and its ripple, relative to the ac load current, are shown in Fig. 12. Since this dc component is about one-half the peak current, its physical size is reduced.

[0091] The embodiment of Fig. 3 provides a six-switch three-phase inverter 30 that increases the number of output PWM levels from two to three, and doubles the effective switching frequency over both the standard six-switch inverter (SS) and the NPC inverter. The embodiment of Fig. 3 has utility in high speed motor drives with a focus on the reduction of the machine losses, as compared to a standard six-switch inverter operating at the same switching frequency. Fig. 13A and Figs. 13C-28 relate to a three phase inverter configuration as follows. [0092] The multi-level six-switch inverter 30 uses three inverters 10, each with a split wound inductor to achieve the V_DC/2 voltage state, without the requirement of a split DC link. The current through the inductor windings of the inverters 10 cannot reverse direction due to the diodes in the state shown in Fig. 5C. As a result, a natural DC "common mode" current flows between the upper and lower switches 13, 16 that is the average of the upper and lower inductor winding currents.

[0093] Two implementations of the three-phase split- wound inductor were examined in the results given here in Figs. 14-28: the three limb core shown at the top of Fig. 13A and the inductor with three separately wound cores shown at the bottom of Fig. 13 A. The separate cores provide a flux return path in the magnetic core for both the high frequency and the "common- mode" DC offset current components that flow through both windings in the same inverter leg. Under fully switched modulation schemes, such as SPWM or SVPWM, the three limb core has the potential for both flux paths to cancel, producing a minimum inductance state (with the potential for shoot-though to occur).

[0094] Additional cores are shown in Figs. 13B for a single phase H-bridge and Fig. 13C for a three phase inverter. The magnetic core flux density produced by the fundamental component of the inverter output current are very small as the fundamental current splits evenly between the upper and lower windings. However, a natural dc current, "common-mode" or "zero sequence", flows through the two windings, roughly equivalent to half the peak of the output fundamental ac current. This current naturally rises and falls with changes in the output current and can produce dc flux in the single phase core. Several magnetic core designs are possible to reduce this flux, but the three phase core has a natural structure, shown in Fig. 13E, whereby the dc iiinif generated by the dc currents in each of the coils oppose each other and no dc flux is produced in the core. However, in practice, unbalanced ac output currents and the leakage flux between limbs can create a small dc magnetic flux.

[0095] Interleaved DPWMl modulation shown in Fig. 7B avoids the minimum inductance state in the three limb core by introducing a voltage drop across both windings of the split wound inductor "common mode voltage" with a zero voltage state lasting for 60°. Fig. 14 demonstrates the common mode voltage and current of an exemplary three limb split- wound inductor using interleaved DPWMl.

[0096] In the six-switch multi-level inverter shown in Fig. 3, the common mode path between the upper and lower switches 13, 16 provides a large magnetizing inductance that eliminates the need for shoot-through protection, and therefore inherently operates without the need for dead-time compensation. Furthermore, without the effects of dead-time, the modulation index for the six-switch multi-level inverter will correspond with a higher fundamental phase voltage - allowing for a lower per-unit phase current in the motor and reducing the high speed machine losses.

[0097] Typically, for digital signal processors such as the TMS320F2812, one carrier controls six PWM signals. Therefore, unlike paralleled six-switch inverters, which at a minimum require synchronization between respective carriers for each inverter module, the SSML topology inherently has a stable common mode because the switching operation is dependent on a single carrier signal.

[0098] The motor common-mode voltage, taken as the voltage between the neutral point of the motor and the center point of the dc-link, can prematurely damage bearings due to currents generated from the shaft to the usually grounded motor case. In Fig. 15, the high frequency common mode voltage, under six-switch multi-level topology, is reduced by 66% as compared to the standard six-switch inverter. The interleaved switching in the proposed topology doubles the frequency of the output phase voltage pwm waveforms, Fig. 17, and the magnitude of 'dv/df is reduced by half throughout the entire range of modulation indexes, Fig. 16. Furthermore, in terms of the harmonic content, the six-switch multi-level inverter provides a reduction of high frequency current ripple by a factor of four over the standard six-switch inverter. Fig. 18, demonstrates the increased number of PWM phase-neutral voltage levels which allows for the reduction in maximum current ripple, Table VI. Both the reduction of high frequency current ripple and the increased PWM levels contribute to the reduction of machine losses and by association, a reduction of rotor temperatures. [0099] TABLE VI: ST JMMARY ( )F ANALYTICAL MAXIMT IM RIPPLE α )MPARIS( >N

SS Inverter SSML Inverter

[00100] L_epu = Motor leakage inductance size in per-unit, R_v = Ratio of DC voltage relative to the peak of the ac voltage, R_f = Ratio ofthepwm switching frequency relative to the ac fundamental frequency

[00101] While achieving three-level PWM using only six-switches, the proposed multilevel inverter does not see an increase in IGBT stress over the standard six-switch inverter. Based on the fact that each IGBT sees half of the AC load current on top of the DC common- mode current - which can be related to half of the peak of the AC load current - each device is rated by:

Y KTBT RMS I ^~ J + I ^ CM RIPPLE RMS I

[00102] For an experimental implementation of the six-switch niulti -level topology, two

PM50CLA120 6-pack IGBT modules (from Powerex Inc.) were run in parallel with the inverter upper switches located in one module and the lower switches located in the second module. Furthermore, use of these paralleled packages allowed for accurate inverter loss comparison between the two topologies examined. Control of each module was accomplished via a TMS320F2812 microcontroller (from Texas Instalments). These are exemplary components for the switches S and controller C shown in Fig. IA. Any of various suppliers may be used for these components, or the switches S and controller C may be custom built according to the principles disclosed here. The experimental setup for the results of Figs. 14-28 included a highspeed induction motor was a standard 2-pole 460V, 60Hz 3 HP motor modified to allow for 18,000 rpni rotor speeds, with the bearing housing and the rotor shaft altered to fit 21,000 rpni rated open bearings. The stator was rewound with five times less series connected turns per phase and the number of poles increased to four. To achieve the original rated motor torque value, the number of parallel paths per slot was increased by five over the original design and thus keeping the original current density due to the reduction in series connected turns. Therefore, with five times the rated current flowing in the motor, the motor rated power increased to 15 HP at 18,000 rpm.

[00103] Two different types of inductor cores were developed to provide insight into the effect of inter-limb magnetic coupling in the three limb core inductor, and also to illustrate two switching schemes for the six-switch multi-level inverter. A three limb split-wound inductor, Fig. 13A upper was developed from a standard 1.5 niH 3-phase 60 Hz reactor. The original windings were replaced with 30 turns of paralleled 16 AWG magnet- wires for each coil, giving 60 turns and 4.7 niH of total magnetizing inductance at 60Hz. The separate cores, Fig. 13 A lower, used T300-40 toroids and wound to physically separate the upper and lower inductor windings, resulting in a 3.2 niH inductance. In order to minimize the inductor winding leakage inductance, both core types were wound in a bifilar fashion. The operation of the proposed topology using two inductor cores was compared against the standard six-switch inverter using symmetrical space vector (separate core) or DPWMl (three limb core) at a modulation depth of 0.9.

[00104] Waveforms were obtained for both the multi-level and six-switch drive at a fundamental frequency of 600 Hz, or 18,000 rpm synchronous speed of the induction motor. To further illustrate the reduction in high frequency current ripple, the 18,000 rpm induction motor was run loaded using its own windage losses: the original 60Hz rotor cooling fins were initially left uncut. Finally, both inverter topologies were operated at 300V_DC and with a switching frequency of 20 IcHz, to give a realistic frequency modulation ratio for a high speed machine of 33: 1. On the six-switch inverter, the dead-time was set to 2.4μs as recommended by the manufacturer. No dead-time was used on the SSML inverter of Fig. 3 used in the experimental set up.

[00105] Since the high speed induction machine used in this test rig was developed from a

60 Hz induction machine, measuring efficiency and losses of the inverter-machine set would be inconclusive due to the un-optimized nature of the test bed. Therefore, the loss and efficiency measurements were obtained using a 60 Hz 7HP, 1800 rpm induction motor - generator set and high accuracy 60Hz power meters. The induction motor efficiency results were obtained on a three-hour test am for each topology by fixing the measured shaft torque between the two test ains.

[00106] The line-line PWM voltage waveform on the 18,000 rpni induction machine increased from two to three levels, Fig. 19, with the three limb core under DPWMl, when compared to the standard six-switch inverter. Similarly, the phase currents for the three limb SSML topology produces a significant reduction in phase current ripple, and zero cross over distortion as evident in Fig. 20. One can see the peak ripple magnitude of the phase currents has been roughly reduced by a factor of four, Fig. 21, resulting in the harmonic spectaim, Fig. 22. The odd switching frequency harmonics have been eliminated, while reducing the sub-harmonic distortion due to dead-time, in Fig. 22 - essentially doubling the effective switching frequency of the six-switch multilevel inverter and consequently reducing the switching losses when compared to the six-switch inverter at the same effective switching frequency [00107] Similar to the three limb core results, the separate core results for the six-switch niulti -level topology show an increase of PWM levels, Fig. 23. Unlike Fig. 19, the line-line PWM voltage of the six-switch multi-level inverter switches from 0 to 300V at the peak of the modulation cycle - due to space vector modulation being used for the separate core results as opposed to DPWMl, which holds the appropriate phase inactive at this point of the modulation cycle. Furthermore, it is apparent from Fig. 23 that the line-line PWM voltage steps have a fundamental ripple voltage component when compared to the six-switch waveform - a consequence of the high leakage inductance of the split-wound toroids. This additional inductive "filtering effect" is also apparent in the phase currents of the 18,000 rpni induction machine, Fig. 24, as the even harmonics show a significant reduction in the harmonic spectrum of Fig. 26. [00108] Fig. 25 demonstrates an approximate high frequency current ripple reduction by a factor of four, under space vector modulation in the six-switch inverter to the six-switch multilevel inverter at the same modulation depth (0.9). Unlike the three limb core DPWMl results, the six-switch multi-level inverter seems to experimentally demonstrate an increase of sub- harmonics when compared to the SVPWM modulated six-switch inverter. A likely explanation for this sub-harmonic increase is again due to the large leakage inductance - roughly 110 μH per toroid - causing a large fundamental voltage drop at 600 Hz, distorting the sub-harmonic quality of the phase currents.

[00109] Before the performance of the six-switch multi-level drive is analyzed in terms of drive performance, it is important to have an understanding of the effect of the split inductor winding common mode current on the efficiency of the inverter. Fig. 27 demonstrates the experimental winding currents for phase A of the 18,000 rpni induction machine, the resulting common mode current and the common mode voltage of the split- wound inductor. Since the three limb inductor was originally intended for 60 Hz applications, and the 18,000 rpni inductor motor results were done at a switching frequency of 20 IcHz, the resulting high frequency flux in the 18 mil laminations of the original reactor likely caused severe skin depth issues in the iron - reducing the effective common mode inductance and leading to a common mode ripple of 6.5 A. In fact, updated results taken with a dimensionally similar core composed of 4 mil laminations, Fig. 27, demonstrate a reduction of common mode ripple to approximately IA - allowing for a significant decrease in core losses. Although the performance impact of the six-switch multilevel level inverter is unaffected by this large common mode ripple, the excessive core losses led to a reduced overall efficiency when compared to an improved design on the split-wound inductor.

[00110] In terms of inverter efficiency, the three limb core six-switch multi-level inverter is roughly 4.5% less efficient under the same modulation scheme as the six-switch inverter. It is important to note that this reduction in efficiency is solely due to this implementation of the three limb core being a 'proof-of-concepf and therefore not optimized as the core losses exceeded roughly 200W of inverter loss. In fact, for a high speed drive system - where power density is a key factor - even trading losses from the machine to the inverter is beneficial due to ease of cooling an inductor versus a compact machine - resulting in an improvement in the power rating of the high speed machine. The improvement in power loss is demonstrated on a utility speed 7 HP machine, as summarized in table VII. [00111] TABLE VII : STEADY STATE INDT JCTK >N MACHINE PERF( )RMANCE

Topology V_PH(V) I_PH(A) Pi_N(kW) Poιτ(kW) P_Loss(kW)

SS 155.01 16.994 3.981 2.914 1.067

SSML 155.15 16.455 3.897 2.937 0.960

[00112] For a fixed output torque and fundamental phase voltage, the multi-level inverter experimentally demonstrates a decrease in steady state machine loss of 11.4% over the standard six-switch inverter - as the losses in an induction machine are directly related to the magnitude of switched voltage across the machine. Steady state performance was necessary to fully appreciate the effects of rotor heating and the resulting change in slip speed for a given mechanical output power level. Indeed, the lower harmonic content provided by the six-switch multi-level inverter results in a lower rotor temperature, as the steady state slip changes from 5.7% in the six-switch inverter to 5.0% for the six-switch multi-level inverter. [00113] The results of table VII highlight the differences in machine losses for a fixed phase voltage magnitude between the two topologies - with the fixed phase voltage eliminating the differences in phase voltages resulting from the differences in dead-time between the two topologies. Therefore, at a fixed phase voltage, the loss differences in the machine can be attributed to the quality of phase voltage alone. Essentially, the loss reduction of table VII can be related to the harmonic content of the phase current (for the copper losses) and the stepped voltage magnitude. In a six-switch system without dead-time compensation, the fundamental voltage would be reduced by the effects of dead-time and therefore not equal to the fundamental voltage of the six-switch multi-level inverter. This reduction in fundamental voltage, results in an increase of phase current for a fixed mechanical output power, Fig. 28. At 20 IcHz, the fixed 2.4 μs dead-time of the six-switch inverter effectively increases the phase current, Fig. 28, resulting in an increase of machine losses - and therefore reduction in efficiency - for a fixed mechanical output. Furthermore, without the possibility of dropped pulses due to dead-time, Fig. 28 demonstrates the further decrease in phase current magnitude possible with a modulation depth of θ.95.

[00114] Referring to Figs. 29-33, several 3 phase NPC inverters using the inverter leg 10 are illustrated, each of which includes a split DC supply defining the positive P and negative N rails. Inverter leg 100 has the same design as inverter leg 10 of Fig. 1 but includes an additional switch 102 connected between the upper inductor terminal and the upper switch, an additional switch 104 connected between the lower inductor terminal and the lower switch, an additional diode 106 connected between the upper switches and the center tap of the split DC supply, and an additional diode 108 connected between the lower switches and the center tap of the split DC supply. The circuits of Figs. 29-33 are suitable for higher power and for lowering the size of the coupled inductor used.

[00115] Fig. 30 illustrates the active devices of Fig. 29 for a positive output voltage, with switch 102 on. Fig. 31 illustrates the active devices of Fig. 29 for a negative output voltage, with switch 104 on.

[00116] These circuits produce a 5 level pwm output voltage in each phase rather than 3 level described for the embodiments of Figs. 1-3.

[00117] Fig. 32 shows an embodiment of a three phase inverter using three inverter legs

100, and Fig. 33 shows an embodiment of a three phase inverter using three inverter legs 110, which are the same as inverter legs 100 but include parallel diodes to reduce voltage stress. The embodiments of Figs. 32 and 33 may use the three limb core and winding arrangement shown in Fig. 13C. The embodiments of Fig. 32 and 33 provide 9 voltage levels with 12 switches. The circuits of Figs. 29-33 produce 5-level PWM voltage waveforms at the centre tap of the coupled inductor windings, representing the inverter leg output terminal, with a PWM frequency twice the switching frequency. This refinement to the basic inverter topologies produces 9-level PWM voltage waveforms between two inverter leg terminals. This is achieved with half the number of switches used in known alternative schemes.

[00118] The use of a coupled split- wound inductor has been described to allow interleaved

PWM switching of the upper and lower switches in an inverter leg. This increases the number of PWM voltage levels at the inverter output terminals and doubles the PWM frequency. Benefits of the various embodiments of inverter topology described here include the following. Multilevel PWM uses half the power electronics of alternative schemes; e.g., when compared with the standard topologies, two-level is increased to three-level and three-level is increased to five-level. The load high-frequency current ripple in the ac output current is lowered, which can lower the losses in the ac filter inductor or an ac motor: the latter has potential benefits in terms of increasing the motor power ratings and efficiency of the machine. These features have great potential in high-speed machine drives. The multilevel output voltage waveforms also places less stress on the motor windings and help to alleviate motor winding dvldt stresses. The ac filter inductor can be reduced in size and its fundamental voltage drop reduced: this results in more fundamental voltage reaching the load. The switch control deadtimes can be eliminated, helping to improve the quality of the PWM voltage generation and increasing the maximum potential output voltage and switching frequency. The coupled inductor provides excellent protection against dc-rail shoot-through conditions.

[00119] The six-switch multi-level topology is useful as a drive topology for high speed machines. With the same number of active devices, the proposed inverter topology achieves five-level PWM at twice the effective switching frequency with inherent dead-time free operation. With increased attention due to loss density, high speed motors exhibit a definite need for harmonic quality from the inverter topology.

[00120] The coupled inductor used to achieve the niulti -level switching is the primary design factor in the optimization of the SSML inverter. However, preliminary designs suggest that the core size is limited by the iron and copper losses rather that the energy storage requirements. The core flux is naturally very low, but transient and drifting effects, such as PWM pulse dropping, variations in device switching times, and variable on-state device voltages should not be ignored. Fortunately, the semiconductor device on-state voltage drops provide an inherent safe guard against any increasing flux density trends. Furthermore, similar to the use of dead-time in standard inverters, the switch turn on and turn off times can be altered. Unlike standard inverters, this signal alteration in the SSML topology can be used to control the build up of the common mode inductor winding DC current and has no effect on the output fundamental PWM voltage produced.

[00121 ] Naturally, the addition of an inductor to the inverter topology can raise concerns about cost, but in fact, this should be judged relative to the various benefits such as the reduction in active devices and the smaller filter inductor required. Note that the filter inductor is probably considered a necessity in high speed machine applications, and can have a large fundamental voltage drop and excessive core losses when used with a standard inverter. The SSML topology significantly improves machine performances with much lower power losses, and removing these losses to an external inductor is a benefit by itself, as high speed machines are difficult to cool and can experience significant power derating when driven from a standard inverter. Finally, the superior inverter performance could also result in a smaller induction motor design - reducing the cost from the machine perspective - making the six-switch multilevel inverter an excellent candidate for high speed drive system.

[00122] Immaterial modifications may be made to the embodiments described here without departing from what is covered by the claims. In the claims, the word "comprising" is used in its inclusive sense and does not exclude other elements being present. The indefinite article "a" before a claim feature does not exclude more than one of the feature being present. Each one of the individual features described here may be used in one or more embodiments and is not, by virtue only of being described here, to be constaied as essential to all embodiments as defined by the claims.

Claims

What is claimed is:

1. An inverter comprising: a positive rail; a negative rail; a first inverter leg comprising a split inductor with center tap, the split inductor having a first inductor terminal connected through a first switch to the positive rail and through a first diode to the negative rail, the split inductor having a second inductor terminal connected through a second switch to the negative rail and through a second diode to the positive rail; and a pwm controller connected to supply control voltage to the first switch and to the second switch, the pwm controller being configured to provide the first switch and second switch with switching states that include at least the following positions: a) first switch off and second switch on; b) first switch on and second switch off; and c) one or both of the states: cl) first switch on and second switch on, and c2) first switch off and second switch off.

2. The inverter of claim 1 in which the split inductor comprises a split wound coupled inductor.

3. The inverter of claim 1 or 2 in which the pwm controller is configured to provided the first switch and second switch of the first inverter leg with switching states that include the states cl and c2.

4. The inverter of claim 1, 2 or 3 in which the inverter further comprises: the positive and negative rail being connected to a dc link, the dc link having a dc center tap; a third switch between the first inductor terminal and the first switch; a fourth switch between the second inductor terminal and the second switch; a third diode connected between a point between the first switch and second switch and the dc center tap; a fourth diode connected between a point between the third switch and fourth switch and the dc center tap; and the pwm controller being connected to control the on and off state of the third switch and fourth switch.

5. The inverter of any one of claims 1-4 further comprising parallel connected diodes on the second inductor terminal to reduce voltage stress.

6. The inverter of any one of claims 1-5 further comprising a second inverter leg connected in an H-bridge configuration with the first inverter leg, the second inverter leg comprising: a second split inductor with second center tap; the second split inductor having a first inductor leg connected through a first switch to the positive rail and through a first diode to the negative rail, the second split inductor having a second inductor terminal connected through a second switch to the negative rail and through a second diode to the positive rail; and the pwm controller being connected to supply control voltage to the first switch and to the second switch of the second inverter leg, the pwm controller being configured to provide the first switch and second switch of the second inverter leg with switching states that include at least the following positions: a) first switch off and second switch on; b) first switch on and second switch off; and c) one or both of the states: cl) first switch on and second switch on, and c2) first switch off and second switch off.

7. An N-phase inverter, where N is one or more, the inverter comprising: a positive rail; a negative rail;

N inverter legs, where each inverter leg comprises a split inductor with center tap, the split inductor having a first inductor terminal connected through a first switch to the positive rail and through a first diode to the negative rail and the split inductor having a second inductor terminal connected through a second switch to the negative rail and through a second diode to the positive rail; and a pwm controller connected to supply control voltage to each first switch and to each second switch, the pwm controller being configured to provide each first switch and each second switch with switching states that include at least the following positions in each inverter leg: a) first switch off and second switch on; b) first switch on and second switch off; and c) one or both of the states: cl) first switch on and second switch on, and c2) first switch off and second switch off.

8. The N-phase inverter of claim 7 in which N is three.

9. The N-phase inverter of claim 7 or 8 in which each split inductor comprises a split wound coupled inductor.

10. The N-phase inverter of claim 9 in which each split inductor comprises a limb of a three limb core, and the pwm controller is configured to prevent fluxes generated in the three limb core from canceling each other.

11. The N-phase inverter of any one of claims 7-9 in which the pwm controller is configured so that not all of the first and second switches are simultaneously on.

12. The N-phase inverter of any one of claims 7-11 in which the pwm controller is configured to provide each first switch and second switch with switching states that include the states cl and c2.

13. The N-phase inverter of any one of claims 7-12 in which each inverter leg further comprises: the positive and negative rail being connected to a dc link, the dc link having a dc center tap; a third switch between the first inductor terminal and the first switch; a fourth switch between the second inductor terminal and the second switch; a third diode connected between a point between the first switch and second switch and the dc center tap; a fourth diode connected between a point between the third switch and fourth switch and the dc center tap.

14. The N-phase inverter of any one of claims 7-13 further comprising parallel connected diodes on the second inductor terminal to reduce voltage stress.

15. The inverter configuration of any one of Figs. 1, 2, 3, 29, 32 or 33.

16. A method of voltage conversion, comprising: providing a first inverter leg comprising a split inductor with respective inductor terminals connected into respective switching networks under pwm control; and operating the switching networks to flow current, in respective switching positions, through the split inductor terminals in parallel and in series.

17. The method of claim 16 in which current flows through the inductor terminals in series between positive and negative rails of a dc link when an upper switch in the switching network and a lower switch in the switching network are both closed or both open.

18. The method of claim 16 or 17 in which current flows through the inductor terminals in parallel between one of the positive and negative rails of a dc link and center tap in the split inductor when one of an upper switch in the switching network and a lower switch in the switching network is open and the other is closed.

19. The method of claim 16, 17 or 18 in which additional switches are provided in the switching network to connect and disconnect the inductor terminals to a center tap of a dc link.

20. The method of any one of claims 16-19 further comprising providing a second inverter leg comprising a split inductor with respective inductor terminals connected into respective switching networks under pwm control, and operating the first inverter leg and the second inverter leg in an H-bridge configuration.

21. The method of claim 16 applied to three phase voltage inversion.