WO2004064234A2

WO2004064234A2 - Converter

Info

Publication number: WO2004064234A2
Application number: PCT/IL2004/000026
Authority: WO
Inventors: Guy Picha; Amir Katz
Original assignee: Guy Picha; Amir Katz
Priority date: 2003-01-10
Filing date: 2004-01-11
Publication date: 2004-07-29
Also published as: WO2004064234A3

Abstract

System for converting at least one input voltage signal of at least a selected power source of a power source array (182) including at least one power source, to at least one output voltage signal (Vout) associated with a respective predetermined electrical current, the system including a capacitor array (174), a variable impedance element array (176), and a connection scheme controller (178), the capacitor array including a plurality of capacitors, the variable impedance element array being coupled with the power source array and with the capacitor array, the variable impedance element array including a plurality of variable impedance elements, the connection scheme controller being coupled with the variable impedance element array.

Description

CONVERTER

FIELD OF THE DISCLOSED TECHNIQUE

The disclosed technique relates to power supplies in general, and to methods and systems for producing a substantially ripple-free direct current, in particular.

BACKGROUND OF THE DISCLOSED TECHNIQUE

A major problem associated with direct-current-to-direct-current (DC-to-DC) converters is the inefficiency of electrical energy conversion. Especially, as the voltages for digital circuitry are dropping to extremely low values (e.g., 1.8V, 1.5V, 1.2V, 1.0V and 0.9V), the conversion efficiency drops drastically. Thus, nowadays, conversion efficiency introduces an acute and pressing problem. Several main lines of technology emerged in order to cope with this problem.

The first technology was DC-to-DC converters based on a class D (either pulse width modulation - PWM or ΣΔ) switched converter followed by a reactive L-C (inductor-capacitor) low pass filter. The L-C filter outputs the DC part of the class D switched output signal, while storing substantially all the energy of the non-DC part, which is then reused.

There are several problems associated with class D based ultra efficient DC-to-DC converters. The L-C filter at the output is an electrically unstable system when the load is zero (i.e., resonance loop) and thus should be close-loop controlled. Furthermore, at regular operation, the inductor is practically used as a current source, thereby introducing a very poor response to sudden load changes (usually referred to as "transient response").

Moreover, the output of the class D based converter produces large differences of voltage over the inductor. These voltage differences produce in turn, large ripple currents over the inductor, which result in efficiency degradation due to parasitic resistance (especially at light loads). US Patent No. 5,436,820 issued to Fumanczyk, and entitled "Power Converter with Dual PWM Control" and US Patent No. 5,450,777 issued to Muto, and entitled "Switching Type DC-DC Converter having increasing Conversion Efficiency at Light Load", disclose examples of this kind of architecture.

The aforementioned problems make the design of an ultra-efficient DC-to-DC converter based on a class D switched converter followed by an L-C filter, an extremely difficult task. Furthermore, class D switched converter uses an external L-C filter. Unfortunately, the inductors of the L-C filters are not suitable for integrated circuits and therefore such prior art is not useful in applications involving miniaturized equipment, battery-operated equipment, secured equipment, or a combination thereof.

Another DC-to-DC converter technology known in the art, which eliminates the need for an external L-C filter is capacitor based N-level class D switched converter incorporating active loads or linear output stage. Examples of this kind of architecture are shown in US Patent No. 6,504,426 issued to Picha et al., and entitled "Methods and Systems for Power Amplification of Signals", and US Patent No. 6,573,695 B2 issued to Shashoua, and entitled "High-efficiency Power Supply". The problem with this solution is degradation of efficiency due to power dissipation over the active loads or the output linear stage.

A further DC-to-DC converter technology known in the art, which eliminates the need for an external L-C filter is a charge pump based DC-to-DC converter. This technology is based on a sequential use of different circuit structures that approximately set a linear set of equations over the capacitors' voltages with a single solution. Thus, the voltages across the capacitors in the capacitor array are forced to approximately fixed rational proportion of the voltage at its input. A holding capacitor is periodically charged by the switched capacitor array to compensate for charge that is removed due to current flow to the load. Examples of this kind of architecture are shown in US Patent No. 6,438,005 issued to Walter, and entitled "High-Efficiency, Low Noise, Inductorless Step-Down DC/DC Converter", US Patent application No. 20020051402 entitled "Voltage Drop DC-DC Converter", and US Patent No. 6,563,235 B1 issued to Mclntyre et al., and entitled "Switched Capacitor Array Circuit for use in DC-DC Converter and Method".

SUMMARY OF THE DISCLOSED TECHNIQUE

It is an object of the disclosed technique to provide a novel method and system for voltage conversion which overcomes the disadvantages of the prior art. In accordance with the disclosed technique, 5 there is thus provided a system for converting voltage signals. The system receives as input at least one input voltage signal of at least a selected power source of a power source array including at least one power source. The system produces as output at least one output voltage signal associated with a respective predetermined electrical current. The system 0 includes a capacitor array, a variable impedance element array coupled with the power source array and with the capacitor array, and a connection scheme controller coupled with the variable impedance element array. The capacitor array includes a plurality of capacitors. The variable impedance element array includes a plurality of variable impedance elements. 5 The connection scheme controller selects at least one set of connection schemes. The connection schemes in the selected set of connection schemes are represented by a respective set of differential equations. The respective set of differential equations has a respective single solution. The respective single solution defines a plurality of o substantially constant shape voltage functions for selected ones of the capacitors with respect to the respective predetermined electrical current. The connection scheme controller operates the variable impedance element array by varying the impedance of respective ones of the variable impedance elements, to apply the connection schemes to the capacitor 5 array and to the power source array, in a sequence, thereby substantially obtaining the respective single solution. According to the disclosed technique, for at least part of the time, at least one of the substantially constant shape voltage functions, combined with none or more of the input voltage signals, define at least one of the output voltage signal. o In accordance with another aspect of the disclosed technique, there is thus provided a system which produces one or more output voltage signals which are not associated with a respective predetermined electrical current. This system further includes a capacitor array, a variable impedance element array, a monitor module and a connection scheme controller. The variable impedance element array is coupled with the power source array and with the capacitor array. The monitor module is coupled with the capacitor array. The connection scheme controller coupled with the variable impedance element array and with the monitor module. The monitor module monitoring at least one electrical parameter at the capacitor array, thereby producing at least one monitored electrical parameter signal. The connection scheme controller selects at least one set of connection schemes. The connection schemes in each set of connection schemes are represented by a respective set of differential equations. The respective set of differential equations has a respective single solution. The respective single solution defines a plurality of substantially constant shape voltage functions for selected ones of the capacitors. The connection scheme controller operates the variable impedance element array by varying the impedance of respective ones of the variable impedance elements, to apply the connection schemes to the capacitor array and to the power source array, in a sequence, thereby substantially obtaining the respective single solution. The connection scheme controller operates the variable impedance element array, for at least part of the time, at least according to one of the monitored electrical parameter signals. According to the disclosed technique, for at least part of the time, at least one of the substantially constant shape voltage functions, combined with none or more of the input voltage signals, define at least one of the output voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed technique will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which: Figure 1 is a schematic illustration of a voltage conversion system for producing a reduced ripple output voltage, constructed and operative in accordance with an embodiment of the disclosed technique;

Figure 2 is a schematic illustration of an electric circuitry which implements an example of the system of Figure 1 , constructed and operative in accordance with another embodiment of the disclosed technique;

Figure 3A and 3B are schematic illustrations of current flow path through the electric circuitry of Figure 2, according to different connection schemes; Figure 4 is a schematic illustration of a voltage conversion system for producing reduced ripple output voltages, constructed and operative in accordance with an embodiment of the disclosed technique;

Figure 5 is a schematic illustration of an electric circuitry which implements an example of the system of Figure 4, constructed and operative in accordance with a further embodiment of the disclosed technique;

Figure 6A, 6B, 6C and 6D are schematic illustrations of current flow path through the electric circuitry of Figure 5, according to different connection schemes; Figure 7 is a schematic illustration of an electric circuitry which implements an example of the system of Figure 4, constructed and operative in accordance with yet another embodiment of the disclosed technique; and

Figure 8A, 8B, and 8C are schematic illustrations of current flow path through the electric circuitry of Figure 7, according to different connection schemes. DETAILED DESCRIPTION OF THE EMBODIMENTS

The disclosed technique overcomes the disadvantages of the prior art by controlling the impedance of one or more variable impedance elements, which connect one or more power sources and a plurality of capacitors. By setting each variable impedance element to appropriate impedance, the variable impedance elements regulate the charge flow in the circuit, thus control the voltage across the capacitors and can reduce the voltage ripple across them. Additionally, the voltage reading across the capacitors and the power sources can be employed for controlling the impedance of the variable impedance elements, thereby maintaining the output voltage at a substantially steady level, despite fluctuations of the external load and the power produced by the power sources. Further additionally, one or more control signals can be employed to maintain the output voltage at a desired level. Two or more capacitors and one or more power sources of an electronic circuit can be connected in different manners. By varying the impedance of one or more variable impedance elements connecting these capacitors and power sources, a target output voltage and a maximal output voltage ripple can be achieved. Reference is now made to Figure 1 , which is a schematic illustration of a voltage conversion system for producing a reduced ripple output voltage, generally referenced 100, constructed and operative in accordance with an embodiment of the disclosed technique.

System 100 includes a connection scheme controller 102, a variable impedance element array 104, a power source array 106 and a capacitor array 108. Variable impedance element array 104 is coupled with connection scheme controller 102, power source array 106 and with capacitor array 108. Capacitor array 108 is further coupled with power source array 106. The output terminals V uτ[1 :N] are selected from nodes within capacitor array 108. It is noted that two output terminals can be considered as a differential output. Capacitor array 108 includes a plurality of capacitors. It is noted that each of the capacitors included in capacitor array 108, may be floating or constantly connected with one end to a power source, within power source array 106. Power source array 106 includes one or more power sources, which provide DC voltage at their output. A power source of power source_, array 106 can be an electrical to electrical converter (e.g., alternating-current-to-direct-current "AC-to-DC" converter, doubling voltage circuitry, and the like), chemical to electrical converter (e.g., rechargeable battery, non-rechargeable battery, fuel cell, voltage generator operating on fossil fuel, alcohol, methanol, natural gas, and the like), mechanical to electrical converter (hand-operated dynamo, internal combustion engine dynamo, voltage generator operating on wind energy, voltage generator operating on tidal energy, voltage generator operating on hydroelectric energy, and the like), radiation to electrical converter (e.g., solar cell, nuclear power generator), heat to electrical converter (e.g., steam turbine), and the like.

Variable impedance element array 104 includes variable impedance elements that form a net of connections between the capacitors of capacitor array 108 and the power sources of power source array 106. Each of the variable impedance elements (not shown) in variable impedance element array 104 is an electronic element with controllable or non-controllable impedance. Each of the variable impedance elements can be a field effect transistor (FET), variable or non- variable resistor, variable or non-variable inductor, variable or non-variable capacitor, electronic circuit, semi-conductor element and the like. It is noted that the impedance range of each variable impedance element is partial or equal to the range between substantially zero impedance and substantially infinite impedance. Connection scheme controller 102 includes a finite number of connection schemes. Each connection scheme includes a partial set of variable impedance elements within variable impedance element array 104, to be set to a non substantially-infinite impedance (e.g., substantially zero, finite complex impedance, finite real impedance, finite imaginary impedance and time dependent impedance, unique voltage-current dependency element), while the rest of the variable impedance elements are to be set to substantially infinite impedance. Connection scheme controller 102 can either include a timer, or alternatively receive a timing signal from an external timer.

At each timing signal instance (external or internal), connection scheme controller 102 selects a connection scheme to be operative according to a predetermined or a semi-predetermined infinite sequence of connection schemes. It is noted that any connection scheme is chosen from the finite set of connection schemes stored in connection scheme controller 102. It is also noted that the connection scheme controller 102 can extend the time period for current connection scheme. Connection scheme controller 102 delivers the next connection scheme to variable impedance element array 104 which in turn, sets the connection scheme between power sources within power source array 106, the capacitors within capacitor array 108. Connection scheme controller 102 further controls the impedances of the variable impedance elements of current connection scheme. It is noted that connection scheme controller 102 may change impedances of variable impedance elements of current connection scheme in times synchronized with the timing signal, discrete times not synchronized with the timing signal, continuous time and any time combination there off.

The following is a detailed explanation of the methods to operate connection scheme controller 102. Connection scheme controller 102 is planned to produce a predetermined or semi-predetermined sequence of connection schemes to operate variable impedance element 104. Let G be a set of connection schemes. An infinite sequence S is said to be an appropriate sequence of G if each element of G appears at infinite occurrences in S. Planning connection scheme controller 102 to have an infinite sequence of connection schemes with no pattern can sometimes prove to be non-practical. The following are practical examples for appropriate sequences of G: • An infinite sequence of random permutations of all connection schemes within G.

• An infinite repeated sequence of a single permutation (i.e., cyclic) of all connection schemes within G.

• An infinite sequence which is characterized by a positive integer diversity number N, wherein every sub-sequence of that infinite sequence which is at the length of N, includes all of the connection schemes of G.

Let G be a set of connection schemes and let S be an appropriate sequence of G. If system 100, under sequence S and without load, reaches a constant voltage over some or all capacitors within capacitor array 108, than the null steady state of system 100 under set G, is the described steady state.

Under null steady state condition the voltage over each variable impedance element is constant, thus set G defines a set of linear equations over the voltages of some or all of the capacitors within capacitor array 108 and voltages of power sources within power source array 106 that has a single solution. This single solution is the null steady state of system 100 under G. It is noted that for practical implementations the outputs of system 100 must be well defined by the above single solution. It is additionally noted that at null steady state condition, the voltages of all output terminals are linear combination with rational coefficients (smaller, greater or equal to one) of the voltages of power sources within power source array 106.

System 100 under a set of connection schemes G with a predetermined non-zero load (i.e., predetermined electrical current, which may be substantially constant or variable) can approximately reach the null steady state if all the variable impedance elements of all connection schemes within G are set to zero. Setting some of the variable impedance elements of all connection schemes within G to a non-zero impedance 5 may shift the steady state of system 100 to a quasi steady state, which is different from the null steady state of system 100 under G.

For any given substantially constant load, a quasi steady state that is an approximation of a target steady state can be achieved, by setting the different variable impedance elements of connection schemes o within G to have specific non-zero impedances. It is noted that the maximal output voltage to be achieved at any output, is approximately the one achieved at the null steady state. It is further noted that connection scheme controller 102 may change impedances of variable impedance elements in times independent of changing times of connection schemes. 5 Reference is now made to Figure 2, which is a schematic illustration of an electric circuitry which implements an example of system 100 of Figure 1. Figure 2 illustrates the connections between capacitors 140 (also referenced CV), 142 (also referenced C₂) from capacitor array 108 of system 100 of Figure 1 , power source 120 and ground source 122 0 from power source array 106 of system 100 of Figure 1 , and variable impedance elements 132, 134, 136, 138 from variable impedance element array 104 of system 100 of Figure 1 , generally referenced circuit 130.

The negative terminal of power source 120 and the negative terminal of capacitor 142 are connected together and further to the ground 5 source 122. Output terminal V₀υτ is connected to the positive terminal of capacitor 142. Variable impedance element 132 is connected between Voi_/r and positive terminal of capacitor 140. Variable impedance element 134 is connected between V₀uτ and the negative terminal of capacitor 140. Variable impedance element 136 is connected between ground o source 122 and the negative terminal of capacitor 140. Variable impedance element 138 is connected between the positive terminal of power source 120 and the positive terminal of capacitor 140.

The set of connection schemes defined for system 130 is G={{134,138},{132,136}}. Reference is now made to Figure 3A, which is a schematic illustration of current flow path through circuit 130 of Figure 2, according to connection scheme {134,138}eG, generally referenced 144.

The negative terminal of power source 120 and the negative terminal of capacitor 142 are connected together and further to the ground source 122. Output terminal V₀uτ is connected to the positive terminal of capacitor 142. Variable impedance element 134 is connected between Vour and the negative terminal of capacitor 140. Variable impedance element 138 is connected between positive terminal of power source 120 and positive terminal of capacitor 140. Reference is now made to Figure 3B, which is a schematic illustration of current flow path through circuit 130 of Figure 2, according to connection scheme {132,136}eG, generally referenced 146.

The negative terminal of power source 120 and the negative terminal of capacitor 142 are connected together and further to the ground source 122. Output terminal V₀uτ is connected to positive terminal of capacitor 142. Variable impedance element 132 is connected between I/our and positive terminal of capacitor 140. Variable impedance element 136 is connected between ground source 122 and the negative terminal of capacitor 140. Let V_iN be the voltage of power source 120. The null steady state of system 130 under G={{134,138},{132,136}}, can be calculated from the linear set of equations generated by the connection schemes of G, when all the variable impedance elements have zero impedance.

Connection scheme {134,138} eG represented in Figure 3A, is setting the equation: V(C_λ)+V(C₂) = V_IN (1 )

Connection scheme {132,136} eG represented in Figure 3B, is setting the equation:

V(C_{)-V(C₂) = 0 (2) and the null steady state, which is the solution of (1), (2) set of equations, is:

V_om =V(C_x) = V(C₂) = V_m l2 (3)

Usually a calculation of the analytic solution for a quasi steady state is very complicated. Therefore, for circuit 130 of Figure 2, it is further assumed that:

1. Circuit 130 operates with a constant-frequency time signal of period T.

2. Connection scheme controller 102 of system 100 of Figure 1 , alternately selects the connection schemes of connection scheme set G={{134,138},{132,136}}. 3. Circuit 130 operates under constant load I.

4. All capacitors of circuit 130 are of capacitance C.

5. All variable impedance elements of circuit 130 are of resistance R.

Since circuit 130 works in two phases, the steady state solution is periodic with a period of 2T and can be expressed over one period as:

fV₂₁(t) 0<t<T v_C2(t) =\ ]y₂₂(t-T) T ≤ t < 2T (⁵) '

V (t) and V₂ι(t) are the solutions for the voltages over capacitors d and C₂ correspondingly for connection scheme 144 of Figure 3A. V₁₂(t) and V₂₂(t) are the solutions for the voltages over capacitors C₁ and C₂ correspondingly for connection scheme 146 of Figure 3B.

The set of equations and their boundary conditions defined over V„(t), V₂₁(t), V₁₂(t), V₂₂(t) are: v_IN-v_u-v_2i__cdv_n

v_n-v₂₂ _ _cdv₁₂

(8)

2R dt

c^dv =_I+c^dv (9) dt dt

V_u(0) = V₁₂(T) (10)

V_u(T)=V_n(0) 01)

V₂₁(0) = V₂₂(T) (12) ,

V₂₁(T) = V₂₂(0) (13) and their solution is:

(14)

_M( (15)

wherein the constants k and B are defined by:

k - — e ₀ RC (17)

IT

B = (18)

(l-k)C

The output VOLT of circuit 130 is V₀υτ{t)=Vc^). The average of V_Ouτ ) is:

(19)

Since E[VO_LT] depends on the resistance R, circuit 130 can be designed to reach any positive target output voltage lower than

(V_IN-IT/C)/2. It is noted that for practical systems, the term (V_/N-

\T/C)/2r*V_SN/2, is the output for a null steady state of circuit 130 under set of connection schemes G. For a given load, a system can be designed to achieve any target constant shape voltage function for V₀υτ ) and further target constant shape voltage functions for one or more of the capacitors, as long as voltage function for VO_t t) is compatible with the voltage functions for the capacitors. These constant shape voltage functions incorporate a ripple which is as small as desired.

Reference is now made to Figure 4 which is a schematic illustration of a voltage conversion system for producing reduced ripple output voltages, generally referenced 170, constructed and operative in accordance with an embodiment of the disclosed technique.

System 170 includes a timer 180, connection scheme controller 178, a variable impedance element array 176, a power source array 182, capacitor array 174, control interface 172 and a monitor module 184. Monitor module 184 includes power source monitor 190 and capacitor monitor 188.

Variable impedance element array 176 is coupled with connection scheme controller 178, power source array 182, with capacitor array 174 and with control interface 172. Monitor module 184 is coupled with timer 180, connection scheme controller 178, power source array 182 and with capacitor array 174. Connection scheme controller 178 is further coupled with timer 180 and with control interface 172. Timer 180 is further coupled with control interface 172. Capacitor array 174 is further coupled with power source array 182. The output terminals V₀uτ[1 :N] are some nodes within capacitor array 174. It is noted that two output terminals can be considered as a differential output.

Control interface 172 mediates between the external modules (not shown) and the elements of system 170, in order to introduce control signals to system 170. Control signals may be desired output voltages at one or more output terminals (referenced V_OLT[1 :N]) of system 170, the characteristics of a timing signal produced by timer 180, some additional voltages and/or currents feedback needed by connection scheme controller 102, and the like.

Timer 180 produces a timing signal for changing connection scheme at connection scheme controller 178. It is noted that the timing signal produced by timer 180 may be influenced by control signals from control interface 172 and/or monitored signals from monitor module 184.

Capacitor array 174 includes a plurality of capacitors. Power source array 182 includes one or more power sources, which provide DC voltages at their output. Monitor module 184 monitors electrical parameters (e.g., the voltage between two nodes of capacitor array 174, the voltage of a single node of the capacitor array 174 with respect to a reference voltage, the electrical current at a terminal of a capacitor of capacitor array 174) at capacitor array 174 through capacitor monitor 188 sub-module and monitors the electrical parameters over none or more of the power sources within power source array 182 through power source monitor 190 sub- module. It is noted that monitor module 184 may contain only the capacitor monitor 188.

Variable impedance element array 176 includes variable impedance elements that form some net of connections between the capacitors of capacitor array 174 and the power sources of power source array 182.

Connection scheme controller 178 includes a finite set H of connection schemes sets. At each timing signal from timer 180, connection scheme controller 178 selects the active set of connection schemes G from a set of connection schemes sets H within connection scheme controller 178, and for at least a portion of the time, further according to control signals from control interface 172 and/or monitored signals from monitor module 184. It is noted that control interface 172 can be adapted to receive data or commands for connection scheme controller 178, which are directed, for example, at selecting another connection scheme, modifying the order of the connection schemes within the sequence, changing the impedance of at least one of the variable impedance elements included in at least one of the connection schemes, and the like. Connection scheme controller 178 further selects the active connection scheme from the active set of connection schemes G to be operative at variable impedance element array 176. Connection scheme controller 178 further selects the impedances of the variable impedance elements of variable impedance element array 176, according to control signals from control interface 172 and/or monitored signals from monitor module 184. Variable impedance element array 176 sets the connection scheme and the impedances of variable impedance elements within active connection scheme between the capacitors of capacitor array 174 and the power sources of power source array 182, according to connection scheme controller 178. It is noted that changing the null steady state of system 170 (by changing the active connection schemes set) reduces the power efficiency, thus practical implementation should try to reduce the number of active connection schemes set changes at connection scheme controller 178. Connection scheme controller 178 selects the impedances of variable impedance elements from variable impedance element array 176 in order to reduce output ripple, to achieve constant output voltage at changing conditions (such as changing loads and changing voltages of power sources), and the like. It is noted that connection scheme controller 178 may select the impedances of the variable impedance elements of variable impedance element array 176 at discrete times synchronized with timing signal from timer 180, at discrete times not synchronized with timing signal from timer 180, in a continuous time, and in any other fashion.

The following are examples of the ways to operate timer 180 of system 170, according to its different inputs. For all examples, it is assumed that timer 180's basic waveform is a square clock, f₀ is some basic frequency and that control input Ctrl1 is a binary ("0" or "1") control from control interface 172.

1. The clock frequency of timer 180 is f₀+Ctrl1 ^* f₀.

2. Let V be the voltage of power source Source_! within power source array 182 that is monitored by monitor module 184 and passed to timer

180, and let V₀,V-ι be some threshold voltages. Timer 180's clock frequency is:

• fo V< V₀

• 1.5% V₀<V<V_! • 2^*f₀ else

3. Let Vc be the voltage across capacitor C-i within capacitor array 174 that is monitored by monitor module 184 and passed to timer 180, and let V₀ be some threshold voltage. Timer 180's clock frequency is fo+fo^*(Vc-V₀)/V₀. 4. Let V be the voltage of power source Source_! within power source array 182 that is monitored by monitor module 184 and passed to timer 180, and let V₀ be some threshold voltage. Timer 180's clock frequency is:

• f₀ V<V₀+Ctrl1^*V₀ • 1.5*f₀ else

5. Let V_c be the voltage across capacitor Ci within capacitor array 174 that is monitored by monitor module 184 and passed to timer 180, and let V₀ be some threshold voltage. Timer 180's clock frequency is Ctrl1^*[f₀+fo^*(V_c- Vo)/V₀]. 6. Let V be the voltage of power source Sourcβi within power source array 182 that is monitored by monitor module 184 and let V_c be the voltage across capacitor Ci within capacitor array 174 that is monitored by monitor module 184, both are passed to timer 180. Timer 180's clock frequency will be f₀+fo^*Vc/(V+V_c). 7. Let V be the voltage of power source Source_! within power source array 182 that is monitored by monitor module 184 and let V_c be the voltage across capacitor Ci within capacitor array 174 that is monitored by monitor module 184, both are passed to timer 180. Timer 180's clock frequency 5 will be Ctrl rf₀+f₀*Vc/V.

Reference is now made to Figure 5, which is a schematic illustration of an electric circuitry which implements an example of system 170 of Figure 4, constructed and operative in accordance with a further embodiment of the disclosed technique. Figure 2 illustrates the o connections between capacitors 220 (also referenced C-i), 222 (also referenced C₂), 224 (also referenced C₃) from capacitor array 174 of system 170 of Figure 4, power sources 214 (also referenced V_?), 216 (also referenced V₂) and ground source 212 from power source array 182 of system 170 of Figure 4, and variable impedance elements 230, 232, 234, 5 236, 238, 240 from variable impedance element array 176 of system 170 of Figure 4, generally referenced circuit 210.

The negative terminals of power sources 214 and 216 and the negative terminal of capacitor 224 are all connected together and further connected to ground source 212. Output terminal V_OLT is connected to the o positive terminal of capacitor 220. The negative terminal of capacitor 220 is connected to the positive terminal of power source 214. Variable impedance element 230 is connected between the positive terminal of capacitor 222 and V₀υτ- Variable impedance element 232 is connected between the positive terminal of capacitor 222 and the positive terminal of 5 power source 216. Variable impedance element 234 is connected between the positive terminal of capacitor 224 and the negative terminal of capacitor 222. Variable impedance element 236 is connected between the negative terminal of capacitor 222 and ground source 212. Variable impedance element 238 is connected between the negative terminal of 0 capacitor 220 and the negative terminal of capacitor 222. Variable impedance element 240 is connected between the positive terminal of capacitor 222 and the positive terminal of capacitor 224.

There are two sets of connection schemes defined for system 170 which are G1={{232,234},{236,240},{230,238}} and G2={{232,236},{230,238}}, and let G=G 1 UG2.

Reference is now made to Figure 6A which is a schematic illustration of current flow path through circuit 210 of Figure 5, according to connection scheme {232,234} eG, generally referenced 250.

The negative terminals of power sources 214 and 216 and the negative terminal of capacitor 224 are all connected together and further connected to ground source 212. Output terminal V_OL is connected to the positive terminal of capacitor 220. The negative terminal of capacitor 220 is connected to the positive terminal of power source 214. Variable impedance element 232 is connected between the positive terminal of capacitor 222 and the positive terminal of power source 216. Variable impedance element 234 is connected between the positive terminal of capacitor 224 and the negative terminal of capacitor 222.

Reference is now made to Figure 6B which is a schematic illustration of current flow path through circuit 210 of Figure 5, according to connection scheme {236,240} eG, generally referenced 260.

The negative terminals of power source 214 and the negative terminal of capacitor 224 are connected together and further connected to ground source 212. Output terminal V_OL is connected to the positive terminal of capacitor 220. The negative terminal of capacitor 220 is connected to the positive terminal of power source 214. Variable impedance element 236 is connected between the negative terminal of capacitor 222 and ground source 212. Variable impedance element 240 is connected between the positive terminal of capacitor 222 and the positive terminal of capacitor 224. Reference is now made to Figure 6C which is a schematic illustration of current flow path through circuit 210 of Figure 5, according to connection scheme {230,238} eG, generally referenced 270.

The negative terminal of capacitor 224 is connected to ground source 212. Output terminal OLT is connected to the positive terminal of capacitor 220. The negative terminal of capacitor 220 is connected to the positive terminal of power source 214. Variable impedance element 230 is connected between the positive terminal of capacitor 222 and VOLT. Variable impedance element 238 is connected between the negative terminal of capacitor 220 and the negative terminal of capacitor 222.

Reference is now made to Figure 6D which is a schematic illustration of current flow path through circuit 210 of Figure 5, according to connection scheme {232,236} G, generally referenced 280.

The negative terminals of power sources 214 and 216 and further connected to ground source 212. Output terminal VOLT is connected to the positive terminal of capacitor 220. The negative terminal of capacitor 220 is connected to the positive terminal of power source 214. Variable impedance element 232 is connected between the positive terminal of capacitor 222 and the positive terminal of power source 216. Variable impedance element 236 is connected between the negative terminal of capacitor 222 and ground source 212.

The null steady state of system 170 under set of connection schemes G1 ={{232,234},{236,240},{230,238}} and under set of connection schemes G2={{232,236},{230,238}}, can be calculated from the set of linear equations generated by the connection schemes of G1 ,G2 respectively, when all the variable impedance elements have zero impedance.

Connection scheme {232,234}eG1 presented in Figure 6A, is setting the equation: V(C₂)+V(C₃) =V₂ (20) Connection scheme {236,240}eG1 presented in Figure 6B, is setting the equation:

V(C₂)-V(C₃) = 0 (21 )

Connection scheme {230,238} eG1 ,G2 presented in Figure 6C, is setting the equation: (c₁)-y(c₂)=o (22)

Connection scheme {232,236}eG2 presented in Figure 6D, is setting the equation:

V(C₂) = V₂ (23) The null steady state of system 170 under G1 , which is the solution of (20), (21), (22) set of equations, is: y(c₁) =y(c₂) = (c₃) =y₂ /2 (24)

V_OUT =V₁ +V(C₁) = V_l +V₂ /2 and the null steady state of system 170 under G2, which is the solution of (22), (23) set of equations, is:

V(C_λ) ^V(C₂) = V₂ (25) v_om =v, +v(c_λ)=v +v₂

The following is an example of a way to operate system 170 of Figure 4, when its capacitor array 174 includes capacitors 220, 222, 224, its power source array 182 includes sources 212, 214, 216 and its variable impedance elements array 176 includes variable impedance elements 230, 232, 234, 236, 238, 240. All mentioned capacitors, power sources and variable impedance elements are connected as described at 210 in Figure 5 and the output voltage VOLT is defined identically. Timer 180 produces a constant-frequency timing signal. Let

V_TRGτ (i.e., provided via control interface 172) be the target voltage at the output in the range [V^OAV^ Vi+O.βV_∑]. At each timing signal: 1. System 170 monitors by monitor module 184 the voltage over power sources V V₂ at power source array 182 and V(C-ι), the voltage over capacitor C_? at capacitor array 174.

2. System 170 calculates V_oυτ=Vι+V(C₁). 3. If V_TRGT<VI+0.5V₂, connection scheme controller 178 selects a connection schemes set G1={{232,234},{236,240},{230,238}} to be the active connection schemes set, else connection scheme controller 178 selects connection schemes set G2={{232,236},{230,238}} to be the active connection schemes set. 4. Connection scheme controller 178 selects from the active connection schemes set, the longest non-used connection scheme (or randomly selects between all connection schemes that are longest non-used) to be the active connection scheme.

5. If active connection scheme is first time used since last change to active connection schemes set, scheme controller 178 sets all variable impedance elements within active connection scheme to be Z_CNST (a non-zero, predefined impedance). Else, if VOLT< V r, scheme controller 178 sets all variable impedance elements within active connection scheme to be half their impedance when the active connection scheme has been last time used. Else, scheme controller

178 sets all variable impedance elements within active connection scheme to be 1.1 of their impedance when the active connection scheme has been last time used.

Reference is now made to Figure 7, which is a schematic illustration of the electric connections between capacitors 320 (also referenced C-i), 322 (also referenced C₂), 324 (also referenced C₃) from capacitor array 174 of system 170 of Figure 4, power sources 314 (also referenced Vy) and ground source 312 from power source array 182 of system 170 of Figure 4, and variable impedance elements 330, 332, 334, 336, 338, 340 from variable impedance element array 176 of system 170 of Figure 4, generally referenced circuit 310. The negative terminal of power source 314 and the negative terminal of capacitor 324 are connected together and further connected to ground source 312. The positive terminal of capacitor 320 is connected to the positive terminal of power source 314. Output terminal V_OLT_1] is connected to the negative terminal of capacitor 320. Output terminal ^_OLT[2] is connected to the positive terminal of capacitor 324. Variable impedance element 330 is connected between the positive terminal of capacitor 322 and the positive terminal of capacitor 320. Variable impedance element 332 is connected between the positive terminal of capacitor 322 and VO_LT_LI]- Variable impedance element 334 is connected between the negative terminal of capacitor 322 and V_OLT[1]. Variable impedance element 336 is connected between the negative terminal of capacitor 322 and V_OLT[2]. Variable impedance element 338 is connected between the positive terminal of capacitor 322 and V_OLΠ{2]. Variable impedance element 340 is connected between the negative terminal of capacitor 322 and ground source 312.

The set of connection schemes defined for system 170 is G={{332,336},{330,334},{338,340}}.

Reference is now made to Figure 8A which is a schematic illustration of current flow path through circuit 310 of Figure 7, according to connection scheme {332,336} eG, generally referenced 350.

The negative terminal of power source 314 and the negative terminal of capacitor 324 are connected together and further connected to ground source 312. The positive terminal of capacitor 320 is connected to the positive terminal of power source 314. Output terminal V_OLTLI] is connected to the negative terminal of capacitor 320. Output terminal Vo_Lτ_2] is connected to the positive terminal of capacitor 324. Variable impedance element 332 is connected between the positive terminal of capacitor 322 and V_OLTD]- Variable impedance element 336 is connected between the negative terminal of capacitor 322 and V₀υτ[2]. Reference is now made to Figure 8B which is a schematic illustration of current flow path through circuit 310 of Figure 7, according to connection scheme {330,334}eG, generally referenced 360.

The negative terminal of power source 314 and the negative terminal of capacitor 324 are connected together and further connected to ground source 312. The positive terminal of capacitor 320 is connected to the positive terminal of power source 314. Output terminal V_OLTD] is connected to the negative terminal of capacitor 320. Output terminal _OLT_2] is connected to the positive terminal of capacitor 324. Variable impedance element 330 is connected between the positive terminal of capacitor 322 and the positive terminal of capacitor 320. Variable impedance element 334 is connected between negative terminal of capacitor 322 and V_OLT[2].

Reference is now made to Figure 8C which is a schematic illustration of current flow path through circuit 310 of Figure 7, according to connection scheme {338,340} eG, generally referenced 370.

The negative terminal of power source 314 and the negative terminal of capacitor 324 are connected together and further connected to ground source 312. The positive terminal of capacitor 320 is connected to the positive terminal of power source 314. Output terminal V_OLTD] is connected to the negative terminal of capacitor 320. Output terminal Vo_Lτ[ 3 is connected to the positive terminal of capacitor 324. Variable impedance element 338 is connected between the positive terminal of capacitor 322 and V_OLT_2]. Variable impedance element 340 is connected between the negative terminal of capacitor 322 and ground source 312.

The null steady state of system 170 under G={{332,336},{330,334},{338,340}} can be calculated from the linear set of equations generated by the connection schemes of G, when all the variable impedance elements have zero impedance. Connection scheme {332,336} G presented in Figure 8A, is setting the equation:

V^ + V^ + V^) ^ (26)

Connection scheme {330,334} eG presented in Figure 8B, is setting the equation:

V(C_λ)-V(C₂) = 0 (27)

Connection scheme {338,340}eG presented in Figure 8C, is setting the equation: y(c₂)-y(c₃) = o (28) and the null steady state of system 170 under G, which is the solution of (26) , (27) , (28) set of equations, is:

V(C₁) = y(C₂) =V(C₃) = V₁ /3 (29) v_oorι ] =y₁ -y(c₁) = 2y₁ /3 y_0ϋ7[2] =y(c₃) = y₁ /3 The following is an example of a way to operate system 170 of

Figure 4, when its capacitor array 174 includes capacitors 320, 322, 324, its power source array 182 includes sources 312, 314 and its variable impedance elements array 176 includes variable impedance elements 330, 332, 334, 336, 338, 340. All mentioned capacitors, power sources and variable impedance elements are connected as described at 310 in Figure 7 and the output voltages V_OLTD], VO_LT_.2] is defined identically.

Timer 180 produces a constant-frequency timing signal. Let the target voltage for V_OL_T[1] be 0.6 Vy and the target voltage for V_OLT[2] be

0.3 W 1. At each timing signal, connection scheme controller 178 changes the active connection scheme to be the longest non-used connection scheme from connection schemes set

G={{332,336},{330,334},{338,340}} (or randomly selects between all connection schemes that are longest non-used). 2. Monitor module 184, continually monitors the voltage over power source V_1} at power source array 182 and monitors ViC-_t), V(C₂), the voltages over capacitors C_1} C₂ at capacitor array 174.

3. Connection scheme controller 178, continually adjusts the impedances of variable impedance elements of the active connection scheme to best achieve the target voltages, while maintaining minimal ripple.

It will be appreciated by persons skilled in the art that the disclosed technique is not limited to what has been particularly shown and described hereinabove. Rather the scope of the disclosed technique is defined only by the claims, which follow.

Claims

1. System for converting at least one input voltage signal of at least a selected power source of a power source array including at least one power source, to at least one output voltage signal associated with a respective predetermined electrical current, the system comprising: a capacitor array, said capacitor array including a plurality of capacitors; a variable impedance element array coupled with said power source array and with said capacitor array, said variable impedance element array including a plurality of variable impedance elements; and a connection scheme controller coupled with said variable impedance element array, said connection scheme controller selecting at least one set of connection schemes, said connection schemes in each of said at least one set of connection schemes being represented by a respective set of differential equations, said respective set of differential equations having a respective single solution, said respective single solution defining a plurality of substantially constant shape voltage functions for selected ones of said capacitors with respect to said respective predetermined electrical current, said connection scheme controller operating said variable impedance element array by varying the impedance of respective ones of said variable impedance elements, to apply said connection schemes to said capacitor array and to said power source array, in a sequence, thereby substantially obtaining said respective single solution,

Wherein for at least part of the time, at least one of said substantially constant shape voltage functions, combined with none or more of said at least one input voltage signal, defining said at least one output voltage signal.

2. The system according to claim 1 , wherein said capacitor array is further coupled with said power source array.

3. The system according to either of claims 1 and 2, wherein each of said connection schemes defining a respective unique set of said variable impedance elements being set to non substantially-infinite impedances.

4. The system according to of claim 3, wherein every other of said variable impedance elements, not included in said respective unique set, is being set to substantially-infinite impedances.

5. The system according to claim 3, wherein at least one of said connection schemes defines for at least one of said variable impedance elements included in said respective unique set of said variable impedance elements, a respective plurality of non substantially-infinite impedances.

6. The system according to claim 5, wherein said connection scheme controller continuously sets said at least one of said variable impedance elements, between at least selected ones of said respective plurality of non substantially-infinite impedances.

7. The system according to claim 5, wherein said connection scheme controller sets said at least one of said variable impedance elements, in discrete times, between at least selected ones of said respective plurality of non substantially-infinite impedances.

8 The system according to claim 5, wherein said connection scheme controller sets said at least one of said variable impedance elements, to at least a selected one of said respective plurality of non substantially-infinite impedances during a first activation of the respective at least one of said connection schemes and to at least a selected other of said respective plurality of non substantially-infinite impedances during a second activation of the respective at least one of said connection schemes.

9. The system according to claim 3, wherein said non substantially- infinite impedances are selected from the list consisting of: substantially zero; finite complex impedance; finite real impedance; finite imaginary impedance; and time dependent impedance.

10. The system according to either of claims 1 and 2, wherein at least one of said variable impedance elements includes at least one component selected from the list consisting of: resistor; variable resistor; inductor; variable inductor; capacitor; variable capacitor; semi-conductor element; and electronic circuitry.

1 1 . The system according to either of claims 1 and 2, wherein said connection scheme controller operates said variable impedance element array to move from one of said connection schemes to the next of said connection schemes, according to a timing signal.

12. The system according to either of claims 1 and 2, wherein the type of each said at least one power source is selected from the list consisting of: chemical to electrical sources; mechanical to electrical sources; radiation to electrical sources; heat to electrical sources; and electrical to electrical sources.

13. The system according to either of claims 1 and 2, wherein said sequence is characterized by a positive integer diversity number, and wherein every sub-sequence of said sequence which is at the length of said positive integer diversity number, includes all of the connection schemes of said selected set of connection schemes.

14. The system according to either of claims 1 and 2, wherein said sequence includes cyclic instances of all of said connection schemes of said selected set of connection schemes.

15. The system according to either of claims 1 and 2, wherein each of said variable impedance elements is characterized by a unique voltage-current dependency, and wherein the differential portions of said differential equations are a linear combination of at least selected ones of the derivatives of voltages of said capacitors.

16. System for converting at least one input voltage signal of at least a selected power source of a power source array including at least one power source, to at least one output voltage signal, the system comprising: a capacitor array, said capacitor array including a plurality of capacitors; a variable impedance element array coupled with said power source array and with said capacitor array, said variable impedance element array including a plurality of variable impedance elements; a monitor module, coupled with said capacitor array, said monitor module monitoring at least one electrical parameter at said capacitor array, thereby producing at least one monitored electrical parameter signal; and a connection scheme controller coupled with said variable impedance element array and with said monitor module, said connection scheme controller selecting at least one set of connection schemes, said connection schemes in each of said at least one set of connection schemes being represented by a respective set of differential equations, said respective set of differential equations having a respective single solution, said respective single solution defining a plurality of substantially constant shape voltage functions for selected ones of said capacitors, said connection scheme controller operating said variable impedance element array by varying the impedance of respective ones of said variable impedance elements, to apply said connection schemes to said capacitor array and to said power source array, in a sequence, thereby substantially obtaining said respective single solution, wherein, said connection scheme controller operating said variable impedance element array, for at least part of the time, at least according to said at least one monitored electrical parameter signal, and wherein for at least part of the time, at least one of said substantially constant shape voltage functions, combined with none or more of said at least one input voltage signal, defining said at least one output voltage signal.

17. The system according to claim 16, wherein said capacitor array is 5 coupled with said power source array.

18. The system according to either of claims 16 and 17, wherein each of said connection schemes defining a respective unique set of said variable impedance elements being set to non substantially-infinite o impedances.

19. The system according to of claim 18, wherein every other of said variable impedance elements, not included in said respective unique set, is being set to substantially-infinite impedances. 5

20. The system according to claim 18, said connection scheme controller operates said variable impedance element array, for at least a portion of said at least part of the time, at least according to a selected one of said at least one monitored electrical parameter signal, by changing o the impedance of at least one of said variable impedance elements from non substantially-infinite impedance to substantially-infinite impedance, thereby moving from one of said connection schemes to the next of said connection schemes.

5 21 . The system according to claim 18, said connection scheme controller operates said variable impedance element array, for at least a portion of said at least part of the time, at least according to a selected one of said at least one monitored electrical parameter signal, by changing the impedance of at least one of said variable impedance elements 0 from substantially-infinite impedance to non substantially-infinite impedance, thereby moving from one of said connection schemes to the next of said connection schemes.

22. The system according to claim 18, said connection scheme controller operates said variable impedance element array, for at least a portion of said at least part of the time, at least according to a selected one of said at least one monitored electrical parameter signal, by changing the impedance of at least one of said variable impedance elements from a first non substantially-infinite impedance value to a second non substantially-infinite impedance value.

23. The system according to claim 16, further comprising a timer coupled with said connection scheme controller, for timing changes between said connection schemes.

24. The system according to claim 23, wherein said monitor module is further coupled with said timer, and wherein for at least part of the time, said timer produces a timing signal at least according to said at least one monitored electrical parameter signal.

25. The system according to claim 16, further comprising a control interface coupled with said connection scheme controller, for receiving commands relating to operations selected from the list consisting of: selecting another connection scheme from said at least one set of connection schemes; modifying the order of said connection schemes within said sequence; and changing of the impedance of at least one of said variable impedance elements included in at least one connection scheme within said selected at least one set of connection schemes.

26. The system according to claim 23, further comprising a control interface coupled with said timer, for modifying the operation of said timer.

27. The system according to claim 16, wherein at least one of said connection schemes defines, for at least one of said variable impedance elements included in said respective unique set of said variable impedance elements, a respective plurality of non substantially-infinite impedances.

28. The system according to claim 16, wherein said connection scheme controller continuously sets said at least one of said variable impedance elements, between at least selected ones of said respective plurality of non substantially-infinite impedances.

29. The system according to claim 16, wherein said connection scheme controller sets said at least one of said variable impedance elements, in discrete times, between at least selected ones of said respective plurality of non substantially-infinite impedances.

30. The system according to claim 16, wherein said connection scheme controller sets said at least one of said variable impedance elements, to at least a selected one of said respective plurality of non substantially-infinite impedances during a first activation of the respective at least one of said connection schemes and to at least a selected other of said respective plurality of non substantially-infinite impedances during a second activation of the respective at least one of said connection schemes.

31. The system according to claims 18, wherein said non substantially- infinite impedances are selected from the list consisting of: substantially zero; finite complex impedance; finite real impedance; finite imaginary impedance; and time dependent impedance.

32. The system according to claim 16, wherein at least one of said variable impedance elements includes at least one component selected from the list consisting of: resistor; variable resistor; inductor; variable inductor; capacitor; variable capacitor; semi-conductor element; and electronic circuitry.

33. The system according to claim 16, wherein the type of each said at least one power source is selected from the list consisting of: chemical to electrical sources; mechanical to electrical sources; radiation to electrical sources; heat to electrical sources; and electrical to electrical sources.

34. The system according to claim 16, wherein said sequence is characterized by a positive integer diversity number, and wherein every sub-sequence of said sequence which is at the length of said positive integer diversity number, includes all of the connection schemes of said selected set of connection schemes.

35. The system according to claim 16, wherein said sequence includes cyclic instances of all of said connection schemes of said selected set of connection schemes.

36. The system according to claim 16, wherein each of said variable impedance elements is characterized by a unique voltage-current dependency, and wherein the differential portions of said differential equations are a linear combination of part or all of the derivatives of voltages of said capacitors.

37. The system according to claim 16, wherein each of said at least one electrical parameter is the voltage between two respective nodes of said capacitor array.

38. The system according to claim 16, wherein each of said at least one electrical parameter is the voltage of a respective node of said capacitor array.

39. The system according to claim 16, wherein each of said at least one electrical parameter is the electrical current at a terminal of at least a respective capacitor of said capacitor array.

40. The system according to claim 25, wherein said commands are selected from the list consisting of: a temperature control signal; and a target value for at least one of said at least one output voltage signal.