WO2003001644A1

WO2003001644A1 - An arrangement and a method in a dc system

Info

Publication number: WO2003001644A1
Application number: PCT/SE2001/001454
Authority: WO
Inventors: Göran LÖF
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2001-06-21
Filing date: 2001-06-21
Publication date: 2003-01-03
Also published as: GB2392027A; GB2392027B; GB0328010D0

Abstract

A DC system (31) is fed by an external power source (6, 7). When power fails, circuits (32) in the system are to be rapidly alerted (S1) to save unstored information, before the input DC (S4) has fallen too low. A capacitor device (34) is connected to the system input (30) and a current (I1) in the capacitor connection (37) is detected (36). When power fails the current (I1) flows from the capacitor device (34) and a detection circuit (36) generates a corresponding signal. This signal is delayed a predetermined time interval into an alerting signal (S1), which is transmitted to the DC circuit (32). Delaying the signal before the alerting ensures that a very short fail in the DC voltage (S4), or ripple in this voltage, will not unnecessarily alert the DC circuit (32) to start saving information.

Description

AN ARRANGEMENT AND A METHOD IN A DC SYSTEM TECHNICAL FIELD OF THE INVENTION

The present invention relates to an arrangement and a method in a DC system for detecting presence of DC power supply to the system from an external power source.

DESCRIPTION OF RELATED ART

Many DC systems involves a data store for storage of information. In a situation when the DC feeding power is lost some still unstored information can get lost. Therefore a correct and immediate power loss indication is required to make it possible to save the unstored information before the DC voltage falls below a minimum working voltage, at which the function of the DC system will stop. It must also be able to get time to inform other connected systems of the loss of system power.

An example is a DC system that is powered by an AC power source via an AC/DC converter. If the converter is external to the DC system the AC side of the converter is not accessable in the connected DC system for detection of status. The AC side can e.g. be common mains supply of 230V, 50 Hz and the DC side is low voltage, about 10 volts. A complicated isolation is required to directly detect the AC from the DC side. Instead the voltage on the DC side, the input to the system, is sensed to make it possible to detect that the AC is lost. Here a problem arises that the minimum working DC voltage for the system is often close to the AC/DC converter DC output voltage, especially at low AC voltage (nominal voltage minus 10 %) . As the DC voltage is continuously dropping when the AC is lost, the time from the voltage detection of the AC loss to the time for the minimum working DC voltage for the system is very short. It is therefore also difficult to generate a reliable alerting signal to the DC system. As an alternative to the above the DC system can be powered from some type of DC backup circuit. In the U.S. patent No. 5,978,236 is disclosed a DC circuit powered by an AC source via a rectifier. To maintain function in the DC circuit during AC loss, a rechargeable battery is connected to the DC circuit input via a power converter. Depending on need the battery is charged or discharged and the direction of the current flow is sensed by the power converter.

The U.S. patent No. 6,108,217 discloses a terminal device with a backup power circuit having an energy storage device. The terminal is normally powered from a main power source. The terminal has a first circuit operating at a higher voltage and second circuit operating at a lower voltage. The storage device is charged at the higher voltage and is discharged to the second circuit at the lower voltage when the main power source is lost and the voltage to the first circuit is too low. Backup power is stored automatically and the loss of the main power is detected.

The U.S. patent No. 5,771,161 discloses a DC link circuit coupled to a supplementary DC power source. The latter is a rectifier circuit connected to a storage capacitor. When the DC link drops in voltage due to loss of a feeding AC circuit this voltage drop is sensed and the storage capacitor provides DC power.

SUMMARY OF THE INVENTION

The present invention relates to the abovementioned DC system which is powered by an external power source. A main problem is to quickly detect on the DC input of the system when the power is lost.

A further problem is to generate a power loss indicating signal for the DC system. Still a problem is to generate a correct, reliable power loss signal that does not unnecessarily alert the DC system

The problem is solved by a capacitor device being connected to a DC input of the system. A current flow direction between the DC system input and the capacitor is sensed.

More closely, when the direction of the current flow from the capacitor device to the DC input is sensed, a detecting signal is generated to detect the power loss.

The problem of generating the power loss signal in a reliable way is solved by delaying the detecting signal to guarantee that this signal alerts the DC system only when the external power is lost for more than a very short time interval.

A purpose with the invention is to quickly detect power loss for a DC system fed by an external power source.

Another purpose is to generate a correct, reliable power loss indicating signal for the DC system.

Still a purpose is to alert the DC system in good time before its DC function is lost due to low feeding DC voltage but not to unnecessarily alert the DC system.

An advantage with the invention is that power loss for the DC system can be quickly detected.

Another advantage is that a correct, reliable power loss indication signal can be generated.

Still an advantage is that the DC system can be alerted in good time before loss of the DC function due to low feeding DC voltage and that a very short power loss does not alert the DC system. The invention will now be described more in detail with the aid of prefered embodiments in connection with enclosed figures .

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a block diagram over a prior art system;

Figure 2 shows a time diagram over voltages in the system;

Figure 3 shows a block diagram over an inventive system;

Figure 4 shows a more detailed block diagram over a part of the inventive system;

Figure 5 shows a time diagram over voltages in the inventive system;

Figures 6a-βe show time diagrams over voltages and currents;

Figures 7a-7d show alternative time diagrams over voltages and currents; and

Figure 8 shows a flow chart over an inventive method.

DETAILED DESCRIPTION OF EMBODIMENTS

In figure 1 is shown a prior art device for detecting presence of power supply. A DC system 1 includes a DC circuit 2 and a DC voltage sensing circuit 3. The DC circuit has a control input 4, which is connected to the voltage sensing circuit, and a power input 5 which is connected to both a sensing input on the voltage sensing circuit and to a DC power output 8 on an AC/DC converter 6. The latter has an input 9 connected to an AC power source 7 and both the converter 6 and the power source 7 are external to the DC system 1. Therefore they are not accessable in a simple way for detection of status in the DC system 1. The AC side is common mains supply of 230 volts and the DC side is low voltage, about 10 volts, and a complicated isolation is required to directly detect the AC from the DC side. If the AC power is lost the voltage sensing circuit 3 senses this on the DC side of the AC/DC converter 6. A signal input 10 and a signal output 11 are also shown in the figure.

The DC circuit 2 includes a data store. If the AC power goes down the circuit 2 must either be powered from an alternative source or, as in figure 1, be alerted by the circuit 3 to save still unsaved data before the system DC power is totally lost. The problem with the latter method is to get time enough to stor the data, as will be more closely described in connection with figure 2.

Figure 2 is a diagram for the prior art device in figure 1, in which T denotes time and VDC denotes DC voltage from the AC/DC converter. The nominal DC voltage is denoted by Vnom, a curve 21 shows the voltage Vnom+ 10% and a curve 22 shows the voltage Vnom-10%. The variations in DC voltage depends on a corresponding variation in the 230 V input AC voltage, which is normally permitted to vary +10% and -10%. It should be noted that the curves 21 and 22 only show the main behaviour of the DC voltage. Details in the curves will be described later in connection with figure 6. At a moment Tl the power source 7 is lost and the voltage VDC starts to fall. At a voltage VI, corresponding to a moment T2 or T4 the falling voltage is sensed by the DC voltage sensing circuit 3. The function of the DC circuit 2 goes off due to too low DC input at a voltage V2 corresponding to a moment T3 or T5. A time interval T3-T2 is about 30 ms and is a very short time to store unsaved information in the circuit 2. The reason why the detection is made so late as at the moments T2 and T4 is firstly that the voltage detection can only be performed at one and the same voltage VI, which must work also for the curve 22. Secondly there must be a safety margin to avoid unnecessary alerting of the DC system and also a ripple in the detected DC voltage must be covered.

Figure 3 is a brief block diagram over an inventive arrangement. The AC power source 7 is connected to the AC/DC converter 6 at the input 9. The DC power output 8 of the converter is connected to an input 30 of a DC system 31. This system includes a DC circuit 32 having a DC power input 33 connected to the input 30. The system also includes a capacitor device 34 having a terminal 35 of the capacitor connected to the input 33 via a line 37. A current direction sensing circuit 36 has an input 38, which is connected to the wire 37, and a control output 39 connected to the DC circuit 32. The latter has a signal input 40 and a signal output 41. The sensing circuit 36 senses the direction of a current II in the connecting line 37. The sensing of this current direction is utilised to detect presence of power supply from the AC/DC converter 6 to the DC system 31. When the output 8 of the AC/DC converter 6 has a higher voltage than the terminal 35 of the capacitor device 34, the current flows in a direction to the capacitor device until it is fully loaded, as is exemplified in the figure. If the DC voltage at the output 8 (or input 30) falls when the capacitor device 34 is fully loaded, then the current II starts to flow in the opposite direction. As mentioned earlier, the presence of power supply is sensed at the input 30 because the AC power source 7 and the AC/DC converter 6 are external to the DC system 31 and the AC side is difficult to access from the system 31. The sensing of the presence of power supply is used to generate an alerting signal SI when the power supply is lost. The DC circuit 32 is alerted by the signal SI to e.g. save unstored information before the DC input voltage has fallen to a too low level.

Figure 4 shows parts of the arrangement in figure 3 some more in detail. The capacitor device is exemplified by a single capacitor Cl with the terminal 35 connected to the line 37 and an opposite terminal connected to a reference potential device 45. The current direction sensing circuit 36 includes a resistor Rl connected in the line 37. A comparator 42 has inputs 42a and 42b connected parallelly over the terminals of the resistor Rl, these terminals constituting the input 38 to the current direction sensing circuit 36. The latter has an output 42c connected to a delay circuit 43, which has the control output 39 for the alerting signal SI. The comparator generates a current direction signal S2 to the delay circuit 43. As will be described in connection with figure 6, the delay circuit is used to guarantee that the alerting signal SI is correct and reliable. A DC/DC converter 44 in the DC circuit 32 is connected to the DC power input 33 to generate a smoothend DC voltage having a predetermined voltage. A capacitor C2 is connected between the DC system input 30 and the reference potential device to filter the DC voltage from the converter 6. The converter emits a voltage S3 which is filtered into a voltage S4 by the capacitor C2.

Figure 5 shows the diagram from figure 2 with the voltage curves 21 and 22 and the moment Tl when the AC power source 7 gets lost. The diagram illustrates the detection of the presence of power supply in the DC system 31 with the aid of the inventive arrangement. It is presumed that the DC system 31 has been connected to the AC/DC converter 6 for a while and that the capacitor has reached its top voltage, e.g. the voltage Vnom + 10% according to curve 21. At the moment Tl, when the source 7 gets lost, the potential of the input 30 starts to fall according to curve 21. As the capacitor Cl has its top voltage, the current II starts to flow in a direction from the capacitor terminal 35 towards the DC power input 33. A voltage drop arises over the resistor Rl such that the input 42a of the comparator 42 will have lower potential than the input 42b. The comparator 42 senses this voltage drop and generates the current direction signal S2, which is transmitted to the delay circuit 43. This circuit generates the alerting signal SI, which is transmitted to the DC circuit 32. When receiving the alerting signal the DC circuit starts to save unstored information. This saving process can go on until the moment T5 when the DC input voltage to the circuit 32 has the level V2, which is so low that the DC circuit goes off. The time interval T5-T6 for saving information is about 150 ms.

If the AC power source 7 operates at its lower voltage Vnom- 10% according to the curve 22 and the power source gets lost, the DC circuit 32 goes off at the moment T3. The time interval T3-T6 for saving information will then be about 65 ms .

It can seem contradictory to have the delay circuit connected to the comparator and delay the signal S2 as it is also emphasized that the alerting signal SI must be swiftly generated. A main reason for the delaying is that the DC output voltage from the AC/DC converter 6 has a ripple as mentioned above. This ripple influences the detection of an eventually lost AC source as will be more closely described in connection with figures 6a-6e. Another reason for the delay is that a very short loss of the AC source may not unnecessarily start the saving of information in the DC system, as will be discussed in connection with figures 7a- 7d.

Figure 6a is a diagram in which T denotes time as above and V denotes a voltage. The figure shows the fullwave rectified voltage S3 from the AC/DC converter 6.

Figure 6b is a corresponding time diagram showing the raw voltage S4 having a ripple period DT4.

Figure 6c is a time diagram in which A denotes current. The figure shows the current II through line 37 and the resistor Rl, between the input 30 and the capacitor terminal 35. When the current II in the diagram is below the time axis, a range 61, it flows out from the capacitor Cl and when the current is over the time axis, a range 62, it flows into the capacitor Cl.

Figure 6d is also a time diagram and V denotes as above voltage. The figure shows the current direction signal S2 at the comparator output. The signal S2 is a rectangular pulse train with the same frequency as the voltage S3.

Figure 6e, also a time diagram, shows the alerting signal

SI.

In normal operation, before the moment Tl when the AC is lost, every pulse in the voltage S3 gives rise to a corresponding pulse in the voltage S4 in wellknown manner. The voltage S4 generates the current II, which flows back and forth in the resistor Rl . The comparator 42 generates the rectangular pulses in the signal S2, one of the pulses starting at a moment T7 and stopping at a moment T8. The start moment T7 is when the current II begins to rise and the stop moment T8 is when the current II passes zero level in the diagram and begins to flow in the direction from the capacitor. The pulses give rise to the alerting signal SI having a normal voltage level V3. This level is held by the delay circuit 43 until a moment T10, but already at an erlier moment T9 a new pulse in the signal S2 takes over and keeps the signal Si at the normal voltage level V3.

When the AC current is lost the following happens. At the moment Tl the fullwave rectified voltage S3 falls to zero level. The voltage S4 falls continuously, as shown by the dotted line 60. Also the current II falls continuously as shown by a dotted line 63, even after a normal period for the current II has ended. The last pulse in the signal S2, starting at the moment T9, keeps the level of the alerting signal SI unchanged during its duration. The delay circuit also keeps the alerting signal SI unchanged during the last delay interval 64. When this delay interval ends at the moment T6 the level of the alerting signal SI drops to zero, which initiates the DC circuit 32 to start to store unsaved information.

It is illustrative to compare the above with the prior art voltage detection. At the moment T6 the voltage S4 has fallen only a very little amount below its normally lowest level V0 and it is a very uncertain value to use as alerting signal. To get a rasonably reliable voltage level one has to wait until the voltage S4 has fallen to the level VI at the moment T2.

A further example on how the inventive arrangement works will be given below in connection with figures 7a-7d. These figures show time diagrams with voltages and currents for the arrangement in figure 4.

Figure 7a shows a diagram with a voltage S5, which is intended to be a constant input voltage V3 to the DC system 31 in figure 3. Figure 7b shows a diagram with a current 12 through the resistor Rl. Figure 7c shows a diagram with the current direction signal 32 and figure 7d shows a diagram with the alerting signal Si.

The voltage S5 has its constant value V3 until the moment Tl, when a feeding voltage is lost for a time interval DTI. After this interval the voltage rises to its normal value again. During the interval DTI the capacitor is discharged and after the interval, at a moment Til, the current 12 turns direction and the capacitor is recharged. The current direction signal S2 falls to zero at the moment Tl and rises to its normal value at the moment Til. The delay circuit 43 keeps the signal SI at its normal constant value during a time interval DT2. At the end of the interval DT2 the current direction signal has rised to its normal value again and keeps the signal SI at its normal value. The DC circuit 32 is not alerted to start storing unsaved information.

In figure 7a the moment T5 is given, when the input voltage S5 has fallen to the value V2 and the DC circuit stops to work. The alerting signal must be transmitted to the DC circuit in good time prior to that, but a fail in the input voltage of the duration of the interval DTI is acceptable and should not lead to a start for storing unsaved information. It is demonstrated that this is the case. If on the other hand the feeding voltage had been lost for a longer time interval DT3 an alerting signal had been transmitted to the DC circuits to store information.

It is apparent from the above that if the inventive arrangement is utilised, the DC circuit can reliably save unstored information during a longer time interval than if prior art voltage sensing is utilised. The exemplified prior art device will give the time interval 30 ms while the exemplified inventive device will give 65 ms in the worst case and 150 ms in the best case. It is also apparent that an alerting signal to store information is not unnecessarily generated when using the invention. The capacitance value of the capacitor device can be selected from case to case to give the time required to save unstored information.

In connection with the flow chart in figure 8, the method of detecting presence of power supply and alerting the DC system will be described in summary. The method can be performed by the arrangement described in connection with figure 3 or figure 4.

In a first step 80 the current II is generated through the resistor Rl with the aid of the capacitor device 34. In a step 81 the current direction sensing device 36, including the resistor Rl and the comparator 42, senses the current direction in the connecting line 37. In a following step 82 the current direction signal S2 is generated by the comparator 42. The current direction signal S2 is delayed the delay interval in the delay circuit 43, step 83. In a step 84 it is decided whether the feeding voltage is lost after the end of the delay interval. In an alternative "NO" no alerting signal is generated and the DC system is let to run, step 85. In an alternative "YES" the alerting signal Si is generated in dependence on the signal S2 in a step 86. In a step 87 the alerting signal SI is transmitted to the DC circuit 32 from the delay circuit 43 and in a step 88 the DC system starts to store unsaved information.

Claims

1. An arrangement for detecting presence of power supply in a DC system (31), the arrangement including:

an external DC source (6) having a DC output (8) for connection to a DC fed circuit (32) ;

a device (34,36) for power loss detection connected to the DC output,

characterized in that the arrangement includes:

a capacitor device (34) having a connection (37) from one of its terminals (35) to said DC output (8) ;

a sensing device (36) connected (38) to said capacitor device connection (37) , sensing a flow direction of a current (II) in the capacitor device connection.

2. An arrangement for detecting presence of power supply from an external power source (6,7) to a DC system (31), the arrangement including a detecting device (34,46) connected to a DC supply input (30) to the DC system, characterized in that the arrangement includes:

- a capacitor device (34) having a connection (37) from one of its terminals (35) to said DC supply input;

a sensing device (36) connected to said capacitor device connection (37), sensing a flow direction of a current (II) in the capacitor device connection.

3. An arrangement according to claim 1 or 2 characterized in that the sensing device (36) is arranged to generate an alerting signal (SI) when the current (II) in the capacitor device connection (37) flows in a direction from the capacitor.

4. An arrangement according to claim 1 or 2, characterized in that the arrangement includes a delay circuit (43) which is connected to the sensing device (36,42)), the sensing device being arranged to generate a current direction signal (S2), which is delayed in the delay circuit to form the alerting signal (SI) .

5. An arrangement according to claim 4, wherein the supplied power includes a DC voltage (S3,S4) with a periodic ripple, characterized in that the delay circuit (43) delays the current direction signal (S2) a time interval (64; T8-T10) of at least one half period (DT4) for the DC voltage ripple.

6. An arrangement according to claim 3, 4 or 5 characterized in the sensing device (36,42) being arranged to transmit the alerting signal (SI) to the DC system (32).

7. A method for detecting presence of power supply to a DC system (31) , the DC system having a DC input (30) for connection to an external DC suorce (6), the method including detecting power loss at the DC input, characterized in that the method includes:

sensing (81) a flow direction of a current (II) in a connection (37) between a terminal (35) of a capacitor device (34) and said DC input; and

generating (82) a current direction signal (S2) in dependence on said current flow direction.

8. A method according to claim 7, characterized in generating (86) an alerting signal (SI) in dependence on the current direction signal (S2) when the current (II) in the capacitor connection (37) flows in a direction from the capacitor device (34) .

9. A method according to claim 7, characterized in

delaying (83) the current direction signal signal (S2) ; and

generating (82) an alerting signal (SI) in dependence on the delayed current direction signal (S2) .

10. A method according to claim 9, wherein the supplied power includes a DC voltage (S3,S4) with a periodic ripple, characterized in delaying the current direction signal (S2) a time interval (64) of at least one half of a period (DT4) for the DC voltage ripple.

11. A method according to claim 8, 9 or 10, characterized in transmitting (87) the alerting signal to the DC system (32) .