WO1999009639A2

WO1999009639A2 - Full wave converter switching at zero voltage

Info

Publication number: WO1999009639A2
Application number: PCT/US1998/017264
Authority: WO
Inventors: Dennis J. Solley
Original assignee: International Power Systems
Priority date: 1997-08-20
Filing date: 1998-08-20
Publication date: 1999-02-25

Abstract

A full wave DC-DC converter is operated with two primary switches across a capacitor bank comprising two capacitors in series. Between the mid-point of the capacitor bank and the mid-point of the primary switches is connected the primary winding of an isolation transformer. Across the primary winding is connected a clamping circuit comprising a series combination of two auxiliary switches. At certain times during each switching period, the clamping circuit maintains the energy stored in the transformer. All the switches are operated through control logic so that no primary switch is ON at the same time. A predetermined time is provided between turning OFF each auxiliary switch and turning ON the next appropriate primary switch. During this predetermined time, the transformer's magnetizing energy is released to charge/discharge parasitic circuit capacitances and achieve zero voltage switching conditions for the primary switches. Current discharge into the transformer secondary during this predetermined time is limited either by saturable reactors in series with the secondary forward rectifiers or by selectively controlled rectifiers.

Description

FULL WAVE CONVERTER SWITCHING AT ZERO VOLTAGE Field of the Invention

This invention relates generally to power converters and, more particularly, to a DC to DC zero voltage switching converter .

Background of the Invention

Zero voltage switching techniques were developed in response to the demand for small, efficient, light weight switching power supplies capable of processing power at high frequency typically above 200KHz and at high power density typically above 20Watts/cu. in. Zero voltage switching has evolved in the 1990 's from earlier innovations such as zero current switching in the 1980 's and prior resonant techniques. All these techniques attempt to "use" rather than to fight the parasitics, namely stray capacitance and leakage inductance, associated with semiconductors and magnetics, during each switching cycle.

By using the parasitics, it is possible to increase the power processing fundamental frequency without paying a large penalty in power dissipation because of "snubbing" losses. There is an added benefit to these techniques in that they have controlled current and voltage transients (dV/dt's and dl/dt's) which reduces the amount of conducted and radiated noise generated from the power conversion process . U.S. Patent No. 5,126,931 to Jitaru discloses the concept of zero voltage switching. By the addition of an auxiliary switch, a reset capacitor, and a particular combination of switch commutations it is possible to use the energy stored in the primary inductance of the isolating transformer to drive the voltage across the main switch to zero volts before that switch is turned on. In this way, the energy dissipated to force all circuit capacitances from a high voltage to zero each switching cycle is eliminated. Another major feature of this technique involves clamping the main transformer's leakage inductance via the reset capacitor and cycling it losslessly. Also, during each cycle, the main transformer is reset in the third quadrant of its B-H loop. A feature, which in principle allows for a more efficient transformer design, but which is difficult to realize if high switching frequencies are employed. Hysteresis losses in the transformer core will limit the usable flux swing.

While processing power from a low input voltage (48VDC) for telecommunication purposes, the ZVS single-ended forward converter is close to being an optimum solution. At higher power levels and in off-line applications, employing zero voltage switching techniques with full wave topologies such as the half bridge or full bridge may offer a better solution. The voltage stress on the switching FETs is lowered, as is voltage that the parasitic circuit capacitances are discharged from. That is, less inductive energy per cycle is required to achieve ZVS operation.

Brief Summary of the Invention The present invention utilizes an active clamp circuit, comprised of not one but two auxiliary switches connected in series. This bilateral switch allows current to selectively flow in either direction and may be constructed from bipolar transistors, insulated gate transistors (IGBT) or MOSFET transistors having N or P channels. External diodes or integral body diodes may be employed with these devices to selectively block, or allow the passage of current in both directions. N-channel MOSFET devices having an integral body diode will be used as the preferred embodiment to implement the active clamp for the purposes of this discussion. This active clamp is connected in various configurations across any winding of a power transformer to clamp both the energy accumulated in the magnetic field and also the magnetic flux of the transformer of any full wave converter for a period of time determined by the control function. At the end of this time, the active clamp is released and the stored energy allowed to charge/discharge the output capacitance of the primary switches and any additional parasitic circuit capacitances to facilitate zero voltage switching (ZVS) also referred to as zero voltage transition (ZVT) switching. The benefits of ZVS or "soft switching" converters compared to "hard switched" converters are well documented: absence of capacitive switching loss, absence of transistor turn-on loss, controlled dV/dt and dl/dt transitions reducing conducted and radiated electromagnetic emissions, constant frequency PWM operation and efficiency improvements in the gate drive of power MOSFETS due to the absence of Miller effects. In the case of the single switch forward converter, other advantages include extended duty cycle operation beyond 50% and operation of the transformer core into the third quadrant of the B-H loop.

One potential disadvantage of all ZVS single ended forward converters, is that during line or load transients, the dc flux in the transformer core moves from zero towards positive or negative saturation Bs . During this time the voltage across the active clamp reset capacitor is being charged/discharged to its new equilibrium value. The amount of saturation is determined by the rate of change of duty cycle dD/dt generated by the transient, the primary magnetizing inductance and the value of the reset capacitor. The invention transfers ZVS benefits to any full wave topology, but as no reset capacitor is required, eliminates the potential failure mechanism described above. The discussion is referenced to a ZVS half bridge converter and extended to full bridge and the family of center-tapped push-pull converters.

The invention is a half bridge, zero voltage switching, DC-DC converter, having a primary and secondary windings. Each of the two primary switches alternately couples half the input voltage across the primary winding of the transformer. Two auxiliary switches selectively allow the voltage across each primary switch to reach zero sequentially. The primary switches and the auxiliary switches each have an OFF period and an ON period. One auxiliary switch is non- conductive prior to the ON period of the next appropriate primary switch in the switching cycle, for a predetermined period sufficient to allow the voltage across the primary switch to reach zero voltage. This auxiliary switch remains non-conductive for a period after the appropriate primary switch is turned OFF. A fifth and sixth secondary switch is coupled in series with the secondary windings of the trans- former and selectively remain at least partially non- conductive as the voltage across the appropriate primary switch decreases. These fifth and sixth switches become conductive when the voltage across the appropriate main switch reaches zero. Two rectifiers are selectively coupled with the fifth and sixth secondary switches for the means of conducting current to the output. A control circuit selectively operates the main switches, the auxiliary switches and the secondary switches to transfer energy through the converter by modification of the duty cycle of operation of at least the main and auxiliary switches to turn ON the primary switches at zero voltage. In the preferred embodiment, the fifth and sixth secondary switches are saturable reactors.

The converter may comprise discrete resonant capacitors in parallel with the main switches. In one embodiment, each secondary switch and rectifier comprise a unidirectionally controlled switch circuit. The unidirectional controlled switch circuits are selectively operated by the control circuit, so that they remain non- conductive until after the voltage across the appropriate main switch reaches zero and conductive during the appropriate ON time of the main switch.

In another embodiment, the transformer comprises a plurality of secondary windings. In another embodiment, the half bridge topology may be exchanged for a full bridge topology with the necessary drive signals for the two additional two primary switches being provided by the control circuit .

In yet another embodiment, a bifilar winding may be wound with primary of the isolation transformer and the auxiliary switches may be series connected across the bifilar winding .

The converter further comprises a load in parallel with a filter capacitor and a load inductor.

The control circuit comprises a sensory circuit for sensing the voltage across the load. The control circuit maintains a constant voltage across the load by varying the ON period of the primary switches, the auxiliary switches and also the secondary switches, if saturable reactors are not employed.

The converter further comprises a voltage reference. The control compares the difference in voltage across the load and the voltage reference. The difference may be directly used to modulate the switches ON time as in voltage mode control. Alternatively, the difference may be compared to an average current or a peak event sensed in the power train before switch modulation is performed as in current mode control .

The invention is a half bridge converter in which energy is transferred from a primary winding to a secondary winding of a transformer during each ON period of the primary switches. A circuit is provided for maintaining the magnetic energy stored in the transformer during the OFF period of the primary switches. When this energy is released, it charges/ discharges the voltage across any capacitance associated with the primary switches, the transformer winding and the printed wiring board. In particular, it discharges the voltage across the appropriate primary switch to zero, prior to turn ON of that switch. Two auxiliary switches, each including an anti- parallel diode, is coupled in series connection. A switch control circuit operates the auxiliary switches including the anti-parallel diode in accordance with the control logic such that: (a) one auxiliary switch including the anti- parallel diode is opened prior to the ON period of the appropriate primary switch for a period of time sufficient to discharge the output capacitance of the primary switch;

(b) each auxiliary switch including the anti- parallel diode closes after a period of time after the primary switch is driven OFF. This period of time is sufficient to allow the mid point of the primary switches to charge to the mid point of the input source .

In the illustrated embodiment, the primary and/or auxiliary switches may comprise a field effect transistor in parallel with a discrete and/or a body diode, but are not limited to this type of semiconductor.

The converter further comprises a circuit for inhibiting current flow in the secondary windings of the transformer until the output capacitance of the appropriate primary switch is discharged. The invention is also a method of operating a half bridge DC to DC converter comprising the steps of storing energy in a primary winding of a transformer by flowing AC current through the primary winding in series with two primary switches. After each primary switch is turned OFF an auxiliary switch in a series connection with a diode (body diode of the other auxiliary switch) and across the primary of the transformer clamps the transformer voltage to almost zero.

The circulating current, consisting of primary load current and magnetizing current is commutated from the body diode of the second auxiliary switch to its channel by control action. The turn ON of the second auxiliary switch is also accomplished under zero voltage conditions. The transformer's energy including leakage is then clamped by both auxiliary switches to zero volts. After a time determined by the control circuit, the auxiliary switch is opened allowing the transformer's energy to drive the primary switch and circuit capacitances to the other input bus. The voltage across the appropriate primary switch is reduced to zero, thereby allowing the switch to turn on at zero voltage. Voltage discharge is implemented in part and facilitated by selective opening of the appropriate secondary switch in series with one of the secondary windings of the transformer. Other objects and advantages of the present invention will become apparent after reading the detailed description of the present invention.

Brief Description of the Drawings

The accompanying drawings illustrate preferred embodiments of the invention according to the practical application of the principles thereof, and in which:

Figure 1 is a schematic of a half bridge converter made in accordance with the teachings of the present invention. Figures 2a - 2k are timing diagrams for the schematic of Figure 1.

Figure 3 shows one embodiment of the invention where the active clamp is placed across a bifilar winding of the transformer. Figure 4 shows one embodiment of the invention where the active clamp is placed across a center-tapped transformer secondary winding.

Figure 5 shows one embodiment of the invention where the active clamp is placed across the transformer secondary winding of a current doubler.

Figure 6 shows one embodiment of the invention where the active clamp is placed across the transformer of a full bridge converter.

Figure 7 shows one embodiment of the invention where three active clamps are placed across the phases of a three phase motor-control bridge.

Figure 8 shows one embodiment of the invention where two active clamps are placed across each primary winding of a center-tapped push-pull converter. Figure 9 shows one embodiment of the invention where one active clamp is placed across both primary windings of a center-tapped push-pull converter.

Detailed Description of Preferred Embodiments

The invention is now described with reference to the accompanying figures.

Referring to Figure 1, there is shown a half bridge DC-DC converter is operated with two primary switches in series circuit with a primary winding of the isolation transformer and two auxiliary switches which provide a clamping function across the primary winding. The main switches and auxiliary switches are operated through control logic, so that no primary switch is ON at the same time. A combination of the magnetizing current plus the load current that is cycled by auxiliary field effect transistors generates the zero voltage action. A predetermined time T4-T3 is provided between turning OFF the appropriate auxiliary switch to allow the output capacitance of both main switches and all other circuit parasitic capacitance to be charged/discharged from the mid-point of the DC source to one or the other rail. Current flow into the secondary of the transformer during this time period is limited by secondary switches, which may be either a saturable reactor in series with the secondary or a selectively controlled switch. A second predetermined time "T2-T1" is provided between turning OFF the primary switch and turning ON the appropriate auxiliary switch to allow the voltage at the midpoint of the primary switches to charge from zero to the midpoint of the input voltage source.

With reference to Figure 1 wherein the methodology of the invention is illustrated, primary switches SI and S2 and auxiliary switches S3 and S4 are MOSFETS which are the preferred choice because of the existence within the such devices of body diodes Dl, D2, D3 and D4 respectively, to provide a reverse current flow without an additional external diode. In Figure 1, the circuit equivalent of the actual MOSFET devices has been illustrated within a dotted outline.

The body diodes Dl, D2, D3 and D4 thus represent the parasitic diode within the actual MOSFET. External diodes may be paralleled across SI, S2, S3 or S4 to enhance circuit performance. Similarly, the circuit equivalent of a transformer Tl is illustrated within a dotted outline and includes the parasitic magnetization inductance Lm and the parasitic leakage inductance Lk. Control signals VGl, VG2 , VG3 and VG4 are provided to the gates of the MOSFETS SI, S2 , S3 and S4 from a control circuit, the timing of which is described in greater detail in connection with Figures 2 and 3.

A description of one cycle of the circuit operation follows .

Mode 1 (TO - Tl) Assume the primary switch SI is ON driven by its control signal VGl. Energy flows from the input source VI and the bulk capacitors Cl, C2 through the primary of transformer Tl and switch SI and flows to the output via the secondary winding TS1 and secondary switch S5 and rectifier D5. Auxiliary switch S3 is gated ON by its gate drive VG3 but auxiliary switch S4 is OFF, hence the active clamp selectively blocks the flow of current during Mode 1. The primary switch Si conducts load current and transformer magnetizing current which has a value of -Imag at time "TO" increasing linearly to +Imag at time "Tl".

The change in magnetizing current is defined by:

D ( Imag) = 2 * Imag = { V\ / 2 * ( Tl - TO) } / Lm

The current through the output inductor also increases during this interval by:

D { I ( Lo) } = { ( Vs - Vo) * ( Tl - TO) } / Lo

where VS is the voltage appearing before Lo in Figure 2j . The effect of these current changes appears in the switch SI current waveform shown in Figure 2f.

Mode 2 (Tl- T2)

Gate drive signal VGl turns switch SI OFF at time Tl . The load current and magnetizing current flowing in SI is commutated from its channel to its output capacitance Cl. The switch current I(Sw) charges the output capacitance Cl from zero volts and discharges the output capacitance C2 initially at VI volts in a linear ramp, together with all other circuit capacitances connected to this circuit node VN in Figure 2e. When the voltage across Cl reaches half of the input source, VI/2, the body diode D4 of auxiliary switch S4 conducts, clamping the transformer primary and leakage inductance Lk to a small voltage (~ lvolt) . The interval "T1-T2" is short, typically a few hundred nanoseconds, depending on load.

T2 - Tl = { ( C1 +C2) *V\ / 2 ) / I ( Sw)

The output is being maintained by the energy stored in the output inductor Lo . The output current I(Lo) continues to flow through secondary winding TS1, secondary switch S5 and rectifier D5. By transformer action, reflected load current (Lo) / N continues to flow in the transformer primary, which together with primary magnetizing current Imag is conducted by D4 and auxiliary switch S3. The transformer Tl turns ratio is defined as N:l.

I (Sw) = \ ( Lo) / N + Imag

No energy is being drawn from the input source VI at the end of Mode 2. All the transformer's magnetic energy, including that due to leakage inductance Lk, is being maintained with minimal loss. No voltage ringing, usually associated with discharging the primary leakage inductance at this time, is present in the voltage waveform VN.

Mode 3 (T2 - T3)

After Mode 2 is completed, gate drive VG4 turns ON the auxiliary switch S4, clamping the transformer primary to essentially zero volts. The reflected load current and magnetizing current now circulate through the transformer primary and auxiliary switches S4 and S3 in a clockwise direction. The transformer flux is clamped since:

D ( fl ux) = Lm * D ( Imag) = Vm * ( T3 - T2)

where the voltage Vm across the transformer Tl primary is essentially zero (a few hundred millivolts) . Where the primary magnetizing current remains essentially constant at ÷lmag, the output current through the choke decreases by the value:

D { I ( Lo) } = { Vo * ( T3 - T2) } / Lo

This effect is seen in the auxiliary switch current of S3 and in the primary current of Tl as shown in Figures 2h and 2i respectively. Note that the transformer's magnetic energy, including that due to leakage inductance Lk, is being maintained, with only minimal loss in the auxiliary switches S3 and S4.

Mode 4 (T3 - T4) Mode 4 is initiated when control signal VG3 turns

OFF auxiliary switch S3. The active clamp across the primary of transformer Tl is released and the primary current can continue to charge the parasitic capacitance Cl of primary switch SI and discharge the parasitic capacitance C2 of primary switch S2. Ignoring additional node capacitance the time for Cl to be charged from VI/2 to VI is given by:

T4 - T3 = { ( C1 + C2) * 71/2} /| ( Sw)

This time duration is a little longer than that of mode 2 since I(Sw) is smaller at time "T3" than at time "Tl", depending on the value of Lo . The charging interval is completed when the voltage across Cl is clamped to VI by the body diode D2 across the primary switch S2.

The voltages across the transformer secondary windings now reverse polarity, TS2 is positive. However the energy stored in the transformer primary is prevented from flowing to the secondary during Mode 4 by the switch S6. In the preferred embodiment this is a saturable reactor but it could equally be a synchronous rectifier gated ON by a delayed control signal.

Mode 5 (T4 - T5)

Gate drive VG2 drives the primary switch S2 ON, when the voltage across it is essentially zero (~ -1 volt) . Current initially flows in the reverse direction through S2 but as the output current is commutated from the secondary rectifier D5 to Dβ, the primary switch S2 conducts load current in the forward direction (Figure 2g) . Energy is transferred from primary source VI to Vo, via secondary winding TS2. During this interval, control signal VG4 maintains auxiliary switch LS4 ON, while control signal VG3 maintains auxiliary switch S3 OFF. Thus the active clamp selectively blocks the flow of current during Mode 5.

The magnetizing current changes linearly from +Imag (1st quadrant B-H loop) to -Imag (3rd quadrant B-H loop) and the secondary load current also increases as explained in Mode 1 equations . Mode 6 (T5 - T6 )

Gate drive signal VG2 turns switch S2 OFF to terminate Mode 5 operation. The load and magnetizing current I (Sw) flowing in S2 is commutated from its channel to its output capacitance C2. The switch current I (Sw) charges the output capacitance C2 from zero volts and discharges the output capacitance Cl initially at VI volts in a linear ramp, together with all other parasitic capacitance connected to this node. When the voltage across C2 is charged to half the input source, VI/2, the body diode D3 of auxiliary switch S3 conducts, clamping the transformer primary to a small voltage (~ lvolt) . The interval "T5-T6" is identical with the interval "T1-T2", given in Mode 2. The output is maintained by the energy stored in the output inductor Lo . The output current continues to flow through the secondary winding TS2 , secondary switch S6 and rectifier D6.

Mode 7 (T6-T7)

After Mode 6 is completed, gate drive VG3 turns ON the auxiliary switch S3, clamping the transformer primary to essentially zero volts. The reflected load current and primary magnetizing current now circulates through the channels of both auxiliary switches S3 and S4. Operation is identical to that described in Mode 3, with the exception that the current flows counter-clockwise through the transformer and auxiliary switches. No energy is drawn from the input source VI during Mode 7.

Mode 8 (T7 - T8)

Mode 8 is initiated when control signal VG4 turns OFF auxiliary switch S4. The active clamp across the transformer Tl is released and the primary current can continue to charge the parasitic capacitance C2 of primary switch S2 and discharge the parasitic capacitance Cl of primary switch SI. The time to charge C2 from VI/2 to VI volts is identical to that given in mode 4 equations . The charging interval is completed when the voltage across C2 is clamped to VI by the body diode DL1 across primary switch SI.

The voltages across the transformer secondary windings reverse polarity, TS1 is positive. However, the energy stored in the transformer primary is prevented from flowing to the secondary during mode 8 by the switch S5. In the preferred embodiment this is a saturable reactor but it could equally be a synchronous rectifier gated ON by a delayed control signal. The sequence is repeated by returning to Mode 1 operation.

It is evident from the above discussion, that fixed timing delays must exist between the turning OFF of each of the four switches in the circuit and the turning ON of the next switch in the control sequence. (Modes 2/6 and 4/8) These delays guarantee that zero voltage switching conditions can be established on all four switches. In practice, the interval "T4-T3" (Modes 4/8) is a little longer than the interval "T2-T1" (Modes 2/6) and a single fixed time delay "TD" equal to the interval "T4-T3" is sufficient to guarantee correct circuit operation. This delay is selected not at full load but at some reduced load condition where the ZVS boundary is to be established. Assuming this is I(Lo)min then:

I (SV)min = I ( Lo) min + Imag

TD = { ( Cl + C2+node capaci tance) *V|max/2}/ | (Spv) in

The transformer core Tl can be gapped to increase the value of Imag and extend the load range for zero voltage switching. At sufficiently small loads, the voltage excursion during Mode 4/8 is no longer linear, but a sinusoid defined by the resonant circuit of (Lm + Lk) inductance and (Cl+C2+node capacitance) together with an initial driving current function Imag flowing in the circuit inductances . For zero voltage switching to be maintained, the energy stored in the magnetic structure must equal or exceed the energy to charge the circuit capacitance through half the input voltage. If the magnetic inductance is lumped together as Lr (= Lm + Lk) and the circuit capacitance denoted as Cr (= Cl + C2 + node capacitance) and the current flowing through Lr, when the active clamp is released is I(Sw) (= Imag at no load) then

Lr * I ( Sw) 2* _ = Cr * ( V\ /2

Rewriting this expression

V\ /2 = J r/Cr * \ ( Sw)

this states that the voltage change on the capacitor of the resonant circuit is the product of the characteristic impedance

Zr ( = sjLrl Cr)

of the circuit and the current impulse I(Sw) causing the resonance. The resonant circuit has an oscillation period

Tr = 2 *πJLr * Cr .

Hence to achieve ZVS under light load conditions, the maximum time delay "TD" required by the control circuit is equated to one quarter of the resonant sinusoid period.

TD = (π * Lr/ Cr) / 2

More detailed circuit analysis of this second order system with initial conditions may be found in the literature. It is also apparent that the control can be designed to include a variable delay TD that changes with the input line and/or the output load.

Figure 3 shows another embodiment of the invention. A bifilar winding has been added to the transformer Tl . This has been wound tightly coupled to the primary winding and with the same turns as the primary winding to illustrate the principle. However, in general this winding may have a different turns ratio to the primary or it may be coupled to a secondary winding. The laws of current and voltage transformation apply. It may also be included in any of the push-pull topologies described within. In Figure 3 the active clamp consisting of auxiliary switches S3 and S4 are connected in series across the bifilar winding with the correct phase relationship to the primary winding of a half bridge converter 1. The source connections of S3 and S4 are now common and may be connected to any reference point in the converter on either the primary or secondary side. The circuit operation is essentially the same as discussed previously. However, because it is impossible to obtain perfect coupling between the two bifilar windings, the leakage inductance Lk shown in Figure 3 is no longer clamped by the active clamp during Modes 3 and 7. Consequently the energy stored in Lk coupled with the parasitic capacitance at node VN will generate a high frequency oscillation which may be limited by a dissipative snubber circuit. The active clamp may also be connected across the secondary winding of any push-pull topology. By way of illustration, Figure 4 shows the active clamp connected across one secondary winding of a center tapped transformer configured as a half bridge converter. In this configuration, the leakage inductance Lk in the figure is not clamped during Modes 3 and 7. Hence oscillation will be present during these intervals. Also because of the position of the active clamp across the secondary, this arrangement may be more appropriate for high voltage, low current converters. The principle of operation remains the same. At the end of each main switch's ON period (Modes 1/5) , the transformer's magnetizing current N* Imag referred to the secondary is clamped at zero volts by the auxiliary switches S3 and S4 (Modes 3/7) . At the same time the output current I(Lo) continues to flow through the active clamp. When the clamp is released the stored magnetic energy is used to charge/discharge the primary switch capacitances so that zero voltage switching can be achieved. Energy flow to the opposite output rectifier is delayed by selective blocking of the secondary rectifiers S5 or S6. Another embodiment of the invention is shown in Figure 5 with the active clamp across a single secondary winding of a current doubler scheme. For illustration, the transformer is configured as a half bridge but is not limited to this topology. The discussion relating to Figure 4 pertains . The active clamp described in this patent may be applied to other push-pull topologies. The invention is a full bridge zero voltage switched converter shown in Figure 6. In this arrangement two primary switches are replaced by four primary switches. Each diagonal pair are denoted by SI or S2. Control signal VGl is isolated and drives each of the two SI primary switches and control signal VG2 is isolated and drives each of the two S2 primary switches. The operation is identical with the earlier discussion. The only exception is that now both voltage nodes VNl and VN2 , on either side of the transformer primary are driven rail to rail in opposite phase.

There is prior art in this case, which is known as the zero voltage switched phase-shifted full bridge. (ZVS-PS full bridge) . In the case of the ZVS-PS bridge, the circuit operation is almost identical but with some significant exceptions.

ZVS - PS FULL BRIDGE Drive Signals:

Each leg of the bridge (known as the right and left phase legs) and driven with a push-pull drive. Control is achieved by varying the phase shift between the right and left drives .

There are delays between the gate drive signals to effect the ZVS transitions. The right hand leg transitions are noticeably faster than the left hand leg transitions. The control function requires two separate delay times.

Additional Primary Inductor:

The leakage inductance is not sufficient to achieve ZVS operation over an extended load range without the necessity of adding an additional inductor is series with the transformer's primary leakage inductance.

Magnetic Energy Storage:

The magnetic energy required to effect the phase transitions is stored by the clamping action of either the upper primary switches or the lower primary switches in the bridge. This requires additional power being dissipated in these switches.

Phase Transitions:

The phase transitions are from one rail to the other. The node capacitance on the right and left phase legs are charged/discharged to the input bus VI.

ZVS FULL BRIDGE Drive Signals:

The drive signals to the primary switches are the same as a conventional "hard switched" full bridge. There is no significant difference in the right and left hand phase transitions. The control function is satisfied with a single delay time .

Leakage Inductance : No additional primary inductance is required to effect ZVS over an extended load range. Magnetic Energy Storage:

The magnetic energy storage is accomplished with two additional switches. The additional power to effect this is dissipated in the auxiliary switches and not in the primary switches.

Phase Transitions:

The phase transitions are from the mid-point to either bus. The node capacitance on the right and left phase legs are charged/discharged to half the input bus. The magnetic energy to accomplish this is one quarter that required by the ZVS-PS bridge. The EMI noise spectrum may also be lower because the transition amplitude is halved.

The concept of adding an active clamp may be extended from a half bridge and a full bridge to a three phase bridge as used in motor control applications. The invention is a ZVS three phase bridge as illustrated in Figure 7 and is obtained by placing three active clamps across the phase arms of the motor controller. The control signals for the active clamps have to be extended to three phases . A center-tapped push-pull converter is an old topology in power conversion terms, used primarily for low power and low input voltage applications . The active clamp may be added to this topology. The invention is a ZVS center- tapped push-pull converter. For illustration the voltage fed converter topology is shown in Figure 8. The transformer Tl consists of two primary windings TPl and TP2 , two secondary windings TS1 and TS2 , phased as shown in Figure 8. The turns ratio between each primary and secondary winding is N:l. The leakage inductances, referred to the primary are denoted Lkl and Lk2. The primary switches are denoted as SI and S2. Two active clamps, for illustration are positioned across each half of the transformer primary. Two of the auxiliary switches are referenced S3 and two additional auxiliary switches are referenced S4. It is also possible to operate this structure with one auxiliary clamp as shown in Figure 9, with some performance degradation. The timing relationships between the drive signals to the four switches are the same as illustrated in Figure 2 together with the main current and voltage waveforms of the converter. A description of the operating modes of the converter is presented below. The major differences in operation, arising from the topology having two, not one, primary windings are discussed.

Mode 1 (TO - Tl)

The gate drive signal VGl turns primary switch SI ON to initiate Mode 1 operation. Power is drawn from the input

DC source VI and delivered through the primary winding TPl and primary switch SI to the output, via the transformer secondary TS1, secondary switch S5 and secondary rectifier D5. The primary switch current I(Sw) in Figure 2f has a positive slope because the primary magnetizing is increasing in a linear ramp, as is the current flowing through the output Lo . The equations for Mode 1 were presented in the ZVS half bridge discussion.

Mode 2 (LT1 - T2) Mode 1 is completed when the gate drive signal VGl turns OFF primary switch SI. At this instant, both primary windings have to conduct primary current. The primary current I(Sw) is halved. The primary switch current 0.5* I(Sw) now flows through both primary windings TPl and TP2 , because transformer action requires that the amp-turns equality below be satisfied

0.5 * \ ( Sw) * N( TP1 ) + 0.5 * I ( Sw) * N( TP2) = \ ( TS1 ) * N( TS1 )

This simplifies to

N * I ( Sw) = I ( TS1 ) The reduced switch current is commutated to the combined output capacitance of the four primary switches SI, S2 , S3 and S4. The voltage across SI increases at the same time the voltage across S2 falls. The voltage waveform across is SI illustrated in Figure 2e. The mode continues until the voltage across SI and S2 is clamped to the input source VI, by the body diode D4 of auxiliary switch S4 and the channel of auxiliary switch S3.

T2 - T1 = { ( C1 + C2) / / ( C3 + C4 ) } * V\ / { 0.5 * | ( Sw) }

Note in this topology, even though the transformer leakage inductances Lkl and Lk2 are included in the active clamp circuitry, there is ringing in the current/voltage waveforms because the primary current is abruptly halved when SI is opened. The magnetic energy initially stored in TPl and Lkl is redistributed and maintained TPl, Lkl as well as TP2 and Lk2. This resonant ringing is superimposed on the charging process described above.

Mode 3 (T2-T3)

At time "T2", control signal VG4 turns auxiliary switch S4 ON, under zero voltage conditions. Reflected load current and primary magnetizing current is circulated anticlockwise through the transformer primary windings TP2 , TPl and the channels of S3 and S4. The output current continues to flow through TS1, S5 and D5 , maintained by the energy stored in the output inductor Lo. During this mode, no energy is provided by the input source. The current through the output inductor Lo has a negative slope defined by the equation given in the ZVS half bridge discussion. Resonant ringing is terminated if two active clamps are employed. However if a single clamp is used, parasitic ringing will continue during this interval, and dissipative snubbing techniques must be employed. (Mode 4 (T3 - T4 )

At the end of Mode 3, control signal VG3 turns auxiliary switch S3 OFF. The energy stored in the magnetic structure of transformer Tl is released and can continue to charge the capacitance of SI to twice the source voltage and discharge the capacitance of S2 to zero volts. The voltage across the secondary windings reverse polarity, TS2 is Now positive. The energy is selectively blocked from flowing to the secondary by the secondary switch S6. The charging interval is given by the equation below.

T4 - T3 = { ( C1 +C2) / / ( C3+C4 ) } * V\ / { 0.5 * | ( Sw) }

As I (Sw) has a smaller value at the "T3" that at time "T2", the Mode 4 interval is longer than the Mode 2 interval, dependent on the value of the output inductor Lo . The voltage across S2 is clamped to ~ - 1 volt by the body diode D2 of switch S2.

Mode 5 (T4 - T5)

Control signal VG2 turns ON the primary switch S2 under zero voltage conditions. The current initially negative becomes positive as power flows from the input DC source VI through primary TP2 and switch S2 via the secondary winding

TS2 , secondary switch S6 and rectifier D6. As in Mode 2, the switch current abruptly changes from 0.5* | (Sw) to | (Sw) as only one primary winding LP2 is involved with the conversion process. Parasitic ringing occurs. This is observed at the drain of the primary switch SI.

Mode 6 (T5 - T6)

Control signal VG2 terminates the ON period of primary switch S2 and allows the circuit capacitances to be charged across S2 and discharged across switch SI as described in Mode 2. Mode 7 ( T6 - T7 )

Control signal VG3 turns ON auxiliary switch S3, clamping the energy and flux in the transformer Tl structure. Primary current 0.5* | (Sw) is circulating clockwise through TPl, TP2, S4 and S3.

Mode 8 (T7 - T8)

Control signal VG4 turns auxiliary switch S4 OFF. The active clamp is released, allowing the stored magnetic energy to continue to charge the capacitance across S2 to twice the input voltage and to discharge the voltage across SI to zero. The cycle is repeated by returning to Mode 1 operation.

Claims

CLAIMSWhat is claimed is:

1. A full wave zero voltage switching, DC-DC converter comprising: a primary winding; a plurality of secondary windings; a pair of primary switches which alternately couple half the input voltage across the primary winding of a transformer; a pair of auxiliary switches which selectively allow the voltage across each primary switch to reach zero sequentially, the primary switches and the auxiliary switches each having an OFF period and an ON period, wherein each of said pair of auxiliary switches is non-conductive prior to the ON period of the next corresponding primary switch in the switching cycle, for a predetermined period sufficient to allow the voltage across the primary switch to reach zero voltage, said auxiliary switch remains non-conductive for a period after the corresponding primary switch is turned OFF; a plurality of secondary switches coupled in series with ones of the secondary windings of the transformer to selectively remain at least partially non-conductive as the voltage across the corresponding primary switch decreases, the plurality of secondary switches becomes conductive when the voltage across the corresponding primary switch reaches zero; a pair of rectifiers selectively coupled with the plurality of secondary switches for conducting current to an output ; and a control circuit to selectively operate the primary switches, the auxiliary switches and the secondary switches to transfer energy through the converter by modification of a duty cycle of operation of at least the primary and auxiliary switches to turn ON the primary switches at zero voltage.

2. The converter of claim 1 wherein said each auxiliary switch includes an anti-parallel diode, such that: said each auxiliary switch is opened prior to the ON period of the corresponding primary switch for a period of time sufficient to discharge an output capacitance of the primary switch, and closes after a period of time after the primary switch is driven OFF, said period of time being sufficient to allow the mid point of the primary switches to charge to the mid point of an input source.

3. The converter of claim 1 further comprising a circuit for inhibiting current flow in the secondary windings of the transformer until an output capacitance of the appropriate primary switch is discharged.

4. The converter of claim 1 wherein each of the secondary switches has a saturation voltage.

5. The converter of claim 1 wherein the control circuit comprises a sensory circuit for sensing the voltage across a load.

6. A full wave zero voltage switching, DC-DC converter comprising: a primary and a plurality of secondary windings; two primary switches which alternately couple half the input voltage across the primary winding of a transformer; two auxiliary switches which selectively allow the voltage across each of said two primary switches to reach zero sequentially, the primary switches and the auxiliary switches each having an OFF period and an ON period, wherein each of said two auxiliary switches is non-conductive prior to the ON period of the next corresponding primary switch in the switching cycle, for a predetermined period sufficient to allow the voltage across the primary switch to reach zero voltage, and said auxiliary switch remains non-conductive for a period after the corresponding primary switch is turned OFF; a pair of secondary switches coupled in series with the secondary windings of the transformer to selectively remain at least partially non-conductive as the voltage across the corresponding primary switch decreases, wherein each one of said pair of secondary switches becomes conductive when the voltage across the corresponding primary switch reaches zero; two rectifiers selectively coupled with the pair of secondary switches for conducting current to an output; and a control circuit to selectively operate the primary switches, the auxiliary switches and the secondary switches to transfer energy through the converter by modification of a duty cycle of operation of at least the primary and auxiliary switches to turn ON the primary switches at zero voltage.

7. The converter of claim 6, wherein each of the auxiliary switches is a bilateral switch which can block voltage of either polarity and which can selectively allow the passage of current in either direction, implemented by the series connection of two N-channel MOSFETS, or two P-channel MOSFETS, or any combination of IGBT or bipolar transistor, or a semiconductor device in series with a blocking diode, or any other bilateral semiconductor device.

8. The converter of claim 6 further comprising: a bifilar winding coupled to one of the group consisting of the primary and secondary windings of the transformer, wherein the auxiliary switches are connected across the bifilar winding of the transformer.

9. The converter of claim 6 wherein a zero voltage switching conditions are effected on all the primary and auxiliary switches employed in the converter.

10. The converter of claim 6 wherein two delays between the turning OFF of one of said primary switches in the sequence and the turning ON of the next one of said primary switches are reduced to a single delay in the control sequence without impacting zero voltage switching operation.

11. The converter of claim 6, wherein a plurality of switches are connected across any number of windings of the transformer.

12. The converter of claim 8 wherein said auxiliary switches conduct both load and current and transformer magnetizing current for a period in a power conversion process when the primary switches are OFF.

13. The converter of claim 8 where said auxiliary switches clamp both the energy stored in the primary and secondary windings and a magnetic flux in the primary and secondary windings with minimal loss.

14. The converter of claim 10 wherein the converter includes means for varying a delay between switching OFF one of the auxiliary switches and the switching ON of the next corresponding primary switch as a function of line and/or load.

15. A method of operating a half bridge DC to DC converter comprising the steps of: storing energy in a primary winding of a transformer which has two primary switches, two auxiliary switches and a plurality of secondary windings, by flowing AC current through the primary winding in series with said two primary switches, clamping a voltage of the transformer to almost zero, after each of said two primary switches is turned OFF, said clamping being performed by a first one of said two auxiliary switches in a series connection with a body diode of a second one of said two auxiliary switches and across the primary winding of the transformer, commutating a circulating current, consisting of primary load current and magnetizing current, from the body diode of the second auxiliary switch to a channel of the second auxiliary switch by control action, turning ON the second auxiliary switch under zero voltage conditions, clamping the transformer's energy, including leakage, to zero volts, said clamping being performed by said two auxiliary switches, opening the second auxiliary switch after a time determined by a control circuit of the converter, allowing the transformer's energy to drive the corresponding primary switch and circuit capacitances to an input bus, reducing the voltage across the corresponding primary switch to zero, thereby allowing the corresponding primary switch to turn on at zero voltage, selectively opening a corresponding secondary switch in series with one of the secondary windings of the transformer to discharge voltage.

16. The method of claim 15 further comprising the step of selectively limiting an energy flow to the secondary windings with either saturable reactors or a semiconductor switch used with a delayed control signal .

17. The method of claim 15 wherein zero voltage switching conditions are achieved with less magnetic energy than when using a method in which the parasitic capacitances are charged and discharged by a voltage equal to or greater than the input voltage source.

18. The method of claim 15 further comprising the step of shorting at least on of the primary and secondary windings with a very small, symmetric clamping voltage.

19. The method of claim 15 further comprising the step of limiting the amplitude of any voltage transients to half of an input source voltage to the DC to DC converter.

20. The method of claim 15 wherein no reset capacitor is required in series between the primary winding and a voltage source of the DC to DC converter.