US9761669B1 - Seed-mediated growth of patterned graphene nanoribbon arrays - Google Patents

Seed-mediated growth of patterned graphene nanoribbon arrays Download PDF

Info

Publication number
US9761669B1
US9761669B1 US15/212,413 US201615212413A US9761669B1 US 9761669 B1 US9761669 B1 US 9761669B1 US 201615212413 A US201615212413 A US 201615212413A US 9761669 B1 US9761669 B1 US 9761669B1
Authority
US
United States
Prior art keywords
graphene
nanoribbons
semiconductor substrate
array
graphene nanoribbons
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/212,413
Inventor
Michael Scott Arnold
Austin James Way
Robert Michael Jacobberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wisconsin Alumni Research Foundation
Original Assignee
Wisconsin Alumni Research Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wisconsin Alumni Research Foundation filed Critical Wisconsin Alumni Research Foundation
Priority to US15/212,413 priority Critical patent/US9761669B1/en
Assigned to WISCONSIN ALUMNI RESEARCH FOUNDATION reassignment WISCONSIN ALUMNI RESEARCH FOUNDATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JACOBBERGER, ROBERT, WAY, AUSTIN, ARNOLD, MICHAEL
Application granted granted Critical
Publication of US9761669B1 publication Critical patent/US9761669B1/en
Assigned to UNITED STATES DEPARTMENT OF ENERGY reassignment UNITED STATES DEPARTMENT OF ENERGY CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: UNIVERSITY OF WISCONSIN-MADISON
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606Graphene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02425Conductive materials, e.g. metallic silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02527Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02609Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • H01L21/02645Seed materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Definitions

  • Graphene is a two-dimensional carbon allotrope, the electronic, optical, and magnetic properties of which can be tuned by engineering two-dimensional graphene sheets into one-dimensional structures with confined widths, known as graphene nanoribbons.
  • the properties of graphene nanoribbons are highly dependent on their width and edge structure.
  • a major challenge facing graphene nanoribbon-based devices is that scalable approaches to create high-quality graphene nanoribbons with atomically-smooth edges are lacking.
  • Conventional, top-down techniques in which graphene nanoribbons are etched from continuous graphene sheets result in structures with rough, disordered edges that are riddled with defects, which significantly degrade graphene's exceptional properties.
  • This blunt top-down etching can be avoided by synthesizing nanoribbons from the bottom-up.
  • organic synthesis can yield ribbons with smooth edges, defined widths, and complex architectures.
  • organic synthesis forms short nanoribbons (typically ⁇ 20 nm in length) and is not adapted to technologically relevant substrates, such as insulators or semiconductors, limiting its potential for commercial development.
  • Graphene nanoribbon arrays methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided.
  • a graphene nanoribbon array comprises a semiconductor substrate having a (001) facet and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate.
  • the graphene nanoribbons have aspect ratios of at least 4.
  • the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes and an armchair configuration along their edges. At least 60 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate.
  • a graphene nanoribbon array comprises a semiconductor substrate having a (001) facet and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate, each of the graphene nanoribbons comprising an amorphous carbon seed along its length.
  • the graphene nanoribbons have aspect ratios of at least 4.
  • the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes with an armchair configuration along their edges and have their long axes oriented along a [110] direction of the semiconductor substrate.
  • One embodiment of a method of growing graphene nanoribbons comprises: forming an array of graphene seeds on the (001) facet of a semiconductor substrate, wherein a majority of the graphene seeds have a single crystallographic orientation; and growing graphene nanoribbons from the graphene seeds via chemical vapor deposition from a mixture of methane gas and hydrogen gas, wherein the partial pressures of the methane and hydrogen are selected to result in the growth of graphene nanoribbons having their long axes oriented along a [110] direction of the semiconductor substrate and their armchair edges running parallel with the [110] direction of the semiconductor substrate.
  • FIG. 1A Schematic illustration of a graphene seed particle on the (001) facet of a substrate.
  • FIG. 1B Schematic illustration of a graphene nanoribbon growing anisotropically from a graphene seed particle on the (001) facet of a substrate. The armchair configuration along the edges of the graphene nanoribbon is shown, as is the orientation of the long axis of the graphene nanoribbon along a [110] direction of the substrate.
  • FIG. 2 Schematic illustration of a regular rectangular pattern of graphene nanoribbons on a substrate.
  • the circles represent graphene seed particles and the rectangles represent the graphene nanoribbons.
  • FIG. 3 Schematic illustration of a graphene nanoribbon with armchair edges perfectly aligned along the Ge [110] direction (upper nanoribbon) and a graphene nanoribbon with armchair edges aligned within about ⁇ 3° of the Ge [110] direction (lower nanoribbon).
  • FIG. 4A Scanning electron microscope image of a graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a dry transfer technique.
  • FIG. 4B Scanning electron microscope image of another graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a dry transfer technique.
  • FIG. 4C Scanning electron microscope image of a graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a wet transfer technique.
  • FIG. 4D Enlarged view of a portion of the image of FIG. 4C .
  • FIG. 5 Scanning electron microscope image of an array of graphene crystal structures, including graphene crosses and graphene nanoribbons, as well as other lower aspect ratio structures, made by amorphous carbon seed-mediated chemical vapor deposition growth on a Ge (001) substrate. Graphene nanoribbons having a vertical or horizontal orientation in the image are circled.
  • the graphene nanoribbons in the arrays are narrow, elongated strips (or “ribbons”) of monolayer graphene having widths and crystallographic edge structures that provide the ribbons with electronic properties, such as electronic bandgaps, that are absent in continuous two-dimensional films of graphene.
  • the graphene nanoribbons in the arrays are formed using a scalable, bottom-up, chemical vapor deposition (CVD) technique to grow oriented graphene nanoribbons with atomically-smooth edges from seed particles (“seeds”) on the (001) facet of a semiconductor substrate.
  • CVD chemical vapor deposition
  • the graphene seeds comprise the same material as the graphene nanoribbons grown therefrom, they can be distinguished from heterogeneous nucleation sites that are provided by other types of materials, such as metals or metal oxides.
  • the methods are able to produce high density graphene nanoribbon arrays in which the graphene nanoribbons are preferentially aligned along a single [110] direction on the substrate. In the methods, no terraces or other topographical features of the growth substrate are used to template the growth of the nanoribbons.
  • the graphene seeds can be patterned from a continuous monolayer graphene sheet.
  • the graphene sheet can be grown on a sheet-growth substrate and then transferred onto the semiconductor substrate for patterning and nanoribbon growth.
  • the sheet-growth substrate comprises a material on which the graphene is grown preferentially in a single crystallographic orientation. By grown preferentially, it is meant that most of the graphene in the monolayer is grown with a single crystallographic orientation. However, it should be recognized that there may be imperfections in the sheet-growth substrate that result in a minority of the graphene domains being grown with a different crystallographic orientation. Thus, it is advantageous to use a high-quality sheet-growth surface having a single in-plane orientation.
  • Cu (111) is an example of a sheet-growth substrate material that is suitable for orientation-controlled graphene growth.
  • suitable materials for the sheet-growth substrate include Ru (0001), Ni (111), Pd (111), Ir (111), Ge(110), and SiC (0001). Methods for the orientation-controlled CVD growth of graphene on Cu(111) are illustrated in the Example.
  • the monolayer graphene sheet is then released from its sheet-growth substrate and transferred onto the (001) facet of a semiconductor substrate.
  • Germanium (Ge) is an example of a semiconductor having a (001) facet.
  • Other examples include Group III-V semiconductors, such as GaAs and InAs.
  • the transfer process may involve transferring the monolayer graphene sheet onto a temporary host substrate, followed by a transfer from the host substrate to the semiconductor substrate and the removal of any residual host substrate material. Both wet and dry thin film transfer techniques can be used. Both techniques are illustrated in the Examples which describe the dry transfer of graphene using a poly(methyl methacrylate) (PMMA)/gold (Au) bilayer host substrate and the wet transfer of graphene using a PMMA host substrate.
  • PMMA poly(methyl methacrylate)
  • Au gold
  • One or more seeds can then be patterned into the transferred graphene sheet.
  • an array comprising a plurality of seeds will be patterned into the graphene sheets.
  • the arrays of seeds can comprise at least 10, at least 100, at least 1,000, or at least 10,000 seeds.
  • High resolution lithographic techniques such as electron beam lithography or extreme ultraviolet lithography, can be used to carry out the patterning. Because the graphene in the monolayer graphene sheet had a preferred crystallographic orientation, the seeds patterned from it will also have that same preferred crystallographic orientation. Again, however, a minority of the seeds may have a different orientation stemming from, for example, imperfections in the original sheet-growth substrate or imperfections introduced during the transfer process.
  • the graphene transfer and subsequent patterning are carried out such that the armchair direction of the seeds is preferentially aligned along a single [110] direction of the (001) facet.
  • anisotropic CVD growth of graphene nanoribbons from the seeds will be preferentially directed along that same [110] direction.
  • CVD is an inexpensive scalable technique, offering high throughput and compatibility with planar processing.
  • the graphene nanoribbons are grown directly from the seeds on the (001) facet of a semiconductor platform using hydrocarbon precursor molecules, such as methane.
  • the semiconductor platform can be purchased as a single-crystal wafer or can be epitaxially grown. Single-crystal semiconductor materials are available in large formats and are prevalent in the semiconductor industry.
  • the growth conditions are selected to provide a graphene growth rate that is highly anisotropic, resulting in faceted graphene nanoribbons with high aspect ratios.
  • the (001) facet of the semiconductor substrate is used to orient the long edges of the graphene nanoribbons, as well as the armchair direction of the graphene lattice within the ribbons, along the [110] directions of the semiconductor substrate.
  • the growth of the graphene nanoribbons can be directed preferentially along that same [110] direction, with exclusively or almost exclusively armchair configurations along their edges.
  • FIG. 1A is a schematic illustration of a graphene seed particle on the (001) facet of a substrate.
  • the anisotropic, seed-mediated growth of directionally aligned graphene nanoribbons from a graphene seed is illustrated schematically in FIG. 1B .
  • Conditions and reactants suitable for achieving anisotropic growth of graphene nanoribbons on the (001) facet of a semiconductor substrate are illustrated in U.S. Pat. No. 9,324,804 and in Jacobberger et al., Nature Comm., DOI: 10.1038/ncomms9006, the entire disclosures of which are incorporated herein by reference.
  • the width of the nanoribbons corresponds closely to the width of the seed particles, with wider seeds producing wider nanoribbons. Although, the nanoribbons may be slightly wider than their seeds by the end of the nanoribbon growth process.
  • lithographic patterning of the seed particles makes it possible to control the positions, density, inter-nanoribbon spacing, and the widths of the nanoribbons grown from the seeds.
  • the size of the seed particles produced via lithographic patterning can be further reduced by annealing the seed particles in an atmosphere comprising a mixture of argon and hydrogen.
  • the size of the seed particles and, therefore, the width of the nanoribbons grown therefrom can be further controlled by controlling the annealing conditions (e.g., temperature, time, and hydrogen concentration).
  • the seeds are disposed at random (i.e., non-pre-selected) locations on the surface of the substrate and, therefore, the nanoribbons grown from the seeds form arbitrary designs on the substrate.
  • the seeds are patterned into a regular pattern, such that nanoribbons grown from the directionally aligned graphene seeds are laid out on the substrate in a regular pattern.
  • a “regular pattern of graphene nanoribbons” is one in which the end-to-end spacing between the nanoribbons and/or the lateral (i.e., edge-to-edge) spacing between the nanoribbons is equal and/or periodically repetitious.
  • the schematic diagram in FIG. 2 shows a plurality of graphene nanoribbons laid out in a rectangular array in which the end-to-end and edge-to-edge distances between the nanoribbons are equal.
  • the circles represent graphene seeds, as shown in FIG. 1A and the rectangles represent graphene nanoribbons, as shown in FIG. 1B .
  • the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 20 nm.
  • the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 10 nm and further includes embodiments in which the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 5 nm.
  • the nanoribbons that are aligned along a single [110] direction of the (001) facet have a lateral and/or end-to-end spacing with respect to their nearest neighbors (i.e., an inter-nanoribbon spacing) of no greater than 20 nm.
  • larger lateral and/or end-to-end spacings are also possible, including spacings greater than 20 nm, greater than 50 nm, and greater than 100 nm.
  • the present disclosure is not limited to arrays of graphene nanoribbons in which all of the nanoribbons are aligned along a single [110] direction of the (001) of a substrate.
  • Factors such as the quality of the sheet-growth substrate, the transfer process, and the accuracy of the seed patterning can result in a minority of the nanoribbons being grown at right angles from the selected, predominant [110] direction.
  • the level of alignment provided by the present graphene nanoribbon arrays even using imperfect procedures and substrates, makes them readily distinguishable from arrays of nanoribbons that are randomly aligned along the two equivalent [110] directions of a (001) facet.
  • the percentage of alignment for a given distribution of graphene nanoribbons can be determined by analyzing SEM images of the graphene nanoribbons and counting the number of graphene nanoribbons that are in alignment.
  • the long axis of a graphene nanoribbon does not have to be perfectly aligned with (i.e., have a 0° rotation with respect to) a [110] direction of the semiconductor substrate surface in order to be considered aligned along that direction.
  • Small rotational deviations may stem from, for example, an initial rotation in the growth direction that becomes energetically unfavorable as the nanoribbons grow.
  • a graphene nanoribbon is considered to be aligned along a [110] direction if its long axis is rotated with respect to that directed by a smaller degree than it is with respect to the other [110] direction.
  • a graphene nanoribbon may be considered to be aligned along (or aligned with) a [110] direction if its long axis is rotated by no more than ⁇ 15° from the [110] direction of the semiconductor surface.
  • FIG. 3 This is illustrated schematically in FIG. 3 for graphene nanoribbons on the (001) facet of a germanium substrate in which one nanoribbon has a perfect alignment and the other is rotated by about 3°.
  • the lighter grey circles represent the top two layers of germanium in the substrate, while the darker grey circles, which are only partially visible under the top two layers, represent germanium atoms in lower layers of the substrate.
  • the arrow represents the Ge [110] direction.
  • the upper graphene nanoribbon is perfectly aligned along the Ge [110] direction.
  • the armchair crystallographic direction of graphene and the long axis of the ribbons deviate by about 3° from perfect alignment.
  • the degree of edge smoothness can be characterized by the average root mean square (rms) roughness of the edges of the nanoribbons in the array.
  • the rms edge roughness along the length of a nanoribbon can be measured using scanning tunneling microscopy (STM). Methods of using STM to determine the rms edge roughness of a graphene nanoribbon can be found in U.S. Pat. No. 9,287,359.
  • the average rms edge roughness for the nanoribbons in a nanoribbon array will vary since longer nanoribbons within the array will tend to have rougher edges.
  • a nanoribbon is considered to have an atomically smooth edge if its edge has an rms roughness of less than 1 nm over a length of at least 40 nm.
  • Some embodiments of the present nanoribbon growth methods form nanoribbons having an rms roughness of less than 0.5 nm over an edge length of at least 40 nm. This includes embodiments of the growth methods that form nanoribbons that have perfectly atomically smooth edges, that is—having an rms roughness of 0 nm, over an edge length of at least 10 nm.
  • Short nanoribbons having atomically smooth edges are well-suited for use as channel materials in FETs having channel lengths of 40 nm or less, including those having channel lengths of 10 nm or less. Therefore, short nanoribbons having atomically smooth edges can be identified within the nanoribbon arrays and selectively incorporated into an FET. Alternatively, short nanoribbon segments having atomically smooth edges can be cut from longer nanoribbons and selectively incorporated into an FET.
  • graphene nanoribbon growth is selected to provide graphene nanoribbon growth.
  • the present methods are distinguishable from methods in which CVD is used to grow graphene sheets on a substrate via island growth.
  • graphene nanoribbons are defined, for the purposes of this disclosure, as graphene structures having aspect ratios of at least 4 and having at least two edges that run substantially parallel with each other, where the aspect ratio is the ratio of the length of the nanoribbon to its width.
  • the present graphene nanoribbons as grown on the semiconductor substrate, are characterized by the armchair crystallographic direction of graphene running substantially parallel to the long nanoribbon axis, which is oriented along a [110] direction of the surface.
  • the phrase ‘substantially parallel’ is used in recognition of the fact that the edges may be parallel on a global scale, but might include edge portions that deviate slightly from perfectly parallel on an atomic scale due to edge roughness.
  • the graphene nanoribbons can be deposited from a mixture of methane gas and hydrogen gas.
  • the composition of the precursor gas mixture during growth By varying the composition of the precursor gas mixture during growth, the duration of the growth time, the growth temperature, and the size and crystallographic orientation of the seeds, the graphene nanoribbon width, length, and aspect ratio can be controlled.
  • This control over the nanoribbon structure makes it possible to tune the graphene properties. For example, graphene undergoes a metallic-to-semiconducting transition as the nanoribbon width decreases, wherein the induced bandgap is inversely proportional to the nanoribbon width. Therefore, the present approach makes it possible to control the width of the nanoribbons and, therefore, to tailor their electronic structure.
  • nanoribbons with widths below 10 nm can be grown.
  • seed-mediated anisotropic growth of nanoribbons from a mixture of H 2 and CH 4 can be achieved at certain combinations of temperatures in the range from about 860 to 935° C., H 2 mole fractions in the range from about 5.0 ⁇ 10 ⁇ 3 to 0.33 and CH 4 mole fractions in the range from about 3.0 ⁇ 10 ⁇ 5 to 2.0 ⁇ 10 ⁇ 2 .
  • the growth conditions are selected to provide growth rates of no greater than 500 nm/hr.
  • the growth conditions are selected to provide growth rates of no greater than 300 nm/hr, further includes embodiments in which the growth conditions are selected to provide growth rates of no greater than 100 nm/hr and still further includes embodiments in which the growth conditions are selected to provide growth rates of no greater than 35 nm/hr.
  • These growth rates refer to the growth rate of the fastest growing edge dimension of the graphene crystal structures.
  • the growth time plays a role in determining the dimensions of the CVD-grown graphene nanoribbons. Generally, as growth time is decreased, narrower, shorter nanoribbons are formed. Therefore, by tuning the duration of the growth time and the ratio of precursor gas to carrier gas in the gas mixture, nanoribbons with desired lengths and widths can be selectively grown using bottom-up CVD growth.
  • the optimal conditions for achieving anisotropic graphene growth may vary somewhat depending upon the laboratory conditions. For example, in a cleaner environment, the growth rate at a given set of conditions would be expected to be slower than in a dirtier environment. Therefore, to achieve the same low growth rate observed under standard laboratory conditions in a cleaner system, such as a clean room, a higher CH 4 mole fraction and/or a lower H 2 mole fraction could be used.
  • the average aspect ratio of the nanoribbons in the array is at least 5.
  • Included in some embodiments of such arrays are graphene nanoribbons having aspect ratios of at least 30, at least 40, at least 50, at least 60 and/or at least 70.
  • the average width of the graphene nanoribbons in some of the graphene nanoribbon arrays is no greater than 60 nm.
  • the average length of the graphene nanoribbons in some of the graphene nanoribbon arrays is at least 20 nm.
  • graphene seed-mediated, CVD-based graphene nanoribbon growth methods can be used to grow graphene nanoribbons having their graphene crystal lattice oriented preferentially along one [110] direction of a (001) facet, without the need to use step edges or trenches to dictate the growth direction, they can also be used to grow graphene nanoribbons having their crystal lattice oriented non-preferentially along both of the two equivalent [110] directions of a (001) surface.
  • Preferential orientation along one direction can be carried out by transferring a monolayer graphene sheet with a preferred crystal orientation onto the (001) facet of a semiconductor substrate, patterning an array of graphene seeds into the monolayer graphene sheets, and carrying out anisotropic CVD growth of graphene nanoribbons from the seeds, as described above.
  • the graphene seeds need not be formed with a preferred crystallographic orientation with their crystal lattice aligned along a single [110] direction of the (001) facet. In the graphene nanoribbon arrays made under these conditions, the nanoribbon alignment will closely reflect the distribution of each crystal orientation in the graphene monolayer from which the seeds were formed.
  • amorphous carbon seeds can be used, rather than crystalline graphene seeds, for nucleating anisotropic CVD growth of nanoribbons on the (001) facet of a semiconductor substrate. Because the amorphous carbon seeds lack a lattice orientation capable of directing graphene nanoribbon growth along a single direction, graphene nanoribbon growth from the amorphous carbon seeds will be random and, therefore, evenly distributed along the two equivalent [110] directions and, in some cases, may grow in cross shapes on the substrate surface.
  • selective growth along a single [110] direction can be achieved by miscutting the growth surface of the semiconductor substrate toward a 110 direction, such that a series of parallel (001) faceted terraces, separated by steps that are a multiple of two atomic layers in height, are formed and the graphene nanoribbons are grown with a parallel alignment along the terraces.
  • the steps can be two, four, six, eight, ten, etc., atomic layers in height.
  • the terraces can be formed using a miscut angle of, for example, about 9° or higher in order to provide steps that are two atomic layers high.
  • the present methods can produce graphene nanoribbon arrays having a high density of very narrow, smooth-edged, nanoribbons over a large area.
  • Arrays of these atomically-smooth nanoribbons can include thousands of nanoribbons and can be formed over areas of, for example, at least 1 ⁇ m 2 .
  • the graphene nanoribbon arrays can be incorporated into a variety of devices, including electronic and photonic devices, such as field effect transistors and photodetectors.
  • a field effect transistor comprising a graphene nanoribbon array comprises: a source electrode; a drain electrode; a gate electrode; a conducting channel in electrical contact with the source electrode and the drain electrode; a gate dielectric disposed over the conducting channel, but below the gate electrode; and a semiconductor substrate having a (001) facet.
  • the conducting channel comprises a plurality of directionally aligned graphene nanoribbons on the (001) facet of the semiconductor substrate, wherein the long nanoribbon axis is oriented along a [110] direction of the semiconductor surface and the nanoribbons have the armchair crystallographic direction of graphene running parallel to the long edges of the nanoribbons.
  • the graphene nanoribbon arrays can be transferred to other substrates, such as silicon substrates, polymer (e.g., plastic) substrates, dielectric substrates or metal substrates.
  • substrates such as silicon substrates, polymer (e.g., plastic) substrates, dielectric substrates or metal substrates.
  • Methods for transferring graphene from a germanium substrate to another substrate are described in Wang et al., Scientific Reports 3, Article number: 2465.
  • the transfer procedure described in the Examples that follow illustrates a modified version of the methods described in Wang et al.
  • the transferred graphene nanoribbons and the substrate onto which they are transferred can then be incorporated into a variety of devices.
  • Example 1 Graphene Seed-Mediated CVD Growth of Preferentially Aligned Graphene Nanoribbons on Germanium (001)
  • a copper (Cu) thin film was deposited onto a sapphire (0001) substrate (MTI Corp.) using a CVC 601 DC magnetron sputterer operating at 1 kW with 5 mtorr of argon (Ar) backfill.
  • Graphene growth was performed in a horizontal hot-walled chemical vapor deposition (CVD) system with a quartz tube having an inner diameter of 34 mm.
  • CVD chemical vapor deposition
  • the Cu/sapphire sample was loaded into the system and the system was then filled to atmospheric pressure with a mixture of Ar (purity of 99.999%) and hydrogen (H 2 ) (purity of 99.999%) with a flow rate of 345 sccm and 18 sccm, respectively.
  • the Cu/sapphire sample was annealed for 4 minutes at 1000° C. and then 87 ppm of methane (CH 4 ) (purity of 99.99%) was introduced to begin the graphene synthesis. Growth occurred for 1.5 hours before the sample was rapidly cooled to terminate synthesis, at which point a continuous monolayer of graphene was coated onto the Cu (111) thin films.
  • CH 4 methane
  • the first method used to transfer the monolayer graphene from the Cu growth substrate onto Ge was a dry transfer.
  • a 60 nm layer of gold (Au) was thermally evaporated on the graphene/Cu/sapphire substrate.
  • a solution of 4% 950 kg/mol PMMA in anisole was spin coated on the Au/graphene/Cu/sapphire structure at 3000 rpm for 1 minute.
  • the sample was then baked on a hot plate at 185° C. for 10 minutes.
  • Thermal release tape (TRT) was adhered to the PMMA/Au/graphene/Cu/sapphire and then removed, separating the PMMA/Au/graphene from the Cu/sapphire substrate.
  • This stack was immediately stamped onto Ge (001) and the TRT was subsequently released on a hot plate at 120° C., resulting in a PMMA/Au/graphene/Ge stack.
  • the sample was baked on a hot plate at 185° C. for 10 minutes.
  • the stack was then loaded into a horizontal tube furnace and the system was filled to atmospheric pressure with a mixture of 95% Ar (purity of 99.999%) and 5% H 2 (purity of 99.999%) with a total flow rate of 50 sccm.
  • the sample was annealed for 1 hour at 400° C. to remove the PMMA.
  • the Au/graphene/Ge was placed in potassium iodide (KI) for 20 minutes to etch the Au layer and then rinsed in a water (H 2 O) bath at 90° C. for 20 minutes, resulting in a continuous monolayer of graphene on a Ge (001) wafer.
  • KI potassium iodide
  • H 2 O water
  • the second method used to transfer monolayer graphene from Cu onto Ge was a wet transfer.
  • a solution of 4% 950 kg/mol PMMA in anisole was spin coated on the graphene/Cu/sapphire substrate at 2000 rpm for 1 minute.
  • the PMMA/graphene/Cu/sapphire stack was submerged in 0.2 M iron (III) chloride (FeCl 3 )/0.2 M hydrochloric acid (HCl) to etch the Cu layer.
  • the resulting PMMA/graphene membrane was transferred to and floated on the surface of a water bath.
  • Ge (001) was then used to lift the PMMA/graphene membrane out of the water bath.
  • the PMMA/graphene/Ge was placed on a spin coater and rotated at 4000 rpm to spin dry.
  • the PMMA/graphene/Ge stack was placed in acetone at 120° C. for 15 minutes to dissolve the PMMA and then washed with isopropyl alcohol (IPA), resulting in a continuous monolayer of graphene on a Ge (001) wafer.
  • IPA isopropyl alcohol
  • the Al mask/graphene/Ge stack was placed in a Unaxis 790 Reactive Ion Etcher for a 30 second O 2 plasma (50 W, 10 mtorr) etch to remove all graphene that was not covered by the Al mask.
  • the Al was etched in phosphoric acid (H 3 PO 4 ) for 30 minutes, leaving the patterned graphene seeds on Ge (001).
  • the graphene seed array on Ge (001) was loaded into a horizontal hot-walled CVD system with a quartz tube having an inner diameter of 34 mm.
  • the system was evacuated to ⁇ 10 ⁇ 6 torr and then filled to atmospheric pressure with a mixture of Ar (purity of 99.999%) and H 2 (purity of 99.999%) with a total flow rate of 300 sccm.
  • the sample was annealed for 1 hour at 910° C. and then CH 4 (purity of 99.99%) was introduced to begin synthesis.
  • Nanoribbons can be grown over a wide range of conditions, some of which are provided in Supplementary Table 1 of the article “Direct oriented growth of armchair graphene nanoribbons on germanium” in Jacobberger et al., Nature Comm., DOI: 10.1038/ncomms9006.
  • graphene nanoribbons can be grown from the graphene seeds using 200 sccm Ar, 100 sccm H 2 , and 2.0 sccm CH 4 at 910° C. for 2 hours. Growth was terminated by rapidly cooling the samples in the same atmosphere used during synthesis by sliding the furnace away from the growth region.
  • graphene nucleation occurred preferentially at the lithographically-defined seeds, resulting in the formation of nanoribbons at these locations.
  • the graphene seeds have a single orientation (or predominantly a single orientation), as they do if graphene grown on Cu (111) is transferred to Ge (001), and if the seeds are aligned along a single in-plane Ge [110] direction (or predominantly a single in-plane Ge [110] direction), the long-axis of the nanoribbons preferentially aligns along that same direction, resulting in unidirectional (or predominantly unidirectional) arrays of graphene nanoribbons.
  • the samples are characterized using a Zeiss LEO 1530 Scanning Electron Microscope (SEM).
  • FIG. 4A An SEM image of a graphene nanoribbon array on a Ge (001) substrate is shown in FIG. 4A .
  • FIG. 4B is an SEM image of another graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001). These arrays were made by dry transferring the graphene. The seeds were annealed for 1 hour and then the nanoribbons were grown for 2 hours with growth conditions of 200 sccm Ar, 100 sccm H 2 , and 2.0 sccm CH 4 at 910° C. In the sample of graphene nanoribbons in FIG. 4A , 73% are aligned along the vertical direction in the image.
  • graphene nanoribbons were considered aligned if they were rotated by no more than ⁇ 5° from the [110] direction of the semiconductor surface.
  • the average length is 393 ⁇ 72 nm
  • the average width is 51.3 ⁇ 15.8 nm
  • average aspect ratio is 7.6 ⁇ 3.4.
  • 82% are aligned along the vertical direction in the image.
  • the average length is 319 ⁇ 75 nm
  • the average width is 35 ⁇ 19 nm
  • the average aspect ratio is 11.3 ⁇ 7.6.
  • FIG. 4C An SEM image of another graphene nanoribbon array on a Ge (001) substrate is shown in FIG. 4C .
  • FIG. 4D An enlarged portion of the array is shown in FIG. 4D .
  • This array was made by wet transferring the graphene. The seeds were annealed for 1 hour and then the nanoribbons were grown for 1.75 hours with growth conditions of 200 sccm Ar, 100 sccm H z , and 2.0 sccm CH 4 at 910° C.
  • 79% are aligned along the vertical direction in the image.
  • the average length is 338 ⁇ 48 nm
  • the average width is 89.6 ⁇ 17.5 nm
  • the average aspect ratio is 3.77 ⁇ 0.8.
  • Example 2 Amorphous Carbon-Mediated CVD Growth of Randomly Aligned Graphene Nanoribbons on Germanium (001)
  • a-C amorphous carbon
  • a solution of 1% 950 kg/mol PMMA in chlorobenzene was spin coated onto a Ge (001) substrate at 4000 rpm for 1 minute.
  • the sample was then baked on a hot plate at 185° C. for 1.5 minutes.
  • Electron-beam lithography was used to define the seed patterns.
  • the patterns were developed in 1:3 methyl isobutyl ketone (MIBK):IPA for 1 minute.
  • MIBK methyl isobutyl ketone
  • a plasma sputterer was used to deposit 5 nm of carbon (C) onto the sample using a graphite source.
  • the sample was then placed in acetone at 120° C. for 10 minutes before being sonicated for 10 minutes to remove a-C/PMMA in regions that were not exposed to the electron beam during patterning. This resulted in a patterned array of a-C seeds on Ge (001).
  • the array of graphene crystal structures is shown in the SEM image of FIG. 5 .
  • the structures include graphene nanoribbons aligned along both [110] directions of the germanium (circled), as well as graphene crosses and crystal structures having low aspect ratios (e.g., graphene islands).

Abstract

Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a seed-mediated, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of a semiconductor substrate and the orientation of the seed particles on the substrate are used to orient the graphene nanoribbon crystals preferentially along a single [110] direction of the substrate.

Description

REFERENCE TO GOVERNMENT RIGHTS
This invention was made with government support under SC0006414 awarded by the US Department of Energy. The government has certain rights in the invention.
BACKGROUND
Graphene is a two-dimensional carbon allotrope, the electronic, optical, and magnetic properties of which can be tuned by engineering two-dimensional graphene sheets into one-dimensional structures with confined widths, known as graphene nanoribbons. The properties of graphene nanoribbons are highly dependent on their width and edge structure.
It has been proposed that graphene nanoribbons will outperform conventional materials and lead to next-generation technologies. Graphene nanoribbons have already shown tremendous promise for providing enhanced performance in nanoelectronics, spintronics, optoelectronics, plasmonic waveguiding, photodetection, solar energy conversion, molecular sensing, and catalysis. However, the full potential of graphene nanoribbons in such applications has not been realized.
A major challenge facing graphene nanoribbon-based devices is that scalable approaches to create high-quality graphene nanoribbons with atomically-smooth edges are lacking. Conventional, top-down techniques in which graphene nanoribbons are etched from continuous graphene sheets result in structures with rough, disordered edges that are riddled with defects, which significantly degrade graphene's exceptional properties. This blunt top-down etching can be avoided by synthesizing nanoribbons from the bottom-up. For instance, organic synthesis can yield ribbons with smooth edges, defined widths, and complex architectures. However, organic synthesis forms short nanoribbons (typically ˜20 nm in length) and is not adapted to technologically relevant substrates, such as insulators or semiconductors, limiting its potential for commercial development.
SUMMARY
Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided.
One embodiment of a graphene nanoribbon array comprises a semiconductor substrate having a (001) facet and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate. In the array, the graphene nanoribbons have aspect ratios of at least 4. Further, the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes and an armchair configuration along their edges. At least 60 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate.
Another embodiment of a graphene nanoribbon array comprises a semiconductor substrate having a (001) facet and a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate, each of the graphene nanoribbons comprising an amorphous carbon seed along its length. In the array, the graphene nanoribbons have aspect ratios of at least 4. Further, the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes with an armchair configuration along their edges and have their long axes oriented along a [110] direction of the semiconductor substrate.
One embodiment of a method of growing graphene nanoribbons comprises: forming an array of graphene seeds on the (001) facet of a semiconductor substrate, wherein a majority of the graphene seeds have a single crystallographic orientation; and growing graphene nanoribbons from the graphene seeds via chemical vapor deposition from a mixture of methane gas and hydrogen gas, wherein the partial pressures of the methane and hydrogen are selected to result in the growth of graphene nanoribbons having their long axes oriented along a [110] direction of the semiconductor substrate and their armchair edges running parallel with the [110] direction of the semiconductor substrate.
Other principal features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Illustrative embodiments of the invention will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements.
FIG. 1A. Schematic illustration of a graphene seed particle on the (001) facet of a substrate. FIG. 1B. Schematic illustration of a graphene nanoribbon growing anisotropically from a graphene seed particle on the (001) facet of a substrate. The armchair configuration along the edges of the graphene nanoribbon is shown, as is the orientation of the long axis of the graphene nanoribbon along a [110] direction of the substrate.
FIG. 2. Schematic illustration of a regular rectangular pattern of graphene nanoribbons on a substrate. The circles represent graphene seed particles and the rectangles represent the graphene nanoribbons.
FIG. 3. Schematic illustration of a graphene nanoribbon with armchair edges perfectly aligned along the Ge [110] direction (upper nanoribbon) and a graphene nanoribbon with armchair edges aligned within about ±3° of the Ge [110] direction (lower nanoribbon).
FIG. 4A. Scanning electron microscope image of a graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a dry transfer technique. FIG. 4B. Scanning electron microscope image of another graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a dry transfer technique. FIG. 4C. Scanning electron microscope image of a graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001) substrate and a wet transfer technique. FIG. 4D. Enlarged view of a portion of the image of FIG. 4C.
FIG. 5. Scanning electron microscope image of an array of graphene crystal structures, including graphene crosses and graphene nanoribbons, as well as other lower aspect ratio structures, made by amorphous carbon seed-mediated chemical vapor deposition growth on a Ge (001) substrate. Graphene nanoribbons having a vertical or horizontal orientation in the image are circled.
DETAILED DESCRIPTION
Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are narrow, elongated strips (or “ribbons”) of monolayer graphene having widths and crystallographic edge structures that provide the ribbons with electronic properties, such as electronic bandgaps, that are absent in continuous two-dimensional films of graphene. The graphene nanoribbons in the arrays are formed using a scalable, bottom-up, chemical vapor deposition (CVD) technique to grow oriented graphene nanoribbons with atomically-smooth edges from seed particles (“seeds”) on the (001) facet of a semiconductor substrate. Because the graphene seeds comprise the same material as the graphene nanoribbons grown therefrom, they can be distinguished from heterogeneous nucleation sites that are provided by other types of materials, such as metals or metal oxides. Without intending to be bound to any particular theory of the invention, it is proposed that by using monolayer graphene seeds having a single crystallographic orientation and their armchair direction (that is, the direction of their lattice that is parallel with the C—C bonds) aligned along a single [110] direction of the (001) facet, the methods are able to produce high density graphene nanoribbon arrays in which the graphene nanoribbons are preferentially aligned along a single [110] direction on the substrate. In the methods, no terraces or other topographical features of the growth substrate are used to template the growth of the nanoribbons.
The graphene seeds can be patterned from a continuous monolayer graphene sheet. The graphene sheet can be grown on a sheet-growth substrate and then transferred onto the semiconductor substrate for patterning and nanoribbon growth. The sheet-growth substrate comprises a material on which the graphene is grown preferentially in a single crystallographic orientation. By grown preferentially, it is meant that most of the graphene in the monolayer is grown with a single crystallographic orientation. However, it should be recognized that there may be imperfections in the sheet-growth substrate that result in a minority of the graphene domains being grown with a different crystallographic orientation. Thus, it is advantageous to use a high-quality sheet-growth surface having a single in-plane orientation. Cu (111) is an example of a sheet-growth substrate material that is suitable for orientation-controlled graphene growth. Other suitable materials for the sheet-growth substrate include Ru (0001), Ni (111), Pd (111), Ir (111), Ge(110), and SiC (0001). Methods for the orientation-controlled CVD growth of graphene on Cu(111) are illustrated in the Example.
The monolayer graphene sheet is then released from its sheet-growth substrate and transferred onto the (001) facet of a semiconductor substrate. Germanium (Ge) is an example of a semiconductor having a (001) facet. Other examples include Group III-V semiconductors, such as GaAs and InAs. The transfer process may involve transferring the monolayer graphene sheet onto a temporary host substrate, followed by a transfer from the host substrate to the semiconductor substrate and the removal of any residual host substrate material. Both wet and dry thin film transfer techniques can be used. Both techniques are illustrated in the Examples which describe the dry transfer of graphene using a poly(methyl methacrylate) (PMMA)/gold (Au) bilayer host substrate and the wet transfer of graphene using a PMMA host substrate.
One or more seeds can then be patterned into the transferred graphene sheet. Typically, an array comprising a plurality of seeds will be patterned into the graphene sheets. For example, the arrays of seeds can comprise at least 10, at least 100, at least 1,000, or at least 10,000 seeds. High resolution lithographic techniques, such as electron beam lithography or extreme ultraviolet lithography, can be used to carry out the patterning. Because the graphene in the monolayer graphene sheet had a preferred crystallographic orientation, the seeds patterned from it will also have that same preferred crystallographic orientation. Again, however, a minority of the seeds may have a different orientation stemming from, for example, imperfections in the original sheet-growth substrate or imperfections introduced during the transfer process. The graphene transfer and subsequent patterning are carried out such that the armchair direction of the seeds is preferentially aligned along a single [110] direction of the (001) facet. As a result, anisotropic CVD growth of graphene nanoribbons from the seeds will be preferentially directed along that same [110] direction.
CVD is an inexpensive scalable technique, offering high throughput and compatibility with planar processing. The graphene nanoribbons are grown directly from the seeds on the (001) facet of a semiconductor platform using hydrocarbon precursor molecules, such as methane. The semiconductor platform can be purchased as a single-crystal wafer or can be epitaxially grown. Single-crystal semiconductor materials are available in large formats and are prevalent in the semiconductor industry. During the CVD growth, the growth conditions are selected to provide a graphene growth rate that is highly anisotropic, resulting in faceted graphene nanoribbons with high aspect ratios. During nanoribbon growth, the (001) facet of the semiconductor substrate is used to orient the long edges of the graphene nanoribbons, as well as the armchair direction of the graphene lattice within the ribbons, along the [110] directions of the semiconductor substrate. In addition, by orienting the graphene seed particles preferentially along a single [110] direction on the (001) facet, as discussed above and illustrated in the Examples, the growth of the graphene nanoribbons can be directed preferentially along that same [110] direction, with exclusively or almost exclusively armchair configurations along their edges. Although there may be a minute portion of zigzag segments near defects or kinks at the nanoribbon edges. FIG. 1A is a schematic illustration of a graphene seed particle on the (001) facet of a substrate. The anisotropic, seed-mediated growth of directionally aligned graphene nanoribbons from a graphene seed is illustrated schematically in FIG. 1B. Conditions and reactants suitable for achieving anisotropic growth of graphene nanoribbons on the (001) facet of a semiconductor substrate are illustrated in U.S. Pat. No. 9,324,804 and in Jacobberger et al., Nature Comm., DOI: 10.1038/ncomms9006, the entire disclosures of which are incorporated herein by reference.
The width of the nanoribbons corresponds closely to the width of the seed particles, with wider seeds producing wider nanoribbons. Although, the nanoribbons may be slightly wider than their seeds by the end of the nanoribbon growth process. Thus, lithographic patterning of the seed particles makes it possible to control the positions, density, inter-nanoribbon spacing, and the widths of the nanoribbons grown from the seeds. In addition, the size of the seed particles produced via lithographic patterning can be further reduced by annealing the seed particles in an atmosphere comprising a mixture of argon and hydrogen. Thus, the size of the seed particles and, therefore, the width of the nanoribbons grown therefrom can be further controlled by controlling the annealing conditions (e.g., temperature, time, and hydrogen concentration).
In some embodiments, the seeds are disposed at random (i.e., non-pre-selected) locations on the surface of the substrate and, therefore, the nanoribbons grown from the seeds form arbitrary designs on the substrate. However, in other embodiments the seeds are patterned into a regular pattern, such that nanoribbons grown from the directionally aligned graphene seeds are laid out on the substrate in a regular pattern. For the purposes of this disclosure a “regular pattern of graphene nanoribbons” is one in which the end-to-end spacing between the nanoribbons and/or the lateral (i.e., edge-to-edge) spacing between the nanoribbons is equal and/or periodically repetitious. (Spacings can be considered equal if they deviate from perfectly equal and the difference is due to limitations in the tolerances of the equipment used to form them.) For example, the schematic diagram in FIG. 2 shows a plurality of graphene nanoribbons laid out in a rectangular array in which the end-to-end and edge-to-edge distances between the nanoribbons are equal. In that figure, the circles represent graphene seeds, as shown in FIG. 1A and the rectangles represent graphene nanoribbons, as shown in FIG. 1B. In some embodiments, the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 20 nm. This includes embodiments in which the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 10 nm and further includes embodiments in which the average width of the seeds in the plurality of seeds and the average width of the nanoribbons in the plurality of nanoribbons is no greater than 5 nm. In some embodiments of the nanoribbon arrays, the nanoribbons that are aligned along a single [110] direction of the (001) facet have a lateral and/or end-to-end spacing with respect to their nearest neighbors (i.e., an inter-nanoribbon spacing) of no greater than 20 nm. This includes embodiments of the nanoribbon arrays in which the nanoribbons that are aligned along a single [110] direction of the (001) facet have a lateral and/or end-to-end spacing with respect to their nearest neighbors of no greater than 10 nm and further includes embodiments of the nanoribbon arrays in which the nanoribbons that are aligned along a single [110] direction of the (001) facet have a lateral and/or end-to-end spacing with respect to their nearest neighbors of no greater than 5 nm. However, larger lateral and/or end-to-end spacings are also possible, including spacings greater than 20 nm, greater than 50 nm, and greater than 100 nm.
The present disclosure is not limited to arrays of graphene nanoribbons in which all of the nanoribbons are aligned along a single [110] direction of the (001) of a substrate. Factors such as the quality of the sheet-growth substrate, the transfer process, and the accuracy of the seed patterning can result in a minority of the nanoribbons being grown at right angles from the selected, predominant [110] direction. However, the level of alignment provided by the present graphene nanoribbon arrays, even using imperfect procedures and substrates, makes them readily distinguishable from arrays of nanoribbons that are randomly aligned along the two equivalent [110] directions of a (001) facet. In a randomly aligned nanoribbon array, 50% of the graphene nanoribbons would be aligned along the first of the two equivalent [110] directions and 50% along the second of the two equivalent [110] directions. In the present graphene nanoribbon arrays, a majority of the graphene nanoribbons are aligned along the same [110] direction. For example, in some embodiments of the graphene nanoribbon arrays, at least 60% of the graphene nanoribbons are aligned along the same [110] direction of the (001) facet of the semiconductor substrate. This includes embodiments in which at least 70% of the graphene nanoribbons are aligned along the same [110] direction of the (001) facet of the semiconductor substrate, further includes embodiments in which at least 80% of the graphene nanoribbons are aligned along the same [110] direction of the (001) facet of the semiconductor substrate, and still further includes embodiments in which at least 90% of the graphene nanoribbons are aligned along the same [110] direction of the (001) facet of the semiconductor substrate. The percentage of alignment for a given distribution of graphene nanoribbons can be determined by analyzing SEM images of the graphene nanoribbons and counting the number of graphene nanoribbons that are in alignment.
For graphene nanoribbon arrays in which less than 100% nanoribbon alignment is achieved over the entire (001) facet, there may be local areas on the (001) facet in which the graphene nanoribbons have perfect (100%) or near perfect (e.g., >95%) alignment along a single [110] direction. For example, even for arrays in which only about 60% of the nanoribbons are aligned along the same [110] direction, there may be portions of the array having a surface area of, for example, at least 4 μm2, in which at least 90%, at least 95%, at least 99%, or even 100% of the nanoribbons are aligned along the same [110] direction.
For the purposes of this disclosure, the long axis of a graphene nanoribbon does not have to be perfectly aligned with (i.e., have a 0° rotation with respect to) a [110] direction of the semiconductor substrate surface in order to be considered aligned along that direction. Small rotational deviations may stem from, for example, an initial rotation in the growth direction that becomes energetically unfavorable as the nanoribbons grow. Thus, at a minimum, a graphene nanoribbon is considered to be aligned along a [110] direction if its long axis is rotated with respect to that directed by a smaller degree than it is with respect to the other [110] direction. For example, a graphene nanoribbon may be considered to be aligned along (or aligned with) a [110] direction if its long axis is rotated by no more than ±15° from the [110] direction of the semiconductor surface. This includes graphene nanoribbon arrays in which nanoribbons that are rotated by no more than ±5° from the [110] direction of the semiconductor surface are considered to be aligned along (or aligned with) a [110] direction, further includes graphene nanoribbon arrays in which nanoribbons that are rotated by no more than ±3° from the [110] direction of the semiconductor surface are considered to be aligned along (or aligned with) a [110] direction, and still further includes graphene nanoribbon arrays in which nanoribbons that are rotated by no more than ±0° from the [110] direction of the semiconductor surface are considered to be aligned along (or aligned with) a [110] direction.
This is illustrated schematically in FIG. 3 for graphene nanoribbons on the (001) facet of a germanium substrate in which one nanoribbon has a perfect alignment and the other is rotated by about 3°. In that figure, the lighter grey circles represent the top two layers of germanium in the substrate, while the darker grey circles, which are only partially visible under the top two layers, represent germanium atoms in lower layers of the substrate. The arrow represents the Ge [110] direction. The upper graphene nanoribbon is perfectly aligned along the Ge [110] direction. In the lower graphene nanoribbon, the armchair crystallographic direction of graphene and the long axis of the ribbons deviate by about 3° from perfect alignment.
Because the graphene nanoribbons are grown via seed-mediated bottom-up growth, rather than patterned lithographically from graphene sheets, they are formed with nearly atomically smooth edges. The degree of edge smoothness can be characterized by the average root mean square (rms) roughness of the edges of the nanoribbons in the array. The rms edge roughness along the length of a nanoribbon can be measured using scanning tunneling microscopy (STM). Methods of using STM to determine the rms edge roughness of a graphene nanoribbon can be found in U.S. Pat. No. 9,287,359. The average rms edge roughness for the nanoribbons in a nanoribbon array will vary since longer nanoribbons within the array will tend to have rougher edges. For the purposes of this disclosure, a nanoribbon is considered to have an atomically smooth edge if its edge has an rms roughness of less than 1 nm over a length of at least 40 nm. Some embodiments of the present nanoribbon growth methods form nanoribbons having an rms roughness of less than 0.5 nm over an edge length of at least 40 nm. This includes embodiments of the growth methods that form nanoribbons that have perfectly atomically smooth edges, that is—having an rms roughness of 0 nm, over an edge length of at least 10 nm.
Short nanoribbons having atomically smooth edges, including those with perfectly atomically smooth edges, are well-suited for use as channel materials in FETs having channel lengths of 40 nm or less, including those having channel lengths of 10 nm or less. Therefore, short nanoribbons having atomically smooth edges can be identified within the nanoribbon arrays and selectively incorporated into an FET. Alternatively, short nanoribbon segments having atomically smooth edges can be cut from longer nanoribbons and selectively incorporated into an FET.
The use of the (001) facet as a growth surface and the conditions for depositing graphene via CVD from a hydrocarbon precursor described herein are selected to provide graphene nanoribbon growth. As a result, the present methods are distinguishable from methods in which CVD is used to grow graphene sheets on a substrate via island growth. In order to distinguish the present graphene nanoribbons from other graphene structures that have been grown via CVD, graphene nanoribbons are defined, for the purposes of this disclosure, as graphene structures having aspect ratios of at least 4 and having at least two edges that run substantially parallel with each other, where the aspect ratio is the ratio of the length of the nanoribbon to its width. In addition, the present graphene nanoribbons, as grown on the semiconductor substrate, are characterized by the armchair crystallographic direction of graphene running substantially parallel to the long nanoribbon axis, which is oriented along a [110] direction of the surface. The phrase ‘substantially parallel’ is used in recognition of the fact that the edges may be parallel on a global scale, but might include edge portions that deviate slightly from perfectly parallel on an atomic scale due to edge roughness.
As illustrated in the Examples below, the graphene nanoribbons can be deposited from a mixture of methane gas and hydrogen gas. By varying the composition of the precursor gas mixture during growth, the duration of the growth time, the growth temperature, and the size and crystallographic orientation of the seeds, the graphene nanoribbon width, length, and aspect ratio can be controlled. This control over the nanoribbon structure makes it possible to tune the graphene properties. For example, graphene undergoes a metallic-to-semiconducting transition as the nanoribbon width decreases, wherein the induced bandgap is inversely proportional to the nanoribbon width. Therefore, the present approach makes it possible to control the width of the nanoribbons and, therefore, to tailor their electronic structure. By tuning the seed size, precursor composition, and growth time, nanoribbons with widths below 10 nm can be grown.
Key parameters for realizing anisotropic growth are the mole fractions of the precursor molecules and the carrier molecules used in the CVD gas mixture, where the mole fractions can be adjusted by adjusting the partial pressures of the precursor and carrier gases. However, these parameters are not independent, so the optimal value for one of the parameters will depend on the others. By way of illustration only, seed-mediated anisotropic growth of nanoribbons from a mixture of H2 and CH4 can be achieved at certain combinations of temperatures in the range from about 860 to 935° C., H2 mole fractions in the range from about 5.0×10−3 to 0.33 and CH4 mole fractions in the range from about 3.0×10−5 to 2.0×10−2. Guidance for selecting an appropriate combination of temperatures and mole fractions (partial pressures) is provided in the Examples, below. In general, nanoribbon growth is favored by a high H2 mole fraction and low CH4 mole fraction, which corresponds to a slow growth rate. For example, in some embodiments of the growth methods, the growth conditions are selected to provide growth rates of no greater than 500 nm/hr. This includes embodiments in which the growth conditions are selected to provide growth rates of no greater than 300 nm/hr, further includes embodiments in which the growth conditions are selected to provide growth rates of no greater than 100 nm/hr and still further includes embodiments in which the growth conditions are selected to provide growth rates of no greater than 35 nm/hr. These growth rates refer to the growth rate of the fastest growing edge dimension of the graphene crystal structures.
In addition to the seed size and seed annealing conditions (discussed above), the growth time plays a role in determining the dimensions of the CVD-grown graphene nanoribbons. Generally, as growth time is decreased, narrower, shorter nanoribbons are formed. Therefore, by tuning the duration of the growth time and the ratio of precursor gas to carrier gas in the gas mixture, nanoribbons with desired lengths and widths can be selectively grown using bottom-up CVD growth.
The optimal conditions for achieving anisotropic graphene growth may vary somewhat depending upon the laboratory conditions. For example, in a cleaner environment, the growth rate at a given set of conditions would be expected to be slower than in a dirtier environment. Therefore, to achieve the same low growth rate observed under standard laboratory conditions in a cleaner system, such as a clean room, a higher CH4 mole fraction and/or a lower H2 mole fraction could be used.
By way of illustration, in some embodiments of the graphene nanoribbon arrays, the average aspect ratio of the nanoribbons in the array is at least 5. This includes graphene nanoribbon arrays in which the average aspect ratio of the nanoribbons in the array is at least 10, further includes graphene nanoribbon arrays in which the average aspect ratio of the nanoribbons in the array is at least 20 and still further includes graphene nanoribbon arrays in which the average aspect ratio of the nanoribbons in the array is at least 30. Included in some embodiments of such arrays are graphene nanoribbons having aspect ratios of at least 30, at least 40, at least 50, at least 60 and/or at least 70.
The average width of the graphene nanoribbons in some of the graphene nanoribbon arrays is no greater than 60 nm. This includes graphene nanoribbon arrays in which the average width of the graphene nanoribbons is no greater than 40 nm and further includes graphene nanoribbon arrays in which the average width of the graphene nanoribbons is no greater than 20 nm. Included in some embodiments of such arrays are graphene nanoribbons having widths of no greater than 10 nm and/or widths of no greater than 5 nm.
The average length of the graphene nanoribbons in some of the graphene nanoribbon arrays is at least 20 nm. This includes graphene nanoribbon arrays in which the average length of the graphene nanoribbons is at least 50 nm, further includes graphene nanoribbon arrays in which the average length of the graphene nanoribbons is at least 100 nm, further includes graphene nanoribbon arrays in which the average length of the graphene nanoribbons is at least 200 nm, and further includes graphene nanoribbon arrays in which the average length of the graphene nanoribbons is at least 500 nm.
While graphene seed-mediated, CVD-based graphene nanoribbon growth methods can be used to grow graphene nanoribbons having their graphene crystal lattice oriented preferentially along one [110] direction of a (001) facet, without the need to use step edges or trenches to dictate the growth direction, they can also be used to grow graphene nanoribbons having their crystal lattice oriented non-preferentially along both of the two equivalent [110] directions of a (001) surface. Preferential orientation along one direction can be carried out by transferring a monolayer graphene sheet with a preferred crystal orientation onto the (001) facet of a semiconductor substrate, patterning an array of graphene seeds into the monolayer graphene sheets, and carrying out anisotropic CVD growth of graphene nanoribbons from the seeds, as described above. However, if preferential alignment of the nanoribbons is not required or desired, the graphene seeds need not be formed with a preferred crystallographic orientation with their crystal lattice aligned along a single [110] direction of the (001) facet. In the graphene nanoribbon arrays made under these conditions, the nanoribbon alignment will closely reflect the distribution of each crystal orientation in the graphene monolayer from which the seeds were formed.
Alternatively, for applications where it is not required or desired for the graphene nanoribbons to be preferentially aligned along a single [110] direction, amorphous carbon seeds can be used, rather than crystalline graphene seeds, for nucleating anisotropic CVD growth of nanoribbons on the (001) facet of a semiconductor substrate. Because the amorphous carbon seeds lack a lattice orientation capable of directing graphene nanoribbon growth along a single direction, graphene nanoribbon growth from the amorphous carbon seeds will be random and, therefore, evenly distributed along the two equivalent [110] directions and, in some cases, may grow in cross shapes on the substrate surface.
In addition, if amorphous carbon seeds are used, selective growth along a single [110] direction can be achieved by miscutting the growth surface of the semiconductor substrate toward a 110 direction, such that a series of parallel (001) faceted terraces, separated by steps that are a multiple of two atomic layers in height, are formed and the graphene nanoribbons are grown with a parallel alignment along the terraces. For example, the steps can be two, four, six, eight, ten, etc., atomic layers in height. The terraces can be formed using a miscut angle of, for example, about 9° or higher in order to provide steps that are two atomic layers high.
The present methods can produce graphene nanoribbon arrays having a high density of very narrow, smooth-edged, nanoribbons over a large area. Arrays of these atomically-smooth nanoribbons can include thousands of nanoribbons and can be formed over areas of, for example, at least 1 μm2. This includes high density nanoribbon arrays that extend over areas of at least 100 μm2, at least 1 mm2, and at least 10 mm2, the area of the nanoribbon arrays being limited only by the area of the surface of the substrate.
The graphene nanoribbon arrays can be incorporated into a variety of devices, including electronic and photonic devices, such as field effect transistors and photodetectors. One embodiment of a field effect transistor comprising a graphene nanoribbon array comprises: a source electrode; a drain electrode; a gate electrode; a conducting channel in electrical contact with the source electrode and the drain electrode; a gate dielectric disposed over the conducting channel, but below the gate electrode; and a semiconductor substrate having a (001) facet. In the transistor, the conducting channel comprises a plurality of directionally aligned graphene nanoribbons on the (001) facet of the semiconductor substrate, wherein the long nanoribbon axis is oriented along a [110] direction of the semiconductor surface and the nanoribbons have the armchair crystallographic direction of graphene running parallel to the long edges of the nanoribbons.
Alternatively, once the graphene nanoribbon arrays are formed on the semiconductor substrates, they can be transferred to other substrates, such as silicon substrates, polymer (e.g., plastic) substrates, dielectric substrates or metal substrates. Methods for transferring graphene from a germanium substrate to another substrate are described in Wang et al., Scientific Reports 3, Article number: 2465. The transfer procedure described in the Examples that follow illustrates a modified version of the methods described in Wang et al. The transferred graphene nanoribbons and the substrate onto which they are transferred can then be incorporated into a variety of devices.
EXAMPLES Example 1: Graphene Seed-Mediated CVD Growth of Preferentially Aligned Graphene Nanoribbons on Germanium (001)
Materials and Methods:
Monolayer Graphene Synthesis on Cu (111):
A copper (Cu) thin film was deposited onto a sapphire (0001) substrate (MTI Corp.) using a CVC 601 DC magnetron sputterer operating at 1 kW with 5 mtorr of argon (Ar) backfill. Graphene growth was performed in a horizontal hot-walled chemical vapor deposition (CVD) system with a quartz tube having an inner diameter of 34 mm. The Cu/sapphire sample was loaded into the system and the system was then filled to atmospheric pressure with a mixture of Ar (purity of 99.999%) and hydrogen (H2) (purity of 99.999%) with a flow rate of 345 sccm and 18 sccm, respectively. The Cu/sapphire sample was annealed for 4 minutes at 1000° C. and then 87 ppm of methane (CH4) (purity of 99.99%) was introduced to begin the graphene synthesis. Growth occurred for 1.5 hours before the sample was rapidly cooled to terminate synthesis, at which point a continuous monolayer of graphene was coated onto the Cu (111) thin films.
Dry Transfer of Graphene onto Germanium:
The first method used to transfer the monolayer graphene from the Cu growth substrate onto Ge was a dry transfer. In this process, a 60 nm layer of gold (Au) was thermally evaporated on the graphene/Cu/sapphire substrate. A solution of 4% 950 kg/mol PMMA in anisole was spin coated on the Au/graphene/Cu/sapphire structure at 3000 rpm for 1 minute. The sample was then baked on a hot plate at 185° C. for 10 minutes. Thermal release tape (TRT) was adhered to the PMMA/Au/graphene/Cu/sapphire and then removed, separating the PMMA/Au/graphene from the Cu/sapphire substrate. This stack was immediately stamped onto Ge (001) and the TRT was subsequently released on a hot plate at 120° C., resulting in a PMMA/Au/graphene/Ge stack. The sample was baked on a hot plate at 185° C. for 10 minutes. The stack was then loaded into a horizontal tube furnace and the system was filled to atmospheric pressure with a mixture of 95% Ar (purity of 99.999%) and 5% H2 (purity of 99.999%) with a total flow rate of 50 sccm. The sample was annealed for 1 hour at 400° C. to remove the PMMA. The Au/graphene/Ge was placed in potassium iodide (KI) for 20 minutes to etch the Au layer and then rinsed in a water (H2O) bath at 90° C. for 20 minutes, resulting in a continuous monolayer of graphene on a Ge (001) wafer.
Wet Transfer of Graphene onto Germanium:
The second method used to transfer monolayer graphene from Cu onto Ge was a wet transfer. In this process, a solution of 4% 950 kg/mol PMMA in anisole was spin coated on the graphene/Cu/sapphire substrate at 2000 rpm for 1 minute. The PMMA/graphene/Cu/sapphire stack was submerged in 0.2 M iron (III) chloride (FeCl3)/0.2 M hydrochloric acid (HCl) to etch the Cu layer. The resulting PMMA/graphene membrane was transferred to and floated on the surface of a water bath. Ge (001) was then used to lift the PMMA/graphene membrane out of the water bath. The PMMA/graphene/Ge was placed on a spin coater and rotated at 4000 rpm to spin dry. The PMMA/graphene/Ge stack was placed in acetone at 120° C. for 15 minutes to dissolve the PMMA and then washed with isopropyl alcohol (IPA), resulting in a continuous monolayer of graphene on a Ge (001) wafer.
Graphene Dot Array Production:
In order to pattern the continuous graphene film on Ge (001) into isolated seeds, a solution of 1% 950 kg/mol PMMA in chlorobenzene was spin coated at 4000 rpm for 1 minute. The sample was then placed on a hot plate at 185° C. for 1.5 minutes. Electron-beam lithography was used to define the graphene seed patterns. The patterns were developed in 1:3 methyl isobutyl ketone (MIBK)/IPA for 1 minute. Thermal evaporation was used to deposit 10 nm of aluminum (Al) onto the sample. The sample was then placed in acetone at 120° C. for 10 minutes before being sonicated for 10 minutes to remove Al/PMMA in regions that were not exposed to the electron beam during patterning. The Al mask/graphene/Ge stack was placed in a Unaxis 790 Reactive Ion Etcher for a 30 second O2 plasma (50 W, 10 mtorr) etch to remove all graphene that was not covered by the Al mask. The Al was etched in phosphoric acid (H3PO4) for 30 minutes, leaving the patterned graphene seeds on Ge (001).
Graphene Nanoribbon Growth:
The graphene seed array on Ge (001) was loaded into a horizontal hot-walled CVD system with a quartz tube having an inner diameter of 34 mm. The system was evacuated to ˜10−6 torr and then filled to atmospheric pressure with a mixture of Ar (purity of 99.999%) and H2 (purity of 99.999%) with a total flow rate of 300 sccm. The sample was annealed for 1 hour at 910° C. and then CH4 (purity of 99.99%) was introduced to begin synthesis. Nanoribbons can be grown over a wide range of conditions, some of which are provided in Supplementary Table 1 of the article “Direct oriented growth of armchair graphene nanoribbons on germanium” in Jacobberger et al., Nature Comm., DOI: 10.1038/ncomms9006. For example graphene nanoribbons can be grown from the graphene seeds using 200 sccm Ar, 100 sccm H2, and 2.0 sccm CH4 at 910° C. for 2 hours. Growth was terminated by rapidly cooling the samples in the same atmosphere used during synthesis by sliding the furnace away from the growth region. During synthesis, graphene nucleation occurred preferentially at the lithographically-defined seeds, resulting in the formation of nanoribbons at these locations. If the graphene seeds have a single orientation (or predominantly a single orientation), as they do if graphene grown on Cu (111) is transferred to Ge (001), and if the seeds are aligned along a single in-plane Ge [110] direction (or predominantly a single in-plane Ge [110] direction), the long-axis of the nanoribbons preferentially aligns along that same direction, resulting in unidirectional (or predominantly unidirectional) arrays of graphene nanoribbons.
Characterization:
After growth, the samples are characterized using a Zeiss LEO 1530 Scanning Electron Microscope (SEM).
Results:
An SEM image of a graphene nanoribbon array on a Ge (001) substrate is shown in FIG. 4A. FIG. 4B is an SEM image of another graphene nanoribbon array made by graphene seed-mediated chemical vapor deposition growth on a Ge (001). These arrays were made by dry transferring the graphene. The seeds were annealed for 1 hour and then the nanoribbons were grown for 2 hours with growth conditions of 200 sccm Ar, 100 sccm H2, and 2.0 sccm CH4 at 910° C. In the sample of graphene nanoribbons in FIG. 4A, 73% are aligned along the vertical direction in the image. For the purposes of this example and the percentages of alignment recited herein, graphene nanoribbons were considered aligned if they were rotated by no more than ±5° from the [110] direction of the semiconductor surface. The average length is 393±72 nm, the average width is 51.3±15.8 nm, and average aspect ratio is 7.6±3.4. In the sample of graphene nanoribbons in FIG. 4B, 82% are aligned along the vertical direction in the image. The average length is 319±75 nm, the average width is 35±19 nm, and the average aspect ratio is 11.3±7.6.
An SEM image of another graphene nanoribbon array on a Ge (001) substrate is shown in FIG. 4C. An enlarged portion of the array is shown in FIG. 4D. This array was made by wet transferring the graphene. The seeds were annealed for 1 hour and then the nanoribbons were grown for 1.75 hours with growth conditions of 200 sccm Ar, 100 sccm Hz, and 2.0 sccm CH4 at 910° C. In the sample of graphene nanoribbons in FIGS. 4C and 4D, 79% are aligned along the vertical direction in the image. The average length is 338±48 nm, the average width is 89.6±17.5 nm, and the average aspect ratio is 3.77±0.8.
Example 2: Amorphous Carbon-Mediated CVD Growth of Randomly Aligned Graphene Nanoribbons on Germanium (001)
a-C Array Production:
In order to pattern an array of amorphous carbon (a-C) seeds on Ge (001), a solution of 1% 950 kg/mol PMMA in chlorobenzene was spin coated onto a Ge (001) substrate at 4000 rpm for 1 minute. The sample was then baked on a hot plate at 185° C. for 1.5 minutes. Electron-beam lithography was used to define the seed patterns. The patterns were developed in 1:3 methyl isobutyl ketone (MIBK):IPA for 1 minute. A plasma sputterer was used to deposit 5 nm of carbon (C) onto the sample using a graphite source. The sample was then placed in acetone at 120° C. for 10 minutes before being sonicated for 10 minutes to remove a-C/PMMA in regions that were not exposed to the electron beam during patterning. This resulted in a patterned array of a-C seeds on Ge (001).
Graphene nanoribbon growth and characterization were carried out as described in Example 1.
The array of graphene crystal structures is shown in the SEM image of FIG. 5. As shown in the image, the structures include graphene nanoribbons aligned along both [110] directions of the germanium (circled), as well as graphene crosses and crystal structures having low aspect ratios (e.g., graphene islands).
The word “illustrative” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “illustrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Further, for the purposes of this disclosure and unless otherwise specified, “a” or “an” means “one or more”.
The foregoing description of illustrative embodiments of the invention has been presented for purposes of illustration and of description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and as practical applications of the invention to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (21)

What is claimed is:
1. A graphene nanoribbon array comprising:
a semiconductor substrate having a (001) facet; and
a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate;
wherein the graphene nanoribbons have aspect ratios of at least 4; and
further wherein the graphene nanoribbons have an armchair crystallographic direction of graphene running all the way along their long axes and an armchair configuration along their edges, and further wherein at least 60 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate.
2. The graphene nanoribbon array of claim 1, wherein at least 80 percent of the graphene nanoribbons have their long axis oriented along a single [110] direction of the semiconductor substrate.
3. The graphene nanoribbon array of claim 1, wherein the at least 60 percent of the graphene nanoribbons have their long axes rotated by no more than ±15° from the [110] direction of the semiconductor substrate.
4. The graphene nanoribbon array of claim 1, wherein the at least 80 percent of the graphene nanoribbons have their long axes rotated by no more than ±5° from the [110] direction of the semiconductor substrate.
5. The graphene nanoribbon array of claim 1, wherein the semiconductor substrate having a (001) facet is a germanium substrate.
6. The graphene nanoribbon array of claim 1, wherein the semiconductor substrate having a (001) facet is a semiconductor substrate.
7. The array of claim 1, wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor are arranged in a regular pattern.
8. The array of claim 1, wherein the average width of the graphene nanoribbons in the array is no greater than 50 nm.
9. The array of claim 8, wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor have a lateral spacing of no greater than 50 nm.
10. The array of claim 1, wherein the plurality of graphene nanoribbons comprises graphene nanoribbons having edges with an rms roughness of 1 nm or lower over edge lengths of at least 40 nm.
11. The array of claim 1 comprising at least 1000 of the graphene nanoribbons.
12. The array of claim 1, wherein the graphene nanoribbons do not comprise heterogeneous nucleation sites along their lengths.
13. The array of claim 1 comprising at least 1000 of the graphene nanoribbons, the graphene nanoribbons having an average width of no greater than 10 nm and a lateral spacing of no greater than 10 nm, wherein the graphene nanoribbons having their long axes oriented along a single [110] direction of the semiconductor are arranged in a regular pattern.
14. A graphene nanoribbon array comprising:
a semiconductor substrate having a (001) facet; and
a plurality of graphene nanoribbons on the (001) facet of the semiconductor substrate, each of the graphene nanoribbons comprising an amorphous carbon seed along its length;
wherein the graphene nanoribbons have aspect ratios of at least 4; and
wherein the graphene nanoribbons have the armchair crystallographic direction of graphene running all the way along their long axes with an armchair configuration along their edges; and
further wherein the graphene nanoribbons have their long axes oriented along a [110] direction of the semiconductor.
15. A method of growing graphene nanoribbons, the method comprising:
forming an array of graphene seeds on the (001) facet of a semiconductor substrate, wherein a majority of the graphene seeds have a single crystallographic orientation; and
growing graphene nanoribbons from the graphene seeds via chemical vapor deposition from a mixture of methane gas and hydrogen gas, wherein the partial pressures of the methane and hydrogen are selected to result in the growth of graphene nanoribbons having their long axes oriented along a [110] direction of the semiconductor substrate and their armchair edges running parallel with the [110] direction of the semiconductor substrate.
16. The method of claim 15, wherein at least 60% of the graphene nanoribbons are oriented along the same [110] direction of the semiconductor substrate.
17. The method of claim 15, wherein the step of forming an array of graphene seeds on the (001) facet of a semiconductor substrate comprises:
growing a sheet of monolayer graphene on a surface of a sheet-growth substrate;
transferring the sheet of monolayer graphene onto a (001) facet of a semiconductor substrate; and
patterning an array of graphene seeds into the sheet of monolayer graphene and removing the remainder of the sheet of monolayer graphene.
18. The method of claim 17, wherein the surface of the sheet-growth substrate is the (111) facet of a copper substrate.
19. The method of claim 15, wherein the graphene nanoribbons have an average width of no greater than about 10 nm.
20. The method of claim 15, further comprising incorporating the graphene nanoribbons and the semiconductor substrate into an electronic or photonic device.
21. The method of claim 15, further comprising releasing at least a portion of the graphene nanoribbons from the semiconductor substrate and transferring the released graphene nanoribbons to a second substrate.
US15/212,413 2016-07-18 2016-07-18 Seed-mediated growth of patterned graphene nanoribbon arrays Active US9761669B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/212,413 US9761669B1 (en) 2016-07-18 2016-07-18 Seed-mediated growth of patterned graphene nanoribbon arrays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/212,413 US9761669B1 (en) 2016-07-18 2016-07-18 Seed-mediated growth of patterned graphene nanoribbon arrays

Publications (1)

Publication Number Publication Date
US9761669B1 true US9761669B1 (en) 2017-09-12

Family

ID=59752907

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/212,413 Active US9761669B1 (en) 2016-07-18 2016-07-18 Seed-mediated growth of patterned graphene nanoribbon arrays

Country Status (1)

Country Link
US (1) US9761669B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170242083A1 (en) * 2016-02-19 2017-08-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Magnetic Field Sensor Using In Situ Solid Source Graphene and Graphene Induced Anti-Ferromagnetic Coupling and Spin Filtering
US20200286732A1 (en) * 2019-03-04 2020-09-10 Samsung Electronics Co., Ltd. Method of pre-treating substrate and method of directly forming graphene using the same
US11618681B2 (en) 2021-06-28 2023-04-04 Wisconsin Alumni Research Foundation Graphene nanoribbons grown from aromatic molecular seeds

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100200840A1 (en) 2007-07-16 2010-08-12 International Business Machines Corporation Graphene-based transistor
US20100255219A1 (en) 2009-04-07 2010-10-07 Samsung Electronics Co., Ltd. Methods of preparing a graphene sheet
US20110114919A1 (en) 2009-11-13 2011-05-19 International Business Machines Corporation Self-aligned graphene transistor
US20110244662A1 (en) 2010-03-31 2011-10-06 Samsung Electronics Co., Ltd. Method of manufacturing graphene by using germanium layer
US20120003438A1 (en) 2009-02-20 2012-01-05 University Of Florida Research Foundation, Inc. Graphene processing for device and sensor applications
US20120068157A1 (en) 2010-09-21 2012-03-22 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transistor Having Graphene Base
US20120085991A1 (en) 2010-10-12 2012-04-12 International Business Machines Corporation Graphene nanoribbons, method of fabrication and their use in electronic devices
US20120141799A1 (en) 2010-12-03 2012-06-07 Francis Kub Film on Graphene on a Substrate and Method and Devices Therefor
US20120181507A1 (en) 2011-01-19 2012-07-19 International Business Machines Corporation Semiconductor structure and circuit including ordered arrangment of graphene nanoribbons, and methods of forming same
JP2012172065A (en) 2011-02-22 2012-09-10 Morinobu Endo Pencil lead and method for producing the same
US20120261644A1 (en) 2011-04-18 2012-10-18 International Business Machines Corporation Structure and method of making graphene nanoribbons
EP2540662A2 (en) 2011-06-27 2013-01-02 Samsung Electronics Co., Ltd. Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device
US20130027778A1 (en) 2011-07-27 2013-01-31 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Broadband Absorptive Neutral Density Optical Filter
US20130099195A1 (en) 2011-10-19 2013-04-25 Kansas State University Research Foundation Direct Formation of Graphene on Semiconductor Substrates
US20130099205A1 (en) 2011-10-21 2013-04-25 University Of Utah Research Foundation Homogeneous multiple band gap devices
US20130108839A1 (en) 2011-10-27 2013-05-02 Wisconsin Alumni Research Foundation Nanostructured graphene with atomically-smooth edges
US20130160701A1 (en) 2011-08-25 2013-06-27 Michael S. Arnold Barrier guided growth of microstructured and nanostructured graphene and graphite
US20140264281A1 (en) 2013-03-13 2014-09-18 Intermolecular, Inc. Channel-Last Methods for Making FETS
US20150037048A1 (en) 2013-08-02 2015-02-05 Yun-Chung Na Low voltage photodetectors
US9287359B1 (en) 2014-09-15 2016-03-15 Wisconsin Alumni Research Foundation Oriented bottom-up growth of armchair graphene nanoribbons on germanium
US9324804B2 (en) 2014-03-21 2016-04-26 Wisconsin Alumni Research Foundation Graphene-on-semiconductor substrates for analog electronics

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100200840A1 (en) 2007-07-16 2010-08-12 International Business Machines Corporation Graphene-based transistor
US20120003438A1 (en) 2009-02-20 2012-01-05 University Of Florida Research Foundation, Inc. Graphene processing for device and sensor applications
US20100255219A1 (en) 2009-04-07 2010-10-07 Samsung Electronics Co., Ltd. Methods of preparing a graphene sheet
US20110114919A1 (en) 2009-11-13 2011-05-19 International Business Machines Corporation Self-aligned graphene transistor
US20110244662A1 (en) 2010-03-31 2011-10-06 Samsung Electronics Co., Ltd. Method of manufacturing graphene by using germanium layer
US20120068157A1 (en) 2010-09-21 2012-03-22 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transistor Having Graphene Base
US20120085991A1 (en) 2010-10-12 2012-04-12 International Business Machines Corporation Graphene nanoribbons, method of fabrication and their use in electronic devices
US20120141799A1 (en) 2010-12-03 2012-06-07 Francis Kub Film on Graphene on a Substrate and Method and Devices Therefor
US20120181507A1 (en) 2011-01-19 2012-07-19 International Business Machines Corporation Semiconductor structure and circuit including ordered arrangment of graphene nanoribbons, and methods of forming same
JP2012172065A (en) 2011-02-22 2012-09-10 Morinobu Endo Pencil lead and method for producing the same
US20120261644A1 (en) 2011-04-18 2012-10-18 International Business Machines Corporation Structure and method of making graphene nanoribbons
EP2540662A2 (en) 2011-06-27 2013-01-02 Samsung Electronics Co., Ltd. Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device
US20130027778A1 (en) 2011-07-27 2013-01-31 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Broadband Absorptive Neutral Density Optical Filter
US20130160701A1 (en) 2011-08-25 2013-06-27 Michael S. Arnold Barrier guided growth of microstructured and nanostructured graphene and graphite
US20130099195A1 (en) 2011-10-19 2013-04-25 Kansas State University Research Foundation Direct Formation of Graphene on Semiconductor Substrates
US20130099205A1 (en) 2011-10-21 2013-04-25 University Of Utah Research Foundation Homogeneous multiple band gap devices
US20130108839A1 (en) 2011-10-27 2013-05-02 Wisconsin Alumni Research Foundation Nanostructured graphene with atomically-smooth edges
US20140264281A1 (en) 2013-03-13 2014-09-18 Intermolecular, Inc. Channel-Last Methods for Making FETS
US20150037048A1 (en) 2013-08-02 2015-02-05 Yun-Chung Na Low voltage photodetectors
US9324804B2 (en) 2014-03-21 2016-04-26 Wisconsin Alumni Research Foundation Graphene-on-semiconductor substrates for analog electronics
US9287359B1 (en) 2014-09-15 2016-03-15 Wisconsin Alumni Research Foundation Oriented bottom-up growth of armchair graphene nanoribbons on germanium

Non-Patent Citations (31)

* Cited by examiner, † Cited by third party
Title
A. Toriumi, Recent Progress of Germanium MOSFETs, 2012 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Osaka, May 9, 2012, pp. 1-2.
Biro et al., Nanopatterning of graphene with crystallographic orientation control, Carbon, vol. 48, Apr. 14, 2010, pp. 2677-2689.
Bodlaki et al., Ambient stability of chemically passivated germanium interfaces, Surface Science, vol. 543, 2003, pp. 63-74.
Bortug et al., Strained-Germanium Nanostructures for Infrared Photonics, ACS Nano, vol. 8, No. 4, Mar. 5, 2014, pp. 3136-3151.
Brey, L., et al., "Electronic states of graphene nanoribbons studied with the Dirac equation," Physical Review (Jun. 15, 2006), vol. 73, 235411, 5 pp. See, abstract and figure 1.
Brunco et al., Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance, Journal of the Electrochemical Society, vol. 155, No. 7, May 23, 2008, pp. H552-H561.
Chui et al., A Sub-400° C. Germanium MOSFET Technology with High-K Dielectric and Metal Gate, International Electron Devices Meeting, 2002. IEDM '02, San Francisco, CA, Dec. 8, 2002, pp. 437-440.
Chung, H.C., et al., "Exploration of edge-dependent optical selection rules for graphene nanoribbons," Optic Express (Nov. 1, 2011) (Online), vol. 19, pp. 23351-23363. See, abstract and figure 1.
Cooper et al., Experimental Review of Graphene, International Scholarly Research Network Condensed Matter Physics, vol. 2012, article ID 501686, 2012, pp. 1-56.
International Search Report & Written Opinion issued on Oct. 30, 2015, for Intl. Patent Appl. No. PCT/US2015/049325, 11 pp.
Jacobberger et al., Direct oriented growth of armchair graphene nanoribbons on germanium, Nature Communications | 6:8006, Aug. 10, 2015, pp. 1-8.
K. Saraswat, Novel Electronic and Optoelectronic Devices in Germanium Integrated on Silicon, ECS Transactions, vol. 33, No. 6, 2010, pp. 101-108.
Klekachev et al., Graphene Transistors and Photodetectors, The Electrochemical Society Interface, vol. 22, No. 1, Spring 2013, pp. 63-68.
Lee et al., Wafer-Scale Growth of Single-Crystal Monolayer Graphene on Reusable Hydrogen-Terminated Germanium, Science, vol. 344, Apr. 3, 2014, pp. 286-289.
Li et al., Synthesis, Characterization, and Properties of Large-Area Graphene Films, ECS Transactions, vol. 19, No. 5, 2009, pp. 41-52.
Lippert et al., Graphene Grown on Ge(001) from Atomic Source, Obtained online from Cornell University Library, published prior to Mar. 21, 2014.
Murdock et al., Controlling the Orientation, Edge Geometry, and Thickness of Chemical Vapor Deposition Graphene, ACS Nano, vol. 7, No. 2 , Jan. 24, 2013, pp. 1351-1359.
Nazarenkov et al., Mechanism of photo-stimulated processes in GeOx films, Thin Solid Films, vol. 254, 1995, pp. 164-168.
Nemes-lncze et al., Graphene nanoribbons with zigzag and armchair edges prepared by scanning tunneling microscope lithography on gold substrates microscope lithography on gold substrates, Applied Surface Science, vol. 291, Nov. 13, 2013, pp. 48-52.
Non-Final Office Action for U.S. Appl. No. 14/222,163, mailed on Jun. 29, 2015, 23 pp.
Online Disclosure for P130002US01, Available online prior to Mar. 21, 2014.
Prabhakaran et al., Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces, Applied Physics Letters, vol. 76, No. 16, Apr. 17, 2000, pp. 2244-2246.
Saraswat et al., High performance germanium MOSFETs, Materials Science and Engineering B, vol. 135, 2006, pp. 242-249.
T. Wogan, Growing great graphene on germanium, Chemistry World, http://www.rsc.org/chemistryworld/2014/04/growing-great-graphene-germanium-defect-free-electronics, Apr. 3, 2014.
Toriumi et al., Material Potential and Scalability Challenges of Germanium CMOS, 2011 IEEE International Electron Devices Meeting (IEDM), Washington, DC , Dec. 5, 2011, pp. 28.4.1-28.4.4.
Wang et al., Direct Growth of Graphene Film on Germanium Substrate, Scientific Reports, vol. 3, No. 2465, Aug. 19, 2013.
Wang et al., Etching and Narrowing of Graphene from the Edges, Nature Chemistry, vol. 2, Jun. 27, 2010, pp. 661-665.
Wang et al., Germanium nanowire field-effect transistors with SiO2 and high-k HfO2 gate dielectrics, Applied Physics Letters, vol. 83, No. 12, Sep. 22, 2003, pp. 2432-2434.
Wu et al., Growth of Single Crystal Graphene Arrays by Locally Controlling Nucleation on Polycrystalline Cu Using Chemical Vapor Deposition, Adv. Mater., 23, Sep. 23, 2011, pp. 4898-4903.
Y. Kamata, High-k/Ge MOSFETs for future nanoelectronics, materials today, vol. 11, No. 1-2, Jan. 2008, pp. 30-38.
Yu et al., Control and characterization of individual grains and grain boundaries in graphene grown by chemical vapour deposition, Nature Materials, vol. 10, May 8, 2011, pp. 443-449.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170242083A1 (en) * 2016-02-19 2017-08-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Magnetic Field Sensor Using In Situ Solid Source Graphene and Graphene Induced Anti-Ferromagnetic Coupling and Spin Filtering
US10261139B2 (en) * 2016-02-19 2019-04-16 The United States Of America, As Represented By The Secretary Of The Navy Method of making a magnetic field sensor
US20200286732A1 (en) * 2019-03-04 2020-09-10 Samsung Electronics Co., Ltd. Method of pre-treating substrate and method of directly forming graphene using the same
US11618681B2 (en) 2021-06-28 2023-04-04 Wisconsin Alumni Research Foundation Graphene nanoribbons grown from aromatic molecular seeds

Similar Documents

Publication Publication Date Title
US9287359B1 (en) Oriented bottom-up growth of armchair graphene nanoribbons on germanium
US8597738B2 (en) Fabrication of single-crystalline graphene arrays
US6413880B1 (en) Strongly textured atomic ridge and dot fabrication
US9803292B2 (en) Barrier guided growth of microstructured and nanostructured graphene and graphite
US9108850B2 (en) Preparing nanoparticles and carbon nanotubes
Choi et al. Fabrication of SiC nanopillars by inductively coupled SF6/O2 plasma etching
US8852342B2 (en) Formation of a vicinal semiconductor-carbon alloy surface and a graphene layer thereupon
US9761669B1 (en) Seed-mediated growth of patterned graphene nanoribbon arrays
US20150376778A1 (en) Graphene growth on sidewalls of patterned substrate
Tada et al. Spontaneous production of 10-nm Si structures by plasma etching using self-formed masks
JP2007182349A (en) Method for producing nanotube and quantum dot
Barbagini et al. Critical aspects of substrate nanopatterning for the ordered growth of GaN nanocolumns
Reina et al. Graphene growth by CVD methods
Jacobberger et al. Effect of Germanium Surface Orientation on Graphene Chemical Vapor Deposition and Graphene-Induced Germanium Nanofaceting
Karmous et al. Ordering of Ge nanocrystals using FIB nanolithography
Sala et al. Ordered array of Ga droplets on GaAs (001) by local anodic oxidation
US11136666B2 (en) Ordered nanotubes on a two-dimensional substrate consisting of different material properties
Lee et al. A growth method for creating arrays of atomically flat mesas on silicon
US11085130B2 (en) Method for producing nanostructures
US11618681B2 (en) Graphene nanoribbons grown from aromatic molecular seeds
US11651958B2 (en) Two-dimensional material device and method for manufacturing same
Boulanger et al. Gallium loading of gold seed for high yield of patterned GaAs nanowires
Lei et al. Fabrication of Highly Ordered Nanoparticle Arrays Using Thin Porous Alumina Masks
Schmidt et al. Selective growth of SiGe structures in the sub 100 nm range using low pressure vapor phase epitaxy
KR20120096850A (en) Nano wire fabrication method

Legal Events

Date Code Title Description
AS Assignment

Owner name: WISCONSIN ALUMNI RESEARCH FOUNDATION, WISCONSIN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARNOLD, MICHAEL;JACOBBERGER, ROBERT;WAY, AUSTIN;SIGNING DATES FROM 20160801 TO 20160805;REEL/FRAME:039890/0908

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

Year of fee payment: 4

AS Assignment

Owner name: UNITED STATES DEPARTMENT OF ENERGY, DISTRICT OF COLUMBIA

Free format text: CONFIRMATORY LICENSE;ASSIGNOR:UNIVERSITY OF WISCONSIN-MADISON;REEL/FRAME:059441/0087

Effective date: 20160729