US3745562A

US3745562A - Digital transmission system with frequency weighted noise reduction

Info

Publication number: US3745562A
Application number: US00214051A
Authority: US
Inventors: A Rosenbaum
Original assignee: Bell Telephone Laboratories Inc
Current assignee: AT&T Corp
Priority date: 1971-12-30
Filing date: 1971-12-30
Publication date: 1973-07-10
Anticipated expiration: 1990-07-10
Also published as: NL7217828A; DE2263757A1; JPS4875161A; BE793564A; DE2263757C2; JPS5639577B2; GB1370710A; IT976174B; CA991311A; FR2166220A1; SE387796B

Abstract

An analog-to-digital encoder uses an N dimensional quantizer to simultaneously generate N digits of the output code for an input analog signal. When the quantizer is used as a Delta modulator, the inputs to it are developed in N summing circuits. The first summing circuit has the present sample of the analog signal as an input and the other summing circuits have one of (N-1) future samples applied to their inputs, respectively. A local decoder at the output of the quantizer generates a reconstruction or approximation of the analog signal and applies it to each of the summing circuits. In addition, past error terms are stored, multiplied by weighting coefficients, and combined into signals which are also applied to the summing circuits. The proper selection of weighting coefficients and decision threshold levels in the quantizer produces an output code which has a minimum frequency weighted quantizing error.

Description

Rosenbaum ted States Patent 11 1 DIGITAL TRANSMISSION SYSTEM WITH FREQUENCY WEIGHTED NOISE 3,500,331 3/1910 Conway 340/347x REDUCTION Primary Examiner-Charles D. Miller Att ne --W. L. Keefauver [75] inventor: Arnold Stephen Rosenbaum, or y Mrddletown, NJ. 7 ABSTRACT [73] Assignee: Bell Telephone Laboratories, An analog-to-digital encoder uses an N dimensional Incorporated, Murray Hill, NJ. quantizer to simultaneously generate N digits of the output code for an input analog signal. When the quan- [22] 1971 tizer is used as a Delta modulator, the inputs to it are [21] Appl. No.: 214,051 developed in N summing circuits. The first summing circuit has the present sample of the analog signal as an input and the other summing circuits have one of (5 IIIIIIII 340/347 ;52:333; (N-l) future samples applied to their inputs, respec- [58] Fie'm T 325/38 tively. A local decoder at the output of the quantizer "5 333/18 generates a reconstruction or approximation of the analog signal and applies it to each of the summing circuits. In addition, past error terms are stored, multi- [56] References Cited plied by weighting coefficients, and combined into sig- UNITED STATES PATENTS nals which are also applied to the summing circuits. 3,414,819 12/1968 Lucky 333/18 X The proper selection of weighting coefficients and de- 3,026,375 3/1962 Graham 325/38 X cision threshold levels in the quantizer produces an output code which has a minimum frequency weighted 3:354:267 11/1967 Crater .1: "1325/38 )1 quamzmg 3,479,458 11/1969 Lord at a]. 325/42 15 Claims, 8 Drawing Figures IOO INPUT -5AMPLER COMBlNER I v 1- T 50 A COMBINER LOCAL L DECODER ,140 F when I COMBINER I PAIENIH] JUL 1 0 I975 SHEET 3 OF 5 u r F FREQUENCY IN KC FIG. .38

FREQUENCY IN KC l I 0 I5 FREQUENCY lN KC FIG. 30

I PATENTEU JUN '3 SHEET 5 BF 5 FIG. 5

LOCAL DECODER 500 T N-l N SOURCE SAMPLES DIGITAL TRANSMISSION SYSTEM WITH FREQUENCY WEIGHTED NOISE REDUCTION BACKGROUND OF THE INVENTION This invention relates to pulse code modulation (PCM) systems and, more particularly, to systems for encoding groups of samples of an input signal in such a way as to reduce the frequency weighted quantizing noise.

In PCM encoders in general, an input analog signal is sampled at or above the Nyquist rate. These samples are then applied to a quantizer which typically has the input signal range divided into an arbitrary number of quantizing intervals. The output generated by the quantizer is the digital representation of the quantizing level that most closely approximates the sample. In other types of quantizers the digital signal generated depends not on the absolute value of the input signal but on the difference between the present sample and some predicted value. Since in either case there is rarely a quantizing level or predicted value which is exactly the same as the input analog signal, there will be a difference between the input analog signal and the signal recon structed from its digital representation. This difference is called the quantizing noise.

In digital transmission systems, information about past and future samples of the input signal can be used to code the present sample in such a way as to reduce the quantizing noise. In particular, future samples give the coder information about any change of direction-in the input signal which is about to occur. Also, past samples show the direction in which the signal was going previously. In prior art encoders, quantizing errors are calculated by subtracting the output of a local decoder from the input signal. These quantizing errors are then stored and used to vary the quantizing levels in the quantizer or to aid in predicting what the next sample will be. If these quantizing errors are properly weighted they can be used in a way which will cause a reduction in the quantizing noise in a particular frequency band with the sacrifice of increased noise in other parts of the frequency spec rum. Also, in other prior art coders future samples (samples subsequent to the one being encoded) are used to improve the quantizers ability to predict future samples in such a way as to reduce the means squarednoise which is the total noise in the entire frequency spectrum. From a theoretical point of view, it would seem that a more effective method of reducing quantizing noise in a particular frequency band rather than the mean squared noise over the entire spectrum could be achieved by using both past and future samples of the input signal. In addition, when future samples are available through the use of storage and delay, it is possible to encode the present sample and several subsequent samples simultaneously, that is, the input samples can be encoded in groups or blocks. Therefore, by using past and future samples of an input analog signal it is possible to perform block encoding of the input signal with reduced quantizing noise in a particular frequency range. This is true regardless of the type of coder used.

It is therefore an object of this invention to provide a practical system for block encoding an input signal in such a way as to reduce the frequency weighted quantizing noise.

SUMMARY OF THE INVENTION The present invention is directed to reduction of the frequency weighted quantizing noise in a digital transmission system by selecting the output code; according to the past, present and future samples of the input signal along with the possible decoder reconstructions; that minimizes this noise. This has the advantage of greater efficiency since all the available information about the signal and the possible coding choices is used to reduce the noise in the band of interest without regard to the remaining frequency spectrum. This invention also provides for the simultaneous generation of groups of output bits.

In an illustrative embodiment of the invention, a Delta modulator is arranged to make use of the present and one future sample and three past errors. In this Delta modulator an input analog signal is applied to a sampling circuit which samples it at several times the Nyquist rate. The output of the sampling circuit is passed through a first delay line which delays the signal for one sampling period. If the output of this first delay line is defined as the present sample, then the output of the sampling circuit will represent a sample which is one sampling time in the future. The present sample and the future sample are then applied to first and second summing means, respectively. These summing means algebraically combine all the signals applied to their inputs and perform the same function as the summing circuit in a conventional Delta modulator. The outputs of the first and second summing means are applied to the two inputs of a two-dimensional quantizer, respectively. This quantizer simultaneously generates two output digits in joint response to the inputs from the two summing means. The decision boundaries in the quantizer are particularly chosen so that a code is generated which minimizes the frequency weighted quantizing noise when used in conjunction with a feedback signal, to be described later. The two outputs of the quantizer are then sequentially applied to a local decoder whose output will be an analog equivalent of the digital representation of the input signal. As in a conventional Delta modulator, this signal is applied to the first and second summing means in order to generate a difference signal for the quantizer. However, the output of the integrator is also subtracted from the present sample in a third summing means. This will generate a signal equivalent to the present quantizing error. This quantizing error is applied to the inputs of a second, third and fourth delay lines. The second delay line delays this present error signal for one sampling period; the third delay line delays the error signal for two sampling periods; and the fourth delay line delays the error signal for three sampling periods. The output of the second delay line is passed through a first multiplier, which effectively multiplies it by a factor b(l). The output of the third delay line passes through a second multiplier, which multiplies it by a factor b(2). Likewise, the output of the fourth delay line passes through a third multiplier, which multiplies it by a factor b(3). The outputs of these multipliers are summed and applied to a combining circuit. In addition, the outputs of the second, third and fourth delay lines are also passed through fourth, fifth and sixth multipliers, respectively. The fourth, fifth and sixth multipliers multiply the outputs of the delay lines by factors b(Z), b(3) and b(4), respectively. The outputs of the fourth, fifth and sixth multipliers are also summed and applied to the combining circuit.

In summary, this combination of delay lines and multipliers generates information about the past error terms in the encoder. These past error terms are then multiplied by the b coefficients which tend to weight their effect. These b coefficients are determined by the Fourier coefficients of the noise penalty function desired. The combining circuit generates first and second feedback signals which are applied to the first and second summing means, respectively. These feedback signals are used to alter the difference signal from the first and second summing means. This corrected output of -the summing means, in conjunction with the specially selected coding boundaries in the two-dimensional quantizer, in effect generates coding combinations, depending on the past, present and future samples and selects the one which gives the minimum quantizing noise in the band of interest.

The foregoing and other features of the present invention will be more readily apparent from the following detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic of an illustrative embodiment of the invention;

FIG. 2 is a graph of the boundaries in the quantizer of FIG. 1;

FIG. 3A is a graph of a typical frequency spectrum of the quantizing noise of a standard Delta modulator with a sine wave input;

- FIG. 3B is the graph of a typical noise penalty function;

FIG. 3C is a graph of the b coefficients corresponding to the penalty function of FIG. 38;

FIG. 3D is a graph of a typical frequency spectrum of the quantizing noise using the encoder of FIG. 1',

FIG. 4 is an alternative arrangement for the circuit of FIG. 1; and

FIG. 5 is a schematic of an illustrative embodiment of the invention for large block sizes.

DETAILED DESCRIPTION Most of the quantizers developed in the past seek to reduce the total means square quantizing noise. However, in a situation where the sampling rate is far above the Nyquist rate, a great deal of this noise occurs in a frequency range far above the information band and will eventually be removed by output circuit filters.

Therefore, any technique employed in a digital transmission system which uses the available coding combinations to reduce the overall noise will be relatively inefficient. Instead, these coding combinations should be used to reduce the noise only in the frequency band where the information is contained, since the other noise will be eliminated by the system filters. While the prior art has disclosed methods for reducing some of the in-band noise using past error terms, the present invention utilizes both past and future samples of the input signal to greatly reduce the in-band noise. This is accomplished by minimizing at each block encoding an estimate of the weighted noise power, D This estimate is derived from M past errors in conjunction with the N future. errors produced by the next block-N encoding, where block-N refers to the simultaneous encoding of Nsamples of the input signal, one being the present sample and the rest being future samples. Now

if the digital representation for a sample of the input signal can take on one of K possible values, then there are k distinct possible sequences of past and future errors, since the past errors have already been generated and are not changed by the encoding of the future samples. In a Delta modulator K would be equal to 2 and in a two-bit DPCM it would be 4.

In order to arrive at the minimum weighted noise power, D the system must in effect compute all the kK error patterns, and then generate the digital sequence that results in the error pattern, which gives rise to the least amount of noise in the frequency range of interest.

However, it can be shown that it is not necessary to compute D for each of the K possible codes every time a group of input samples is to be encoded. Instead, the concept of an L-dimensional encoding or source sample space can be used, where L is the sum of the number of past input terms, M, and the number of future input terms, N. However, since the past errors will be fixed at any particular time, the space can be reduced to N dimensions, with the present and each of the future sample input terms as coordinates. The effect of the past samples is then included by a translation of the various coordinates. In the case of a block-2 encoder, the space would be a simple plane as shown in FIG. 2, with the present sample measured along one axis and the future sample measured along the other. The factors lil and 1b, in FIG. 2 represent the translation of the coordinates in response to the past errors. When the encoding problem is viewed in this geometric way, the minimization of D is achieved by partitioning this new N-dimensional space into K regions, each being identified with an optimum choice of the coding sequence. For the block-2 encoder these regions are indicated by the areas I, II, III, and IV in FIG. 2. Also, since the noise is to be reduced only in a particular frequency band, the effect of the various inputs will have to be taken together. This, in part, explains the unusual shape of the boundaries in FIG. 2. Encoding, therefore, reduces to translating the coordinates in the N- dimensional space in response to the past error terms;

- partitioning the space into regions in response to the shape and frequency band of the noise reduction desired; and deciding in which of the K regions a particular set of input samples lies. FIG. 1 is a practical example of the use of this encoding technique.

FIG. 1 is an illustrative embodiment of the invention created by modifying a Delta modulator to use a present and one future sample together with three past errors. In FIG. 1, the input analog signal is applied to sampling circuit 100. This circuit samples the input signal under the control of the local timing clock 160. The output samples, S, of this circuit are applied to a delay circuit 105. This circuit delays the output of the sampler by one sampling time. Therefore, if the output of the delay circuit, S is considered to be the present sample, then the output of the sampler, S is a future sample, one sampling time in the future. The sample, S is applied to one of the positive inputs of combiner circuit and the sample, 8,, is applied to one of the positive inputs of combiner circuit 110. These combiner circuits perform the same function as the difference circuits in a conventional Delta modulator. Therefore, the previously reconstructed signal, 5- from the local decoder is applied to the MINUS inputs of both combiner circuits. In addition, feedback signals,

09 o and 41 from bias computer 140, are applied to positive inputs of

combiners

115 and 110, respectively. The outputs of these combiners, which represent the difference between the previously reconstructed signal and the present and future samples (plus the feedback signals), are applied to the two inputs of 2-dimensional quantizer 120. This quantizer simultaneously generates two digits of the output code, C and C which are loaded into shift register 125. The quantizer generates these codes under the control of flip-flop 165. Since flip-flop 165 is controlled by the local. clock 160, the quantizer will generate outputs at one-half the sampling rate. The shift register 125 is also under the control of the local clock, thus producing a serial output rate that is the same as the sampling rate. The output of the quantizer representing the code for the present sample is stored in the next-to-last stage of the shift register and the output code representing the future sample is stored in the last stage. The contents of the next-to-last stage of the shift register are applied to local decoder 130. ln effect, local decoder 130 converts the output digital code stored in the shift register into an analog signal which is a reconstruction of that code, S This reconstruction signal is applied to the negative inputs of

combiners

110 and 115 as described above. However, it is also subtracted from the present sample, S in summing circuit 135. This causes the generation of the present quantizing error term, q,,. This error term is applied to delay

circuits

141, 142 and 143 of bias computer 140, which delay it for one, two and three timing periods, respectively. The outputs of these delay circuits are applied to

multiplier circuits

144, 145 and 146, respectively. These circuits, in effect, multiply the outputs of the delay circuits by the coefficients b(l), b(2) and [1(3), respectively. The outputs of

multiplier circuits

144, 145 and 146 are summed in summing

circuits

150 and 151 and are applied to input 156 of combiner circuit 155. In addition, the outputs of

delay circuits

141, 142 and 143 are applied to

multipliers

147, 148 and 149, respectively. Similar to the other multiplier circuits, these have the effect of multiplying the outputs of

delay circuits

141, 142 and 143 by the coefficients b(2), b(3) and b(4), respectively. The outputs of these multipliers are added together in summing

circuits

152 and 153 and are applied to input 157 of combiner circuit 155. This combiner circuit generates the two feedback signals 111 and 1111, which are applied to

combiners

110 and 115, respectively.

With this arrangement, a present and future sampl are generated and applied to

combiner circuits

110 and 115. In these circuits the analog reconstruction signal from the local decoder is subtracted from the input signals in order to generate difference signals for the quantizer 120. In addition, feedback signals U1, and 41 are added to these difference signals. If the b coefficients are given proper values and if the quantiz ing regions in circuits 120 are appropriately chosen, the resulting output code, C, will have minimum quantizing noise for a particular frequency band.

The quantizing regions for quantizer 120 are shown in FIG. 2. A determination of the boundaries for the coding regions is made by considering the N- dimensional space mentioned previously. Each of the K possible output codes is associated with an optimum combination of input samples that results in the least amount of weighted quantizing noise. These o timum combinations of source samples are represented by K points in the encoding space. A given point in this encoding space, represented by an actual set of inputs, will then be in a particular region if it is closer to the optimum point of that region than to any other optimum point. In FIG. 2 these optimum points are denoted by A, B, C and D. Therefore, the boundaries of the various regions are determined by the loci of points which are equidistant from given pairs of optimum points. However, because of the frequency weighting applied to the noise, distance in this space is not measured in the usual way, but is in fact dependent on the orientation of the two points involved. This anisotropic nature of the space is indicatd by the fact that the equidistance lines around each optimum point in FIG. 2 have an elliptical rather than a circular shape.

If S, is defined as an M-vector of the past inputs and S, is defined as an N-vector of the future inputs, then where the positive subscripts indicate sample periods in the future and the negative ones indicate sample periods in the past. Also, '5, and S, can similarly be defined as the local decoder reconstructions of the digital output of the quantizer. Therefore, the past and future error vectors are, respectively,

Qu iand 61 3- Now the complete vector for the inputs is and the reconstruction vector is The distance between S and 5 in the present anistropic space, given in matrix notation, is

where T indicates a transpose matrix and B is a transformation matrix which describes the anisotropic na ture of the space. Using Equations (2), (3), and (4) in Equation (5) yields which is in partitioned form. Carrying out the indicated operation, completing the square of the result and dropping terms in O only, gives the expression where i17= B-"B Q Now, the modified distance Equation (7) can be used to find the loci of points equidistant from adjacent reconstruction points 3'; and 3]; that is, (PST?) (PS3?) will indicate the equation for the boundary. Equations (2) and (7) then yield E.S.) BNST+ (El-swap All that remains in order to completely define the quantizer of FIG. 1 is to determine the matrix B which specifies the anisotropic nature of the space that will result in reduced quantizing noise according to the given noise frequency weighting criterion. All of the error terms, both pastand future, represent a finite length record which can be represented by the L dimensional vector 6, where L M N. The components of this vector can then be indexed as iq q To determine the matrix B, the weighted noise power, D must be estimated. This can be accomplished by relying on the Weiner-Khintchine theory which states that the autocorrelation function and the power spectral density are Fourier transforms of each other. A derivation of this theorem can be found on pages 431 and 432 of Information Transmission, Modulation, and Noise by Schwartz, McGraw-Hill, 1959. However, since the vector 6 is not a function, but is only a series of numbers, the power spectrum may be estimated by the technique disclosed on pages 120 to 124 of The Measurement of Power Spectra by Blackman and Tukey, Dover Publications, 1958. Using this technique, one first determines the apparent autocorrelation of the finite record {q,... q,,} as

A 1 mm) im where the largest lag time for which data is available is (L U1. The triangular shaped lag window W): an)

is then applied to the autocorrelation. A triangular shape is chosen to implement this concept because it simplifies the mathematics. Upon Fourier series expansion of the windowed autocorrelation values, the modified spectral density estimate is produced. This can be expressed in matrix form as s, (w) l/L (i x6 2) where the elements of the X matrixare X cos (i-j) tor.

(13) Now the weighted noise power estimate, D,,.,,, can be determined by integrating the product of the spectral density and the noise penalty function W(a)).

sired by comparing Equation (6) with Equation (14). Now for any block length encoder, the encoding region boundaries will be determined by Equation (8 and the numerical valuesfor the elements of B by Equation (15). These results can now be used with FIG. 1 to determine the encoding region in quantizer 120, the b coefficients in bias computer and the outputs of combiner 155.

In the circuit of FIG. 1, M 3 and N 2. Therefore,

the B matrix will be b 0 1) 1) 1) (2 1) (a 1) (4) B b l) b b b m 1) 2) 1) (1) 1) 0) 1) 1) 1) 2) 1) (a) 1) 2) 1) 1) 1) o) 1) 1) '1) 4) 1) a) 1) 2 1) 1 1) (0 (Hi) The values of the elements of this matrix are determined from Equation (15), depending on the noise penalty function W(w). A typical noise penalty function is shown in FIG. 3B. In this case a reduction of the noise only in the information band (0 to 5 ke) is desired, and so a rectangular function is chosen. However, this function could be any arbitrary non-negative function and does not have to be restricted to a particular frequency range. In fact, it could be used to penalize the noise throughout the entire frequency spectrum. FIG. 3C shows the Fourier coefficients of the function of FIG. 3B which are essentially the elements of the B matrix.

The waveform shown in FIG. 3A is a representation of the quantizing noise spectrum of a conventional Delta modulator with a sine wave input. When the function of FIG. 3B is used in a Delta modulator constructed under the principles of the present invention, its quantizing noise spectrum can be represented by a curve somewhat like that in FIG. 3D. A comparison of FIGS. 3A and 3D shows that the in-band noise has been decreased at the expense of the out-of-ba'nd noise by using the present invention. However, this out-of-band noise can be removed by the system filters.

From Equations (6) and (16) M 4 4' RON BN=B ]and where N represents the block length.

If the reconstruction by the local decoder of the previous sample is S. and the step size is 8, the decoding rule for the delta modulator is To find the boundary between

pattern

0,1 and 1,1 assign 5, to 0,1 and S, to 1,1. Then which is the equation for the boundary. The other boundaries can be determined by using the same procedure on the other possible combination of outputs. An exemplified in Equation (20), the b coefficients always appear normalized with respect to b(0). This is because only the shape of W(w) is important, not its absolute amplitude scale. Since b(0) is the total area under the W(m) function as shown by Equation (15), it may conveniently be scaled such that b(0) 1. In the expressions which follow, this normalization has already been done.

10 The combining of the weighted summations of past errors is performed in the combiner 155 of bias computer 140. From Equation (7) it can be seen that the outputs of the combiner are required to be respectively th and 111, which are the components of the vector.

.Carrying out the indicated multiplication gives The signal at input 156 of the combiner 155 is and the signal at input 157 is M jz h-Hlqr Therefore, the combiner 155 forms the signals i11 and 111, from these inputs according to Equations (22) and (23).

At this point the operation of the bias computer 140 which generates the feedback terms 11: and 1,0, for combiners and has been described. Also, the boundaries of the decision regions in the quantizer have been described. However, a method of implementing the quantizer remains to be described. In a block-1 coder the conventional threshold detector circuit can be used since it is one-dimensional. However, in a block-2 coder the apparatus described in U.S. Pat. No. 2,721,900 of B. M. Oliver, which issued on Oct. 25, 1955, would be useful. In using the Oliver apparatus the outputs of

combiners

110 and 115 would be applied to the horizontal and vertical plates of a cathode ray tube. The face of the c.r.t. would then be covered with four groups of photo diodes, each group covering the area representing a particular output code. The particular output code generated would then depend on how the combiner output signals deflected the c.r.t. beam. When the block length is increased beyond two, the quantizer must take on a new form in order to ascertain in which region the combination of inputs lies. FIG. 4 is an illustrative embodiment of a reorganized quantizer which can be expanded to handle the greater number of inputs in larger block length encoders.

FIG. 4 is similar to FIG. 1 except that the delay lines have been replaced with analog shift registers and the quantizer has been divided into two

circuits

410 and 420, which also include the

combiners

110, 115, and 155 of FIG. 1. The input samples are applied to analog shift register 400. This shift register is under the control of the output signal, T, of the local clock. The analog signals are stored in the shift register and translated in response to the timing pulses. The contents of the shift register are applied to the first bit quantizer 410 along with the partial feedback signals 2,, and 2, from summing

circuits

441 and 442, respectively. In addition, the output of the local decoder 425 is applied to the first bit quantizer. This two-dimensional quantizer merely decides whether the first bit of the code for the two samples should be a 1 or a 0. This is done by determining on which side of the boundary between the 1 regions (land ll of FIG. 2) and the 0 regions (III and IV) the input combination lies. This boundary is indicated by the line drawn inside quantizer 410. The output of this quantizer is fed through switch 415 to the input of local decoder 425 and to the circuit output. This switch 415 is also under the control of the local clock. Once this first bit has been determined, the contents of shift register 400 are shifted one stage, whereby a new input sample, 5,, is loaded into the first stage, and the signal, 8,, (now in the last stage of shift register 400) is applied to the input of the second bit quantizer 420 along with partial feedback signal 2 and the new output of local decoder 425. This one-dimensional quantizer generates the second bit of the code, after switch 415 has changed position so that the output of quantizer 420 can be applied to the input of the local decoder and to the circuit output. This quantizer makes a simple threshold decision based in part on the output of the first bit quantizer through the signal 2 After the second bit is determined switch 415 returns to the output of quantizer 410, which generates the first bit of the code for the block of samples 8, and S, which by then will be stored in shift register 400. With this arrangement, the output code is generated sequentially and each of the quantizers determines only one of the two bits of the output code block.

As in FIG. 1, the present sample is subtracted from the output of the local decoder in a summing circuit, 430, in order to generate the error terms, q. These terms are applied to analog shift register 435, which is under the control of the local clock. At each timing pulse the error terms are shifted right one space. Therefore, the contents of the shift register represent the past error terms. The outputs of various stages of shift register 435 are multiplied by the b coefficients and are summed in combiner circuit 440. The output of this circuit is delayed one sampling time by delay circuit 443 before it is summed with the product of the present error term and theb( l) coefficient. This summing operation takes place in summing circuit 441, whose output is the partial feedback signal This signal can be used in the formation of the signals th and 111, in the quantizer. However, as will be shown later, it may not be necessary to form the signals i11 and #1,. With an appropriate arrangement of the quantizer it ispossible to use the partial feedback signals 2, 2,, and ,2, directly. When a 0 prefix subscript is used with one of these signals it indicates that it is used in the determination of the first bit of the block of the code and a 1 indicates use in the determination of the sec- 0nd bit in the block. The post-subscripts differentiate between the various partial feedback signals used to determine a code bit. The output of the combiner 440 is also summed with the contents of the last stage of shift register 435 multiplied by the coefficient b(M+l) in summing circuit 442, whose output is partial feedback term This arrangement allows for the simultaneous generation of

feedback terms

2,, and 2, with the use of one multistage shift register. The product of b(M+l) and the contents of the last stage of shift register 435 are delayed one sampling period by delay circuit 444. The output of delay circuit 444 is then summed in summing circuit 445 with the output of summing

circuit

441, 2 to form the partial feedback signal,

which is used in the determination of the second bit in quantizer 420. It should be noted that a good approximation to the signal 2 can be achieved without the output of delay circuit 444, since the b(M+l) coefficient will usually be very small.

The sequentially operating block encoder of FIG. 4 can be implemented using the arrangement in the Oliver patent with two groups of photodiodes forquantizer 410, and a simple threshold detecting circuit for quantizer 420. However, as the block length increases, a different arrangement for the quantizer must be used. This new arrangement will allow this circuit to be expanded to become a block-N encoder, as shown in FIG. 5. The initial step in such an expanded encoder is to make only the first digit decision in a block-N encoding, using M past errors as before. This decision is then used to update the analog reconstruction 5:, to S thereby determining an additional error term, Now the M+l errors can be used to make a first digit decision in the remaining block (N-l) encoding. This establishes 5,, q, and gives M+2 error terms. This continues until the last encoding, which is just a block-l decision using M+N-l errors. This bit-by-bit encoding process, when implemented as described, produces the desired output code without explicit time buffering of the input source samples or the output code bits.

in FIG. 5 the analog shift register 500 is the same as the shift register 400 of FIG. 4 except that additional stages have been added to handle the increased number of future input samples. Also, the quantizer has been divided into N separate units. The first digit encoder, 512, is an N dimensional quantizer with inputs from each of the N stages of the analog shift register 500. It generates the first bit of the output code for the block of input samples contained in shift register 500. The second digit encoder, 520, is an (N-l) dimensional quantizer with inputs from all except the first stage of the shift register. Howver, since it makes its decision during the second timing interval, after the contents of the shift register has moved, it considers the (N-l block of inputs from S to S Each of the succeeding digit encoders has one less input than the preceding encoder and makes its decision based on a block of inputs reduced by dropping the earlier input terms. The last digit encoder is a one-dimensional quantizer with an input from only the last stage of the shift register. At

the time it makes its decision, this last stage will contain the input term S As in FIG. 4, each of the quantizers or digit encoders has partial feedback terms 2 supplied to it, so that the updated effect of past quantizing errors is thereby included in the sequential block decision making process.

The outputs of the various quantizing units are collected by commutating switch 515, which applies them to both the circuit output and the input of local decoder 525. This local decoder generates an analog equivalent of the digital code appearing at the output. Difference circuit 530 is used to subtract this analog equivalent signal from the input samples. As with the other circuit arrangements, this creates quantizing error terms which are used in bias computer 540 to generate the partial feedback signals for the various units of the quantizer.

Each of the N separate digit encoders in FIG. is arranged differently than the quantizers in the other embodiments of the invention. The First Digit Encoder has N inputs and circuitry which will differentiate between 2 different coding regions; but generates only the first bit of the code. These regions are divided into two classes, those which have a 0" for the first bit and those which have a 1. The quantizer then determines in which of the two classes the combination of input signals belongs. This is done by making all possible comparisons of the relative distance of the source sample combination to pairs of code points where one point is in the 0 class and the other is in the 1 class. The results of these comparisons are logically combined to determine in which class the closest code point lies. Each comparison of code points can be implemented with a different threshold detecting circuit through the use of Equation (8). In this case the code points will be in opposite classes. Various summing, difference and multi lier circuits are used to determine if Is7 B-;+ Y a (st-WEN 3 7 where 3: is the reconstruction of the code point in the 0 class, Ii; is the reconstruction of the code point in the 1 class, 3", is the input combination, and Z= (3Q, is the vector of partial feedback terms,

2 (j) at (25) The threshold circuit determines if the sense of the inequality in Equation (24) is correct or not. If it is, this shows that the input combination is closer to code point than to point 37, and the value of an internal digital bit is set to 1121f it is not, the input combination is closer to point 25 and the internal bit is set to 0. Then the internal digital bits from the comparisons using the other pairs of code points from opposite classes are combined in logic circuits to generate the digit encoder output bit.

By way of example, the code points of FIG. 2 are divided into the 0"

class containing codes

0,0 and 0,1, and the 1" class containing 1,] and 1,0. Then four separate circuits are arranged according to Equation (24) to determine if the input is closer to code points A or B than it is to code points C or D. These four circuits will generate internal digital bits, depending on the comparison, according to the following conditions:

Output of (26) C0= Ckt. *1 (Ckt. *3)(Ckt. *4).

It should be noted that with this arrangement it is not necessary to generate the complete feedback terms th and 41 used in FIG. 1. Instead, only the partial feedback terms 2 need be generated. This results in a savings in design effort since it is not necessary to obtain the inverse of a large B matrix in order to get IF= 8f 86;. Additional savings can also be obtained by not comparing all the possible pairs of code points. Some comparisons have very little effect on the result. In some instances, certain comparisons may rigorously be eliminated since they involve redundant terms in the logical expression for the output. For example, the comparison between points A and D represented by Ckt. *2 was not necessary for the result in Equation (27).

In this way the quantizer can be expanded to handle any number of future inputs with the only practical limitation being the complexity of the circuitry required for this determination.

Although preferred embodiments of this invention have been shown and described, it will be understood by those skilled in the art that various modifications may be made without departing from the spirit and scope of this invention.

I claim: I

1. In a digital transmission system an encoder for converting an input analog signal into an output digital code, comprising:

means for obtaining a present and (N-l) future samples of said input analog signal at a particular sampling rate, where N is an integer;

means for generating an analog equivalent signal from the output digital code, the analog equivalent signal being an analog replica of the output digital code;

means for generating quantizing error terms based upon the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal;

means for storing M successive previously generated quantizing error terms; and

means for quantizing the present and (N-l) future samples of the input analog signal into the digital code according to a plurality of quantizing regions, which produce a reduced frequency weighted quantizing error, said means for quantizing including means for varying the quantizing regions to correct for quantizing errors as indicated by the M successive previously generated quantizing error terms, and means for encoding the quantized signals. 2. A digital encoder for converting an input analog signal into a digital code comprising:

I means for obtaining a present and (N-l future samples of said input analog signal'at a particular sampling rate; a plurality of summing means for combining each sample with a separate feedback signal;

quantizing means responsive to the outputs of said plurality of summing means for simultaneously generating the combination of bits of the'digital code, representing the present and (N-l) future samples of the input analog signal;

means for generating an analog equivalent signal from the bits of the digital code;

means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal;

means responsive to the present and previously generated quantizing error terms for generating the separate feedback signals, the feedback signals being generated in such a way asto allow the quantizing means to generate the digital code which produces a reduced frequency weighted quantizing error'according to a noise penalty function when taken together with thevpresent and previously generated quantizing error terms.

3. An encoder as claimed 'in claim 2 wherein said means for obtaining a present and ('N--1) future samples of said input analog signal comprises:

means for sampling the-amplitude of the input signal and holding the sample fora period'of time; and

means for storing the shifting at the sampling rate a plurality of successive samples of the input signal,

th'e earliest stored sample being considered the present sample and all subsequent samples being considered future samples.

4. An encoder as claimed in claim 2 wherein said quantizing means comprises means for determining in which of a plurality of encoding regions the combination of outputs from said summing means belongs and generating digital bits for the output code whichrepresent that region.

5. An encoder as claimed in claim 4 wherein the boundary between encoding regions is determined by the equation g L) 4" A (EL- "BNJ H (FIJI) B Q2= i) "ms, 37), with-i: being the analog reconstruction of the digital'bits representing one region, S: being the analog reconstruction of the digital bits representing another "region, B and ,B being segments of a matrix B Hail BTEBM B being an (M N) dimensional matrix whose ele-' ments are W(w) being the noise penalty function which describes the frequency weighting desired, 1' being the period of the sampling rate, i indicating the row of the B matrix, j indicating the column of the B matrix, 0: being the radian frequency, 8,, being the matrix of the first N rows and columns of B, B being the matrix of the last M rows and columns of B, B being the matrix of the first u 7 H il B Q;- 8. An encoder as claimed in claim 7 wherein said means for storing and shifting comprises an'an'alogshift register;

9;An encoder as claimed in claim 7 whereinsaid means for storing and shifting comprises a plurality of means for delaying the present error terms'for aplurality of successive sampling periods.

10. An encoder as claimed in claim' 2 wherein said encoder is arranged to function as a delta modulator by further including means for subtracting the output of said means for generating an analog equivalent signal from the present and future samples of the input signal. 11. An encoder'as claimed in claim 10 wherein said means for generating an analog equivalent signal comprises:

a digital shift register having a plurality of stages, the

output bits of the quantizing means being uniformly loaded in parallel into the stages of said shift digital register, the first bit of the code being loaded into the last stage of said digital shift register and the last bit of the code being loaded into the first stage of said digital shift register; and

means for integrating impulses generated in response to the bits stored in said digital shift register as they are shifted into the last stage of said digital shift register.

12. A digital encoder for converting an input analog signal into a digital code comprising:

means for obtaining a present and (N-l successive future samples of said input analog signal;

N quantizing means for sequentially generating the output code, the first quantizing means generating the first bit of the code in response to a first partial feedback signal, the presentsample, and the (N-l future samples, the succeeding quantizing means each generating a succeeding bit of the code in response to succeeding separate partial feedback signals and one less sample than the preceding quantizing means, the one less sample being the one least in the future, the N' of said quantizing means generating the last bit of the code in response to a nals being those analog equivalent signals of digital codes having a 1 as the first bit, said zero analog equivalent signals being those analog equivalent signals of digital codes having a as the first bit;

last partial feedback signal and the most future sample;

means for sequentially collecting the output bits of said N quantizing means and generating an analog equivalent signal in response to the bits;

means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code during the time a bit is generated and the sample of the input analog signal used in the generation of that bit which is the one least in the future; and

means responsive to the present and previously genand means for logically combining the internal bits of said plurality of comparison means to determine if the combination of inputs to a particular quantizing means is closer to a particular one analog equivalent signal than to any zero analog equivalent signal and generating a 1" output bit for said particular quantizing means if it is and a 0' output bit if it is not. 14. A digital encoder as claimed in claim 13 wherein said comparison means comprises circuit means for determining if the input combination is closer to the one Hated quantizing error terms for generating the analo e uivalent si nals than to the zero anal e uivseparate partial feedback signals, the partial feedq 0g q alent signals according to the expression:

back signals being generated in such a way as to T A T allow each of the N quantizing means to generate 2Q 3;+ 6;- ?l) 2 SL3?) a di ital bit of the out ut di ital code which ro- J ducfs a reduced freql lency weighted quanti ing 3; being one of the one analog equwalem 811 hsl error according to a noise penalty function when being i h analog eqlfivaleni Signals lh l in error terms. i D r 13. i digital encoder as claimed in claim 12 wherein ticular quamlzlhg means, N being s egmem of each of said N quantizing means comprises: Weighting matrix B determmed y the P y a plurality f comparison means f comparing ll function, T indicating the transpose of the indicated possible pairs f one a d zero a al i l t matrix, and a positive result for the expression indicay signals for a particular quantizer with the combinag that the input combination is 7 than t0 tion of inputs to said particular quantizer and gen- 15. A digital encoder as claimed in claim 14 wherein crating an internal 1 bit if the input combination said partial feedback terms are given by the matrix is closer to the one analog equivalent signal than to BC, the zero analog equivalent signal, and an internal 0 bit if it is not, said one analog equivalent sig-

Claims

1. In a digital transmission system an encoder for converting an input analog signal into an output digital code, comprising: means for obtaining a present and (N-1) future samples of said input analog signal at a particular sampling rate, where N is an integer; means for generating an analog equivalent signal from the output digital code, the analog equivalent signal being an analog replica of the output digital code; means for generating quantizing error terms based upon the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal; means for storing M successive previously generated quantizing error terms; and means for quantizing the present and (N-1) future samples of the input analog signal into the digital code according to a plurality of quantizing regions, which produce a reduced frequency weighted quantizing error, said means for quantizing including means for varying the quantizing regions to correct for quantizing errors as indicated by the M successive previously generated quantizing error terms, and means for encoding the quantized signals.

2. A digital encoDer for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) future samples of said input analog signal at a particular sampling rate; a plurality of summing means for combining each sample with a separate feedback signal; quantizing means responsive to the outputs of said plurality of summing means for simultaneously generating the combination of bits of the digital code, representing the present and (N-1) future samples of the input analog signal; means for generating an analog equivalent signal from the bits of the digital code; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal; means responsive to the present and previously generated quantizing error terms for generating the separate feedback signals, the feedback signals being generated in such a way as to allow the quantizing means to generate the digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with the present and previously generated quantizing error terms.

3. An encoder as claimed in claim 2 wherein said means for obtaining a present and (N-1) future samples of said input analog signal comprises: means for sampling the amplitude of the input signal and holding the sample for a period of time; and means for storing the shifting at the sampling rate a plurality of successive samples of the input signal, the earliest stored sample being considered the present sample and all subsequent samples being considered future samples.

4. An encoder as claimed in claim 2 wherein said quantizing means comprises means for determining in which of a plurality of encoding regions the combination of outputs from said summing means belongs and generating digital bits for the output code which represent that region.

5. An encoder as claimed in claim 4 wherein the boundary between encoding regions is determined by the equation (Se - Si)T BN Sf + (Se - Si)T Beta Qp 1/2 (Se - Si)T BN(Se + Si), with Se being the analog reconstruction of the digital bits representing one region, Si being the analog reconstruction of the digital bits representing another region, BN and Beta being segments of a matrix B describing the frequency weighting, Qp being the vector of past quantizing error terms, and T indicating the transpose of the indicated matrix.

6. An encoder as claimed in claim 5, wherein the matrix B in partition form is given by

7. An encoder as claimed in claim 6 wherein said means for generating the separate feedback signals comprises: means for storing and shifting at the sampling rate a plurality of quantizing error terms; means for multiplying the stored quantizing error terms by coefficients of the B matrix and generating partial products by summing the results; and means for combining the partial products to produce the feedback terms psi such that psi BN 1 Beta Qp.

8. An encoder as claimed in claim 7 wherein said means for storing and shifting comprises an analog shift register.

9. An encoder as claimed in claim 7 wherein said means for storing and shifting comprises a plurality of means for delaying the present error terms for a plurality of successive sampling periods.

10. An encoder as claimed in claim 2 wherein said encoder is arranged to function as a delta modulator by further including means for subtracting the output of said means for generating an analog equivalent signal from the present and future samples of the input signal.

11. An encoder as claimed in claim 10 wherein said means for generating an analog equivalent signal comprises: a digital shift register having a plurality of stages, the output bits of the quantizing means being uniformly loaded in parallel into the stages of said shift digital register, the first bit of the code being loaded into the last stage of said digital shift register and the last bit of the code being loaded into the first stage of said digital shift register; and means for integrating impulses generated in response to the bits stored in said digital shift register as they are shifted into the last stage of said digital shift register.

12. A digital encoder for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) successive future samples of said input analog signal; N quantizing means for sequentially generating the output code, the first quantizing means generating the first bit of the code in response to a first partial feedback signal, the present sample, and the (N-1) future samples, the succeeding quantizing means each generating a succeeding bit of the code in response to succeeding separate partial feedback signals and one less sample than the preceding quantizing means, the one less sample being the one least in the future, the Nth of said quantizing means generating the last bit of the code in response to a last partial feedback signal and the most future sample; means for sequentially collecting the output bits of said N quantizing means and generating an analog equivalent signal in response to the bits; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code during the time a bit is generated and the sample of the input analog signal used in the generation of that bit which is the one least in the future; and means responsive to the present and previously generated quantizing error terms for generating the separate partial feedback signals, the partial feedback signals being generated in such a way as to allow each of the N quantizing means to generate a digital bit of the output digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with previously generated quantizing error terms.

13. A digital encoder as claimed in claim 12 wherein each of said N quantizing means comprises: a plurality of comparison means for comparing all possible pairs of one and zero analog equivalent signals for a particular quantizer with the combination of inputs to said particular quantizer and generating an internal ''''1'''' bit if the input combination is closer to the one analog equivalent signal than to the zero analog equivalent signal, and an internal ''''0'''' bit if it is not, said one analog equivalent signals being those analog equivalent signals of digital codes having a ''''1'''' as the first bit, said zero analog equivalent signals being those analog equivalent signals of digital codes having a ''''0'''' as the first bit; and means for logically combining the internal bits of said plurality of comparison means to determine if the combination of inputs to a particular quantizing meAns is closer to a particular one analog equivalent signal than to any zero analog equivalent signal and generating a ''''1'''' output bit for said particular quantizing means if it is and a ''''0'''' output bit if it is not.

14. A digital encoder as claimed in claim 13 wherein said comparison means comprises circuit means for determining if the input combination is closer to the one analog equivalent signals than to the zero analog equivalent signals according to the expression: (Sl - Si)TBN Sf + (Sl - Si)T Sigma - 1/2 (S - Si)TBN (Sl + Si) > 0, Si being one of the one analog equivalent signals, Sl being one of the zero analog equivalent signals, Sf being the combination of inputs to said particular quantizing means, Sigma being the partial feedback term for said particular quantizing means, BN being a segment of weighting matrix B determined by the noise penalty function, T indicating the transpose of the indicated matrix, and a positive result for the expression indicating that the input combination is closer to Sl than to Si.

15. A digital encoder as claimed in claim 14 wherein said partial feedback terms are given by the matrix Sigma Beta Qp.