US20140284040A1 - Heat spreading layer with high thermal conductivity - Google Patents
Heat spreading layer with high thermal conductivity Download PDFInfo
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- US20140284040A1 US20140284040A1 US13/848,960 US201313848960A US2014284040A1 US 20140284040 A1 US20140284040 A1 US 20140284040A1 US 201313848960 A US201313848960 A US 201313848960A US 2014284040 A1 US2014284040 A1 US 2014284040A1
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- heat spreading
- spreading layer
- supporting frame
- heat
- top surface
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K7/20509—Multiple-component heat spreaders; Multi-component heat-conducting support plates; Multi-component non-closed heat-conducting structures
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Definitions
- This invention relates generally to the field of controlling thermal conduction in computer chip packaging, and more specifically to a heat spreading cap structure having high thermal conductivity.
- chip level packages can be constructed with one or more chips mounted on a thin flexible first level package substrate, such as an organic laminate build up package substrate, using micro solder bump connections, referred to as C4's (controlled collapse chip connection).
- C4's controlled collapse chip connection
- the packages are often bonded to a cap, which provides structural stability to the package by reducing warpage, and by spreading heat along a plane, thereby improving the package thermal performance.
- the cap is attached to a secondary cooling structure, such as a heat sink or a liquid cooling system.
- a flip chip ball grid array (BGA) package 100 comprises a chip die 112 having an operational surface mounted onto a substrate 106 via a series of C4's 108 encased in an underfill layer 110 . These components are operatively connected to a circuit board 102 via a separate series of solder balls 104 .
- the die 112 is said to be flipped because its operational connections face down towards the substrate 106 and the circuit board 102 , and its other side is connected to a heat sink 140 via a protective heat spreading cap 114 .
- TIM1 thermal interface material
- TIM2 thermal interface material
- the heat spreading cap 114 may be made from copper, having a thermal conductivity of 400 W/m-° C., at 300° K.
- copper has relatively high structural stability and extends that stability to the package 100 , it is not the most thermally conductive material available.
- Other forms of graphite exhibit thermal conductivity above 1200 W/m-° C. These materials generally are referred to as high-k materials, or high-k graphite.
- a heterogeneous planar graphite element includes a high-conductivity graphite layer having a cavity for housing an insert.
- the graphite layer exhibits high thermal conductivity in the x and y planes, but low thermal conductivity in the z plane.
- the insert layer has relatively higher thermal conductivity across the z plane, but not across the x or y planes.
- Embodiments of the invention include a cooling system for a semiconductor package comprising a heat spreading layer partially encased in a supporting frame along an outer perimeter, the supporting frame encasing the perimeter and an adjacent portion of the heat spreading layer to define centrally exposed top and bottom portions of the heat spreading layer; and a heat generating element thermally connected to the centrally exposed bottom portion of the heat spreading layer.
- FIG. 1 is a cross sectional front elevational view of a flip chip ball grid array package assembly, according to the prior art
- FIG. 2 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, according to an embodiment of the disclosed invention
- FIG. 3 is a cross sectional front elevational view of the flip chip package assembly depicted in FIG. 2 , and further depicts a heat sink, according to an embodiment of the disclosed invention
- FIG. 4 is a cross sectional front elevational view of the flip chip package assembly depicted in FIG. 2 , wherein the supporting frame comprises a plurality of interconnected pieces, according to an embodiment of the disclosed invention
- FIG. 5 is a cross sectional front elevational view of the flip chip package assembly depicted in FIG. 2 , wherein the supporting frame comprises a plurality of interconnected pieces, according to an embodiment of the disclosed invention
- FIG. 6 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, according to an embodiment of the disclosed invention
- FIG. 7 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention
- FIG. 8 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top and a bottom surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention;
- FIG. 9 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top and bottom surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention
- FIG. 10 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top surface of the heat spreading layer are modified to form a rabbet, and a central portion of a top surface of the supporting frame is flush with the top surface of the heat spreading layer, according to an embodiment of the disclosed invention;
- FIG. 11 is a partial cross sectional front elevational view of a wire bonding chip assembly package, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, and central portion of a bottom surface of the heat spreading layer is connected to a central portion of a chip, according to an embodiment of the disclosed invention;
- FIG. 12 is an aerial view of a multi-core processor having a series of heat spreading layers encased in a supporting frame, according to an embodiment of the disclosed invention.
- FIG. 13 is a partial cross sectional front elevational view of the multi-core processor depicted in FIG. 12 .
- a subset 200 of a flip chip package comprises a chip die 112 mounted onto a substrate 106 via a series of C4's 108 encased in an underfill layer 110 .
- a top surface of the chip die 112 is connected to a lid comprising a homogeneous, thermally conductive heat spreading layer 114 a housed within a supporting frame 114 b .
- a bottom surface of the heat spreading layer 114 a is connected to the top surface of the chip die 112 via a thermal interface material (“TIM1”) 132 .
- TIM1 thermal interface material
- a bottom surface of the supporting frame 114 b is connected to the top surface of the substrate 106 via an adhesive layer 130 .
- the heat spreading layer 114 a and the interior cavity of the supporting frame 114 b are also connected via an adhesive layer 136 .
- the purpose the adhesive layer 136 is, in part, to form a strong interaction between the heat spreading layer 114 a and the supporting frame 114 b , and to maintain the integrity of these two components, particularly in light of structural stresses, such as heat fluctuations, exerted upon the chip package during manufacturing and operation.
- One example of the material that can be used to form the layer 136 is epoxy based adhesive.
- the supporting frame 114 b is formed as a single piece, as is the heat spreading layer 114 a . It is not necessary to bond these two components via the adhesive layer 136 , particularly if the supporting frame 114 b is molded onto and around the heat spreading layer 114 a during the fabrication process.
- the heat spreading layer 114 a is made from a material having relatively high thermal conductivity, such as graphite, some forms of which exhibit conductivity above 1200 W/m-° C.
- the graphite heat spreading layer 114 a is effective in spreading heat generated by the chip die 112 and its surrounding components across the z plane, and at least one of the x or y planes.
- the heat spreading layer 114 a provides greater heat spreading and dissipation compared to the prior art where a customary choice of chip cap/lid material is copper.
- the graphite heat spreading layer 114 a has double the thermal conductivity of copper given an equal shape and thickness. Consequently, it is a suitable choice for forming the heat spreading layer 114 a.
- the graphite heat spreading layer 114 a may be formed using two smaller graphite pieces joined at two adjacent edges by an adhesive (not shown) to form a single planar graphite layer.
- Each pyrolytic graphite piece may be grown to a thickness of about 25 mm, where its high thermal conductivity is in the horizontal plane and its low thermal conductivity is in the vertical, or growth, direction. Thereafter, each piece is orientated such that the low thermal conductivity of the graphite is in the x direction.
- a 50 ⁇ 50 mm graphite heat spreader may be constructed by cutting out two pieces that are 25 mm tall, 4 mm thick, and 50 mm long where the thermal conductivity is high in the 4 mm and 50 mm directions.
- the supporting frame 114 b is made from copper, and encompasses the side, and parts of the top and bottom surfaces of the layer 114 a , leaving a central portion of both the top and bottom surfaces of the graphite exposed.
- the heat spreading layer 114 a remains twice as effective as conventional copper caps in thermal conductivity at the exposed area.
- the supporting frame 114 b gives the heat spreading layer 114 a sufficient rigidity at its outer surfaces and edges without creating a thermal penalty at its exposed regions.
- Other embodiments may employ other metals, such as stainless steel, or polymers that are sufficiently strong to provide structural stability to the highly conductive layer 114 a.
- a subset 300 of a flip chip package is similar to the elements recited above in connection with FIG. 2 , wherein like elements have been similarly marked. Additionally, the subset 300 comprises a heat sink 140 having a bottom surface contoured to fit into the opening of the exposed area of the top surface of the heat spreading layer 114 a and the top surface of the frame 114 b , via a TIM2 layer 134 . Contouring the bottom surface of the heat sink 140 to the top surface of the lid is beneficial because it fills a gap that would otherwise form between the heat sink 140 and the top surface of the heat spreading layer 114 a due to the asymmetrical shapes of the two surfaces. Without contouring the bottom surface of the heat sink 140 , the gap may be filled with a TIM2 layer, a solution that likely would create an increased thermal penalty.
- a further embodiment of the disclosed invention comprises a subset 400 of a flip chip package, as described and depicted in FIG. 2 .
- the supporting frame of the subset 400 comprises a top frame 114 c and a foot frame 114 d , joined at a junction point 114 e .
- the two layers may be joined using an adhesive layer (not shown), or mechanically.
- Embodiments of the disclosed invention may comprise top frames 114 c and foot frames 114 d made from, for example, copper or stainless steel.
- the design of the two-piece supporting frame may be used where manufacturing considerations make it less desirable to form a single piece frame. For example, it may not be feasible to implement a molding mechanism that would form a single-piece frame around the layer 114 a due to equipment cost, or the unavailability of a polymer ideal for manufacturing a molded frame.
- a subset 500 of a flip chip package comprises the elements recited and described with respect to FIG. 4 , except that the junction point 114 e between the top frame 114 c and the foot frame 114 d is vertically aligned with the outer edges of the heat spreading layer 114 a , and the foot frame 114 d forms an “L” shape in a cross sectional view.
- the position of the junction point 114 e may be changed according to cost, ease of design, and other manufacturing considerations, without departing from the spirit and scope of the disclosed invention.
- a further embodiment of the disclosed invention comprises a subset 600 of a flip chip package, as described in connection with FIG. 2 .
- the supporting frame 114 b is a single piece having a top portion that is substantially thinner than the side or foot portions of the structure. Moreover, the top portion of the supporting frame 114 b extends onto the top surface of the heat spreading layer 114 a at a fraction of the distance it covers on the bottom surface of the heat spreading layer 114 a . Consequently, the disclosed embodiment allows for greater spreading and dissipation of heat generated by the chip die 112 by allowing a larger surface area of the heat spreading layer 114 a to connect to a heat sink.
- a further embodiment of the disclosed invention comprises a subset 700 of a flip chip package, as recited and described with respect to FIG. 2 .
- the top surface of the heat spreading layer 114 a is chamfered such that the frame 114 b extends over a portion of the layer 114 a .
- the top surface of the supporting frame 114 b is flush with a central portion of the top surface of the heat spreading layer 114 a , and extends over its chamfered edges.
- the bottom surface of the heat spreading layer 114 a is substantially flat.
- Chamfering the heat spreading layer 114 a increases the surface area at which the supporting frame 114 b contacts the heat spreading layer 114 a , improving the supporting frame's 114 b grip, without necessarily reducing the surface area of the heat layer 114 a that remains exposed. Since the exposed portion of the heat spreading layer 114 a contacts the heat sink 140 , it is desirable to maintain as much contact area as possible. Moreover, according to the disclosed embodiment, the heat sink 140 has a flat bottom surface, since the layer 114 a is flush with the supporting frame 114 b.
- a further embodiment of the disclosed invention comprises a subset 800 of a flip chip package, as recited and described with respect to FIG. 2 .
- the heat spreading layer 114 a is chamfered along its top surface, and housed within the supporting frame 114 b , as depicted in FIG. 7 , and described in connection therewith. Additionally, the bottom surface of the heat spreading layer 114 a is also chamfered along its outer edges, with the supporting frame 114 b extending over the chamfered edges. In the depicted embodiment, the chamfered surface on the top surface of the heat spreading layer 114 a is larger than the chamfered surface of the bottom surface.
- a further embodiment of the disclosed invention comprises a subset 900 of a flip chip package, as recited and described with respect to FIG. 2 .
- the top and bottom surfaces of the heat spreading layer 114 a are symmetrically chamfered and encased by the supporting frame 114 b .
- the top surface of the supporting frame 114 b is flush with a central portion of the top surface of the heat spreading layer 114 a.
- a further embodiment of the disclosed invention comprises a subset 1000 of a flip chip package, as recited and described with respect to FIG. 2 .
- the top surface of the heat spreading layer 114 a is processed to form rabbet edges, and encased in the supporting frame 114 b , such that the supporting frame 114 b extends over the rabbet edges.
- the top surface of the supporting frame 114 b is flush with a central portion of the top surface of the heat spreading layer 114 a.
- a further embodiment of the disclosed invention comprises a subset 1100 of a wire bonding chip assembly package similar to the flip chip assembly package depicted in FIG. 6 , wherein like elements are similarly referenced.
- the heat spreading layer 114 a further comprises a protruding central portion on its lower surface, whereby the heat spreading layer 114 a connects to a central portion of a top surface of the chip 112 .
- the chip 112 is operatively connected to the substrate layer 106 via a plurality of wire connections 142 , with the active side of the chip 112 facing the heat spreading layer 114 a .
- the heat spreading layer 114 a is in contact with a central region of the top surface of the chip 112 so as to provide space for the wire connections 142 in a typical wire bonding package.
- the wire connections 142 may be encapsulated in a molding compound.
- FIGS. 2-11 reference an adhesive layer 136 connecting the heat spreading layer 114 a to the supporting frame 114 b (or to the top frame 114 c and the foot frame 114 d in embodiments having a two-piece frame), forming the adhesive layer 136 is not necessary to practice the invention. Whether the adhesive layer 136 is used and at what thickness may be varied without departing from the spirit or the scope of the disclosed invention.
- FIGS. 2-10 are based primarily on a flip chip package, it will be understood by a person of ordinary skill in the art, in light of the present disclosure, that the features of the depicted embodiments (including, without limitation, the shape of the heat spreading layer 114 a or the supporting frame 114 b ) can be incorporated into corresponding embodiments using a wire bonding assembly package, as described with respect to FIG. 11 , without departing from the spirit or scope of the disclosed invention.
- FIGS. 2-11 are discussed in reference to the package 100 using BGA interconnections between the substrate 106 and the circuit board 102 , as depicted in FIG. 1 , these embodiments can be incorporated into a land grid array (LGA) package or a pin grid array (PGA) package.
- LGA land grid array
- PGA pin grid array
- LGA packages use surface contact areas on the underside of the substrate 106 to connect to a corresponding grid of contacts on the circuit board 102 .
- the connection may be implemented using a variety of methods such as LGA sockets, or solder paste.
- the substrate 106 surface contacts in LGA packages are relatively flat compared to the solder ball connections in BGA packages.
- the surface contacts on the underside of the substrate 106 are not flat, but instead are pin shaped protrusions arranged in an array, and may connect to a socket mounted on the circuit board 102 .
- a multichip module (“MCM”) 1200 comprises four chips 112 (not shown) mounted onto a substrate layer 1200 (via, for example, a flip chip package) and thermally connected to respective heat spreading layers 114 a , wherein the heat spreading layers 114 a are encased in a supporting frame 114 b .
- the supporting frame may be formed as a single piece through, for example, a molding manufacturing process using a polymer; or it may be formed as multiple pieces using additional manufacturing methods, such as a high pressure metal press.
- the supporting frame 114 b may comprise a top frame and a foot frame (not shown), similar to similarly referenced components depicted in FIGS. 4 and 5 .
- the multichip module (“MCM”) 1200 comprises additional sets of components beneath top surfaces of the supporting frame 114 b and heat spreading layers 114 a depicted in FIG. 12 .
- each set of components in the MCM 1200 is similar to the embodiment shown in FIG. 6 , wherein like elements have been similarly referenced.
- each shared portion of the supporting frame 114 b situated between each pair of chips 112 (making a total of four shared portions) is a continuous portion of the entire supporting frame 114 b structure.
- each heat spreading layer 114 a may be encased by a corresponding supporting frame 114 b , wherein the supporting frames 114 b are thermally or mechanically joined to one another to form the MCM 1200 .
- the disclosed invention employ a single high-k layer supported by a frame having a stronger structural stability.
- a single graphite layer for example, the disclosed invention allows for high heat dissipation across at least two planes, including the z plane, and at least the x or y planes. Consequently, the disclosed invention allows for effective thermal conduction overall across the entirety of the heat spreading layer, without sacrificing structural integrity or incurring a thermal penalty by covering the high-k material with another material having relatively low thermal conductivity.
- Embodiments of the disclosed invention increase the thermal conductivity of semiconductor packages in which they are employed, and allow for reliable operation in hygrothermal operating conditions, which include temperatures between ⁇ 40° C. and 125° C., and as much as 85% relative humidity.
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Abstract
Description
- This invention relates generally to the field of controlling thermal conduction in computer chip packaging, and more specifically to a heat spreading cap structure having high thermal conductivity.
- Innovations in semiconductor fabrication and packaging technologies have enabled development of high performance, densely integrated semiconductor chip modules. The downscaling of chip geometries and the increase in operating speeds lead to increased power densities, resulting in more heat generation per unit area. The increased power density poses practical limitations to the level of integration density and performance that may be achieved. The ability to implement chip modules with higher densities and higher performance is limited primarily by the ability to effectively cool the chip modules during normal operation. For instance, as heat is generated by integrated circuit (“IC”) chips during normal operation, cooling structures must be employed to provide sufficiently low thermal resistance paths between the chips and ambient air or a circulating liquid coolant to adequately remove heat and maintain the operating temperature of the chips low enough to assure continued reliable operation.
- In conventional packaging technologies, chip level packages can be constructed with one or more chips mounted on a thin flexible first level package substrate, such as an organic laminate build up package substrate, using micro solder bump connections, referred to as C4's (controlled collapse chip connection). The packages are often bonded to a cap, which provides structural stability to the package by reducing warpage, and by spreading heat along a plane, thereby improving the package thermal performance. The cap, in turn, is attached to a secondary cooling structure, such as a heat sink or a liquid cooling system.
- Referring now to
FIG. 1 , a flip chip ball grid array (BGA)package 100, according to the prior art, comprises achip die 112 having an operational surface mounted onto asubstrate 106 via a series of C4's 108 encased in anunderfill layer 110. These components are operatively connected to acircuit board 102 via a separate series ofsolder balls 104. The die 112 is said to be flipped because its operational connections face down towards thesubstrate 106 and thecircuit board 102, and its other side is connected to aheat sink 140 via a protectiveheat spreading cap 114. Several layers of thepackage 100 are connected using layers of material, including, for example, the thermal interface material (TIM1) 132 connecting thedie 112 to thecap 114, theadhesive layer 130 connecting thecap 114 to thesubstrate 106, and the thermal interface material (TIM2) 134 connecting thecap 114 theheat sink 140. - In conventional implementations, the
heat spreading cap 114 may be made from copper, having a thermal conductivity of 400 W/m-° C., at 300° K. Although copper has relatively high structural stability and extends that stability to thepackage 100, it is not the most thermally conductive material available. Some forms of graphite, for example, have much higher thermal conductivity across at least one spatial plane. Other forms of graphite exhibit thermal conductivity above 1200 W/m-° C. These materials generally are referred to as high-k materials, or high-k graphite. - According to an aspect of the prior art (for example, as disclosed by U.S. Pat. No. 6,758,263 B2 entitled “HEAT DISSIPATING COMPONENT USING HIGH CONDUCTIVE INSERTS”), a heterogeneous planar graphite element includes a high-conductivity graphite layer having a cavity for housing an insert. The graphite layer exhibits high thermal conductivity in the x and y planes, but low thermal conductivity in the z plane. The insert layer has relatively higher thermal conductivity across the z plane, but not across the x or y planes.
- Traditional designs and methods in the prior art face significant challenges, particularly because known structures using high-k material exhibit weak structural stability, and experience warpage under normal operating temperatures. This warpage leads to device defects and even to device failure. In fact, the relative instability of these structures also makes more prone to damage during manufacturing processes. Furthermore, prior art solutions using graphite employ one or more heterogeneous layers, adding to device complexity but taking advantage of graphite's thermal conductivity in a limited way.
- Therefore, it is desirable to manage heat spreading and dissipation in semiconductor packaging technology by taking advantage of the relatively high thermal conductivity of available material, such as graphite, while at the same time maintaining structural integrity of the package and its constituent components.
- Embodiments of the invention include a cooling system for a semiconductor package comprising a heat spreading layer partially encased in a supporting frame along an outer perimeter, the supporting frame encasing the perimeter and an adjacent portion of the heat spreading layer to define centrally exposed top and bottom portions of the heat spreading layer; and a heat generating element thermally connected to the centrally exposed bottom portion of the heat spreading layer.
- Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
-
FIG. 1 is a cross sectional front elevational view of a flip chip ball grid array package assembly, according to the prior art; -
FIG. 2 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 3 is a cross sectional front elevational view of the flip chip package assembly depicted inFIG. 2 , and further depicts a heat sink, according to an embodiment of the disclosed invention; -
FIG. 4 is a cross sectional front elevational view of the flip chip package assembly depicted inFIG. 2 , wherein the supporting frame comprises a plurality of interconnected pieces, according to an embodiment of the disclosed invention; -
FIG. 5 is a cross sectional front elevational view of the flip chip package assembly depicted inFIG. 2 , wherein the supporting frame comprises a plurality of interconnected pieces, according to an embodiment of the disclosed invention; -
FIG. 6 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 7 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 8 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top and a bottom surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 9 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top and bottom surface of the heat spreading layer are chamfered, and a top surface of the supporting frame is flush with a top surface of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 10 is a partial cross sectional front elevational view of a flip chip package assembly, having a heat spreading layer encased in a supporting frame, wherein the edges of a top surface of the heat spreading layer are modified to form a rabbet, and a central portion of a top surface of the supporting frame is flush with the top surface of the heat spreading layer, according to an embodiment of the disclosed invention; -
FIG. 11 is a partial cross sectional front elevational view of a wire bonding chip assembly package, having a heat spreading layer encased in a supporting frame, wherein the supporting frame extends over a portion of the heat spreading layer, and central portion of a bottom surface of the heat spreading layer is connected to a central portion of a chip, according to an embodiment of the disclosed invention; -
FIG. 12 is an aerial view of a multi-core processor having a series of heat spreading layers encased in a supporting frame, according to an embodiment of the disclosed invention; and -
FIG. 13 is a partial cross sectional front elevational view of the multi-core processor depicted inFIG. 12 . - Referring now to
FIG. 2 , asubset 200 of a flip chip package, according to an embodiment of the disclosed invention, comprises achip die 112 mounted onto asubstrate 106 via a series of C4's 108 encased in anunderfill layer 110. A top surface of thechip die 112 is connected to a lid comprising a homogeneous, thermally conductiveheat spreading layer 114 a housed within a supportingframe 114 b. A bottom surface of theheat spreading layer 114 a is connected to the top surface of thechip die 112 via a thermal interface material (“TIM1”) 132. A bottom surface of the supportingframe 114 b is connected to the top surface of thesubstrate 106 via anadhesive layer 130. Theheat spreading layer 114 a and the interior cavity of the supportingframe 114 b are also connected via anadhesive layer 136. The purpose theadhesive layer 136 is, in part, to form a strong interaction between theheat spreading layer 114 a and the supportingframe 114 b, and to maintain the integrity of these two components, particularly in light of structural stresses, such as heat fluctuations, exerted upon the chip package during manufacturing and operation. One example of the material that can be used to form thelayer 136 is epoxy based adhesive. - Further referring to
FIG. 2 , the supportingframe 114 b is formed as a single piece, as is theheat spreading layer 114 a. It is not necessary to bond these two components via theadhesive layer 136, particularly if the supportingframe 114 b is molded onto and around theheat spreading layer 114 a during the fabrication process. According to an aspect of the disclosed invention, theheat spreading layer 114 a is made from a material having relatively high thermal conductivity, such as graphite, some forms of which exhibit conductivity above 1200 W/m-° C. - The graphite
heat spreading layer 114 a is effective in spreading heat generated by thechip die 112 and its surrounding components across the z plane, and at least one of the x or y planes. By using a high-k material such as graphite, theheat spreading layer 114 a provides greater heat spreading and dissipation compared to the prior art where a customary choice of chip cap/lid material is copper. In fact, the graphiteheat spreading layer 114 a has double the thermal conductivity of copper given an equal shape and thickness. Consequently, it is a suitable choice for forming theheat spreading layer 114 a. - According to an aspect of the disclosed invention, the graphite
heat spreading layer 114 a may be formed using two smaller graphite pieces joined at two adjacent edges by an adhesive (not shown) to form a single planar graphite layer. Each pyrolytic graphite piece may be grown to a thickness of about 25 mm, where its high thermal conductivity is in the horizontal plane and its low thermal conductivity is in the vertical, or growth, direction. Thereafter, each piece is orientated such that the low thermal conductivity of the graphite is in the x direction. A 50×50 mm graphite heat spreader may be constructed by cutting out two pieces that are 25 mm tall, 4 mm thick, and 50 mm long where the thermal conductivity is high in the 4 mm and 50 mm directions. These pieces are glued together side-by-side (i.e. by joining their respective 4×50 mm faces) to produce the 50×50×4 mm single, planar layer heat spreader. Other embodiments of the invention may have additional pieces in the single planar layer and oriented and joined in a manner different from the described configuration, without departing from the scope or the spirit of the invention. - Although graphite has desirable high thermal conductivity, it is generally susceptible to thermal warpage and cracking or breaking during device operation. Failure of the
heat spreading layer 114 a due to warpage in typical operational conditions may be virtually eliminated by encasing it in the supportingframe 114 b. According to an embodiment of the invention, the supportingframe 114 b is made from copper, and encompasses the side, and parts of the top and bottom surfaces of thelayer 114 a, leaving a central portion of both the top and bottom surfaces of the graphite exposed. By retaining an exposed portion of graphite, theheat spreading layer 114 a remains twice as effective as conventional copper caps in thermal conductivity at the exposed area. The supportingframe 114 b gives theheat spreading layer 114 a sufficient rigidity at its outer surfaces and edges without creating a thermal penalty at its exposed regions. - Other embodiments may employ other metals, such as stainless steel, or polymers that are sufficiently strong to provide structural stability to the highly
conductive layer 114 a. - Referring now to
FIG. 3 , asubset 300 of a flip chip package is similar to the elements recited above in connection withFIG. 2 , wherein like elements have been similarly marked. Additionally, thesubset 300 comprises aheat sink 140 having a bottom surface contoured to fit into the opening of the exposed area of the top surface of theheat spreading layer 114 a and the top surface of theframe 114 b, via aTIM2 layer 134. Contouring the bottom surface of theheat sink 140 to the top surface of the lid is beneficial because it fills a gap that would otherwise form between theheat sink 140 and the top surface of theheat spreading layer 114 a due to the asymmetrical shapes of the two surfaces. Without contouring the bottom surface of theheat sink 140, the gap may be filled with a TIM2 layer, a solution that likely would create an increased thermal penalty. - Referring now to
FIG. 4 , a further embodiment of the disclosed invention comprises asubset 400 of a flip chip package, as described and depicted inFIG. 2 . Additionally, rather than using a single-piece supporting frame (the supportingframe 114 b as shown inFIG. 2 ), the supporting frame of thesubset 400 comprises atop frame 114 c and afoot frame 114 d, joined at ajunction point 114 e. The two layers may be joined using an adhesive layer (not shown), or mechanically. Embodiments of the disclosed invention may comprisetop frames 114 c and foot frames 114 d made from, for example, copper or stainless steel. - Further referring to
FIG. 4 , the design of the two-piece supporting frame (114 c and 114 d) may be used where manufacturing considerations make it less desirable to form a single piece frame. For example, it may not be feasible to implement a molding mechanism that would form a single-piece frame around thelayer 114 a due to equipment cost, or the unavailability of a polymer ideal for manufacturing a molded frame. - Referring now to
FIG. 5 , asubset 500 of a flip chip package, according to an embodiment of the disclosed invention, comprises the elements recited and described with respect toFIG. 4 , except that thejunction point 114 e between thetop frame 114 c and thefoot frame 114 d is vertically aligned with the outer edges of theheat spreading layer 114 a, and thefoot frame 114 d forms an “L” shape in a cross sectional view. - Further referring to
FIGS. 4 and 5 , the position of thejunction point 114 e may be changed according to cost, ease of design, and other manufacturing considerations, without departing from the spirit and scope of the disclosed invention. - Referring now to
FIG. 6 , a further embodiment of the disclosed invention comprises asubset 600 of a flip chip package, as described in connection withFIG. 2 . In the disclosed embodiment, the supportingframe 114 b is a single piece having a top portion that is substantially thinner than the side or foot portions of the structure. Moreover, the top portion of the supportingframe 114 b extends onto the top surface of theheat spreading layer 114 a at a fraction of the distance it covers on the bottom surface of theheat spreading layer 114 a. Consequently, the disclosed embodiment allows for greater spreading and dissipation of heat generated by the chip die 112 by allowing a larger surface area of theheat spreading layer 114 a to connect to a heat sink. - Referring now to
FIG. 7 , a further embodiment of the disclosed invention comprises asubset 700 of a flip chip package, as recited and described with respect toFIG. 2 . In the depicted embodiment, the top surface of theheat spreading layer 114 a is chamfered such that theframe 114 b extends over a portion of thelayer 114 a. The top surface of the supportingframe 114 b is flush with a central portion of the top surface of theheat spreading layer 114 a, and extends over its chamfered edges. The bottom surface of theheat spreading layer 114 a is substantially flat. Chamfering theheat spreading layer 114 a increases the surface area at which the supportingframe 114 b contacts theheat spreading layer 114 a, improving the supporting frame's 114 b grip, without necessarily reducing the surface area of theheat layer 114 a that remains exposed. Since the exposed portion of theheat spreading layer 114 a contacts theheat sink 140, it is desirable to maintain as much contact area as possible. Moreover, according to the disclosed embodiment, theheat sink 140 has a flat bottom surface, since thelayer 114 a is flush with the supportingframe 114 b. - Referring now to
FIG. 8 , a further embodiment of the disclosed invention comprises asubset 800 of a flip chip package, as recited and described with respect toFIG. 2 . In the depicted embodiment, theheat spreading layer 114 a is chamfered along its top surface, and housed within the supportingframe 114 b, as depicted inFIG. 7 , and described in connection therewith. Additionally, the bottom surface of theheat spreading layer 114 a is also chamfered along its outer edges, with the supportingframe 114 b extending over the chamfered edges. In the depicted embodiment, the chamfered surface on the top surface of theheat spreading layer 114 a is larger than the chamfered surface of the bottom surface. - Referring now to
FIG. 9 , a further embodiment of the disclosed invention comprises asubset 900 of a flip chip package, as recited and described with respect toFIG. 2 . Furthermore, in the depicted embodiment, the top and bottom surfaces of theheat spreading layer 114 a are symmetrically chamfered and encased by the supportingframe 114 b. The top surface of the supportingframe 114 b is flush with a central portion of the top surface of theheat spreading layer 114 a. - Referring now to
FIG. 10 , a further embodiment of the disclosed invention comprises asubset 1000 of a flip chip package, as recited and described with respect toFIG. 2 . Furthermore, in the depicted embodiment, the top surface of theheat spreading layer 114 a is processed to form rabbet edges, and encased in the supportingframe 114 b, such that the supportingframe 114 b extends over the rabbet edges. Moreover, the top surface of the supportingframe 114 b is flush with a central portion of the top surface of theheat spreading layer 114 a. - Referring now to
FIG. 11 , a further embodiment of the disclosed invention comprises asubset 1100 of a wire bonding chip assembly package similar to the flip chip assembly package depicted inFIG. 6 , wherein like elements are similarly referenced. However, according to the depicted embodiment, theheat spreading layer 114 a further comprises a protruding central portion on its lower surface, whereby theheat spreading layer 114 a connects to a central portion of a top surface of thechip 112. Thechip 112 is operatively connected to thesubstrate layer 106 via a plurality ofwire connections 142, with the active side of thechip 112 facing theheat spreading layer 114 a. According to the depicted embodiment, theheat spreading layer 114 a is in contact with a central region of the top surface of thechip 112 so as to provide space for thewire connections 142 in a typical wire bonding package. Thewire connections 142 may be encapsulated in a molding compound. - Although the embodiments depicted in
FIGS. 2-11 reference anadhesive layer 136 connecting theheat spreading layer 114 a to the supportingframe 114 b (or to thetop frame 114 c and thefoot frame 114 d in embodiments having a two-piece frame), forming theadhesive layer 136 is not necessary to practice the invention. Whether theadhesive layer 136 is used and at what thickness may be varied without departing from the spirit or the scope of the disclosed invention. - Furthermore, although the embodiments of the disclosed invention depicted in
FIGS. 2-10 are based primarily on a flip chip package, it will be understood by a person of ordinary skill in the art, in light of the present disclosure, that the features of the depicted embodiments (including, without limitation, the shape of theheat spreading layer 114 a or the supportingframe 114 b) can be incorporated into corresponding embodiments using a wire bonding assembly package, as described with respect toFIG. 11 , without departing from the spirit or scope of the disclosed invention. - In addition, although the embodiments of the disclosed invention depicted in
FIGS. 2-11 are discussed in reference to thepackage 100 using BGA interconnections between thesubstrate 106 and thecircuit board 102, as depicted inFIG. 1 , these embodiments can be incorporated into a land grid array (LGA) package or a pin grid array (PGA) package. In contrast to a BGA package, wherein thesubstrate 106 is electrically connected to thecircuit board 102 via a grid ofsolder ball connections 104, LGA packages use surface contact areas on the underside of thesubstrate 106 to connect to a corresponding grid of contacts on thecircuit board 102. The connection may be implemented using a variety of methods such as LGA sockets, or solder paste. Thesubstrate 106 surface contacts in LGA packages are relatively flat compared to the solder ball connections in BGA packages. In PGA packages, the surface contacts on the underside of thesubstrate 106 are not flat, but instead are pin shaped protrusions arranged in an array, and may connect to a socket mounted on thecircuit board 102. - Furthermore, although most of the disclosed embodiments depict a single-piece frame, it will be understood by a person of ordinary skill in the art that the multi-pieced frames, such as those depicted in
FIGS. 4 and 5 , may be employed in the other depicted embodiments, and any other embodiments as claimed, without departing from the spirit or scope of the disclosed invention. - Referring now to
FIG. 12 , a multichip module (“MCM”) 1200 comprises four chips 112 (not shown) mounted onto a substrate layer 1200 (via, for example, a flip chip package) and thermally connected to respectiveheat spreading layers 114 a, wherein theheat spreading layers 114 a are encased in a supportingframe 114 b. As described with respect to other embodiments of the invention (andFIGS. 4 and 5 in particular), above, the supporting frame may be formed as a single piece through, for example, a molding manufacturing process using a polymer; or it may be formed as multiple pieces using additional manufacturing methods, such as a high pressure metal press. According to one embodiment, the supportingframe 114 b may comprise a top frame and a foot frame (not shown), similar to similarly referenced components depicted inFIGS. 4 and 5 . - Referring now to
FIG. 13 , the multichip module (“MCM”) 1200 comprises additional sets of components beneath top surfaces of the supportingframe 114 b andheat spreading layers 114 a depicted inFIG. 12 . According to the depicted embodiment, each set of components in theMCM 1200 is similar to the embodiment shown inFIG. 6 , wherein like elements have been similarly referenced. According to the embodiment depicted inFIG. 13 , each shared portion of the supportingframe 114 b situated between each pair of chips 112 (making a total of four shared portions) is a continuous portion of the entire supportingframe 114 b structure. According to related embodiments, eachheat spreading layer 114 a may be encased by a corresponding supportingframe 114 b, wherein the supportingframes 114 b are thermally or mechanically joined to one another to form theMCM 1200. - The disclosed invention, including the depicted embodiments, employ a single high-k layer supported by a frame having a stronger structural stability. By using a single graphite layer, for example, the disclosed invention allows for high heat dissipation across at least two planes, including the z plane, and at least the x or y planes. Consequently, the disclosed invention allows for effective thermal conduction overall across the entirety of the heat spreading layer, without sacrificing structural integrity or incurring a thermal penalty by covering the high-k material with another material having relatively low thermal conductivity. Embodiments of the disclosed invention increase the thermal conductivity of semiconductor packages in which they are employed, and allow for reliable operation in hygrothermal operating conditions, which include temperatures between −40° C. and 125° C., and as much as 85% relative humidity.
Claims (25)
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US (7) | US20140284040A1 (en) |
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US20140339692A1 (en) * | 2013-05-20 | 2014-11-20 | Yong-Hoon Kim | Semiconductor package stack having a heat slug |
CN105470218A (en) * | 2014-09-28 | 2016-04-06 | 德克萨斯仪器股份有限公司 | Integration of backside heat spreader for thermal management |
US9583408B1 (en) | 2015-08-21 | 2017-02-28 | International Business Machines Corporation | Reducing directional stress in an orthotropic encapsulation member of an electronic package |
US20170317005A1 (en) * | 2014-01-21 | 2017-11-02 | Infineon Technologies Austria Ag | Electronic Component Having a Heat-Sink Thermally Coupled to a Heat-Spreader |
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Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6154369A (en) * | 1998-03-23 | 2000-11-28 | Motorola, Inc. | Electronic assembly for removing heat from a semiconductor device |
US6462410B1 (en) * | 2000-08-17 | 2002-10-08 | Sun Microsystems Inc | Integrated circuit component temperature gradient reducer |
US6559379B2 (en) * | 1995-02-24 | 2003-05-06 | Novasensor, Inc. | Pressure sensor with transducer mounted on a metal base |
US20060214286A1 (en) * | 2005-03-25 | 2006-09-28 | Intel Corporation | Integrated circuit thermal management method and apparatus |
US7250576B2 (en) * | 2005-05-19 | 2007-07-31 | International Business Machines Corporation | Chip package having chip extension and method |
US20070210438A1 (en) * | 2006-03-07 | 2007-09-13 | Briere Michael A | Semiconductor package |
US20080006925A1 (en) * | 2006-03-17 | 2008-01-10 | Yim Choong B | Integrated circuit package-in-package system |
US20080290505A1 (en) * | 2007-05-23 | 2008-11-27 | United Test And Assembly Center Ltd. | Mold design and semiconductor package |
US20080305584A1 (en) * | 2007-06-08 | 2008-12-11 | Chee Seng Foong | Heat spreader for center gate molding |
US7498673B2 (en) * | 2006-11-21 | 2009-03-03 | International Business Machines Corporation | Heatplates for heatsink attachment for semiconductor chips |
US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
US20100295172A1 (en) * | 2009-05-25 | 2010-11-25 | Gao Shan | Power semiconductor module |
US20100327430A1 (en) * | 2009-06-25 | 2010-12-30 | International Business Machines Corporation | Semiconductor device assembly having a stress-relieving buffer layer |
US7900690B2 (en) * | 2008-01-07 | 2011-03-08 | King Fahd University Of Petroleum And Minerals | Moving carbon nanotube heat sink |
US20110128706A1 (en) * | 2005-09-06 | 2011-06-02 | Fujitsu Limited | Electronic apparatus |
US8085531B2 (en) * | 2009-07-14 | 2011-12-27 | Specialty Minerals (Michigan) Inc. | Anisotropic thermal conduction element and manufacturing method |
US8115303B2 (en) * | 2008-05-13 | 2012-02-14 | International Business Machines Corporation | Semiconductor package structures having liquid coolers integrated with first level chip package modules |
US8415809B2 (en) * | 2008-07-02 | 2013-04-09 | Altera Corporation | Flip chip overmold package |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4867235A (en) | 1986-10-20 | 1989-09-19 | Westinghouse Electric Corp. | Composite heat transfer means |
EP0566872A3 (en) * | 1992-04-21 | 1994-05-11 | Motorola Inc | A thermally enhanced semiconductor device and method for making the same |
EP0637070B1 (en) * | 1993-07-28 | 1997-09-24 | The Whitaker Corporation | Perimeter independent precision locating member for a semiconductor chip and method of making said member |
US6507116B1 (en) * | 1997-04-24 | 2003-01-14 | International Business Machines Corporation | Electronic package and method of forming |
US5949137A (en) * | 1997-09-26 | 1999-09-07 | Lsi Logic Corporation | Stiffener ring and heat spreader for use with flip chip packaging assemblies |
US6265771B1 (en) * | 1999-01-27 | 2001-07-24 | International Business Machines Corporation | Dual chip with heat sink |
US6486554B2 (en) * | 2001-03-30 | 2002-11-26 | International Business Machines Corporation | Molded body for PBGA and chip-scale packages |
US6475327B2 (en) | 2001-04-05 | 2002-11-05 | Phoenix Precision Technology Corporation | Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier |
US6758263B2 (en) | 2001-12-13 | 2004-07-06 | Advanced Energy Technology Inc. | Heat dissipating component using high conducting inserts |
US7042084B2 (en) * | 2002-01-02 | 2006-05-09 | Intel Corporation | Semiconductor package with integrated heat spreader attached to a thermally conductive substrate core |
US7196415B2 (en) * | 2002-03-22 | 2007-03-27 | Broadcom Corporation | Low voltage drop and high thermal performance ball grid array package |
US6898084B2 (en) | 2003-07-17 | 2005-05-24 | The Bergquist Company | Thermal diffusion apparatus |
JP2005057088A (en) | 2003-08-05 | 2005-03-03 | Agilent Technol Inc | Heat-conductive member of multilayer structure and electronic apparatus using it |
US7436060B2 (en) * | 2004-06-09 | 2008-10-14 | Lsi Corporation | Semiconductor package and process utilizing pre-formed mold cap and heatspreader assembly |
US7183641B2 (en) | 2005-03-30 | 2007-02-27 | Intel Corporation | Integrated heat spreader with intermetallic layer and method for making |
CN101163828B (en) * | 2005-04-19 | 2011-06-08 | 帝人株式会社 | Carbon fiber composite sheet, use of the same as heat transferring article, and sheet for pitch-based carbon fiber mat for use therein |
US20070062676A1 (en) | 2005-09-20 | 2007-03-22 | Grand Power Sources Inc. | Heat sink module |
JP4986435B2 (en) | 2005-10-12 | 2012-07-25 | 株式会社ソニー・コンピュータエンタテインメント | Semiconductor device and method for producing semiconductor device |
CN101375395B (en) * | 2006-01-26 | 2012-10-03 | 迈图高新材料日本合同公司 | Heat dissipating material and semiconductor device using same |
TW200810040A (en) * | 2006-06-09 | 2008-02-16 | Nec Electronics Corp | Semiconductor device and apparatus and method for manufacturing the same |
CN101536181B (en) * | 2006-11-06 | 2012-06-06 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
JP2008244168A (en) * | 2007-03-27 | 2008-10-09 | Sharp Corp | Semiconductor device, its manufacturing method, heat radiating plate, semiconductor chip, interposer substrate, and glass plate |
TW200845877A (en) * | 2007-05-07 | 2008-11-16 | Tysun Inc | Heat-dissipating substrates of composite structure |
US20090115053A1 (en) * | 2007-11-02 | 2009-05-07 | Koduri Sreenivasan K | Semiconductor Package Thermal Performance Enhancement and Method |
US20090127700A1 (en) | 2007-11-20 | 2009-05-21 | Matthew Romig | Thermal conductor lids for area array packaged multi-chip modules and methods to dissipate heat from multi-chip modules |
JP4627775B2 (en) * | 2007-12-27 | 2011-02-09 | Okiセミコンダクタ株式会社 | A method for manufacturing a semiconductor device. |
DE102008048005B3 (en) | 2008-09-19 | 2010-04-08 | Infineon Technologies Ag | Power semiconductor module arrangement and method for producing a power semiconductor module arrangement |
US7911070B2 (en) * | 2008-09-25 | 2011-03-22 | Stats Chippac Ltd. | Integrated circuit packaging system having planar interconnect |
JP5487704B2 (en) * | 2009-04-27 | 2014-05-07 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
US20110073294A1 (en) | 2009-09-25 | 2011-03-31 | Macdonald Mark | System, method and apparatus of cool touch housings |
US8531012B2 (en) * | 2009-10-23 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV |
US8034661B2 (en) * | 2009-11-25 | 2011-10-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP |
JP2011216564A (en) * | 2010-03-31 | 2011-10-27 | Mitsubishi Electric Corp | Power module and method of manufacturing the same |
US9093392B2 (en) * | 2010-12-10 | 2015-07-28 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
EP2685797B1 (en) | 2011-05-06 | 2017-12-13 | Huawei Device Co., Ltd. | Composite material and electron device |
US8941248B2 (en) * | 2013-03-13 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device package and method |
-
2013
- 2013-03-22 US US13/848,960 patent/US20140284040A1/en not_active Abandoned
-
2015
- 2015-08-27 US US14/837,491 patent/US20150371917A1/en not_active Abandoned
- 2015-08-27 US US14/837,742 patent/US20150373879A1/en not_active Abandoned
- 2015-08-27 US US14/837,871 patent/US20150371918A1/en not_active Abandoned
- 2015-08-28 US US14/838,461 patent/US20150371922A1/en not_active Abandoned
- 2015-08-28 US US14/838,418 patent/US20150373880A1/en not_active Abandoned
- 2015-08-28 US US14/838,524 patent/US9437515B2/en active Active
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6559379B2 (en) * | 1995-02-24 | 2003-05-06 | Novasensor, Inc. | Pressure sensor with transducer mounted on a metal base |
US6154369A (en) * | 1998-03-23 | 2000-11-28 | Motorola, Inc. | Electronic assembly for removing heat from a semiconductor device |
US6462410B1 (en) * | 2000-08-17 | 2002-10-08 | Sun Microsystems Inc | Integrated circuit component temperature gradient reducer |
US20060214286A1 (en) * | 2005-03-25 | 2006-09-28 | Intel Corporation | Integrated circuit thermal management method and apparatus |
US7250576B2 (en) * | 2005-05-19 | 2007-07-31 | International Business Machines Corporation | Chip package having chip extension and method |
US20110128706A1 (en) * | 2005-09-06 | 2011-06-02 | Fujitsu Limited | Electronic apparatus |
US20070210438A1 (en) * | 2006-03-07 | 2007-09-13 | Briere Michael A | Semiconductor package |
US20080006925A1 (en) * | 2006-03-17 | 2008-01-10 | Yim Choong B | Integrated circuit package-in-package system |
US7498673B2 (en) * | 2006-11-21 | 2009-03-03 | International Business Machines Corporation | Heatplates for heatsink attachment for semiconductor chips |
US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
US20080290505A1 (en) * | 2007-05-23 | 2008-11-27 | United Test And Assembly Center Ltd. | Mold design and semiconductor package |
US20080305584A1 (en) * | 2007-06-08 | 2008-12-11 | Chee Seng Foong | Heat spreader for center gate molding |
US7900690B2 (en) * | 2008-01-07 | 2011-03-08 | King Fahd University Of Petroleum And Minerals | Moving carbon nanotube heat sink |
US8115303B2 (en) * | 2008-05-13 | 2012-02-14 | International Business Machines Corporation | Semiconductor package structures having liquid coolers integrated with first level chip package modules |
US8415809B2 (en) * | 2008-07-02 | 2013-04-09 | Altera Corporation | Flip chip overmold package |
US20100295172A1 (en) * | 2009-05-25 | 2010-11-25 | Gao Shan | Power semiconductor module |
US20100327430A1 (en) * | 2009-06-25 | 2010-12-30 | International Business Machines Corporation | Semiconductor device assembly having a stress-relieving buffer layer |
US8085531B2 (en) * | 2009-07-14 | 2011-12-27 | Specialty Minerals (Michigan) Inc. | Anisotropic thermal conduction element and manufacturing method |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9277678B2 (en) * | 2012-06-29 | 2016-03-01 | Hewlett Packard Enterprise Development Lp | Multi-chip socket |
US20140313686A1 (en) * | 2012-06-29 | 2014-10-23 | Hewlett-Packard Development Company, L.P. | Multi-chip socket |
US20140339692A1 (en) * | 2013-05-20 | 2014-11-20 | Yong-Hoon Kim | Semiconductor package stack having a heat slug |
US9142478B2 (en) * | 2013-05-20 | 2015-09-22 | Samsung Electronics Co., Ltd. | Semiconductor package stack having a heat slug |
US10249551B2 (en) * | 2014-01-21 | 2019-04-02 | Infineon Technologies Austria Ag | Electronic component having a heat-sink thermally coupled to a heat-spreader |
US20170317005A1 (en) * | 2014-01-21 | 2017-11-02 | Infineon Technologies Austria Ag | Electronic Component Having a Heat-Sink Thermally Coupled to a Heat-Spreader |
CN105470218A (en) * | 2014-09-28 | 2016-04-06 | 德克萨斯仪器股份有限公司 | Integration of backside heat spreader for thermal management |
US9496198B2 (en) * | 2014-09-28 | 2016-11-15 | Texas Instruments Incorporated | Integration of backside heat spreader for thermal management |
US9698075B2 (en) | 2014-09-28 | 2017-07-04 | Texas Instruments Incorporated | Integration of backside heat spreader for thermal management |
US10468324B2 (en) | 2014-09-28 | 2019-11-05 | Texas Instruments Incorporated | Integration of heat spreader for beol thermal management |
US10542636B2 (en) * | 2014-12-05 | 2020-01-21 | International Business Machines Corporation | Cooling structure for electronic boards |
US10905029B2 (en) | 2014-12-05 | 2021-01-26 | International Business Machines Corporation | Cooling structure for electronic boards |
US10757833B2 (en) | 2014-12-05 | 2020-08-25 | International Business Machines Corporation | Cooling structure for electronic boards |
US10566215B2 (en) | 2015-06-05 | 2020-02-18 | International Business Machines Corporation | Method of fabricating a chip module with stiffening frame and orthogonal heat spreader |
US10892170B2 (en) | 2015-06-05 | 2021-01-12 | International Business Machines Corporation | Fabricating an integrated circuit chip module with stiffening frame and orthogonal heat spreader |
US10424494B2 (en) | 2015-06-05 | 2019-09-24 | International Business Machines Corporation | Chip module with stiffening frame and orthogonal heat spreader |
US10090173B2 (en) | 2015-06-05 | 2018-10-02 | International Business Machines Corporation | Method of fabricating a chip module with stiffening frame and directional heat spreader |
US9583408B1 (en) | 2015-08-21 | 2017-02-28 | International Business Machines Corporation | Reducing directional stress in an orthotropic encapsulation member of an electronic package |
CN109314092A (en) * | 2015-11-16 | 2019-02-05 | 英特尔公司 | Radiator with interlocking insertion piece |
TWI626718B (en) * | 2015-12-02 | 2018-06-11 | 聯詠科技股份有限公司 | Chip on film package |
US10043737B2 (en) | 2015-12-02 | 2018-08-07 | Novatek Microelectronics Corp. | Chip on film package |
US11145567B2 (en) * | 2016-02-26 | 2021-10-12 | National Institute Of Advanced Industrial Science And Technology | Heat-radiating substrate |
US10658263B2 (en) * | 2018-05-31 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
US11621205B2 (en) * | 2018-06-29 | 2023-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill structure for semiconductor packages and methods of forming the same |
US11842936B2 (en) | 2018-06-29 | 2023-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill structure for semiconductor packages and methods of forming the same |
US11410905B2 (en) * | 2019-03-18 | 2022-08-09 | International Business Machines Corporation | Optimized weight heat spreader for an electronic package |
US11317540B2 (en) | 2019-09-20 | 2022-04-26 | Samsung Electronics Co., Ltd. | Solid state drive apparatus and data storage apparatus including the same |
US11800686B2 (en) | 2019-09-20 | 2023-10-24 | Samsung Electronics Co., Ltd. | Solid state drive apparatus and data storage apparatus including the same |
US11846474B2 (en) * | 2020-05-12 | 2023-12-19 | Lisa Draexlmaier Gmbh | Cooling array |
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US11940233B2 (en) * | 2021-01-21 | 2024-03-26 | Cisco Technology, Inc. | Graphene and carbon nanotube based thermal management device |
Also Published As
Publication number | Publication date |
---|---|
US20150373880A1 (en) | 2015-12-24 |
US20150371917A1 (en) | 2015-12-24 |
US20150371922A1 (en) | 2015-12-24 |
US20150371919A1 (en) | 2015-12-24 |
US9437515B2 (en) | 2016-09-06 |
US20150371918A1 (en) | 2015-12-24 |
US20150373879A1 (en) | 2015-12-24 |
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