US20110024894A1 - Chip package and manufacturing method thereof - Google Patents

Chip package and manufacturing method thereof Download PDF

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Publication number
US20110024894A1
US20110024894A1 US12/730,726 US73072610A US2011024894A1 US 20110024894 A1 US20110024894 A1 US 20110024894A1 US 73072610 A US73072610 A US 73072610A US 2011024894 A1 US2011024894 A1 US 2011024894A1
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United States
Prior art keywords
chip
insulating layer
forming
layer
overlying
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Abandoned
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US12/730,726
Inventor
Baw-Ching Perng
Chun-Lung HUANG
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XinTec Inc
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XinTec Inc
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Priority to US12/730,726 priority Critical patent/US20110024894A1/en
Publication of US20110024894A1 publication Critical patent/US20110024894A1/en
Assigned to XINTEC INC. reassignment XINTEC INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, CHUN-LUNG, PERNG, BAW-CHING
Priority to US13/900,494 priority patent/US8916420B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a chip package, and in particular relates to a chip package having a metal layer covering under the chip.
  • a chip package includes a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and also a bottom portion of the cavity, a chip having an upper surface and disposed overlying the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protective layer covering the chip.
  • a method of forming one chip package includes providing a temporary substrate, forming a soft insulating layer overlying the temporary substrate, bonding at least one chip overlying the soft insulating layer, hardening the soft insulating layer to form an insulating layer, forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the insulating layer and the chip, forming a dielectric layer overlying the metal layer, removing the temporary substrate, removing the insulating layer, and forming a protective layer overlying the chip.
  • a method of forming a chip package includes providing a temporary substrate, forming an insulating layer overlying the temporary substrate, forming a soft insulating layer overlying the insulating layer, bonding at least one chip overlying the soft insulating layer, forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the soft insulating layer and the chip, forming a dielectric layer overlying the metal layer, removing the temporary substrate, removing the soft insulating layer, and forming a protective layer overlying the chip.
  • FIGS. 1A-1G are cross-sectional views showing the steps in forming a chip package in accordance with an embodiment of the present invention
  • FIGS. 2A-2G are cross-sectional views showing the steps in forming a chip package in accordance with another embodiment of the present invention.
  • FIGS. 3A-3E are illustrative views showing chip packages in accordance with embodiments of the present invention.
  • FIGS. 4A-4C are cross-sectional views showing the steps of the bonding of a chip in accordance with an embodiment of the present invention.
  • first layer “on,” “overlying,” (and like descriptions) a second layer include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers.
  • FIGS. 1A-1G are cross-sectional views showing the steps in forming a chip package according to an embodiment of the present invention.
  • a temporary substrate 100 is provided.
  • the temporary substrate 100 includes a semiconductor material, insulating material, metal material, or combinations thereof.
  • the temporary substrate 100 may be, for example, a silicon wafer or silicon substrate.
  • a soft insulating layer 102 is formed overlying the temporary substrate 100 .
  • the soft insulating layer 102 is used to fix a chip disposed thereon.
  • the soft insulating layer 102 is capable of allowing the chip to penetrate therein, and thus fix the chip.
  • the soft insulating layer 102 may include, for example, a wax, polymer material, or combinations thereof.
  • the soft insulating layer 102 is formed by, for example, a screen printing, lamination printing, or spin coating.
  • a chip 104 is bonded overlying the soft insulating layer 102 .
  • more than one chip 104 may be bonded overlying the soft insulating layer 102 .
  • the chip 104 may include a logic chip, micro electro mechanical system (MEMS) chip, micro fluidic system chip, physical sensor chip for detecting physical changes such as detecting heat, light, or pressure, RF device chip, accelerator chip, gyroscope chip, micro actuator chip, surface acoustic wave device chip, pressure sensor chip, ink printer head chip, light emitting device chip, or solar cell chip.
  • MEMS micro electro mechanical system
  • a sidewall of the chip 104 shown in FIG. 1B is substantially perpendicular to an upper surface of the temporary substrate 100
  • a chip having a sidewall inclining to the upper surface of the temporary substrate 100 may also be adopted or formed, which may make a conformal deposition of a subsequently formed material layer, such as a metal layer more easy.
  • the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 102 . As shown in FIG. 1B , the chip 104 is pressed such that a portion of the chip 104 penetrates into the soft insulating layer 102 and the chip 104 is fixed.
  • the soft insulating layer 102 is then hardened to form an insulating layer 102 a .
  • the hardened insulating layer 102 a further fixes the chip 104 and makes the temporary substrate 100 easier to remove in the following process.
  • the hardening of the soft insulating layer includes irradiating the soft insulating layer 102 with a UV light or heating the soft insulating layer 102 , such that the soft insulating layer 102 may be hardened to serve as the insulating layer 102 a .
  • the heating temperature may vary according to the material of the soft insulating layer 102 , which may range between about 120° C. and about 350° C.
  • a metal layer 106 is formed overlying the temporary substrate 100 .
  • the metal layer 106 conformally covers the insulating layer 102 a and the chip 104 .
  • the metal layer 106 directly contacts with the chip 104 .
  • another material layer such as a dielectric layer or another conducting layer may be formed between the chip 104 and the metal layer 106 depending on the situation.
  • the metal layer 106 may be formed by, for example, a physical vapor deposition, sputtering, chemical vapor deposition, electroplating, or electroless plating.
  • the metal layer 106 is conformally formed overlying the entire surface of the chip 104 .
  • the metal layer 106 may be patterned according to the requirement.
  • the patterned metal layer 106 may serve as a portion of a passive device under the chip 104 .
  • the metal layer 106 facilitates heat dissipation of the chip 104 or may be used to ground the chip.
  • a dielectric layer 108 is formed overlying the metal layer 106 .
  • the material of the dielectric layer 108 may be, for example, an epoxy resin, solder mask material, or other suitable insulating material, such as inorganic materials including silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or combinations thereof, or organic polymer materials including polyimide, butylcyclobutene (BCB, Dow Chemical Co.), parylene, polynaphthalenes, fluorocarbons, or acrylates and so on.
  • the dielectric layer 108 may be formed by a coating method, such as a spin coating, spray coating, or curtain coating method, or other suitable deposition methods, such as a liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure vapor deposition.
  • a coating method such as a spin coating, spray coating, or curtain coating method
  • suitable deposition methods such as a liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure vapor deposition.
  • the dielectric layer 108 is going to be used as a substrate supporting the chip 104 .
  • the dielectric layer 108 has a substantially planar upper surface.
  • the temporary substrate 100 is removed from the surface of the hardened insulating layer 102 a .
  • the insulating layer 102 a is removed.
  • the material of the hardened insulating layer 102 a is a wax which can be removed easily.
  • the removing of the insulating layer 102 a includes heating the wax to a melting point of the wax, such as 100° C., and then removing the wax using an external force.
  • the upper surface of the chip 104 is higher than the upper surface of the metal layer 106 beside the chip 104 .
  • the chip 104 is merely bonded overlying the soft insulating layer 102 without sinking into the soft insulating layer 102 .
  • the entire chip 104 is located in the dielectric layer 108 .
  • the upper surface of the chip is as high as the upper surface of the metal layer 106 beside the chip 104 .
  • the upper surfaces of the chip and the metal layers are coplanar.
  • the dielectric layer 108 is now used as a substrate, and a protective layer 110 is formed overlying the chip 104 .
  • the material and forming method of the protective layer 110 may be similar to those of the dielectric layer 108 .
  • the protective layer 110 may protect the chip 104 from impact by an external force or contamination from outside.
  • conducting structures 112 are further formed overlying the protective layer 110 .
  • the conducting structure 112 is electrically connected to the chip 104 through, for example, a conducting via (not shown).
  • each of the conducting structures 112 is electrically connected to one chip 104 individually.
  • one of the conducting structures 112 may be electrically connected to two (or more) chips 104 to form a signal transmission bridge between the two different chips.
  • the same chip 104 may be connected with a plurality of conducting structures 112 . However, it does not mean that these conducting structures 112 are electrically connected to each other.
  • These conducting structures 112 may be electrically connected to different pads or different device regions of the chip 104 and electrically insulated from each other.
  • the conducting structure 112 may be electrically connected to the metal layer 106 . In this case, the conducting structure 112 may be used as a ground electrode.
  • the conducting structure 112 may be a solder ball.
  • the conducting structures 112 such as solder balls may be distributed on the protective layer 110 which has a larger area, and thus reduces the problem caused by the high density of the solder balls.
  • solder balls corresponding to each of the chips are together distributed on the protective layer 110 .
  • the area of the protective layer 110 is effectively utilized which allows the size of the chip package to become smaller.
  • FIGS. 2A-2G are cross-sectional views showing the steps in forming a chip package according to another embodiment of the present invention, wherein similar or same reference numbers are used to designate similar elements. Materials or formation methods of similar or same material layers are not described repeatedly.
  • a temporary substrate 100 is provided.
  • an insulating layer 101 a is formed overlying the temporary substrate 100 .
  • the insulating layer 101 a may include a wax, polymer material, or combinations thereof.
  • a soft insulating layer may be formed overlying the temporary substrate 100 and then hardened to form an insulating layer 101 a .
  • the soft insulating layer may be hardened to form the insulating layer 101 a by heating the layer or by means of light irradiation, such as using a UV light.
  • a soft insulating layer 102 is formed overlying the insulating layer 101 a.
  • the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 102 .
  • the chip 104 is pressed such that a portion of the chip 104 penetrates into the soft insulating layer 102 and is fixed. The chip 104 directly contacts with the insulating layer 101 a.
  • a metal layer 106 is formed overlying the temporary substrate 100 .
  • the metal layer 106 conformally covers and overlays the soft insulating layer 102 and the chip 104 .
  • the metal layer 106 directly contacts with the chip 104 .
  • another material layer such as a dielectric layer or another conducting layer, may be formed between the chip 104 and the metal layer 106 depending on the situation.
  • the metal layer 106 may be formed by a physical vapor deposition, sputtering, chemical vapor deposition, electroplating, or electroless plating.
  • the soft insulating layer 102 is formed on the insulating layer 101 a and may protect the insulating layer 101 a thereunder from being bombarded by ion beams and becoming deteriorated, which benefits to a following removing step.
  • a dielectric layer 108 is formed overlying the metal layer 106 .
  • the dielectric layer 108 will be used as a substrate supporting the chip 104 .
  • the dielectric layer 108 has a substantially planar upper surface.
  • the temporary substrate 100 is removed from the surface of the insulating layer 101 a .
  • the insulating layer 101 a is removed.
  • the material of the insulating layer 101 a is a wax and is protected by the soft insulating layer 102 from being deteriorated.
  • the insulating layer 101 a may be removed easily.
  • the soft insulating layer 102 still remains.
  • the upper surface of the soft insulating layer 102 is coplanar with the upper surface of the chip 104 .
  • the soft insulating layer 102 may be completely or partially removed.
  • the soft insulating layer 102 may be hardened.
  • the dielectric layer 108 is now used as a substrate, and a protective layer 110 is formed overlying the chip 104 .
  • the protective layer 110 may protect the chip 104 from impact of an external force or contaminations from the environment.
  • a plurality of conducting structures 112 are further formed overlying the protective layer 110 .
  • the conducting structure 112 is electrically connected to the chip 104 through, for example, a conducting via (not shown).
  • the insulating layer (the soft insulating layer 102 or hardened insulating layer) is located between the metal layer 106 and the protective layer 110 and has an upper surface no higher than the upper surface of the chip 104 .
  • the upper surface of the insulating layer is as high as and substantially coplanar with the upper surface of the upper surface of the chip 104 .
  • a portion of the insulating layer may be removed such that the upper surface of the insulating layer 102 is lower than the upper surface of the chip 104 .
  • FIGS. 4A-4C are cross-sectional views showing the steps in the chip bonding process in accordance with an embodiment of the present invention.
  • a soft insulating layer 201 and a soft insulating layer 202 are formed overlying the temporary substrate 100 in turn.
  • at least one chip 104 is bonded overlying the soft insulating layer 202 .
  • the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 202 .
  • FIG. 4A-4C are cross-sectional views showing the steps in the chip bonding process in accordance with an embodiment of the present invention.
  • FIG. 4A a soft insulating layer 201 and a soft insulating layer 202 are formed overlying the temporary substrate 100 in turn.
  • at least one chip 104 is bonded overlying the soft insulating layer 202 .
  • the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 202 .
  • a portion of the chip 104 is pressed into the soft insulating layer 202 and is fixed.
  • the chip 104 further directly contacts with the soft insulating layer 201 .
  • the chip 104 merely sinks into the soft insulating layer 202 without directly contacting with the soft insulating layer 201 .
  • the chip 104 penetrates through an interface between the soft insulating layer 201 and the soft insulating layer 202 and partially sinks into the soft insulating layer 201 . Depth of the chip 104 sinking into the soft insulating layer 202 and/or the soft insulating layer 201 may be adjusted depending on the situation and requirement.
  • the soft insulating layer 201 is hardened to form an insulating layer 201 a , which facilitates a following process of removing the temporary substrate 100 .
  • the soft insulating layer 202 is also hardened to be an insulating layer 202 a .
  • the soft insulating layers 201 and 202 may be hardened simultaneously by heating.
  • a hardened insulating layer 201 a is first formed overlying the temporary substrate 100 .
  • the soft insulating layer 202 is then formed overlying the insulating layer 201 a .
  • the bonding of the chip 104 and the forming of the insulating layer 202 a by hardening the soft insulating layer 202 are performed.
  • the bonding of the chip 104 may include, for example, pressing the chip 104 such that a portion of the chip 104 penetrates into the soft insulating layer 202 and directly contacts with the insulating layer 201 a .
  • a metal layer 106 is formed overlying the chip 104 and the insulating layer 202 a , and other following packaging processes similar to those shown in FIG. 1G or 2 G may be performed.
  • FIGS. 3A-3F are illustrative views showing chip packages according to embodiments of the present invention.
  • FIG. 3A shows a cross-sectional view of a chip package according to an embodiment of the present invention.
  • the chip package includes a substrate (the dielectric layer 108 used as the substrate), a first cavity 302 a extending downward from the upper surface 108 a of the substrate (dielectric layer 108 ), a metal layer 106 located overlying the substrate and conformally covering a sidewall and a bottom portion of the first cavity 302 a , a first chip 104 a having a first upper surface 105 a and disposed overlying the metal layer 106 in the first cavity 302 a , and a protective layer 110 covering the first chip 104 a .
  • a first upper surface 105 a of the first chip 104 a is no lower than the upper surface 107 of the metal layer 106 outside of the first cavity 302 a .
  • the first upper surface 105 a of the first chip 104 a may be higher than the upper surface 107 of the metal layer 106 outside of the first cavity 302 a .
  • the first upper surface 105 a of the first chip 104 a may be substantially coplanar with the upper surface 107 of the metal layer 106 outside of the first cavity 302 a .
  • the metal layer 106 directly contacts with the first chip 104 a .
  • the chip package may further include a conducting structure 112 disposed overlying the protective layer, wherein the conducting structure 112 is electrically connected to the first chip 104 a .
  • a sidewall of the first chip 104 a is substantially parallel to the sidewall of the first cavity 302 a.
  • FIG. 3C shows a cross-sectional view of a chip package according to an embodiment of the present invention, which is similar to that shown in FIG. 3A .
  • the main difference is that the sidewall of the first cavity 302 a inclines to the upper surface 108 a of the substrate (dielectric layer 108 ).
  • the sidewall of the first chip 104 a also inclines to the substrate and is substantially parallel to the sidewall of the first cavity 302 a.
  • a chip package may include a second chip 104 b (and/or more other chips) disposed overlying the metal layer 106 in the second cavity 302 b .
  • the second cavity 302 b extends downward from the upper surface 108 a of the substrate (dielectric layer 108 ). Similar to the first chip 104 a , a second upper surface 105 b of the second chip 104 b is no lower than the upper surface 107 of the metal layer 106 outside of the second cavity 302 b .
  • the first cavity 302 a may have a size or a shape which is different from that of the second cavity 302 b .
  • the metal layer 106 directly contacts with the second chip 104 b .
  • the second chip 104 b directly contacts with the metal layer 106 in the second cavity 302 b.
  • the first chip 104 a has a size and a shape different from those of the second chip 104 b .
  • the first chip 104 a and the second chip 104 b have different functions.
  • the chip package of the embodiment also includes a protective layer and a first conducting structure 112 a and a second conducting structure 112 b disposed thereon, which are electrically connected to the first chip 104 a and the second chip 104 b , respectively.
  • One of these conducting structures may be electrically connected to first chip 104 a and the second chip 104 b at the same time, serving as a signal transmission bridge between the two chips.
  • the first conducting structure 112 a and/or the second conducting structure 112 b may be electrically connected to the metal layer 106 through, for example, a conducting agent via penetration of the protective layer 110 .
  • the metal layer 106 may further be patterned in the following manner.
  • the patterned metal layer and the substrate may together form a passive device, such as a capacitor, inductor, or resistor.
  • the patterned conducting layer 106 may include a first metal pattern 106 a and a second metal pattern 106 b (as shown in FIG. 3E ).
  • the metal patterns and the substrate may together form a capacitor.
  • the passive device such as a capacitor formed under the bottom portion of the chip may be electrically connected to a specific device in the chip 104 through, for example, the conducting layer 106 and the conducting structure 112 .
  • the passive device formed under the bottom portion of the chip may be electrically connected to a specific device in the chip through a conducting path formed in the chip.
  • a metal layer is formed under the chip, heat generated by the chip during operation will be effectively dissipated.
  • the metal layer under the chip has additional functions.
  • the metal layer may be used as a passive device or it can function to ground the chip.
  • Conducting structures such as solder balls are distributed overlying a protective layer with a larger area. Not only is the distribution density of the conducting structures relaxed but also, the area of the protective layer 110 is employed adequately, leading to size shrinkage of the entire system on chip package.
  • the height of the chip can also be controlled easily because the soft layer which is used for bonding can be molded according to different height specifications. In addition, the soft insulating layer, after being hardened, may be removed easily, facilitating packaging of the chip.

Abstract

An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/229,146, filed on Jul. 28, 2009, the entirety of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a chip package, and in particular relates to a chip package having a metal layer covering under the chip.
  • 2. Description of the Related Art
  • Advances in semiconductor processing technologies are dramatically reducing the feature sizes of integrated circuit (IC) devices such that more semiconductor elements are formed within a smaller chip. In addition to improving chip performance, the wafer area is further saved to reduce manufacturing cost. However, due to the ever-decreasing size of chips and the ever-increasing density of devices formed therein, the amount and the density of the input/output connections are increasing accordingly, such that formation of connection paths to the chip is getting difficult. In addition, when devices with high density operate in a smaller chip, a lot of heat may be generated and performance of the chip may be negatively affected.
    • BRIEF SUMMARY OF THE INVENTION
  • According to an illustrative embodiment, a chip package is provided. The chip package includes a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and also a bottom portion of the cavity, a chip having an upper surface and disposed overlying the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protective layer covering the chip.
  • According to an illustrative embodiment, a method of forming one chip package is provided. The method includes providing a temporary substrate, forming a soft insulating layer overlying the temporary substrate, bonding at least one chip overlying the soft insulating layer, hardening the soft insulating layer to form an insulating layer, forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the insulating layer and the chip, forming a dielectric layer overlying the metal layer, removing the temporary substrate, removing the insulating layer, and forming a protective layer overlying the chip.
  • According to another illustrative embodiment, a method of forming a chip package is provided. The method includes providing a temporary substrate, forming an insulating layer overlying the temporary substrate, forming a soft insulating layer overlying the insulating layer, bonding at least one chip overlying the soft insulating layer, forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the soft insulating layer and the chip, forming a dielectric layer overlying the metal layer, removing the temporary substrate, removing the soft insulating layer, and forming a protective layer overlying the chip.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIGS. 1A-1G are cross-sectional views showing the steps in forming a chip package in accordance with an embodiment of the present invention;
  • FIGS. 2A-2G are cross-sectional views showing the steps in forming a chip package in accordance with another embodiment of the present invention;
  • FIGS. 3A-3E are illustrative views showing chip packages in accordance with embodiments of the present invention; and
  • FIGS. 4A-4C are cross-sectional views showing the steps of the bonding of a chip in accordance with an embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • It is understood, that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers.
  • FIGS. 1A-1G are cross-sectional views showing the steps in forming a chip package according to an embodiment of the present invention. As shown in FIG. 1A, a temporary substrate 100 is provided. The temporary substrate 100 includes a semiconductor material, insulating material, metal material, or combinations thereof. In one embodiment, the temporary substrate 100 may be, for example, a silicon wafer or silicon substrate.
  • Then, a soft insulating layer 102 is formed overlying the temporary substrate 100. In the following process, the soft insulating layer 102 is used to fix a chip disposed thereon. Thus, it is preferable that the soft insulating layer 102 is capable of allowing the chip to penetrate therein, and thus fix the chip. The soft insulating layer 102 may include, for example, a wax, polymer material, or combinations thereof. The soft insulating layer 102 is formed by, for example, a screen printing, lamination printing, or spin coating.
  • As shown in FIG. 1B, a chip 104 is bonded overlying the soft insulating layer 102. In addition, in another embodiment, more than one chip 104 may be bonded overlying the soft insulating layer 102. These chips may be different kinds of chips and each has its specific function. For example, in one embodiment, the chip 104 may include a logic chip, micro electro mechanical system (MEMS) chip, micro fluidic system chip, physical sensor chip for detecting physical changes such as detecting heat, light, or pressure, RF device chip, accelerator chip, gyroscope chip, micro actuator chip, surface acoustic wave device chip, pressure sensor chip, ink printer head chip, light emitting device chip, or solar cell chip. In addition, sizes or shapes of different chips may be different from each other. In addition, although a sidewall of the chip 104 shown in FIG. 1B is substantially perpendicular to an upper surface of the temporary substrate 100, a chip having a sidewall inclining to the upper surface of the temporary substrate 100 may also be adopted or formed, which may make a conformal deposition of a subsequently formed material layer, such as a metal layer more easy.
  • In one embodiment, the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 102. As shown in FIG. 1B, the chip 104 is pressed such that a portion of the chip 104 penetrates into the soft insulating layer 102 and the chip 104 is fixed.
  • As shown in FIG. 1C, the soft insulating layer 102 is then hardened to form an insulating layer 102 a. The hardened insulating layer 102 a further fixes the chip 104 and makes the temporary substrate 100 easier to remove in the following process. In one embodiment, the hardening of the soft insulating layer includes irradiating the soft insulating layer 102 with a UV light or heating the soft insulating layer 102, such that the soft insulating layer 102 may be hardened to serve as the insulating layer 102 a. The heating temperature may vary according to the material of the soft insulating layer 102, which may range between about 120° C. and about 350° C.
  • Then, as shown in FIG. 1C, a metal layer 106 is formed overlying the temporary substrate 100. The metal layer 106 conformally covers the insulating layer 102 a and the chip 104. In this embodiment, the metal layer 106 directly contacts with the chip 104. In another embodiment, another material layer such as a dielectric layer or another conducting layer may be formed between the chip 104 and the metal layer 106 depending on the situation. The metal layer 106 may be formed by, for example, a physical vapor deposition, sputtering, chemical vapor deposition, electroplating, or electroless plating. In one embodiment, the metal layer 106 is conformally formed overlying the entire surface of the chip 104. In another embodiment, the metal layer 106 may be patterned according to the requirement. For example, the patterned metal layer 106 may serve as a portion of a passive device under the chip 104. In addition, the metal layer 106 facilitates heat dissipation of the chip 104 or may be used to ground the chip.
  • As shown in FIG. 1D, a dielectric layer 108 is formed overlying the metal layer 106. The material of the dielectric layer 108 may be, for example, an epoxy resin, solder mask material, or other suitable insulating material, such as inorganic materials including silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or combinations thereof, or organic polymer materials including polyimide, butylcyclobutene (BCB, Dow Chemical Co.), parylene, polynaphthalenes, fluorocarbons, or acrylates and so on. The dielectric layer 108 may be formed by a coating method, such as a spin coating, spray coating, or curtain coating method, or other suitable deposition methods, such as a liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure vapor deposition. In the following process, the dielectric layer 108 is going to be used as a substrate supporting the chip 104. Thus, it is preferable that the dielectric layer 108 has a substantially planar upper surface.
  • As shown in FIG. 1E, the temporary substrate 100 is removed from the surface of the hardened insulating layer 102 a. Then, as shown in FIG. 1F, the insulating layer 102 a is removed. In one embodiment, the material of the hardened insulating layer 102 a is a wax which can be removed easily. The removing of the insulating layer 102 a includes heating the wax to a melting point of the wax, such as 100° C., and then removing the wax using an external force. In this embodiment, the upper surface of the chip 104 is higher than the upper surface of the metal layer 106 beside the chip 104. In another embodiment, the chip 104 is merely bonded overlying the soft insulating layer 102 without sinking into the soft insulating layer 102. The entire chip 104 is located in the dielectric layer 108. Thus, the upper surface of the chip is as high as the upper surface of the metal layer 106 beside the chip 104. The upper surfaces of the chip and the metal layers are coplanar.
  • As shown in FIG. 1G, the dielectric layer 108 is now used as a substrate, and a protective layer 110 is formed overlying the chip 104. The material and forming method of the protective layer 110 may be similar to those of the dielectric layer 108. The protective layer 110 may protect the chip 104 from impact by an external force or contamination from outside.
  • In the embodiment shown in FIG. 1G, conducting structures 112 are further formed overlying the protective layer 110. The conducting structure 112 is electrically connected to the chip 104 through, for example, a conducting via (not shown). In one embodiment, each of the conducting structures 112 is electrically connected to one chip 104 individually. In another embodiment, one of the conducting structures 112 may be electrically connected to two (or more) chips 104 to form a signal transmission bridge between the two different chips. It should be noted that the same chip 104 may be connected with a plurality of conducting structures 112. However, it does not mean that these conducting structures 112 are electrically connected to each other. These conducting structures 112 may be electrically connected to different pads or different device regions of the chip 104 and electrically insulated from each other. In yet another embodiment, the conducting structure 112 may be electrically connected to the metal layer 106. In this case, the conducting structure 112 may be used as a ground electrode.
  • In one embodiment, the conducting structure 112 may be a solder ball. With the ever-decreasing size of chips and the ever-increasing density of devices formed therein, the amount and the density of input/output connections are increased accordingly. In this case, it is difficult to form conducting structures such as solder balls in a limited chip area. In an embodiment of the invention, a protective layer 110 is formed and thus the conducting structures 112 such as solder balls may be distributed on the protective layer 110 which has a larger area, and thus reduces the problem caused by the high density of the solder balls. In embodiments of the invention, it is preferable to integrate a plurality of chips. Thus, solder balls corresponding to each of the chips are together distributed on the protective layer 110. Not only is distribution density of the conducting structures relaxed, but also the area of the protective layer 110 is effectively utilized which allows the size of the chip package to become smaller.
  • FIGS. 2A-2G are cross-sectional views showing the steps in forming a chip package according to another embodiment of the present invention, wherein similar or same reference numbers are used to designate similar elements. Materials or formation methods of similar or same material layers are not described repeatedly.
  • As shown in FIG. 2A, a temporary substrate 100 is provided. Then, an insulating layer 101 a is formed overlying the temporary substrate 100. The insulating layer 101 a may include a wax, polymer material, or combinations thereof. In one embodiment, a soft insulating layer may be formed overlying the temporary substrate 100 and then hardened to form an insulating layer 101 a. For example, the soft insulating layer may be hardened to form the insulating layer 101 a by heating the layer or by means of light irradiation, such as using a UV light. Then, a soft insulating layer 102 is formed overlying the insulating layer 101 a.
  • As shown in FIG. 2B, at least one chip 104 is bonded overlying the soft insulating layer 102. In one embodiment, the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 102. As shown in FIG. 2B, in this embodiment, the chip 104 is pressed such that a portion of the chip 104 penetrates into the soft insulating layer 102 and is fixed. The chip 104 directly contacts with the insulating layer 101 a.
  • Then, as shown in FIG. 2C, a metal layer 106 is formed overlying the temporary substrate 100. The metal layer 106 conformally covers and overlays the soft insulating layer 102 and the chip 104. In this embodiment, the metal layer 106 directly contacts with the chip 104. In another embodiment, another material layer, such as a dielectric layer or another conducting layer, may be formed between the chip 104 and the metal layer 106 depending on the situation. The metal layer 106 may be formed by a physical vapor deposition, sputtering, chemical vapor deposition, electroplating, or electroless plating. Wherein, when a sputtering is chosen to form the metal layer 106, the soft insulating layer 102 is formed on the insulating layer 101 a and may protect the insulating layer 101 a thereunder from being bombarded by ion beams and becoming deteriorated, which benefits to a following removing step.
  • Then, as shown in FIG. 2D, a dielectric layer 108 is formed overlying the metal layer 106. In the following process, the dielectric layer 108 will be used as a substrate supporting the chip 104. Thus, it is preferable that the dielectric layer 108 has a substantially planar upper surface.
  • As shown in FIG. 2E, the temporary substrate 100 is removed from the surface of the insulating layer 101 a. Then, as shown in FIG. 2F, the insulating layer 101 a is removed. In one embodiment, the material of the insulating layer 101 a is a wax and is protected by the soft insulating layer 102 from being deteriorated. Thus, the insulating layer 101 a may be removed easily. In the embodiment shown in FIG. 2F, the soft insulating layer 102 still remains. The upper surface of the soft insulating layer 102 is coplanar with the upper surface of the chip 104. In another embodiment, the soft insulating layer 102 may be completely or partially removed. In yet another embodiment, the soft insulating layer 102 may be hardened.
  • As shown in FIG. 2G, the dielectric layer 108 is now used as a substrate, and a protective layer 110 is formed overlying the chip 104. The protective layer 110 may protect the chip 104 from impact of an external force or contaminations from the environment. In the embodiment shown in FIG. 2G, a plurality of conducting structures 112 are further formed overlying the protective layer 110. The conducting structure 112 is electrically connected to the chip 104 through, for example, a conducting via (not shown).
  • In the embodiment shown in FIG. 2G, the insulating layer (the soft insulating layer 102 or hardened insulating layer) is located between the metal layer 106 and the protective layer 110 and has an upper surface no higher than the upper surface of the chip 104. For example, in the embodiment shown in FIG. 2F, the upper surface of the insulating layer is as high as and substantially coplanar with the upper surface of the upper surface of the chip 104. Alternatively, in another embodiment, a portion of the insulating layer may be removed such that the upper surface of the insulating layer 102 is lower than the upper surface of the chip 104.
  • According to embodiments of the invention, the bonding of the chip 104 is not limited to the methods mentioned above. For example, FIGS. 4A-4C are cross-sectional views showing the steps in the chip bonding process in accordance with an embodiment of the present invention. As shown in FIG. 4A, a soft insulating layer 201 and a soft insulating layer 202 are formed overlying the temporary substrate 100 in turn. Then, as shown in FIG. 4B, at least one chip 104 is bonded overlying the soft insulating layer 202. In this embodiment, the bonding of the chip 104 includes pressing the chip 104 into the soft insulating layer 202. As shown in FIG. 4B, a portion of the chip 104 is pressed into the soft insulating layer 202 and is fixed. The chip 104 further directly contacts with the soft insulating layer 201. In another embodiment, the chip 104 merely sinks into the soft insulating layer 202 without directly contacting with the soft insulating layer 201. In yet another embodiment, the chip 104 penetrates through an interface between the soft insulating layer 201 and the soft insulating layer 202 and partially sinks into the soft insulating layer 201. Depth of the chip 104 sinking into the soft insulating layer 202 and/or the soft insulating layer 201 may be adjusted depending on the situation and requirement.
  • Then, as shown in FIG. 4C, the soft insulating layer 201 is hardened to form an insulating layer 201 a, which facilitates a following process of removing the temporary substrate 100. In this embodiment, when the soft insulating layer 201 is hardened, the soft insulating layer 202 is also hardened to be an insulating layer 202 a. For example, the soft insulating layers 201 and 202 may be hardened simultaneously by heating.
  • Alternatively, in another embodiment, a hardened insulating layer 201 a is first formed overlying the temporary substrate 100. The soft insulating layer 202 is then formed overlying the insulating layer 201 a. Thereafter, the bonding of the chip 104 and the forming of the insulating layer 202 a by hardening the soft insulating layer 202 are performed. The bonding of the chip 104 may include, for example, pressing the chip 104 such that a portion of the chip 104 penetrates into the soft insulating layer 202 and directly contacts with the insulating layer 201 a. Then, a metal layer 106 is formed overlying the chip 104 and the insulating layer 202 a, and other following packaging processes similar to those shown in FIG. 1G or 2G may be performed.
  • FIGS. 3A-3F are illustrative views showing chip packages according to embodiments of the present invention. FIG. 3A shows a cross-sectional view of a chip package according to an embodiment of the present invention. The chip package includes a substrate (the dielectric layer 108 used as the substrate), a first cavity 302 a extending downward from the upper surface 108 a of the substrate (dielectric layer 108), a metal layer 106 located overlying the substrate and conformally covering a sidewall and a bottom portion of the first cavity 302 a, a first chip 104 a having a first upper surface 105 a and disposed overlying the metal layer 106 in the first cavity 302 a, and a protective layer 110 covering the first chip 104 a. In this embodiment of the invention, a first upper surface 105 a of the first chip 104 a is no lower than the upper surface 107 of the metal layer 106 outside of the first cavity 302 a. For example, the first upper surface 105 a of the first chip 104 a may be higher than the upper surface 107 of the metal layer 106 outside of the first cavity 302 a. Alternatively, the first upper surface 105 a of the first chip 104 a may be substantially coplanar with the upper surface 107 of the metal layer 106 outside of the first cavity 302 a. In this embodiment, the metal layer 106 directly contacts with the first chip 104 a. When the metal layer 106 is conformally formed overlying the chip, the first chip 104 a directly contacts with the metal layer 106 in the first cavity 302 a. In addition, the chip package, according to an embodiment of the invention, may further include a conducting structure 112 disposed overlying the protective layer, wherein the conducting structure 112 is electrically connected to the first chip 104 a. In addition, a sidewall of the first chip 104 a is substantially parallel to the sidewall of the first cavity 302 a.
  • FIG. 3C shows a cross-sectional view of a chip package according to an embodiment of the present invention, which is similar to that shown in FIG. 3A. The main difference is that the sidewall of the first cavity 302 a inclines to the upper surface 108 a of the substrate (dielectric layer 108). The sidewall of the first chip 104 a also inclines to the substrate and is substantially parallel to the sidewall of the first cavity 302 a.
  • Referring to FIG. 3B, a chip package according to an embodiment of the invention may include a second chip 104 b (and/or more other chips) disposed overlying the metal layer 106 in the second cavity 302 b. The second cavity 302 b extends downward from the upper surface 108 a of the substrate (dielectric layer 108). Similar to the first chip 104 a, a second upper surface 105 b of the second chip 104 b is no lower than the upper surface 107 of the metal layer 106 outside of the second cavity 302 b. The first cavity 302 a may have a size or a shape which is different from that of the second cavity 302 b. In this embodiment, the metal layer 106 directly contacts with the second chip 104 b. When the metal layer 106 is conformally formed overlying the entire exposed surface of the chip, the second chip 104 b directly contacts with the metal layer 106 in the second cavity 302 b.
  • In the embodiment shown in FIG. 3B, the first chip 104 a has a size and a shape different from those of the second chip 104 b. The first chip 104 a and the second chip 104 b have different functions. The chip package of the embodiment also includes a protective layer and a first conducting structure 112 a and a second conducting structure 112 b disposed thereon, which are electrically connected to the first chip 104 a and the second chip 104 b, respectively. One of these conducting structures may be electrically connected to first chip 104 a and the second chip 104 b at the same time, serving as a signal transmission bridge between the two chips. Alternatively, depending on the situation, the first conducting structure 112 a and/or the second conducting structure 112 b may be electrically connected to the metal layer 106 through, for example, a conducting agent via penetration of the protective layer 110.
  • In addition, in one embodiment, the metal layer 106 may further be patterned in the following manner. The patterned metal layer and the substrate (dielectric layer 108) may together form a passive device, such as a capacitor, inductor, or resistor. For example, as shown in FIGS. 3D and 3E, the patterned conducting layer 106 may include a first metal pattern 106 a and a second metal pattern 106 b (as shown in FIG. 3E). The metal patterns and the substrate may together form a capacitor. The passive device such as a capacitor formed under the bottom portion of the chip may be electrically connected to a specific device in the chip 104 through, for example, the conducting layer 106 and the conducting structure 112. Alternatively, the passive device formed under the bottom portion of the chip may be electrically connected to a specific device in the chip through a conducting path formed in the chip.
  • In a chip package of an embodiment of the invention, because a metal layer is formed under the chip, heat generated by the chip during operation will be effectively dissipated. The metal layer under the chip has additional functions. For example, the metal layer may be used as a passive device or it can function to ground the chip. Conducting structures such as solder balls are distributed overlying a protective layer with a larger area. Not only is the distribution density of the conducting structures relaxed but also, the area of the protective layer 110 is employed adequately, leading to size shrinkage of the entire system on chip package. The height of the chip can also be controlled easily because the soft layer which is used for bonding can be molded according to different height specifications. In addition, the soft insulating layer, after being hardened, may be removed easily, facilitating packaging of the chip.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (20)

1. A chip package, comprising:
a substrate;
a first cavity extending downward from an upper surface of the substrate;
a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the first cavity;
a first chip having a first upper surface and disposed overlying the metal layer in the first cavity, wherein the first upper surface is not lower than an upper surface of the metal layer outside of the first cavity; and
a protective layer covering the first chip.
2. The chip package as claimed in claim 1, further comprising at least a first conducting structure overlying the protective layer and electrically connected to the first chip or the metal layer.
3. The chip package as claimed in claim 1, wherein the sidewall of the first cavity inclines to the upper surface of the substrate.
4. The chip package as claimed in claim 1, further comprising a first insulating layer located between the metal layer and the protective layer, wherein an upper surface of the first insulating layer is not higher than the first upper surface of the first chip.
5. The chip package as claimed in claim 1, further comprising:
a second cavity extending downward from the first surface, wherein the metal layer conformally covers a sidewall and a bottom portion of the second cavity; and
a second chip having a second upper surface and disposed overlying the metal layer in the second cavity, wherein the second upper surface is not lower than the upper surface of the metal layer outside of the second cavity.
6. The chip package as claimed in claim 5, further comprising at least a second conducting structure disposed overlying the protective layer and electrically connected to the second chip or the metal layer.
7. A method of forming a chip package, comprising:
providing a temporary substrate;
forming a first soft insulating layer overlying the temporary substrate;
bonding at least one chip overlying the first soft insulating layer;
hardening the first soft insulating layer to form a first insulating layer;
forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the first insulating layer and the chip;
forming a dielectric layer overlying the metal layer;
removing the temporary substrate;
removing the first insulating layer; and
forming a protective layer overlying the chip.
8. The method of forming a chip package as claimed in claim 7, wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer.
9. The method of forming a chip package as claimed in claim 7, wherein a sidewall of the chip inclines to an upper surface of the temporary substrate.
10. The method of forming a chip package as claimed in claim 7, further comprising forming a second soft insulating layer overlying the temporary substrate before the forming of the first soft insulating layer.
11. The method of forming a chip package as claimed in claim 10, wherein the step of bonding the chip overlying the first soft insulating layer comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer and directly contacts with the second soft insulating layer.
12. The method of forming a chip package as claimed in claim 11, further comprising hardening the second soft insulating layer to form a second insulating layer.
13. The method of forming a chip package as claimed in claim 12, wherein the hardening of the second soft insulating layer and the hardening of the first soft insulating layer are performed simultaneously.
14. The method of forming a chip package as claimed in claim 10, further comprising hardening the second soft insulating layer to form a second insulating layer before the forming the first insulating layer.
15. The method of forming a chip package as claimed in claim 14, wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the first soft insulating layer and directly contacts with the second insulating layer.
16. A method of forming a chip package, comprising:
providing a temporary substrate;
forming an insulating layer overlying the temporary substrate;
forming a soft insulating layer overlying the insulating layer;
bonding at least one chip overlying the soft insulating layer;
forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the soft insulating layer and the chip;
forming a dielectric layer overlying the metal layer;
removing the temporary substrate;
removing the soft insulating layer; and
forming a protective layer overlying the chip.
17. The method of forming a chip package as claimed in claim 16, wherein the bonding of the chip comprises pressing the chip such that a portion of the chip penetrates into the soft insulating layer.
18. The method of forming a chip package as claimed in claim 17, wherein the chip directly contacts with the insulating layer.
19. The method of forming a chip package as claimed in claim 16, wherein the forming of the insulating layer comprises forming a second soft insulating layer overlying the temporary substrate and hardening the second soft insulating layer to form the insulating layer.
20. The method of forming a chip package as claimed in claim 16, further comprising a plurality of conducting structures overlying the protective layer, wherein the conducting structures electrically connect the chip or the metal layer.
US12/730,726 2009-07-28 2010-03-24 Chip package and manufacturing method thereof Abandoned US20110024894A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2974942A1 (en) * 2011-05-06 2012-11-09 3D Plus PROCESS FOR PRODUCING RECONSTITUTED PLATES WITH THE MAINTENANCE OF CHIPS DURING THEIR ENCAPSULATION
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US20170024050A1 (en) * 2015-02-27 2017-01-26 Tactual Labs Co. Alterable ground plane for touch surfaces
US20170038905A1 (en) * 2014-04-21 2017-02-09 Apple Inc. Apportionment of Forces for Multi-Touch Input Devices of Electronic Devices
US20170102788A1 (en) * 2015-10-12 2017-04-13 Denso International America, Inc. Detachable operational device

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966847A (en) * 1987-07-27 1990-10-30 Gary Stacey Recombinant DNA clones containing a broad host range gene from Bradyrhizobium japonicum
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5850690A (en) * 1995-07-11 1998-12-22 De La Rue Cartes Et Systemes Sas Method of manufacturing and assembling an integrated circuit card
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6329213B1 (en) * 1997-05-01 2001-12-11 Micron Technology, Inc. Methods for forming integrated circuits within substrates
US20080265383A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
US20080303157A1 (en) * 2007-06-08 2008-12-11 Ching-Tai Cheng High thermal conductivity substrate for a semiconductor device
US20080315398A1 (en) * 2007-06-22 2008-12-25 Hsing-Lun Lo Packaging substrate with embedded chip and buried heatsink
US8013434B2 (en) * 2007-06-22 2011-09-06 Light Ocean Technology Corp. Thin double-sided package substrate and manufacture method thereof
US8049244B2 (en) * 2008-09-25 2011-11-01 Lextar Electronics Corp. Package substrate and light emitting device using the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3338597A1 (en) * 1983-10-24 1985-05-02 GAO Gesellschaft für Automation und Organisation mbH, 8000 München DATA CARRIER WITH INTEGRATED CIRCUIT AND METHOD FOR PRODUCING THE SAME
DE3923023A1 (en) * 1989-07-12 1991-01-24 Siemens Ag UV CURABLE ADHESIVE FOR A SEMICONDUCTOR CHIP ASSEMBLY PROCESS
US6268648B1 (en) * 1997-04-30 2001-07-31 Hitachi Chemical Co., Ltd. Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
JP2004201285A (en) * 2002-12-06 2004-07-15 Murata Mfg Co Ltd Method of producing piezoelectric component and piezoelectric component
JP4082242B2 (en) * 2003-03-06 2008-04-30 ソニー株式会社 Element transfer method
JP4200285B2 (en) * 2003-04-02 2008-12-24 パナソニック株式会社 Circuit board manufacturing method
KR100510821B1 (en) * 2003-06-09 2005-08-30 한국전자통신연구원 Fabrication method using a temporary substrate of micro structures
TWI297537B (en) * 2006-06-26 2008-06-01 Univ Nat Cheng Kung Embedded metal heat sink for semiconductor device and method for manufacturing the same
CN100561696C (en) * 2007-03-01 2009-11-18 全懋精密科技股份有限公司 The structure of embedded with semi-conductor chip and method for making thereof
CN100565862C (en) * 2007-07-17 2009-12-02 南亚电路板股份有限公司 Embedded type chip substrate structure
US7824965B2 (en) * 2007-08-07 2010-11-02 Skyworks Solutions, Inc. Near chip scale package integration process
JP2009105366A (en) * 2007-10-03 2009-05-14 Panasonic Corp Semiconductor device and method of manufacturing semiconductor device as well as package of semiconductor device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966847A (en) * 1987-07-27 1990-10-30 Gary Stacey Recombinant DNA clones containing a broad host range gene from Bradyrhizobium japonicum
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5850690A (en) * 1995-07-11 1998-12-22 De La Rue Cartes Et Systemes Sas Method of manufacturing and assembling an integrated circuit card
US6329213B1 (en) * 1997-05-01 2001-12-11 Micron Technology, Inc. Methods for forming integrated circuits within substrates
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
US20080265383A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
US20080303157A1 (en) * 2007-06-08 2008-12-11 Ching-Tai Cheng High thermal conductivity substrate for a semiconductor device
US20080315398A1 (en) * 2007-06-22 2008-12-25 Hsing-Lun Lo Packaging substrate with embedded chip and buried heatsink
US8013434B2 (en) * 2007-06-22 2011-09-06 Light Ocean Technology Corp. Thin double-sided package substrate and manufacture method thereof
US8049244B2 (en) * 2008-09-25 2011-11-01 Lextar Electronics Corp. Package substrate and light emitting device using the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
FR2974942A1 (en) * 2011-05-06 2012-11-09 3D Plus PROCESS FOR PRODUCING RECONSTITUTED PLATES WITH THE MAINTENANCE OF CHIPS DURING THEIR ENCAPSULATION
WO2012152672A3 (en) * 2011-05-06 2013-05-30 3D Plus Method for producing reconstituted wafers with support of the chips during their encapsulation
KR20140106386A (en) * 2011-05-06 2014-09-03 3디 플러스 Method for producing reconstituted wafers with support of the chips during their encapsulation
US9111688B2 (en) 2011-05-06 2015-08-18 3D Plus Method for producing reconstituted wafers with support of the chips during their encapsulation
KR101965460B1 (en) 2011-05-06 2019-04-03 3디 플러스 Method for producing reconstituted wafers with support of the chips during their encapsulation
US20170038905A1 (en) * 2014-04-21 2017-02-09 Apple Inc. Apportionment of Forces for Multi-Touch Input Devices of Electronic Devices
US20170024050A1 (en) * 2015-02-27 2017-01-26 Tactual Labs Co. Alterable ground plane for touch surfaces
US20170102788A1 (en) * 2015-10-12 2017-04-13 Denso International America, Inc. Detachable operational device

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CN101986429A (en) 2011-03-16
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US20130256869A1 (en) 2013-10-03
TWI485825B (en) 2015-05-21
CN101986429B (en) 2013-12-04

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