US20050052906A1 - Row decoder in flash memory and erase method of flash memory cell using the same - Google Patents
Row decoder in flash memory and erase method of flash memory cell using the same Download PDFInfo
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- US20050052906A1 US20050052906A1 US10/968,687 US96868704A US2005052906A1 US 20050052906 A1 US20050052906 A1 US 20050052906A1 US 96868704 A US96868704 A US 96868704A US 2005052906 A1 US2005052906 A1 US 2005052906A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
Definitions
- the present disclosure relates to a flash memory device and an erase method thereof, and more particularly, to a row decoder in a flash memory and an erase method of the flash memory cell using the same.
- an insulating film having a structure on which an ONO insulating film being a dielectric film between a floating gate and a control gate, i.e., an oxide film, a silicon nitride film and an oxide film are sequentially stacked be reduced. Meanwhile, as more faster erase speed is required, it is also required that an application voltage during an erasing operation be more high.
- FIG. 1 illustrates a structure of the flash memory cell.
- the flash memory cell includes a source region 104 formed in a semiconductor substrate 100 , and a drain region 102 formed with a channel region (not shown) intervened between the source region 104 and the drain region 102 .
- a floating gate 108 is formed over the channel region with a tunnel oxide film 106 intervened between them.
- a control gate 112 is formed over the floating gate 108 with a dielectric film 110 intervened between them.
- An erasing operation of the flash memory cell is performed by discharging charges (electrons) from the floating gate 108 to the semiconductor substrate 100 by means of F-N (Fowler-Nordheim) tunneling.
- a common erase method includes applying a negative high voltage (for example, ⁇ 8V) to the control gate 112 and applying an adequate voltage (for example, +8V) to the semiconductor substrate 100 .
- a negative high voltage for example, ⁇ 8V
- an adequate voltage for example, +8V
- a strong electric field is formed between the control gate 112 and the semiconductor substrate 100 by the above method. Due to this, F-N tunneling is generated so that the charges (electrons) within the floating gate 108 are discharged toward the semiconductor substrate 100 .
- the potential difference between the control gate 112 and the semiconductor substrate 100 or source/drain 104 / 102 becomes about 16V since ⁇ 8V is applied to the control gate 112 and +8V is applied to the semiconductor substrate 100 .
- This potential difference is distributed by the floating gate 108 , so that the voltage applied between the control gate, 112 and the floating gate 108 proportional to the capacitance ratio of the device is about 8V.
- the breakdown voltage of the dielectric film 110 between the two gates 112 and 108 becomes 14V, the insulating strength of the ONO insulating film 110 can sufficiently cope with the potential difference organized upon erasing.
- the floating gate 108 As shown in FIG. 2 , however, if the floating gate 108 is connected to a contact 1114 (see ‘A’ in FIG. 2 ), it represents a characteristic of a trans-conductance cell (low Gm Cell) in which current flowing with the voltage of the floating gate 108 and the voltage applied to the drain 102 became equipotential is very low.
- the yield loss of this cell is improved by a column that was prepared in advance upon designing, i.e., a repair scheme (see FIG. 3 ) replaced by a redundancy cell.
- the voltage applied upon erasing is simultaneously applied to a failed cell and a repaired cell, the voltage applied between the control gate 112 and the floating gate 108 thus becomes about 15.5V, as shown in FIG. 2 .
- the floating gate 108 when the floating gate 108 is connected to the contact 114 , as the voltage of the floating gate 108 and the voltage applied to the drain 102 are the same voltage, the floating gate 108 has a voltage of 7.5V. Also, the result is that a voltage of about 15.5V is applied to the dielectric film 110 between the floating gate 108 and the control gate 112 . Due to the above, an insulating break phenomenon may happen.
- a row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal.
- the row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
- an erasing method in a flash memory device comprising applying an erasing voltage to a word line of a redundant row during an erasing operation, and applying a non-erasing voltage to a word line of a row having a failed cell during the erasing operation.
- FIG. 1 illustrates a structure of the flash memory cell
- FIG. 2 illustrates a structure of the flash memory cell in which a fail bit is generated
- FIG. 3 illustrates a conventional flash memory cell for which column redundancy repair is performed
- FIG. 4 is a circuit diagram of a flash memory device for which row redundancy repair is performed
- FIG. 5 is a circuit diagram of a row decoder according to a preferred embodiment of the present invention.
- FIG. 6 illustrates a flash memory cell in which a fail bit occurred, to which the ground voltage is applied to the gate thereof using an erase method according to the present invention.
- the potential difference that gives stress to the ONO insulating film is the potential difference between the control gate and the floating gate upon erasing in the flash memory cell.
- a method of keeping a voltage of the control gate sharing the fail bit that may cause break of the ONO insulating film 0V upon erase operation is utilized.
- FIG. 4 is a circuit diagram of a flash memory device for which row redundancy repair is performed.
- the present invention employs row redundancy without existing column redundancy in order to repair low trans-conductance 1 bit fail.
- Gm trans-conductance
- row repair is performed without performing column repair. Thereafter, if an erase operation such as cycling, etc. is to be performed, the potential difference applied between the floating gate and the control gate in the cell in which the fail bit happens is made about 7.5V being a voltage that does not far reach the insulating break voltage of the ONO insulating film, by applying ⁇ 8V to a word line in which a fail bit did not occur and 0V to a word line in which the fail bit occurred using the row decoder according to a preferred embodiment of the present invention. Therefore, it is possible to prohibit an insulating break phenomenon of the ONO insulating film, which may happen upon erasing such as cycling, etc.
- FIG. 5 is a circuit diagram of a row decoder according to a preferred embodiment of the present invention.
- the row decoder RD comprises three transistors including a PMOS transistor PT 1 , a first NMOS transistor NT 1 and a second NMOS transistor NT 2 , and a switching means NT 3 for controlling a negative voltage applied to a word line WL during the erasing operation.
- the output terminal of a row decoder RD is transferred to the word line VVL.
- the PMOS transistor PT 1 and the first NMOS transistor NT 1 are serially connected between a first power supply terminal (Vpp) and a second node N 2 . Also, the PMOS transistor PT 1 and the first NMOS transistor NT 1 are driven by a first input signal (Vinput).
- the PMOS transistor PT 1 is connected between the first power supply terminal (Vpp) and the first node N 1 .
- the first NMOS transistor NT 1 is connected between the first node N 1 and the second node N 2 .
- the PMOS transistor PT 1 and the first NMOS transistor NT 1 are commonly driven by the first input signal (Vinput).
- the second NMOS transistor NT 2 is connected between the second node N 2 and the ground terminal Vss.
- the second NMOS transistor NT 2 is driven by the second input signal (Vdcharge).
- a switching means NT 3 is connected between the second node N 2 and a second power supply terminal Veei.
- the switching means NT 3 is driven by a third input signal (Vsw).
- the switching means NT 3 may be an NMOS transistor.
- the PMOS transistor PT 1 is turned off and the first NMOS transistor NT 1 is turned on.
- the second input signal (Vdcharge) is the High signal, the second NMOS transistor NT 2 is turned on. Due to this, the potential of the second node N 2 becomes a ground voltage level, so that 0V being the voltage of the ground terminal Vss is outputted to the word line WL.
- the first input signal (Vinput) is a High signal
- the second input signal (Vdcharge) is a Low signal and the second NMOS transistor NT 2 is thus turned off, and the switching means NT 3 is turned on
- the potential of the second node N 2 thus becomes the level of the second power supply terminal Veei.
- a negative voltage is thus outputted from the second power supply terminal Veei to the word line.
- the third input signal (Vsw) is a High signal when the switching means NT 3 is an NMOS transistor, the switching means NT 3 is turned on.
- a Low signal is applied to the first input signal (Vinput) to make the PMOS transistor PT 1 turned on and make the first NMOS transistor NT 1 turned off.
- a positive voltage of the first power supply terminal Vpp is thus outputted to the word line WL.
- 0V being the ground voltage is applied to the word line WL to which the fail bit is connected.
- the power supply voltage (Vcc) is applied as the first input signal (Vinput) and the second input signal (Vdcharge), and ⁇ 8V is also applied as the third input signal (Vsw).
- Vcc the power supply voltage
- ⁇ 8V is also applied as the third input signal (Vsw).
- the PMOS transistor PT 1 is turned off
- the first NMOS transistor NT 1 is turned on
- the second NMOS transistor NT 2 is turned on and the switching means NT 3 is turned off
- the potential of the second node N 2 becomes the ground voltage level.
- 0V being the ground voltage is thus outputted to the word line WL.
- a voltage of ⁇ 8V is applied to the second power supply terminal Veei.
- ⁇ 8V being the voltage of the second power supply terminal Veei is applied to the word line WL where the fail bit did not occur.
- the power supply voltage (Vcc) is applied as the first input signal (Vinput) and the third input signal (Vsw) and ⁇ 8V is applied as the second input signal (Vdcharge).
- the PMOS transistor PT 1 is turned off, the first NMOS transistor NT 1 is turned on, the second NMOS transistor NT 2 is turned off and the switching means NT 3 is turned on. Accordingly, as the potential of the second node N 2 becomes the voltage level of the second power supply terminal Veei, ⁇ 8V being the voltage of the second power supply terminal Veei is outputted to the word line WL.
- the present invention has an advantageous effect that it can prevent an insulating break phenomenon of the ONO insulating film that may happen during an erasing operation such as cycling, etc.
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Abstract
Description
- This application is a continuation application of U.S. patent application Ser. No. 10/614,229, filed on Jul. 7, 2003, entitled “ROW DECODER IN FLASH MEMORY AND ERASE METHOD OF FLASH MEMORY CELL USING THE SAME,” which is hereby incorporated by reference herein in its entirety for all purposes.
- 1. Field of the Invention
- The present disclosure relates to a flash memory device and an erase method thereof, and more particularly, to a row decoder in a flash memory and an erase method of the flash memory cell using the same.
- 2. Background of the Related Art
- As the degree of integration in the flash memory device is increased, it is required that the thickness of an insulating film having a structure on which an ONO insulating film being a dielectric film between a floating gate and a control gate, i.e., an oxide film, a silicon nitride film and an oxide film are sequentially stacked be reduced. Meanwhile, as more faster erase speed is required, it is also required that an application voltage during an erasing operation be more high.
-
FIG. 1 illustrates a structure of the flash memory cell. - Referring to
FIG. 1 , the flash memory cell includes asource region 104 formed in asemiconductor substrate 100, and adrain region 102 formed with a channel region (not shown) intervened between thesource region 104 and thedrain region 102. Afloating gate 108 is formed over the channel region with atunnel oxide film 106 intervened between them. Further, acontrol gate 112 is formed over thefloating gate 108 with adielectric film 110 intervened between them. An erasing operation of the flash memory cell is performed by discharging charges (electrons) from thefloating gate 108 to thesemiconductor substrate 100 by means of F-N (Fowler-Nordheim) tunneling. A common erase method includes applying a negative high voltage (for example, −8V) to thecontrol gate 112 and applying an adequate voltage (for example, +8V) to thesemiconductor substrate 100. At this time, thedrain region 102 is kept to be high impedance or floated in order to maximize the effect of erasing. A strong electric field is formed between thecontrol gate 112 and thesemiconductor substrate 100 by the above method. Due to this, F-N tunneling is generated so that the charges (electrons) within thefloating gate 108 are discharged toward thesemiconductor substrate 100. - As described above, conventionally, during the erasing operation, the potential difference between the
control gate 112 and thesemiconductor substrate 100 or source/drain 104/102 becomes about 16V since −8V is applied to thecontrol gate 112 and +8V is applied to thesemiconductor substrate 100. This potential difference is distributed by thefloating gate 108, so that the voltage applied between the control gate, 112 and thefloating gate 108 proportional to the capacitance ratio of the device is about 8V. As the breakdown voltage of thedielectric film 110 between the twogates ONO insulating film 110 can sufficiently cope with the potential difference organized upon erasing. - As shown in
FIG. 2 , however, if thefloating gate 108 is connected to a contact 1114 (see ‘A’ inFIG. 2 ), it represents a characteristic of a trans-conductance cell (low Gm Cell) in which current flowing with the voltage of thefloating gate 108 and the voltage applied to thedrain 102 became equipotential is very low. The yield loss of this cell is improved by a column that was prepared in advance upon designing, i.e., a repair scheme (seeFIG. 3 ) replaced by a redundancy cell. However, as the voltage applied upon erasing is simultaneously applied to a failed cell and a repaired cell, the voltage applied between thecontrol gate 112 and thefloating gate 108 thus becomes about 15.5V, as shown inFIG. 2 . This is more than the insulating strength of the ONO insulating film and a fail is thus caused during the cycling. In other words, upon erasing, thesource 104 and thedrain 102 are floated, −8V is applied to thecontrol gate 112 and +8V is applied to thesemiconductor substrate 100. At this time, as thesemiconductor substrate 100 is a P type and thedrain 102 is an N type, a forward bias is applied between thesemiconductor substrate 100 and thedrain 102, which serves as a P-N diode. Accordingly, the result is that a voltage of about 7.5V is applied to thedrain 102 considering voltage drop of the P-N diode. Therefore, when thefloating gate 108 is connected to thecontact 114, as the voltage of thefloating gate 108 and the voltage applied to thedrain 102 are the same voltage, thefloating gate 108 has a voltage of 7.5V. Also, the result is that a voltage of about 15.5V is applied to thedielectric film 110 between thefloating gate 108 and thecontrol gate 112. Due to the above, an insulating break phenomenon may happen. - In one aspect, a row decoder in a flash memory is provided. The row decoder comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
- In another aspect, an erasing method in a flash memory device, the flash memory device including a row having a failed cell and a redundant row, is provided. The method comprises applying an erasing voltage to a word line of a redundant row during an erasing operation, and applying a non-erasing voltage to a word line of a row having a failed cell during the erasing operation.
- It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The above and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings, in which:
-
FIG. 1 illustrates a structure of the flash memory cell; -
FIG. 2 illustrates a structure of the flash memory cell in which a fail bit is generated; -
FIG. 3 illustrates a conventional flash memory cell for which column redundancy repair is performed; -
FIG. 4 is a circuit diagram of a flash memory device for which row redundancy repair is performed; -
FIG. 5 is a circuit diagram of a row decoder according to a preferred embodiment of the present invention; and -
FIG. 6 illustrates a flash memory cell in which a fail bit occurred, to which the ground voltage is applied to the gate thereof using an erase method according to the present invention. - Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, in which like reference numerals are used to identify the same or similar parts.
- In the present invention, the potential difference that gives stress to the ONO insulating film is the potential difference between the control gate and the floating gate upon erasing in the flash memory cell. Thus a method of keeping a voltage of the control gate sharing the fail bit that may cause break of the ONO insulating film 0V upon erase operation is utilized.
-
FIG. 4 is a circuit diagram of a flash memory device for which row redundancy repair is performed. Referring now toFIG. 4 , the present invention employs row redundancy without existing column redundancy in order to repair low trans-conductance 1 bit fail. - If there is a low Gm (trans-conductance) cell as in
FIG. 4 , row repair is performed without performing column repair. Thereafter, if an erase operation such as cycling, etc. is to be performed, the potential difference applied between the floating gate and the control gate in the cell in which the fail bit happens is made about 7.5V being a voltage that does not far reach the insulating break voltage of the ONO insulating film, by applying −8V to a word line in which a fail bit did not occur and 0V to a word line in which the fail bit occurred using the row decoder according to a preferred embodiment of the present invention. Therefore, it is possible to prohibit an insulating break phenomenon of the ONO insulating film, which may happen upon erasing such as cycling, etc. - The operation of the row decoder for applying −8V to a word line having no any fail bit and 0V to a word line to which a fail bit is connected, will be below described.
-
FIG. 5 is a circuit diagram of a row decoder according to a preferred embodiment of the present invention. - Referring to
FIG. 5 , the row decoder RD comprises three transistors including a PMOS transistor PT1, a first NMOS transistor NT1 and a second NMOS transistor NT2, and a switching means NT3 for controlling a negative voltage applied to a word line WL during the erasing operation. The output terminal of a row decoder RD is transferred to the word line VVL. The PMOS transistor PT1 and the first NMOS transistor NT1 are serially connected between a first power supply terminal (Vpp) and a second node N2. Also, the PMOS transistor PT1 and the first NMOS transistor NT1 are driven by a first input signal (Vinput). In other words, the PMOS transistor PT1 is connected between the first power supply terminal (Vpp) and the first node N1. The first NMOS transistor NT1 is connected between the first node N1 and the second node N2. The PMOS transistor PT1 and the first NMOS transistor NT1 are commonly driven by the first input signal (Vinput). Further, the second NMOS transistor NT2 is connected between the second node N2 and the ground terminal Vss. The second NMOS transistor NT2 is driven by the second input signal (Vdcharge). A switching means NT3 is connected between the second node N2 and a second power supply terminal Veei. The switching means NT3 is driven by a third input signal (Vsw). The switching means NT3 may be an NMOS transistor. - The operation of the row decoder RD according to a preferred embodiment of the present invention will be below described.
- If the first input signal (Vinput) is a High signal, the PMOS transistor PT1 is turned off and the first NMOS transistor NT1 is turned on. At this time, if the second input signal (Vdcharge) is the High signal, the second NMOS transistor NT2 is turned on. Due to this, the potential of the second node N2 becomes a ground voltage level, so that 0V being the voltage of the ground terminal Vss is outputted to the word line WL.
- Further, if the first input signal (Vinput) is a High signal, the second input signal (Vdcharge) is a Low signal and the second NMOS transistor NT2 is thus turned off, and the switching means NT3 is turned on, the potential of the second node N2 thus becomes the level of the second power supply terminal Veei. A negative voltage is thus outputted from the second power supply terminal Veei to the word line. If the third input signal (Vsw) is a High signal when the switching means NT3 is an NMOS transistor, the switching means NT3 is turned on.
- Meanwhile, in a program and read mode, a Low signal is applied to the first input signal (Vinput) to make the PMOS transistor PT1 turned on and make the first NMOS transistor NT1 turned off. A positive voltage of the first power supply terminal Vpp is thus outputted to the word line WL.
- An erasing operation using the row decoder according to a preferred embodiment of the present invention will be below described in detail.
- For the erasing operation such as cycling, etc., a voltage is applied to respective terminals, respectively, using the row decoder according to a preferred embodiment of the present invention.
TABLE 1 Word Line Having Fail Word Line Having No Fail Bit Connected Thereto Bit Vinput Vcc Vcc Veei −8 V −8 V Vsw −8 V Vcc Vdcharge Vcc −8 V - In the erasing mode, 0V being the ground voltage is applied to the word line WL to which the fail bit is connected. For this, the power supply voltage (Vcc) is applied as the first input signal (Vinput) and the second input signal (Vdcharge), and −8V is also applied as the third input signal (Vsw). At this time, as the PMOS transistor PT1 is turned off, the first NMOS transistor NT1 is turned on, the second NMOS transistor NT2 is turned on and the switching means NT3 is turned off, the potential of the second node N2 becomes the ground voltage level. 0V being the ground voltage is thus outputted to the word line WL. Meanwhile, a voltage of −8V is applied to the second power supply terminal Veei. −8V being the voltage of the second power supply terminal Veei is applied to the word line WL where the fail bit did not occur. For this, the power supply voltage (Vcc) is applied as the first input signal (Vinput) and the third input signal (Vsw) and −8V is applied as the second input signal (Vdcharge). At this time, the PMOS transistor PT1 is turned off, the first NMOS transistor NT1 is turned on, the second NMOS transistor NT2 is turned off and the switching means NT3 is turned on. Accordingly, as the potential of the second node N2 becomes the voltage level of the second power supply terminal Veei, −8V being the voltage of the second power supply terminal Veei is outputted to the word line WL.
- As such, as different voltages (−8V and 0V) are each applied to the word line having no fail bit and the word line to which the fail bit is connected using the row decoder of the present invention, the potential difference applied between the floating gate and the control gate become about 7.5V for both the cell in which the fail bit happened and the normal cell. Therefore, it is possible to prohibit an insulating break phenomenon of the ONO insulating film that may happen during the easing operation such as cycling, etc. In other words, in the prior art, −8V is supposed to be applied to all the word lines including the gate, to which the fail bits are connected. In the present invention, however, −8V is applied all the word lines having no fail bits but 0V is applied to the word lines to which the fail bits are connected.
- Therefore, as shown in
FIG. 6 , even though a floatinggate 208 is connected to a contact 214 (see ‘A’ inFIG. 6 ), the potential difference applied between a floatinggate 208 and acontrol gate 212 becomes about 7.5V, which far less amounts to the insulating break voltage of theONO insulating film 210. Accordingly, it is possible to prevent the insulating break phenomenon of theONO insulating film 210 that may happen during the erasing operation such as cycling, etc. and secure reliability of the flash memory device. - As described above, according to the present invention, different voltages (−8V and 0V) are each applied to the word line having no fail bit and the word line to which the fail bit is connected, using the row decoder of the present invention. Due to this, the potential difference applied between the floating gate and the control gate becomes a voltage that far less amounts to an insulating break voltage of an ONO insulating film for the cell in which the fail bit occurred and the normal cell. Therefore, the present invention has an advantageous effect that it can prevent an insulating break phenomenon of the ONO insulating film that may happen during an erasing operation such as cycling, etc.
- The forgoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.
Claims (20)
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US10/968,687 US7099198B2 (en) | 2002-07-18 | 2004-10-19 | Row decoder in flash memory and erase method of flash memory cell using the same |
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KR10-2002-0042155A KR100474200B1 (en) | 2002-07-18 | 2002-07-18 | Row decorder of flash memory and erasing method of flash memory cell using the same |
US10/614,229 US6819597B2 (en) | 2002-07-18 | 2003-07-07 | Row decoder in flash memory and erase method of flash memory cell using the same |
US10/968,687 US7099198B2 (en) | 2002-07-18 | 2004-10-19 | Row decoder in flash memory and erase method of flash memory cell using the same |
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KR100634155B1 (en) * | 1999-06-14 | 2006-10-16 | 삼성전자주식회사 | A wordline selection circuit of flash memory device |
KR100645046B1 (en) | 2004-10-07 | 2006-11-10 | 삼성전자주식회사 | Row decoder circuit for use in non-volatile memory device |
ITMI20050868A1 (en) * | 2005-05-13 | 2006-11-14 | St Microelectronics Srl | ROW DECODING CIRCUIT |
TWI393141B (en) * | 2008-09-03 | 2013-04-11 | Elan Microelectronics Corp | A column decoder that can be used to speed up the read speed in a number of programmable flash memories |
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KR20000027296A (en) * | 1998-10-27 | 2000-05-15 | 김영환 | Row decoder circuit for flash memory cell |
KR100476889B1 (en) * | 2002-04-04 | 2005-03-17 | 삼성전자주식회사 | Wordline decoder of split-gate flash memory |
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2002
- 2002-07-18 KR KR10-2002-0042155A patent/KR100474200B1/en active IP Right Grant
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2003
- 2003-07-07 US US10/614,229 patent/US6819597B2/en not_active Expired - Lifetime
- 2003-07-15 JP JP2003274800A patent/JP2004055134A/en active Pending
- 2003-07-17 DE DE10332590A patent/DE10332590B4/en not_active Expired - Fee Related
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US20050285720A1 (en) * | 2000-04-14 | 2005-12-29 | Cope Leonard D | Power line communication apparatus and method of using the same |
US20060145834A1 (en) * | 2000-04-14 | 2006-07-06 | Berkman William H | Automated meter reading power line communication system and method |
US20080018491A1 (en) * | 2000-04-14 | 2008-01-24 | Berkman William H | Automated Meter Reading Communication System And Method |
US20050169056A1 (en) * | 2002-12-10 | 2005-08-04 | Berkman William H. | Power line communications device and method |
US20050200459A1 (en) * | 2002-12-10 | 2005-09-15 | White Melvin J.Ii | Power line communication apparatus and method of using the same |
US20090309862A1 (en) * | 2008-06-17 | 2009-12-17 | Zhifeng Zhan | Data driver and display apparatus having the same |
CN101609654A (en) * | 2008-06-17 | 2009-12-23 | 三星电子株式会社 | Data driver and display device |
US8599188B2 (en) * | 2008-06-17 | 2013-12-03 | Samsung Display Co., Ltd. | Data driver and display apparatus having the same |
Also Published As
Publication number | Publication date |
---|---|
JP2004055134A (en) | 2004-02-19 |
US6819597B2 (en) | 2004-11-16 |
KR100474200B1 (en) | 2005-03-10 |
US7099198B2 (en) | 2006-08-29 |
KR20040008516A (en) | 2004-01-31 |
US20040027878A1 (en) | 2004-02-12 |
DE10332590B4 (en) | 2011-12-08 |
DE10332590A1 (en) | 2004-03-25 |
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