US10707779B2 - Three-phase switch architecture - Google Patents

Three-phase switch architecture Download PDF

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US10707779B2
US10707779B2 US15/855,251 US201715855251A US10707779B2 US 10707779 B2 US10707779 B2 US 10707779B2 US 201715855251 A US201715855251 A US 201715855251A US 10707779 B2 US10707779 B2 US 10707779B2
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phase current
phase
current inverter
switching
substrate
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Guillaume LEFEVRE
Luis-Gabriel Alves Rodrigues
Jean-Paul Ferrieux
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/383—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
    • H05K7/1427—Housings
    • H05K7/1432—Housings specially adapted for power drive units or power converters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
    • H05K7/1427—Housings
    • H05K7/1432—Housings specially adapted for power drive units or power converters
    • H05K7/14329—Housings specially adapted for power drive units or power converters specially adapted for the configuration of power bus bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the present disclosure generally relates to electronic power conversion circuits, and more particularly to the forming of a three-phase current inverter.
  • the present disclosure more particularly relates to the architecture of a static power converter intended for applications of current inverter type (direct current DC-to-alternating current AC).
  • a three-phase DC-to-AC static power converter is generally based on two sets of three (or three sets of two) electronic switches, typically MOS power transistors (MOSFET) associated with diodes.
  • MOSFET MOS power transistors
  • Voltage inverters where the transistors are directly series-connected two by two and each transistor is equipped with a diode in antiparallel, can be distinguished from current inverters, where each transistor is series-connected with a diode to form a switch which is bidirectional in terms of voltage and unidirectional in terms of current.
  • the present disclosure more specifically targets current inverters.
  • the transistors and the diodes are generally formed individually in the form of discrete components or bare chips.
  • Each controlled switching switch (transistor) or spontaneous switching switch (diode) is manufactured in the form of an individual chip based on semiconductor materials and the different chips are then assembled on a substrate (printed circuit board—PCB, direct bond copper—DBC, insulated metal substrate—IMS, for example, a metal substrate at the surface of a ceramic, etc.) and then electrically connected to carry out the three-phase current inverter function.
  • An embodiment overcomes all or part of the disadvantages of three-phase current inverters.
  • An embodiment provides a solution enabling to homogenize the operating stress between the different switches of a three-phase current inverter.
  • An embodiment provides a solution particularly adapted to the forming of a current inverter.
  • an embodiment provides a three-phase switching unit comprising three identical switching cells, each comprising at least one first electrically-controlled switch series-connected with at least one second spontaneous conduction switch, wherein the cells are arranged, around a conductive central area of a substrate, with a symmetry of revolution of order 3.
  • the spontaneous conduction switches are assembled in the conductive central area with a symmetry of revolution of order 3.
  • the central area also has a symmetry of revolution of order 3.
  • the switch(es) of the switching cells are arranged on conductive peripheral areas of the substrate having a symmetry of revolution of order 3.
  • the central area and the peripheral areas approximately form a Y.
  • the conductive central area supports no component.
  • the conductive central area has a substantially hexagonal shape.
  • said first switch(es) are transistors.
  • said spontaneous conduction switch(es) are diodes or MOS transistors.
  • each switch is welded to a conductive area by a back-side metallization of a chip made of semiconductor materials, defining an electrode of the switch.
  • the conductive central area defines a terminal of electric interconnection of the three cells.
  • the substrate is an insulated metal substrate, preferably on ceramic.
  • An embodiment provides a three-phase current inverter, comprising two units.
  • the cells of the two units are electrically connected two by two, the interconnection nodes defining three phase terminals.
  • At least one current inverter At least one current inverter.
  • FIG. 1 is a simplified representation in the form of blocks of a three-phase inverter of the type to which the described embodiments apply;
  • FIG. 2 shows an electrical scheme of a three-phase current inverter
  • FIG. 3 is a simplified representation of a usual architecture of a switching unit of a three-phase current inverter
  • FIG. 4 very schematically shows an embodiment of an architecture of a first unit of a three-phase current inverter
  • FIG. 5 very schematically shows an embodiment of an architecture of a second three-phase current inverter unit
  • FIG. 6 shows the electrical scheme of a three-phase current inverter formed with the units of FIGS. 4 and 5 ;
  • FIG. 7 shows a variation of the embodiment of FIG. 4 ;
  • FIG. 8 shows a variation of the embodiment of FIG. 5 ;
  • FIG. 9 is a very simplified representation of a semiconductor circuit chip forming a vertical power transistor
  • FIG. 10 is a very simplified representation of a semiconductor circuit chip forming a vertical diode
  • FIG. 11 very schematically shows another embodiment of an architecture of a first unit of a three-phase current inverter
  • FIG. 12 very schematically shows another embodiment of an architecture of a second unit of a three-phase current inverter
  • FIG. 13 shows the electrical scheme of a three-phase current inverter formed with the units of FIGS. 11 and 12 ;
  • FIG. 14 is a simplified representation of a variation of the embodiments of FIGS. 11 and 12 ;
  • FIG. 15 is a very simplified partial representation of another alternative embodiment.
  • Document EP 2 367 281 describes a three-phase current inverter of the type to which the described embodiments apply.
  • Each switching cell comprises a controllable switch (a transistor) in series with a diode.
  • Six cells are series-connected, two by two, between two terminals of application of a DC voltage.
  • the junction points of the series associations define the three phases of the three-phase voltage.
  • the diode of a cell conducts at the same time as the switch which is series-connected therewith.
  • the cells are paired two by two in series and three pairs of series-connected cells are connected in parallel, the junction points of each pair defining a phase.
  • FIG. 1 is a simplified representation in the form of blocks of three-phase current inverter of the type to which the described embodiments apply.
  • a three-phase current inverter 1 The function of a three-phase current inverter 1 is to convert a DC current Idc flowing between two input terminals 11 and 12 into a three-phase AC current Iac on output terminals 15 , 16 , 17 , and 19 .
  • Terminals 15 , 16 , and 17 represent the terminals of the different phases and terminal 19 represents the optional neutral terminal.
  • FIG. 2 shows an electrical scheme of a three-phase current inverter.
  • Inverter 1 comprises two switching units 2 h and 2 l having similar inner structures.
  • Each unit 2 h , 2 l comprises three switching cells, cyclically implying two of the three identical switches, respectively 3 h - 1 , 3 h - 2 , 3 h - 3 and 3 l - 1 , 3 l - 2 , 3 l - 3 , each formed of a MOS transistor (with an N channel) respectively Mh- 1 , Mh- 2 , Mh- 3 , Ml- 1 , Ml- 2 , Ml- 3 , in series with a diode, respectively Dh- 1 , Dh- 2 , Dh- 3 , Dl- 1 , Dl- 2 , Dl- 3 .
  • the drains of transistors Mh- 1 , Mh- 2 , and Mh- 3 are interconnected to terminal 11 of application of a first potential of current source Idc.
  • the sources of transistors Mh- 1 , Mh- 2 , and Mh- 3 are respectively connected to the anodes of diodes Dh- 1 , Dh- 2 , and Dh- 3 , having their cathodes respectively connected to terminals 15 , 16 , and 17 of the three AC voltage phases.
  • the drains of transistors Ml- 1 , Ml- 2 , Ml- 3 are respectively connected to terminals 15 , 16 , and 17 .
  • the sources of transistors Ml- 1 , Ml- 2 , and Ml- 3 are respectively connected to the anodes of diodes Dl- 1 , Dl- 2 , and Dl- 3 , which have their cathodes interconnected to terminal 12 of application of a second potential of current source Idc.
  • the gates of transistors Mh- 1 , Mh- 2 , Mh- 3 , Ml- 1 , Ml- 2 , Ml- 3 are individually connected to a control circuit 4 (CTRL) in charge of organizing the switching of the different cells to generate a three-phase AC current Iac.
  • CTRL control circuit 4
  • a current inverter In a current inverter, the current flow successively takes place in each of the switching cells (for example, 3 h - 1 / 3 h - 2 , 3 h - 1 / 3 h - 3 , 3 h - 2 / 3 h - 3 ) of a first unit jointly with each of the switching cells (for example, 3 l - 1 / 3 l - 2 , 3 l - 1 / 3 l - 3 , 3 l - 2 / 3 l - 3 ) of the other unit.
  • the 9 combinations enabling to generate the three-phase AC current with the appropriate phase shifts are thus obtained.
  • the control of such a current inverter is usual.
  • the high or low unit of the three-phase current inverter to which the element identified by the reference number belongs is identified by letter “h” or “l”. Further, the references are completed with “ ⁇ ”, “ ⁇ 2”, or “ ⁇ 3” to identify the switching branch (representing the phase of the AC voltage) containing the element identified by the reference number. Such reference complements may be omitted when no distinction needs to be made for the needs of the disclosure.
  • FIG. 3 is a simplified representation of a usual architecture of a switching unit of a three-phase current inverter.
  • the transistors and diodes are manufactured in the form of vertical components made of semiconductor materials assembled at the surface of an insulated metal substrate 51 .
  • a high unit 2 h having its diodes and transistors inverted with respect to FIG. 2 , is considered.
  • the anodes of diodes Dh- 1 , Dh- 2 , Dh- 3 are thus interconnected to terminal 11 .
  • the three diodes Dh- 1 , Dh- 2 and Dh- 3 are individually formed on P-type substrates and the cathodes are formed by N-type regions in the substrates.
  • the anode electrodes are generally made in the form of a back-side metallization of the chips forming diodes Dh- 1 , Dh- 2 , Dh- 3 and are placed on a conductive area 53 (typically, a metal conductive plane) of insulated metal substrate 51 .
  • An electrically-conductive area of the insulated metal substrate defining terminal 11 is connected to plane 53 by one or a plurality of wires 55 .
  • Transistors Mh- 1 , Mh- 2 , and Mh- 3 are also individually manufactured in the form of chips 56 - 1 , 56 - 2 , and 56 - 3 .
  • each transistor generally made in the form of a back-side metallization of the chip, is placed on a conductive area 58 - 1 , 58 - 2 , and 58 - 3 , respectively, of insulated metal substrate 51 .
  • the cathode electrodes corresponding to front-side metallizations 52 - 1 , 52 - 2 , and 52 - 3 of the chips forming diodes Dh- 1 , Dh- 2 , and Dh- 3 are respectively electrically connected to areas 58 - 1 , 58 - 2 , and 58 - 3 by one or a plurality of wires 57 - 1 , 57 - 2 , 57 - 3 .
  • each transistor Mh- 1 , Mh- 2 , Mh- 3 corresponds to a front-side metal contact, respectively 59 - 1 , 59 - 2 , 59 - 3 , connected by one or a plurality of wires 60 - 1 , 60 - 2 , 60 - 3 to a contact of the insulated metal substrate, defining a terminal, respectively 15 , 16 , 17 .
  • the gates of transistors Mh- 1 , Mh- 2 , and Mh- 3 are continued on the front side of the chips by contacts 62 - 1 , 62 - 2 and 62 - 3 , individually connected by one or a plurality of wires 63 - 1 , 63 - 2 , 63 - 3 , to respective contacts of insulated metal substrate 51 , defining terminals 64 - 1 , 64 - 2 , 64 - 3 intended to be connected to control circuit 4 ( FIG. 2 ).
  • An architecture such as illustrated in FIG. 3 where the chips are placed next to one another generates functional thermal and electrical stress, different according to the operating phases, which adversely affects its reliability.
  • the structure substantially has a symmetry of revolution of 120°.
  • FIG. 4 very schematically shows an embodiment of an architecture of a first unit 2 h of a three-phase current inverter.
  • FIG. 5 very schematically shows an embodiment of an architecture of a second unit 2 l of a three-phase current inverter.
  • a star- or Y-shaped structure where, for each unit 2 h , 2 l , the three diodes of the cells are arranged at the center of the structure and the transistors are arranged in the branches of the Y, is considered.
  • the diodes and transistors are manufactured individually in the form of discrete chips of vertical components made of semiconductor materials, and are assembled on an insulated metal substrate 51 , called 51 h in FIG. 4 for first unit 2 h and 51 l in FIG. 5 for second unit 2 l .
  • a metallized central area 53 h ( FIG. 4 ), 53 l ( FIG. 5 ) has a shape with a symmetry of revolution of order 3 in the plane with respect to its center, for example, a hexagonal shape.
  • each area 58 is rectangular and has an edge parallel to a side of the hexagon 53 around which it is provided, a free end of hexagonal area 53 separating two sides each having an area 58 opposite thereto.
  • the cathode electrodes corresponding to front-side metallizations 52 h - 1 , 52 h - 2 , and 52 h - 3 of the chips forming diodes Dh- 1 , Dh- 2 , and Dh- 3 are respectively electrically connected to areas 58 h - 1 , 58 h - 2 , and 58 h - 3 by one or a plurality of wires 57 h - 1 , 57 h - 2 , 57 h - 3 .
  • each transistor Mh- 1 , Mh- 2 , Mh- 3 corresponds to a front-side metal contact, respectively 59 h - 1 , 59 h - 2 , 59 h - 3 connected by one or a plurality of wires 60 h - 1 , 60 h - 2 , 60 h - 3 to a contact of the printed circuit, defining a terminal, respectively 15 , 16 , 17 .
  • the gates of transistors Mh- 1 , Mh- 2 , and Mh- 3 are continued on the front side of chips 56 by contacts 62 h - 1 , 62 h - 2 , 62 h - 3 .
  • These contacts are individually connected by one or a plurality of wires 63 h - 1 , 63 h - 2 , 63 h - 3 to respective contacts of the printed circuit, defining terminals 64 h - 1 , 64 h - 2 , 64 h - 3 , intended to be connected to control circuit 4 ( FIG. 2 ).
  • the anode electrodes corresponding to front-side metallizations 54 l - 1 , 54 l - 2 , and 54 l - 3 of the chips forming diodes Dl- 1 , Dl- 2 , and Dl- 3 are respectively electrically connected, by one or a plurality of wires 57 l - 1 , 57 l - 2 , 57 l - 3 , to the respective source electrodes of transistors Ml- 1 , Ml- 2 , and Ml- 3 corresponding to a front-side metal contact, respectively 59 l - 1 , 59 l - 2 , 59 l - 3 , of the chips forming the transistors.
  • Areas 58 l - 1 , 58 l - 2 , and 58 l - 3 are respectively connected, by one or a plurality of wires 60 l - 1 , 60 l - 2 , 60 l - 3 , to a contact of the insulated metal substrate, defining a terminal, respectively 15 , 16 , 17 .
  • the gates of transistors Ml- 1 , Ml- 2 , and Ml- 3 are continued at the front side of chips 56 by contacts 62 l - 1 , 62 l - 2 , 62 l - 3 .
  • These contacts are individually connected by one or a plurality of wires 63 l - 1 , 63 l - 2 , 63 l - 3 to respective contacts of the insulated metal substrate, defining terminals 64 l - 1 , 64 l - 2 , 64 l - 3 , intended to be connected to control circuit 4 ( FIG. 2 ).
  • FIG. 6 shows the electrical scheme of a current inverter formed with the units of FIGS. 4 and 5 .
  • the respective positions of the diodes and transistors of high unit 2 h are inverted, that is, diodes Dh have their anodes interconnected to terminal 11 while transistors Mh- 1 , Mh- 2 , and Mh- 3 have their respective sources connected to terminals 15 , 16 , and 17 .
  • Low unit 2 l is, in terms of electric connection, similar to that of FIG. 2 .
  • FIG. 7 shows a variation of the embodiment of FIG. 4 .
  • FIG. 8 shows a variation of the embodiment of FIG. 5 .
  • FIGS. 7 and 8 illustrate the possibility of providing, at the level of each switching cell 3 , a plurality of diodes and transistors in parallel.
  • metal areas 58 h - 1 , 58 h - 2 , 58 h - 3 , 58 l - 1 , 58 l - 2 , 58 l - 3 of insulated metal substrates 51 h and 51 l each for example receive two transistor chips 56
  • central areas 53 h and 53 l each receive three pairs of diodes D.
  • the connections are similar to those discussed in relation with FIGS. 4 and 5 .
  • a layout of the chips such as illustrated in FIGS. 4 and 5 , or 7 and 8 has the advantage of homogenizing the electrical and thermal behavior of the different current flow meshes.
  • the geometrical symmetry between the different switching cells results in that the three possible switching meshes 3 h - 1 / 3 h - 2 , 3 h - 2 / 3 h - 3 , and 3 h - 1 / 3 h - 3 for high unit 2 h and the three possible switching meshes 3 l - 1 / 3 l - 2 , 3 l - 2 / 3 l - 3 , and 3 l - 1 / 3 l - 3 for low unit 2 l have a same electrical behavior.
  • the impedances of the different switching meshes used are identical and the overvoltage levels seen by the different switches are identical. Further, their thermal behavior is also homogenized due to this geometrical symmetry.
  • FIG. 9 is a very simplified representation of a semiconductor circuit chip 56 forming a vertical power transistor M.
  • transistor M is formed in a substrate 562 having the source and drain regions formed therein.
  • a back-side metallization 564 (generally full plate) defines drain contact D.
  • metallization areas 59 and 62 define source and gate contacts S and G.
  • a plurality of parallel areas 59 may be present.
  • Chip 56 is preferably intended to be assembled by its back side on an insulated metal substrate.
  • FIG. 10 is a very simplified representation of a semiconductor circuit chip 65 forming a vertical diode D.
  • diode D is formed in a substrate 652 having a P-type doped front side.
  • a back-side metallization 54 (for example, full plate) defines the cathode electrode while a front-side metallization 52 (for example, full plate) defines the anode electrode.
  • diodes Dh- 1 , Dh- 2 , and Dh- 3 are assembled on the insulated metal substrate by their anode metallization, that is, by the P-type electrode. It may be desirable to be able to assemble all the diodes of the current inverter by placing their cathode electrodes on the insulated metal substrate.
  • FIG. 11 very schematically shows another embodiment of an architecture of a first unit 2 h of a three-phase current inverter.
  • FIG. 12 very schematically shows another embodiment of an architecture of a second unit 2 l of a three-phase current inverter.
  • FIGS. 11 and 12 fulfill the aim of assembling all the diodes by placing their cathode electrodes on the insulated metal substrate.
  • FIG. 13 very schematically shows the electrical scheme of a three-phase current inverter according to the embodiment of FIGS. 11 and 12 .
  • high unit 2 h is identical to that of the embodiment of FIG. 6 , that is, diodes Dh all have their anodes connected to terminal 11 and the sources of transistors Mh- 1 , Mh- 2 , and Mh- 3 are respectively connected to terminals 15 , 16 , and 17 .
  • the cells of low unit 2 l however have the positions of the diodes and transistors inverted with respect to the embodiment of FIG. 6 .
  • the respective anodes of diodes Dl- 1 , Dl- 2 and Dl- 3 are respectively connected to terminals 15 , 16 , and 17
  • the sources of transistors Ml- 1 , Ml- 2 , and Ml- 3 are all connected to terminal 12 .
  • gates 64 of the transistors are connected to a control circuit 4 .
  • first identical metallization portions 70 each having the shape of a portion of a hexagonal ring-shaped strip forming two side of the hexagon. Each end of a portion 70 is for example orthogonal to the hexagon section that it ends. Further, each portion 70 receives identical diodes and transistors assembled in the same way, that is, by their respective back sides.
  • transistors M and two diodes D per switching cell are provided, it is possible to only provide one transistor and one diode, or more than two of each. Further, to respect the symmetry, transistors M are all assembled on first sections 702 of respective portions 70 and the diodes are all assembled on second sections 704 of portions 70 .
  • Each portion 70 is associated with another conductive portion 72 of a ring-shaped hexagon surrounding the first one (that having portions 70 formed therein).
  • portions 70 and portions 72 are spaced apart from one another to be electrically insulated.
  • a conductive strip 74 defining the gate terminal of the transistor(s) of each cell is provided outside of the corresponding portion 72 .
  • the apparent (upper) contacts are source contacts 59 and gate contacts 62 .
  • apparent metallization 52 corresponds to the anode electrode.
  • gate contacts 62 are connected by wires 63 to the respective conductive strips of the cells.
  • the anode contacts 52 of all diodes D are connected by wires 65 to central portion 53 , while the source contacts 59 of the different transistors M are connected to portion 72 of the corresponding cell by wires 60 .
  • Such an embodiment eases the manufacturing by allowing common structures for the high and low units as long as possible in the industrial process.
  • connection wires provided in FIGS. 11 and 12 are replaced with rigid planar connection elements.
  • FIG. 14 is a simplified representation of an alternative embodiment of a unit of FIGS. 11 and 12 where central area 53 ′ is Y-shaped.
  • Portions 70 ′ similar to portions 70 described in relation with FIGS. 11 and 12 , support diodes D and transistors M, but their layout is inverted to follow, with a complementary shape, the Y shape of central area 53 ′.
  • portions 72 ′ and 74 ′ similar to portions 72 and 74 of FIGS. 11 and 12 , are provided to define terminals 15 , 16 , and 17 as well as the transistor control terminals. To simplify the representation of FIG. 14 , the wire connections have not been shown.
  • FIG. 15 is a simplified representation of another alternative embodiment of a unit where central area 53 ′′ is triangular and areas 72 ′′ are rectilinear and parallel to the sides of the triangle of area 53 ′′. For simplification, the rest of the unit has not been shown in FIG. 15 .
  • Other shapes may be provided for the metal areas of the printed circuit receiving the switching cells, provided to respect a central area and peripheral areas having a symmetry of revolution of order 3, that is, a shift by approximately 120 degrees, preferably exactly 120 degrees, from one cell to the other around the center of the plane containing the unit.
  • the described embodiments particularly apply to applications of conversion of the power supplied by photovoltaic panels.
  • the electrically-conductive areas of the substrate are of course separated from one another to be electrically insulated. Further, these areas may be connected by conductive tracks or wires to other metal regions of the substrate, particularly to connect the inverter to upstream and downstream circuits.
  • the substrate having the components assembled thereon may be any other adapted substrate, for example, a printed circuit, a direct bond copper substrate, etc.
  • each switch may be in fact formed of a plurality of switches in parallel. The selection of the dimensions and of the number of chips to be assembled in parallel to form each switch of an inverter depends on the application and, among others, on the desired operation power.
  • the embodiments have been described in relation with an example applied to switching cells formed of a MOS transistor series-connected with a diode, they may be transposed to other three-phase switching structures, forming or not a switch which is bidirectional in terms of voltage and unidirectional in terms of current, where similar problems are posed.
  • the diode function may be carried out by a MOS transistor.
  • all cells are identical and the high and low units may also have an identical structure and comprise identical wire connections.
  • the two units of a same three-phase current inverter are not necessarily paired on a same integrated circuit (in a same plane) but may be stacked with an interposed insulator (for example, back side against back side of the printed circuits supporting the units), by connecting terminals 15 , 16 , and 17 by means of vias.

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Abstract

A three-phase switching unit including three identical switching cells, each including at least one first electrically-controlled switch in series with at least one second spontaneous conduction switch, wherein the cells are arranged, around a conductive central area of a substrate, with a symmetry of revolution of order 3.

Description

This application claims priority to French patent application number 16/63514, filed Dec. 29, 2016, the content of which is incorporated herein by reference in its entirety to the maximum extent allowable by law.
BACKGROUND
The present disclosure generally relates to electronic power conversion circuits, and more particularly to the forming of a three-phase current inverter. The present disclosure more particularly relates to the architecture of a static power converter intended for applications of current inverter type (direct current DC-to-alternating current AC).
DISCUSSION OF THE RELATED ART
A three-phase DC-to-AC static power converter is generally based on two sets of three (or three sets of two) electronic switches, typically MOS power transistors (MOSFET) associated with diodes.
Voltage inverters, where the transistors are directly series-connected two by two and each transistor is equipped with a diode in antiparallel, can be distinguished from current inverters, where each transistor is series-connected with a diode to form a switch which is bidirectional in terms of voltage and unidirectional in terms of current. The present disclosure more specifically targets current inverters.
In power applications, the transistors and the diodes are generally formed individually in the form of discrete components or bare chips. Each controlled switching switch (transistor) or spontaneous switching switch (diode) is manufactured in the form of an individual chip based on semiconductor materials and the different chips are then assembled on a substrate (printed circuit board—PCB, direct bond copper—DBC, insulated metal substrate—IMS, for example, a metal substrate at the surface of a ceramic, etc.) and then electrically connected to carry out the three-phase current inverter function.
There is a need to improve three-phase current inverters, and in particular their spatial architecture.
SUMMARY
An embodiment overcomes all or part of the disadvantages of three-phase current inverters.
An embodiment provides a solution enabling to homogenize the operating stress between the different switches of a three-phase current inverter.
An embodiment provides a solution particularly adapted to the forming of a current inverter.
Thus, an embodiment provides a three-phase switching unit comprising three identical switching cells, each comprising at least one first electrically-controlled switch series-connected with at least one second spontaneous conduction switch, wherein the cells are arranged, around a conductive central area of a substrate, with a symmetry of revolution of order 3.
According to an embodiment, the spontaneous conduction switches are assembled in the conductive central area with a symmetry of revolution of order 3.
According to an embodiment, the central area also has a symmetry of revolution of order 3.
According to an embodiment, the switch(es) of the switching cells are arranged on conductive peripheral areas of the substrate having a symmetry of revolution of order 3.
According to an embodiment, the central area and the peripheral areas approximately form a Y.
According to an embodiment, the conductive central area supports no component.
According to an embodiment, the conductive central area has a substantially hexagonal shape.
According to an embodiment, said first switch(es) are transistors.
According to an embodiment, said spontaneous conduction switch(es) are diodes or MOS transistors.
According to an embodiment, each switch is welded to a conductive area by a back-side metallization of a chip made of semiconductor materials, defining an electrode of the switch.
According to an embodiment, the conductive central area defines a terminal of electric interconnection of the three cells.
According to an embodiment, the substrate is an insulated metal substrate, preferably on ceramic.
An embodiment provides a three-phase current inverter, comprising two units.
According to an embodiment, the cells of the two units are electrically connected two by two, the interconnection nodes defining three phase terminals.
An embodiment provides a system comprising:
at least one assembly of photovoltaic panels; and
at least one current inverter.
The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified representation in the form of blocks of a three-phase inverter of the type to which the described embodiments apply;
FIG. 2 shows an electrical scheme of a three-phase current inverter;
FIG. 3 is a simplified representation of a usual architecture of a switching unit of a three-phase current inverter;
FIG. 4 very schematically shows an embodiment of an architecture of a first unit of a three-phase current inverter;
FIG. 5 very schematically shows an embodiment of an architecture of a second three-phase current inverter unit;
FIG. 6 shows the electrical scheme of a three-phase current inverter formed with the units of FIGS. 4 and 5;
FIG. 7 shows a variation of the embodiment of FIG. 4;
FIG. 8 shows a variation of the embodiment of FIG. 5;
FIG. 9 is a very simplified representation of a semiconductor circuit chip forming a vertical power transistor;
FIG. 10 is a very simplified representation of a semiconductor circuit chip forming a vertical diode;
FIG. 11 very schematically shows another embodiment of an architecture of a first unit of a three-phase current inverter;
FIG. 12 very schematically shows another embodiment of an architecture of a second unit of a three-phase current inverter;
FIG. 13 shows the electrical scheme of a three-phase current inverter formed with the units of FIGS. 11 and 12;
FIG. 14 is a simplified representation of a variation of the embodiments of FIGS. 11 and 12; and
FIG. 15 is a very simplified partial representation of another alternative embodiment.
 DETAILED DESCRIPTION
For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and will be detailed. In particular, the control of a power converter based on the described three-phase inverters has not been detailed, the described embodiments being compatible with usual industrial manufacturing processes and control circuits. Further, the structure and the forming of the circuits upstream and downstream of the described three-phase inverters have not been detailed either, the described embodiments being compatible with usual applications of such three-phase inverters. It should be noted that, in the drawings, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties. Unless otherwise specified, expressions “approximately”, “substantially”, and “in the order of” mean to within 10%, preferably to within 5%, or to within 10°, preferably to within 5°.
Document U.S. Pat. No. 6,501,172 describes a three-phase voltage inverter where switches are connected in parallel with diodes, a switching cell being formed of a switch electrically connected in parallel with a diode. In a voltage inverter, the diode of a cell conducts while the switch (in parallel) of the same cell is blocked. To form a three-phase voltage inverter, three cells are paired in parallel and are connected with a point common to three other cells. Thus, the six cells have a common junction point.
Document EP 2 367 281 describes a three-phase current inverter of the type to which the described embodiments apply. Each switching cell comprises a controllable switch (a transistor) in series with a diode. Six cells are series-connected, two by two, between two terminals of application of a DC voltage. The junction points of the series associations define the three phases of the three-phase voltage. In a three-phase current inverter, the diode of a cell conducts at the same time as the switch which is series-connected therewith. The cells are paired two by two in series and three pairs of series-connected cells are connected in parallel, the junction points of each pair defining a phase.
FIG. 1 is a simplified representation in the form of blocks of three-phase current inverter of the type to which the described embodiments apply.
The function of a three-phase current inverter 1 is to convert a DC current Idc flowing between two input terminals 11 and 12 into a three-phase AC current Iac on output terminals 15, 16, 17, and 19. Terminals 15, 16, and 17 represent the terminals of the different phases and terminal 19 represents the optional neutral terminal.
FIG. 2 shows an electrical scheme of a three-phase current inverter.
Inverter 1 comprises two switching units 2 h and 2 l having similar inner structures. Each unit 2 h, 2 l comprises three switching cells, cyclically implying two of the three identical switches, respectively 3 h-1, 3 h-2, 3 h-3 and 3 l-1, 3 l-2, 3 l-3, each formed of a MOS transistor (with an N channel) respectively Mh-1, Mh-2, Mh-3, Ml-1, Ml-2, Ml-3, in series with a diode, respectively Dh-1, Dh-2, Dh-3, Dl-1, Dl-2, Dl-3. The drains of transistors Mh-1, Mh-2, and Mh-3 are interconnected to terminal 11 of application of a first potential of current source Idc. The sources of transistors Mh-1, Mh-2, and Mh-3 are respectively connected to the anodes of diodes Dh-1, Dh-2, and Dh-3, having their cathodes respectively connected to terminals 15, 16, and 17 of the three AC voltage phases. The drains of transistors Ml-1, Ml-2, Ml-3 are respectively connected to terminals 15, 16, and 17. The sources of transistors Ml-1, Ml-2, and Ml-3 are respectively connected to the anodes of diodes Dl-1, Dl-2, and Dl-3, which have their cathodes interconnected to terminal 12 of application of a second potential of current source Idc.
The gates of transistors Mh-1, Mh-2, Mh-3, Ml-1, Ml-2, Ml-3 are individually connected to a control circuit 4 (CTRL) in charge of organizing the switching of the different cells to generate a three-phase AC current Iac. In a current inverter, the current flow successively takes place in each of the switching cells (for example, 3 h-1/3 h-2, 3 h-1/3 h-3, 3 h-2/3 h-3) of a first unit jointly with each of the switching cells (for example, 3 l-1/3 l-2, 3 l-1/3 l-3, 3 l-2/3 l-3) of the other unit. The 9 combinations enabling to generate the three-phase AC current with the appropriate phase shifts are thus obtained. The control of such a current inverter is usual.
In the present description, the high or low unit of the three-phase current inverter to which the element identified by the reference number belongs is identified by letter “h” or “l”. Further, the references are completed with “−”, “−2”, or “−3” to identify the switching branch (representing the phase of the AC voltage) containing the element identified by the reference number. Such reference complements may be omitted when no distinction needs to be made for the needs of the disclosure.
FIG. 3 is a simplified representation of a usual architecture of a switching unit of a three-phase current inverter.
In power applications targeted by the present description, the transistors and diodes are manufactured in the form of vertical components made of semiconductor materials assembled at the surface of an insulated metal substrate 51.
In the example of FIG. 3, a high unit 2 h, having its diodes and transistors inverted with respect to FIG. 2, is considered. The anodes of diodes Dh-1, Dh-2, Dh-3 are thus interconnected to terminal 11. The three diodes Dh-1, Dh-2 and Dh-3 are individually formed on P-type substrates and the cathodes are formed by N-type regions in the substrates. The anode electrodes are generally made in the form of a back-side metallization of the chips forming diodes Dh-1, Dh-2, Dh-3 and are placed on a conductive area 53 (typically, a metal conductive plane) of insulated metal substrate 51. An electrically-conductive area of the insulated metal substrate defining terminal 11 is connected to plane 53 by one or a plurality of wires 55. Transistors Mh-1, Mh-2, and Mh-3 are also individually manufactured in the form of chips 56-1, 56-2, and 56-3. The drain electrode of each transistor, generally made in the form of a back-side metallization of the chip, is placed on a conductive area 58-1, 58-2, and 58-3, respectively, of insulated metal substrate 51. The cathode electrodes corresponding to front-side metallizations 52-1, 52-2, and 52-3 of the chips forming diodes Dh-1, Dh-2, and Dh-3 are respectively electrically connected to areas 58-1, 58-2, and 58-3 by one or a plurality of wires 57-1, 57-2, 57-3. The source electrode of each transistor Mh-1, Mh-2, Mh-3 corresponds to a front-side metal contact, respectively 59-1, 59-2, 59-3, connected by one or a plurality of wires 60-1, 60-2, 60-3 to a contact of the insulated metal substrate, defining a terminal, respectively 15, 16, 17. The gates of transistors Mh-1, Mh-2, and Mh-3 are continued on the front side of the chips by contacts 62-1, 62-2 and 62-3, individually connected by one or a plurality of wires 63-1, 63-2, 63-3, to respective contacts of insulated metal substrate 51, defining terminals 64-1, 64-2, 64-3 intended to be connected to control circuit 4 (FIG. 2).
An architecture such as illustrated in FIG. 3 where the chips are placed next to one another generates functional thermal and electrical stress, different according to the operating phases, which adversely affects its reliability.
Further, there is an imbalance between the different conductive meshes, which also adversely affects the operation.
The embodiments which will be described result from a new analysis based on the architecture or the layout of the different switching cells on an insulated metal substrate. This analysis takes into account the specificity of a current inverter, which is that two of the three switches are cyclically implied during switching operations.
It is in particular provided to make the electrical and thermal stress undergone by the different chips of the switch identical whatever the phase. Thus, the aging is homogenized, which increases the reliability of the switches.
More particularly, it is provided to arrange at least the switches of the switching cells around (at the periphery of) a central area with, in the plane, a symmetry of revolution of order 3 with respect to the center of the structure. In other words, the structure substantially has a symmetry of revolution of 120°.
FIG. 4 very schematically shows an embodiment of an architecture of a first unit 2 h of a three-phase current inverter.
FIG. 5 very schematically shows an embodiment of an architecture of a second unit 2 l of a three-phase current inverter.
In the example of FIGS. 4 and 5, a star- or Y-shaped structure where, for each unit 2 h, 2 l, the three diodes of the cells are arranged at the center of the structure and the transistors are arranged in the branches of the Y, is considered.
As previously, the diodes and transistors are manufactured individually in the form of discrete chips of vertical components made of semiconductor materials, and are assembled on an insulated metal substrate 51, called 51 h in FIG. 4 for first unit 2 h and 51 l in FIG. 5 for second unit 2 l. A metallized central area 53 h (FIG. 4), 53 l (FIG. 5), has a shape with a symmetry of revolution of order 3 in the plane with respect to its center, for example, a hexagonal shape. Three peripheral metallized areas 58 h-1, 58 h-2, 58 h-3 (FIG. 4), respectively 58 l-1, 58 l-2, 58 l-3 (FIG. 5) are formed in each portion 51 h, 51 l of the insulated metal substrate. For example, each area 58 is rectangular and has an edge parallel to a side of the hexagon 53 around which it is provided, a free end of hexagonal area 53 separating two sides each having an area 58 opposite thereto.
In the embodiment of FIGS. 4 and 5, it is provided to place the diodes at the centers of the structures. Accordingly, for unit 2 h (FIG. 4), the anode electrodes of diodes Dh-1, Dh-2, Dh-3 are assembled (welded) on area 53 h, while for unit 2 l, the cathode electrodes of diodes Dl-1, Dl-2, Dl-3 (FIG. 5) are assembled (welded) to area 53 l. The electrical scheme which will be discussed hereafter in relation with FIG. 6 is thus different from that of FIG. 2.
The back-side drain contact of each chip 56 h-1, 56 h-2, 56 h-3 (FIG. 4), 56 l-1, 56 l-2, and 56 l-3 (FIG. 5), forming a transistor Ml-1, Ml-2, Ml-3 (FIG. 4), Mh-1, Mh-2, Mh-3 (FIG. 5), is assembled (welded) on an area 58, respectively 58 h-1, 58 h-2, 58 h-3 (FIG. 4) or 58 l-1, 58 l-2, 58 l-3 (FIG. 5) of the concerned unit.
For unit 2 h (FIG. 4), the cathode electrodes corresponding to front-side metallizations 52 h-1, 52 h-2, and 52 h-3 of the chips forming diodes Dh-1, Dh-2, and Dh-3 are respectively electrically connected to areas 58 h-1, 58 h-2, and 58 h-3 by one or a plurality of wires 57 h-1, 57 h-2, 57 h-3. The source electrode of each transistor Mh-1, Mh-2, Mh-3 corresponds to a front-side metal contact, respectively 59 h-1, 59 h-2, 59 h-3 connected by one or a plurality of wires 60 h-1, 60 h-2, 60 h-3 to a contact of the printed circuit, defining a terminal, respectively 15, 16, 17. The gates of transistors Mh-1, Mh-2, and Mh-3, are continued on the front side of chips 56 by contacts 62 h-1, 62 h-2, 62 h-3. These contacts are individually connected by one or a plurality of wires 63 h-1, 63 h-2, 63 h-3 to respective contacts of the printed circuit, defining terminals 64 h-1, 64 h-2, 64 h-3, intended to be connected to control circuit 4 (FIG. 2).
For unit 2 l (FIG. 5), the anode electrodes corresponding to front-side metallizations 54 l-1, 54 l-2, and 54 l-3 of the chips forming diodes Dl-1, Dl-2, and Dl-3 are respectively electrically connected, by one or a plurality of wires 57 l-1, 57 l-2, 57 l-3, to the respective source electrodes of transistors Ml-1, Ml-2, and Ml-3 corresponding to a front-side metal contact, respectively 59 l-1, 59 l-2, 59 l-3, of the chips forming the transistors. Areas 58 l-1, 58 l-2, and 58 l-3 are respectively connected, by one or a plurality of wires 60 l-1, 60 l-2, 60 l-3, to a contact of the insulated metal substrate, defining a terminal, respectively 15, 16, 17. The gates of transistors Ml-1, Ml-2, and Ml-3, are continued at the front side of chips 56 by contacts 62 l-1, 62 l-2, 62 l-3. These contacts are individually connected by one or a plurality of wires 63 l-1, 63 l-2, 63 l-3 to respective contacts of the insulated metal substrate, defining terminals 64 l-1, 64 l-2, 64 l-3, intended to be connected to control circuit 4 (FIG. 2).
FIG. 6 shows the electrical scheme of a current inverter formed with the units of FIGS. 4 and 5.
As compared with the scheme of FIG. 2, the respective positions of the diodes and transistors of high unit 2 h are inverted, that is, diodes Dh have their anodes interconnected to terminal 11 while transistors Mh-1, Mh-2, and Mh-3 have their respective sources connected to terminals 15, 16, and 17. Low unit 2 l is, in terms of electric connection, similar to that of FIG. 2.
FIG. 7 shows a variation of the embodiment of FIG. 4.
FIG. 8 shows a variation of the embodiment of FIG. 5.
FIGS. 7 and 8 illustrate the possibility of providing, at the level of each switching cell 3, a plurality of diodes and transistors in parallel. Thus, in FIGS. 7 and 8, metal areas 58 h-1, 58 h-2, 58 h-3, 58 l-1, 58 l-2, 58 l-3 of insulated metal substrates 51 h and 51 l each for example receive two transistor chips 56, and central areas 53 h and 53 l each receive three pairs of diodes D. The connections are similar to those discussed in relation with FIGS. 4 and 5.
A layout of the chips such as illustrated in FIGS. 4 and 5, or 7 and 8, has the advantage of homogenizing the electrical and thermal behavior of the different current flow meshes. Indeed, the geometrical symmetry between the different switching cells results in that the three possible switching meshes 3 h-1/3 h-2, 3 h-2/3 h-3, and 3 h-1/3 h-3 for high unit 2 h and the three possible switching meshes 3 l-1/3 l-2, 3 l-2/3 l-3, and 3 l-1/3 l-3 for low unit 2 l have a same electrical behavior. In particular, the impedances of the different switching meshes used are identical and the overvoltage levels seen by the different switches are identical. Further, their thermal behavior is also homogenized due to this geometrical symmetry.
FIG. 9 is a very simplified representation of a semiconductor circuit chip 56 forming a vertical power transistor M.
According to this example, transistor M is formed in a substrate 562 having the source and drain regions formed therein. A back-side metallization 564 (generally full plate) defines drain contact D. On the front side, metallization areas 59 and 62 define source and gate contacts S and G. A plurality of parallel areas 59 may be present. Chip 56 is preferably intended to be assembled by its back side on an insulated metal substrate.
FIG. 10 is a very simplified representation of a semiconductor circuit chip 65 forming a vertical diode D.
According to this example, diode D is formed in a substrate 652 having a P-type doped front side. A back-side metallization 54 (for example, full plate) defines the cathode electrode while a front-side metallization 52 (for example, full plate) defines the anode electrode.
In the embodiments of FIGS. 4, 5, 7, and 8, diodes Dh-1, Dh-2, and Dh-3 are assembled on the insulated metal substrate by their anode metallization, that is, by the P-type electrode. It may be desirable to be able to assemble all the diodes of the current inverter by placing their cathode electrodes on the insulated metal substrate.
FIG. 11 very schematically shows another embodiment of an architecture of a first unit 2 h of a three-phase current inverter.
FIG. 12 very schematically shows another embodiment of an architecture of a second unit 2 l of a three-phase current inverter.
The embodiments of FIGS. 11 and 12 fulfill the aim of assembling all the diodes by placing their cathode electrodes on the insulated metal substrate.
To achieve this, it is provided to modify the electrical assembly, that is, the electrical scheme of the three-phase current inverter.
FIG. 13 very schematically shows the electrical scheme of a three-phase current inverter according to the embodiment of FIGS. 11 and 12.
From an electrical scheme viewpoint, high unit 2 h is identical to that of the embodiment of FIG. 6, that is, diodes Dh all have their anodes connected to terminal 11 and the sources of transistors Mh-1, Mh-2, and Mh-3 are respectively connected to terminals 15, 16, and 17. The cells of low unit 2 l however have the positions of the diodes and transistors inverted with respect to the embodiment of FIG. 6. In other words, the respective anodes of diodes Dl-1, Dl-2 and Dl-3 are respectively connected to terminals 15, 16, and 17, and the sources of transistors Ml-1, Ml-2, and Ml-3 are all connected to terminal 12. As in the previous embodiments, gates 64 of the transistors are connected to a control circuit 4.
The architecture described in relation with FIGS. 11 and 12 is based on metallized central areas 53 having a hexagonal shape, no component being placed thereon. These areas respectively define terminals 11 and 12 of the three-phase current inverter. Further, all the switching cells are structurally identical and only differ by the wire connections achieved once the components have been assembled on the insulated metal substrate. Thus, for all the switching cells, first identical metallization portions 70, each having the shape of a portion of a hexagonal ring-shaped strip forming two side of the hexagon, are provided. Each end of a portion 70 is for example orthogonal to the hexagon section that it ends. Further, each portion 70 receives identical diodes and transistors assembled in the same way, that is, by their respective back sides.
Although, in the example of FIGS. 11 and 12, two transistors M and two diodes D per switching cell are provided, it is possible to only provide one transistor and one diode, or more than two of each. Further, to respect the symmetry, transistors M are all assembled on first sections 702 of respective portions 70 and the diodes are all assembled on second sections 704 of portions 70.
Each portion 70 is associated with another conductive portion 72 of a ring-shaped hexagon surrounding the first one (that having portions 70 formed therein). Of course, in the same way as between area 53 and portions 70, portions 70 and portions 72 are spaced apart from one another to be electrically insulated. Finally, vertically in line with sections 702 supporting transistors M, a conductive strip 74 defining the gate terminal of the transistor(s) of each cell is provided outside of the corresponding portion 72.
All the diodes and all transistors M are assembled on conductive portions 70 by their respective back sides. Accordingly, for the transistors, the apparent (upper) contacts are source contacts 59 and gate contacts 62. For diodes D, apparent metallization 52 corresponds to the anode electrode.
Whatever the unit, gate contacts 62 are connected by wires 63 to the respective conductive strips of the cells.
For high unit 2 h (FIG. 11), the anode contacts 52 of all diodes D are connected by wires 65 to central portion 53, while the source contacts 59 of the different transistors M are connected to portion 72 of the corresponding cell by wires 60.
For low unit 2 l (FIG. 12), all the source contacts 59 of transistors M are connected to central portion 53 (terminal 12) by wires 66, while the anode contacts 52 of the different diodes D are connected to portion 72 of the corresponding cell by wires 67.
It can thus be seen that the only two differences between high units and low units are the connections by wires 60 or 66 of the transistor sources and by wires 65 or 67 of the diode anodes.
Such an embodiment eases the manufacturing by allowing common structures for the high and low units as long as possible in the industrial process.
As a variation, the connection wires provided in FIGS. 11 and 12 are replaced with rigid planar connection elements.
FIG. 14 is a simplified representation of an alternative embodiment of a unit of FIGS. 11 and 12 where central area 53′ is Y-shaped.
Portions 70′, similar to portions 70 described in relation with FIGS. 11 and 12, support diodes D and transistors M, but their layout is inverted to follow, with a complementary shape, the Y shape of central area 53′. Similarly, portions 72′ and 74′, similar to portions 72 and 74 of FIGS. 11 and 12, are provided to define terminals 15, 16, and 17 as well as the transistor control terminals. To simplify the representation of FIG. 14, the wire connections have not been shown.
FIG. 15 is a simplified representation of another alternative embodiment of a unit where central area 53″ is triangular and areas 72″ are rectilinear and parallel to the sides of the triangle of area 53″. For simplification, the rest of the unit has not been shown in FIG. 15.
Other shapes may be provided for the metal areas of the printed circuit receiving the switching cells, provided to respect a central area and peripheral areas having a symmetry of revolution of order 3, that is, a shift by approximately 120 degrees, preferably exactly 120 degrees, from one cell to the other around the center of the plane containing the unit.
An advantage of the embodiments which have been described is that it is now possible to form a three-phase current inverter where the electrical and thermal behaviors of the different switching meshes are identical.
The described embodiments particularly apply to applications of conversion of the power supplied by photovoltaic panels.
Various embodiments and variations have been described. Certain embodiments and variations may be combined and other variations and modifications which will occur to those skilled in the art. In particular, the electrically-conductive areas of the substrate are of course separated from one another to be electrically insulated. Further, these areas may be connected by conductive tracks or wires to other metal regions of the substrate, particularly to connect the inverter to upstream and downstream circuits. Further, although reference has been more specifically made to the use of an insulated metal substrate, preferably a metal substrate on ceramic, the substrate having the components assembled thereon may be any other adapted substrate, for example, a printed circuit, a direct bond copper substrate, etc. Further, each switch may be in fact formed of a plurality of switches in parallel. The selection of the dimensions and of the number of chips to be assembled in parallel to form each switch of an inverter depends on the application and, among others, on the desired operation power.
Further, although the embodiments have been described in relation with an example applied to switching cells formed of a MOS transistor series-connected with a diode, they may be transposed to other three-phase switching structures, forming or not a switch which is bidirectional in terms of voltage and unidirectional in terms of current, where similar problems are posed. For example, the diode function may be carried out by a MOS transistor. In this case, all cells are identical and the high and low units may also have an identical structure and comprise identical wire connections.
It should be noted that the two units of a same three-phase current inverter are not necessarily paired on a same integrated circuit (in a same plane) but may be stacked with an interposed insulator (for example, back side against back side of the printed circuits supporting the units), by connecting terminals 15, 16, and 17 by means of vias.
Finally, the practical implementation of the embodiments and variations which have been described is within the abilities of those skilled in the art based on the functional indications given hereabove.
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.

Claims (19)

What is claimed is:
1. A three-phase current inverter, comprising:
a first three phase switching unit and a second three-phase switching unit, each of the first and second three-phase switching units comprising:
a conductive central area of a substrate; and
three identical switching cells arranged around and radially spaced from the conductive central area with a symmetry of revolution of order 3, each of the three identical switching cells comprising at least one first electrically-controlled switch in series with at least one second spontaneous conduction switch,
wherein the conductive central area defines an input terminal of the three-phase current inverter to which the three identical switching cells are electrically interconnected; and
wherein the three identical switching cells of the first three-phase switching unit and the three identical switching cells of the second three-phase switching unit are electrically connected two by two, interconnection nodes connecting the first and second three-phase switching units defining three phase terminals.
2. The three-phase current inverter of claim 1, wherein the at least one second spontaneous conduction switch of each of the three identical switching cells is assembled in the conductive central area of the substrate with a second symmetry of revolution of order 3.
3. The three-phase current inverter of claim 1, wherein the conductive central area of the substrate supports no component.
4. The three-phase current inverter of claim 1, wherein the conductive central area of the substrate has a third symmetry of revolution of order 3.
5. The three-phase current inverter of claim 1, wherein the at least one first electrically-controlled switch and the at least one second spontaneous conduction switch of the three identical switching cells are arranged on conductive peripheral areas of the substrate having a fourth symmetry of revolution of order 3.
6. The three-phase current inverter of claim 5, wherein the conductive central area and the peripheral areas of the substrate approximately form a Y shape.
7. The three-phase current inverter of claim 1, wherein the conductive central area of the substrate has a substantially hexagonal shape.
8. The three-phase current inverter of claim 1, wherein said at least one first electrically-controlled switch comprises a plurality of transistors.
9. The three-phase current inverter of claim 1, wherein said at least one second spontaneous conduction switch comprises a diode, or a MOS transistor.
10. The three-phase current inverter of claim 1, wherein each of the at least one first electrically-controlled switch is welded to a conductive area by a back-side metallization of a chip made of semiconductor materials, defining an electrode of the at least one first electrically-controlled switch.
11. The three-phase current inverter of claim 1, wherein the substrate is an insulated metal substrate.
12. A system comprising:
an assembly of photovoltaic panels; and
the three-phase current inverter of claim 11.
13. The three-phase current inverter of claim 1, wherein each of the first and second three-phase switching units comprises three phase terminal electrodes.
14. A multi-phase current inverter, comprising:
two switching units, each coupling a respective one of two direct current (DC) ports to a plurality of alternating current (AC) terminals;
first and second pluralities of switching cells respectively forming the two switching units, each of the first and second pluralities of switching cells comprising an electrically-controlled switch coupled in series with a spontaneous conduction switch,
wherein each of the first and second pluralities of switching cells is configured for unidirectional conduction of current;
wherein the first plurality of switching cells are identical and are arranged around and radially spaced from a first conductive central area of at least one substrate with a symmetry of revolution of order 3; and
wherein the second plurality of switching cells are identical and are arranged around and radially spaced from a second conductive central area of the at least one substrate with a symmetry of revolution of order 3.
15. The multi-phase current inverter of claim 14, wherein the spontaneous conduction switch of each of the first plurality of switching cells is assembled in the first conductive central area of the at least one substrate.
16. The multi-phase current inverter of claim 14, wherein the first conductive central area of the at least one substrate does not support the spontaneous conduction switches of the first plurality of switching cells.
17. The multi-phase current inverter of claim 14, wherein the electrically-controlled switch of each of the first and second pluralities of switching cells comprises a transistor, and the spontaneous conduction switch of each of the first and second pluralities of switching cells comprises a diode or a MOS transistor.
18. The multi-phase current inverter of claim 14, wherein the multi-phase current inverter is a three-phase inverter, and the first plurality of switching cells and the second plurality of switching cells each include three switching cells.
19. The multi-phase current inverter of claim 14, wherein each of the two switching units comprises a plurality of phase terminal electrodes, each of the plurality of AC terminals comprising one of the plurality of phase terminal electrodes of each of the two switching units.
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FR3061627B1 (en) 2019-09-06
US20180191272A1 (en) 2018-07-05

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