TWI777525B - Switch capable of decreasing parasitic inductance - Google Patents

Abstract

The present invention provides a switch capable of decreasing parasitic inductance. The switch capable of decreasing parasitic inductance includes a semiconductor device, a first top metal line, and a second top metal line. The second top metal line is electrically connected to a power input terminal and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged adjacent to a second part of the second top metal line in parallel. When the semiconductor device is turned on, an input current outflows from the power input terminal, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce a first superposition parasitic inductance of the first top metal line and the second top metal line.

Description

Switches that reduce parasitic inductance

The present invention relates to a switch capable of reducing parasitic inductance, and more particularly, to a switch capable of reducing parasitic inductance for a switching power supply circuit.

FIG. 1 shows a schematic circuit diagram of a typical step-down switching power supply circuit 10 . The step-down switching power supply circuit 10 includes a control circuit 1 and a power stage circuit 2 . As shown in FIG. 1 , the power stage circuit 2 includes an upper bridge switch 11 , a lower bridge switch 12 and an inductor 13 . The upper bridge switch 11 and the lower bridge switch 12 are switched according to the upper bridge signal UG and the lower bridge signal LG respectively, so as to convert the input voltage Vin into the output voltage Vout; and generate the inductor current IL, which flows through the inductor 13 through the phase node PH , to supply power to the load circuit 3 .

FIG. 2A shows a schematic top view of the upper bridge switch 11 . 2B shows a schematic cross-sectional view of the upper bridge switch 11 taken along the line AA' of FIG. 2A , and FIG. 2C shows a schematic cross-sectional view of the upper bridge switch 11 taken along the line BB' of FIG. 2A . Please refer to FIG. 1 and FIGS. 2A-2B at the same time, when the upper bridge switch 11 is turned on (that is, the gate 117 of the semiconductor element 110 in the upper bridge switch 11 is electrically connected to a high level voltage), the input current Iin flows out from the power input terminal 120 , and divided into sub-currents Iin11 and Iin12 as shown in FIG. 2B , wherein the sub-current Iin11 of the input current Iin flows from the metal wire 121 to the drain 119 through the metal plug 122a and the metal wire 123a, and the sub-current of the input current Iin is Iin12 flows from the metal wire 121 to the drain 119' through the metal plug 122b and the metal wire 123b. When the upper bridge switch 11 is kept on, referring to FIG. 1 and FIG. 2C , the on-current Ic1 flows from the drain 119 The channel formed in the semiconductor layer flows to the source electrode 118, and then flows from the source electrode 118 to the metal plug 127a, the metal wire 126 and the metal plug 125; and the on-current Ic2 is formed from the drain electrode 119' through the semiconductor layer The other channel flows to the source electrode 118 ′, and then flows from the source electrode 118 ′ to the metal plug 127 b , the metal wire 126 and the metal plug 125 . The on-currents Ic1 and Ic2 are combined into the inductor current IL, and the inductor current IL finally flows to the phase node PH through the metal wire 124 .

As shown in FIG. 2A , in order to reduce the size of the upper bridge switch 11 as much as possible, in order to reduce the manufacturing cost and improve the operation efficiency, in the prior art, the metal wires 121 and 124 are arranged adjacently and as close to each other as possible; however, According to Ampère's circuital law, when the upper bridge switch 11 is turned on, the directions of the input current Iin and the inductor current IL flowing through the parallel metal wires 121 and 124 are the same (as seen from the upper view 2A, the input current Iin and The inductor currents IL all flow from right to left, as indicated by the dashed hollow arrows in the figure), and the parasitic inductances generated by them are in the same direction. After superposition, the operation slew rate of the upper bridge switch 11 will be limited. .

In view of this, the present invention provides a switch capable of reducing parasitic inductance in metal wires.

In one aspect, the present invention provides a switch capable of reducing parasitic inductance, comprising: a semiconductor element for electrically connecting one of the current inflow terminals and one of the current outflow terminals according to a control voltage to turn on the semiconductor element; a first top wire for electrically connecting a power input terminal and the current inflow terminal; and a second top wire for electrically connecting the power input terminal and the current inflow terminal, wherein the second top wire and The first top wire is formed at the same height, and a first portion of the first top wire and a second portion of the second top wire are arranged in parallel and adjacent; wherein, when the semiconductor device is in a conduction operation, an input The current flows out from the power input and is divided into a first a current and a second current; wherein, the first current and the second current flow through the first part and the second part respectively, and the first current and the second current flow through the first part and the second current respectively When the two parts are opposite to each other, the first superimposed parasitic inductance of one of the first top wire and the second top wire is reduced.

In one embodiment, the switch capable of reducing parasitic inductance further includes: a third top wire for electrically connecting the current outflow terminal and a node; and a fourth top wire for electrically connecting the current outflow terminal and the node. the node, wherein the fourth top wire and the third top wire are formed at the same height, and a third portion of the third top wire and a fourth portion of the fourth top wire are arranged in parallel and adjacent; wherein, when During the conduction operation of the semiconductor device, the input current flows out from the current outflow terminal and is divided into a third current and a fourth current; wherein the third current and the fourth current flow through the third part and the fourth current, respectively. the fourth part, and the third current and the fourth current flow through the third part and the fourth part respectively, they are opposite to each other to lower one of the third top wire and the fourth top wire superimposed parasitic inductance.

In one embodiment, the third top wire and the second top wire are formed at the same height, and the third portion of the third top wire and the second portion of the second top wire are arranged in parallel and adjacent to each other; wherein , when the third current and the second current flow through the third part and the second part respectively, they are opposite to each other, so as to reduce the third superimposed parasitic inductance of the third top wire and one of the second top wire.

In one embodiment, the switch capable of reducing parasitic inductance is a high-side switch in a step-down switching power supply circuit.

In one embodiment, the switch capable of reducing parasitic inductance is a low-bridge switch in a boost switching power supply circuit.

In one embodiment, the semiconductor device is a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device.

In one embodiment, the LDMOS device includes: a well region with a first conductivity type formed in a semiconductor layer; a body region with a second conductivity type formed in the semiconductor layer, the body region is connected with the well region in a channel direction; a gate electrode is formed on the semiconductor layer, and a part of the body region is located directly under the gate electrode and is connected to the gate electrode, so as to provide the semiconductor element with a an inversion current channel; and a source electrode and a drain electrode having the first conductivity type, the source electrode and the drain electrode are respectively located in the body region and the well region under different sides of the outside of the gate electrode, And in the channel direction, a drift region is located in the well region between the drain electrode and the body region, and is used as a drift current channel of the semiconductor element during the conduction operation.

In one embodiment, the first top wire, the second top wire, the third top wire and the fourth top wire are formed at the same height, and the power input terminal and the node are formed at the same height.

In one embodiment, the semiconductor element includes a first LDMOS element and a second LDMOS element, the first LDMOS element and the second LDMOS element share the same body region and the same body pole, and the first LDMOS element and the The second LDMOS elements are arranged in mirror images of each other.

In one embodiment, the first top wire and the second top wire are viewed from a top view, in a channel direction, across a well region and the body region of the first LDMOS device and the second LDMOS device respectively , the body electrode, a gate electrode, a source electrode and a drain electrode.

One advantage of the present invention is that the present invention can reduce the parasitic inductance in the metal wires.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

1: Control circuit

2: Power stage circuit

3: Load circuit

10: Step-down switching power supply circuit

11: Upper bridge switch

12: Lower bridge switch

13: Inductance

21, 31: Switches that reduce parasitic inductance

110: Semiconductor Components

117: Gate

118,118': source

119,119': drain pole

120: Power input terminal

121, 123a, 123b, 124, 126, 223a1, 223a2, 223b1, 223b2, 226a, 226b, 323a2, 323b1: metal wires

122a,122b,125,127a,127b,222a1,222a2,222b1,222b2,225a,225b,227a1,227a2,227b1,227b2,322a2,322b1,325a,325b: metal plug

210,310: Semiconductor Components

211,311: Substrates

211', 311': semiconductor layer

211a, 311a: upper surface

211b, 311b: lower surface

212, 312: Well area

212a, 212b, 312a, 312b: Drift region

213a, 213a', 313a, 313a': Inversion zone

214, 214', 314, 314': drift oxide zone

215,315: Ontology area

216,316: Body pole

217, 217', 317, 317': gate

218, 218', 318, 318': source

219, 219', 319, 319': drain

220,320: power input

221a, 321a: first top layer conductor

221b, 321b: Second top wire

224a, 324a: Third top wire

224b, 324b: Fourth top wire

2171, 2171', 3171, 3171': Dielectric layer

2172, 2172', 3172, 3172': Conductive layer

2173, 2173', 3173, 3173': spacer layer

2211: Part 1

2212: Part II

2213: Part Three

2214: Part Four

Ic1,Ic2,Ic11,Ic12,Ic21,Ic22,Ic13,Ic31: On current

Iin: input current

Iin1: the first current

Iin2: second current

Iin3: the third current

Iin4: the fourth current

Iin11,Iin12,Iin13,Iin21,Iin22,Iin23,Iin31,Iin32,Iin41,Iin42: Sub current

IL: inductor current

LG: Lower bridge signal

LT1, LT2: Lateral Diffused Metal Oxide Semiconductor (LDMOS) devices

PH: Phase Node

UG: Upper bridge signal

Vin: input voltage

Vout: output voltage

FIG. 1 shows a schematic circuit diagram of a conventional step-down switching power supply circuit.

FIG. 2A is a schematic top view of a semiconductor device used as a high-bridge switch in a power stage of a conventional step-down switching power supply circuit.

FIG. 2B is a schematic cross-sectional view of the semiconductor device taken along the line AA' in FIG. 2A .

FIG. 2C is a schematic cross-sectional view of the semiconductor device taken along line BB' in FIG. 2A .

3A is a schematic top view showing a switch capable of reducing parasitic inductance according to an embodiment of the present invention.

3B is a schematic top view showing a switch capable of reducing parasitic inductance according to an embodiment of the present invention.

FIG. 3C is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along the line CC' in FIG. 3A .

FIG. 3D is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along line DD' in FIG. 3A .

FIG. 3E is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along line EE' in FIG. 3A .

FIG. 3F is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along line FF' in FIG. 3A .

4A is a schematic top view showing a switch capable of reducing parasitic inductance according to another embodiment of the present invention.

FIG. 4B is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along the line GG' in FIG. 4A .

FIG. 4C is a schematic cross-sectional view of the switch with reduced parasitic inductance taken along the line HH' in FIG. 4A .

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic, mainly intended to represent the process steps and the top-bottom order relationship between the layers, and the shapes, thicknesses and widths are not drawn to scale.

3A and 3B are schematic top views showing the switch 21 for reducing parasitic inductance according to an embodiment of the present invention. FIG. 3C is a schematic cross-sectional view of the switch 21 for reducing parasitic inductance, taken along the line CC' in FIG. 3A . FIG. 3D is a schematic cross-sectional view of the switch 21 for reducing parasitic inductance taken along the line DD' in FIG. 3A . As shown in FIGS. 3A and 3B , and referring to FIGS. 3C and 3D , the switch 21 capable of reducing parasitic inductance of the present invention includes a semiconductor device 210 , a first top layer wire 221 a and a second top layer wire 221 b . 3A and 3C at the same time, the first top layer wire 221a is used to electrically connect the power input terminal 220 and the current inflow terminal (eg, the drain electrodes 219 and 219'). 3A and 3D at the same time, the second top layer wire 221b is used to electrically connect the power input terminal 220 and the current inflow terminal (eg, the drain electrodes 219 and 219'). In one embodiment, the second top-layer wires 221b and the first top-layer wires 221a are formed at the same height. In one embodiment, as shown in FIG. 3B , the first portion 2211 of the first top layer wire 221a (such as but not limited to the upper thick black and long dotted frame in FIG. 3B ) and the second portion of the second top layer wire 221b Portions 2212 (such as, but not limited to, those shown by the upper thick black dashed box in FIG. 3B ) are arranged in parallel and adjacent.

As shown in FIG. 3A , when the semiconductor device 210 is in the conduction operation, the input current flows from the power input terminal 220 and is divided into the first current Iin1 and the second current Iin2 . When the first current Iin1 and the second current Iin2 flow through the first part 2211 and the second part 2212 respectively, and the first current Iin1 and the second current Iin2 flow through the first part 2211 and the second part 2212 respectively, they are opposite to each other. Therefore, The parasitic inductances generated by them are in opposite directions. After being superimposed, they can substantially cancel each other, thereby reducing the first superimposed parasitic inductance of the first top-layer wire 221a and the second top-layer wire 221b, thereby improving the switch 21 that can reduce the parasitic inductance. operation conversion rate.

As shown in FIG. 3A , the switch 21 capable of reducing parasitic inductance of the present invention further includes a third top layer wire 224a and a fourth top layer wire 224b. FIG. 3E is a schematic cross-sectional view of the switch 21 for reducing parasitic inductance taken along the line EE' in FIG. 3A . 3A and 3E at the same time, the third top layer wire 224a is used to electrically connect the current outflow terminals (eg, the source electrodes 218 and 218') and the node (eg, the phase node PH). FIG. 3F is a schematic cross-sectional view of the switch 21 for reducing parasitic inductance taken along the line FF' in FIG. 3A . 3A and 3F at the same time, the fourth top layer wire 224b is used to electrically connect the current outflow terminals (eg, the source electrodes 218 and 218') and the node (eg, the phase node PH). In one embodiment, the fourth top wire 224b and the third top wire 224a are formed at the same height. As shown in FIG. 3A, the third portion 2213 of the third top layer wire 224a (such as, but not limited to, shown in the lower thick black long dashed frame in FIG. 3B) and the fourth portion 2214 of the fourth top layer wire 224b (such as but not limited to It is not limited to the parallel and adjacent arrangement shown in the lower thick black dashed box in FIG. 3B .

As shown in FIG. 3A , when the semiconductor device 210 is in the ON operation, the ON currents Ic11 , Ic12 , Ic21 and Ic22 flow out from the current outflow terminals (eg, the source electrodes 218 and 218 ′) and are divided into a third current Iin3 and a fourth current Iin4 . The third current Iin3 and the fourth current Iin4 flow through the third portion 2213 and the fourth portion 2214 respectively, and when the third current Iin3 and the fourth current Iin4 flow through the third portion 2213 and the fourth portion 2214 respectively, they are opposite to each other, In order to reduce the second superimposed parasitic inductance of the third top layer wire 224a and the fourth top layer wire 224b. In one embodiment, as shown in FIG. 3A , the third top layer wires 224a and the second top layer wires 221b are formed at the same height. In one embodiment, as shown in FIG. 3A , the third portion 2213 of the third top layer wire 224a and the second portion 2212 of the second top layer wire 221b are arranged in parallel and adjacent to each other. As shown in FIG. 3A , when the semiconductor device 210 is in the ON operation, when the third current Iin3 and the second current Iin2 flow through the third portion 2213 and the second portion 2212 respectively, they are opposite to each other, so as to reduce the connection between the third top layer wire 224a and the second portion 2212 . The third superimposed parasitic inductance of the second top layer conductor 221b. In one embodiment, the first top wire 221a, the second top wire 221b, the third top wire 224a and the fourth top wire 224b are formed at the same height, and the power input terminal 220 and the node (eg, the phase node PH) are formed at the same height high. In one embodiment, the switch 21 that can reduce parasitic inductance can be High-side bridge switch in a step-down switching power supply circuit. In another embodiment, the switch 21 capable of reducing parasitic inductance can be a lower bridge switch in a boost switching power supply circuit.

FIG. 3B is a schematic top view showing the switch 21 capable of reducing parasitic inductance according to an embodiment of the present invention. 3B shows that the first current Iin1 , the second current Iin2 , the third current Iin3 and the fourth current Iin4 flow through the first top wire 221 a , the second top wire 221 b , the third top wire 224 a and the fourth top wire 224 b respectively. The resulting parasitic inductance and its direction. As shown in FIG. 3B , the parasitic inductances generated when the aforementioned currents flow through the top-layer wires can cancel out some of the parasitic inductances. The generated parasitic inductances can more or less cancel each other out: 1. The part of the first top layer wire 221a close to the power input end 220 and the second top layer wire 221b close to the power input end 220; 2. The first top layer wire 221a is close to the power input end 220; The part far from the power input terminal 220 and the part far from the power input terminal 220 of the second top wire 221b; 3. The part of the third top wire 224a close to the phase node PH and the part of the fourth top wire 224b close to the phase node PH; 4. The third The portion of the top layer conductor 224a that is far away from the phase node PH and the portion of the fourth top layer conductor 224b that are far away from the phase node PH; the parasitic inductances generated by the two portions of the top layer conductor of each item listed above are opposite to each other, so they can mutually offset to achieve the effect of reducing parasitic inductance.

Referring to FIG. 3C , the switch 21 with reduced parasitic inductance of the present invention includes a semiconductor element 210 for electrically connecting the current inflow terminals (eg, drains 219 and 219 ′) and the current outflow terminals (eg, source) according to the control voltage. poles 218 and 218 ′) to turn on the semiconductor device 210 . As shown in FIG. 3C , the switch 21 capable of reducing parasitic inductance includes a semiconductor element 210 . The semiconductor element 210 includes: a Lateral Diffused Metal Oxide Semiconductor (LDMOS) element LT1 and LT2. The LDMOS device LT1 includes: a well region 212 , a drift oxide region 214 , a body region 215 , a body electrode 216 , a gate electrode 217 , a source electrode 218 and a drain electrode 219 . The LDMOS element LT2 includes: a well region 212, a drift oxide region 214', a body region 215, a body electrode 216, a gate electrode 217', a source electrode 218' and a drain electrode 219'. When the semiconductor element 210 is fabricated, the LDMOS elements LT1 and LT2 share the body region 215 and the body electrode 216 , and the LDMOS elements LT1 and LT2 are arranged in mirror images to form the semiconductor element 210 . Therefore, as shown in Figure 3C, source 218' is mirror-symmetrical to source 218, gate 217' is mirror-symmetrical to gate 217, and so on.

In one embodiment, the first top-level wiring 221a, the second top-level wiring 221b, the third top-level wiring 224a, and the fourth top-level wiring 224b are viewed from the top view, in the channel direction, across the respective LDMOS element LT1 and LDMOS element LT2 A well region 212, a body region 215, a body electrode 216, gate electrodes 217 and 217', source electrodes 218 and 218', and drain electrodes 219 and 219'.

The semiconductor layer 211' is formed on the substrate 211, and the semiconductor layer 211' has opposite upper surfaces 211a and lower surfaces 211b in the vertical direction (as indicated by the solid arrow direction in FIG. 3C, the same below). The substrate 211 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 211' is formed on the substrate 211 by, for example, an epitaxial process step, or a part of the substrate 211 is used as the semiconductor layer 211'. The method of forming the semiconductor layer 211' is well known to those skilled in the art, and will not be repeated here.

Please continue to refer to FIG. 3C , the drift oxide regions 214 and 214 ′ are respectively formed on the upper surface 211 a and connected to the upper surface 211 a respectively, and are respectively located in the corresponding part of the drift regions 212 a and 212 b (as shown in the LDMOS devices LT1 and LT2 in FIG. 3C ) The dotted line box of ) is directly above and connected to the corresponding drift regions 212a and 212b, respectively. The drift oxide regions 214 and 214' are, for example, but not limited to, the local oxidation of silicon (LOCOS) structure as shown in the figure, and may also be a shallow trench isolation (STI) structure or a chemical vapor deposition (chemical vapor deposition) structure. vapor deposition, CVD) oxidation structure.

The well region 212 has the first conductivity type and is formed in the semiconductor layer 211', and in the vertical direction, the well region 212 is located under the upper surface 211a and connected to the upper surface 211a. The well region 212 is formed, for example, by at least one ion implantation process step. The body region 215 has the second conductivity type, is formed in the well region 212, and is vertically In the straight direction, the body regions 215 are located under the upper surface 211a and are respectively connected to the upper surface 211a. The body electrode 216 has the second conductivity type and is used as an electrical contact of the body region 215. In the vertical direction, the body electrode 216 is formed under the upper surface 211a and connected to the corresponding body region 215 of the upper surface 211a. The gates 217' and 217 are respectively formed on the upper surface 211a of the semiconductor layer 211', and in the vertical direction, a part of the body region 215 is located directly under the gates 217' and 217 and connected to the gates 217' and 217, respectively, so as to The inversion regions 213a' and 213a of the corresponding semiconductor element 210 in the turn-on operation are respectively provided, and the inversion regions 213a' and 213a are respectively located directly under the corresponding partial gate electrodes 217' and 217 and are respectively connected to the corresponding gate electrodes 217' and 213a. 217.

Please continue to refer to FIG. 3C, the source electrodes 218' and 218 and the drain electrodes 219' and 219 have the first conductivity type. In the vertical direction, the source electrodes 218' and 218 and the drain electrodes 219' and 219 are respectively formed under the upper surface 211a and are respectively connected to the upper surface 211a, and the source electrodes 218' and 218 and the drain electrodes 219' and 219 are respectively located outside the corresponding gate electrodes 217' and 217 in the channel direction (as indicated by the dashed arrows in the figure, the same below) In the body region 215 below and in the well region 212 on the side away from the body region 215, and in the channel direction, the drift regions 212b and 212a are located between the corresponding drain electrodes 219' and 219 and the body region 215, respectively, close to the upper surface 211a The well region 212 is used as a drift current path for the LDMOS elements LT2 and LT1 in the turn-on operation.

It should be noted that the so-called inversion regions 213 a ′ and 213 a refer to the voltages applied to the corresponding gate electrodes 217 ′ and 217 during the turn-on operation of the LDMOS elements LT2 and LT1 . A region where an inversion layer is formed to allow the conduction current to pass through is between the corresponding source electrodes 218' and 218 and the corresponding drift regions 212b and 212a, which is well known to those with ordinary knowledge in the art, and is not described here. For further description, other embodiments of the present invention are deduced by analogy.

It should be noted that the first conductivity type and the second conductivity type may be P type or N type. When the first conductivity type is P type, the second conductivity type is N type; when the first conductivity type is N type, the first conductivity type is N type. The second conductivity type is P type.

It should be noted that the so-called drift current channel refers to a region through which the on-current of the semiconductor element 210 drifts through during the on-operation operation, which is well known in the art and will not be repeated here.

It should be noted that, in a preferred embodiment, the gate electrodes 217' and 217 respectively include corresponding dielectric layers 2171' and 2171 connected to the upper surface 211a, and corresponding conductive layers 2172' and 2172 having conductivity , and corresponding spacer layers 2173' and 2173 having electrical insulating properties. The dielectric layers 2171' and 2171 are respectively formed on the body region 215 and connected to the body region 215, respectively. The conductive layers 2172' and 2172 are used as electrical contacts of the corresponding gate electrodes 217' and 217, respectively, are formed on all the corresponding dielectric layers 2171' and 2171, and are respectively connected to the corresponding dielectric layers 2171' and 2171', respectively. 2171. Spacer layers 2173' and 2173 are respectively formed on both sides of the corresponding conductive layers 2172' and 2172 to serve as electrical insulating layers on both sides of the corresponding gate electrodes 217' and 217. In one embodiment, in the LDMOS devices LT1 and LT2, the source electrodes 218 and 218' and the body electrode 216 are respectively electrically connected by a metal silicide layer (not shown).

In addition, it should be noted that the so-called high-voltage device (also referred to as a semiconductor device as above) refers to that the voltage applied to the drain is higher than a specific voltage, such as 5V, during normal operation, and the main body 215 and the corresponding The distance in the channel direction between the drain electrodes 219' and 219 (the lengths of the drift regions 212b and 212a) is adjusted according to the operating voltage experienced during normal operation, so that it can operate at the aforementioned higher specific voltage. These are all well known to those with ordinary knowledge in the art, and will not be repeated here.

As shown in FIG. 3C , in the part of the first top layer wire 221a that is far from the power input terminal 220, the first current Iin1 is first divided into sub-currents Iin11 and Iin12, wherein the sub-current Iin11 passes from the first top layer wire 221a through the metal plug 222a1 And the metal wire 223a1 flows to the drain electrode 219, and the sub-current Iin12 flows from the first top layer wire 221a to the drain electrode 219' through the metal plug 222a2 and the metal wire 223a2. When the semiconductor device 210 is kept on, referring to FIG. 3C , the on-current Ic11 flows from the drain electrode 219 to the source electrode 218 through the channel formed in the semiconductor layer, and the on-current Ic12 flows from the drain electrode 219 ′ through another channel formed in the semiconductor layer. The channel flows to source 218'.

Referring to FIG. 3D , in the embodiment shown in FIG. 3D , the semiconductor device 210 of this embodiment is similar to the embodiment of FIG. 3C , so the detailed description thereof is omitted. As shown in FIG. 3D , in the portion of the second top layer wire 221b that is far from the power input terminal 220, the second current Iin2 is first divided into sub-currents Iin21 and Iin22, The sub-current Iin21 flows from the second top wire 221b to the drain 219 through the metal plug 222b1 and the metal wire 223b1, while the sub-current Iin22 flows from the second top wire 221b to the drain 219 through the metal plug 222b2 and the metal wire 223b2 '. When the semiconductor element 210 is kept on, referring to FIG. 3D, the on-current Ic21 flows from the drain electrode 219 to the source electrode 218 through the channel formed in the semiconductor layer, and the on-current Ic22 flows from the drain electrode 219' through another channel formed in the semiconductor layer. The channel flows to source 218'.

Referring to FIG. 3E , in the embodiment shown in FIG. 3E , the semiconductor device 210 of this embodiment is similar to the embodiment of FIG. 3C , so the detailed description thereof is omitted. After the on-current Ic11 flows from the drain electrode 219 to the source electrode 218, the sub-current Iin31 flows from the source electrode 218 to the metal plug 227a1, the metal wire 226a and the metal plug 225a. After the on-current Ic12 flows from the drain electrode 219' to the source electrode 218', the sub-current Iin32 flows from the source electrode 218' to the metal plug 227a2, the metal wire 226a and the metal plug 225a. The sub-currents Iin31 and Iin32 are combined at the metal plug 225a to form a third current Iin3, and the third current Iin3 finally flows to the phase node PH through the third top wire 224a.

Please refer to FIG. 3F . In the embodiment shown in FIG. 3F , the semiconductor device 210 of this embodiment is similar to the embodiment of FIG. 3C , so the detailed description thereof is omitted. After the on-current Ic21 flows from the drain electrode 219 to the source electrode 218, the sub-current Iin41 flows from the source electrode 218 to the metal plug 227b1, the metal wire 226b and the metal plug 225b. After the on-current Ic22 flows from the drain electrode 219' to the source electrode 218', the sub-current Iin42 flows from the source electrode 218' to the metal plug 227b2, the metal wire 226b and the metal plug 225b. The sub-currents Iin41 and Iin42 are combined at the metal plug 225b to form a fourth current Iin4, and the fourth current Iin4 finally flows to the phase node PH through the fourth top wire 224b.

4A is a schematic top view showing a switch 31 capable of reducing parasitic inductance according to another embodiment of the present invention. The power input terminal 320, the first top wire 321a, the second top wire 321b, the third top wire 324a, the fourth top wire 324b and the phase node PH in this embodiment are similar to the power input terminals 220, The first top wire 221a, the second top wire 221b, the third top wire 224a, the fourth top wire 224b and the phase node PH are omitted in detail. The difference between this embodiment and the embodiment of FIG. 3A is that this embodiment only includes metal plugs 322a2, 322b1, 325a, and 325b.

FIG. 4B is a schematic cross-sectional view of the switch 31 for reducing parasitic inductance taken along the line GG' in FIG. 4A . FIG. 4C is a schematic cross-sectional view of the switch 31 for reducing parasitic inductance taken along the line HH' in FIG. 4A . As shown in FIGS. 4A and 3B, and referring to FIGS. 4B and 4C, the switch 31 capable of reducing parasitic inductance of the present invention includes a semiconductor device 310, a first top layer wire 321a and a second top layer wire 321b. 4A and 4B at the same time, the first top layer wire 321a is used to electrically connect the power input terminal 320 and the current inflow terminal (eg, the drain electrode 319'). 4A and 4C at the same time, the second top layer wire 321b is used to electrically connect the power input terminal 320 and the current inflow terminal (eg, the drain electrode 319). In one embodiment, the second top-layer wires 321b and the first top-layer wires 321a are formed at the same height. In one embodiment, as shown in FIG. 4A , the first portion of the first top layer wire 321a and the second portion of the second top layer wire 321b are arranged in parallel and adjacent to each other.

As shown in FIG. 4A , when the semiconductor device 310 is in the ON operation, the input current flows from the power input terminal 320 and is divided into the first current Iin1 and the second current Iin2 . The first current Iin1 and the second current Iin2 flow through the first part and the second part respectively, and when the first current Iin1 and the second current Iin2 flow through the first part and the second part respectively, they are opposite to each other, so as to reduce the first top layer wire The first superimposed parasitic inductance between 321a and the second top layer wire 321b.

As shown in FIG. 4A , the switch 31 capable of reducing parasitic inductance of the present invention further includes a third top layer wire 324a and a fourth top layer wire 324b. Referring to FIG. 4A , the third top layer wire 324a is used to electrically connect the current outflow terminals (eg, the source electrodes 318 and 318') and the node (eg, the phase node PH). Referring to FIG. 4A, the fourth top layer wire 324b is used to electrically connect the current outflow terminals (eg, the source electrodes 318 and 318') and the node (eg, the phase node PH). In one embodiment, the fourth top layer conductor 324b and the third top layer conductor 324a are formed at the same height. As shown in FIG. 4A , the third portion of the third top layer wire 324a and the fourth portion of the fourth top layer wire 324b are arranged in parallel and adjacent to each other.

As shown in FIG. 4A , when the semiconductor device 310 is in the on operation, the on currents Ic31 and Ic13 flow out from the current outflow terminals (such as the source electrodes 318 and 318') and are divided into a third current Iin3 and a fourth current Iin4. The third current Iin3 and the fourth current Iin4 flow through the third part and the fourth part respectively, and the third current When the Iin3 and the fourth current Iin4 flow through the third part and the fourth part respectively, they are opposite to each other, so as to reduce the second superimposed parasitic inductance of the third top wire 324a and the fourth top wire 324b. In one embodiment, as shown in FIG. 4A , the third top layer wires 324a and the second top layer wires 321b are formed at the same height. In one embodiment, as shown in FIG. 4A , the third portion of the third top layer wire 324a and the second portion of the second top layer wire 321b are arranged in parallel and adjacent to each other. As shown in FIG. 4A , when the semiconductor device 310 is in the ON operation, when the third current Iin3 and the second current Iin2 flow through the third part and the second part respectively, they are opposite to each other, so as to lower the third top wire 324a and the second The third superimposed parasitic inductance of the top wire 321b. In one embodiment, the first top wire 321a, the second top wire 321b, the third top wire 324a and the fourth top wire 324b are formed at the same height, and the power input terminal 320 and the node (eg, the phase node PH) are formed at the same height high. In one embodiment, the switch 31 capable of reducing parasitic inductance can be an upper bridge switch in a step-down switching power supply circuit. In another embodiment, the switch 31 capable of reducing parasitic inductance can be a lower bridge switch in a boost switching power supply circuit.

Referring to FIG. 4B , the switch 31 capable of reducing parasitic inductance of the present invention includes a semiconductor element 310 for electrically connecting a current inflow terminal (eg, drain 319 or 319 ′) and a current outflow terminal (eg, source) according to a control voltage. poles 318 and 318 ′) to turn on the semiconductor device 310 . The semiconductor element 310 of this embodiment is similar to the semiconductor element 210 of FIG. 3C , so the detailed description thereof is omitted.

As shown in FIG. 4B , in the part of the first top layer wire 321a far from the power input terminal 320, the first current Iin1 directly enters the metal plug 322a2, and the sub-current Iin13 flows to the drain through the metal plug 322a2 and the metal wire 323a2 319'. When the semiconductor element 310 is kept on, referring to FIG. 4B, the on-current Ic13 flows from the drain electrode 319' to the source electrode 318' through the channel formed in the semiconductor layer.

Referring to FIG. 4C , in the embodiment shown in FIG. 4C , the semiconductor device 310 of this embodiment is similar to the embodiment of FIG. 4B , so the detailed description thereof is omitted. As shown in FIG. 4C , in the part of the second top layer wire 321b far from the power input terminal 320, the second current Iin2 directly enters the metal plug 322b1, and the sub-current Iin23 flows to the drain through the metal plug 322b1 and the metal wire 323b1 319. When the semiconductor element 310 Keeping on, referring to FIG. 4C , the on-current Ic31 flows from the drain electrode 319 to the source electrode 318 through the channel formed in the semiconductor layer.

It is worth noting that one of the technical features of the present invention superior to the prior art is that, according to the present invention, taking the embodiment shown in FIG. 3B as an example, by using two top-layer wires to transmit currents in opposite directions, the two The respective parts of the top conductors are adjacent and parallel to each other, so that the parasitic inductances caused by the currents in the two top conductors can cancel each other due to the opposite directions, so as to achieve the effect of reducing the parasitic inductance.

The present invention has been described above with respect to the preferred embodiments, but the above-mentioned descriptions are only intended to make it easy for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes will be devised by those skilled in the art. In addition, the described embodiments are not limited to be applied individually, but can also be applied in combination. Accordingly, the scope of the present invention should cover the above and all other equivalent changes. In addition, it is not necessary for any embodiment of the present invention to achieve all the purposes or advantages, and therefore the scope of the claimed patent should not be limited thereto.

21: Switch to reduce parasitic inductance 220: Power input 221a: first top wire 221b: Second top wire 222a1, 222a2, 222b1, 222b2, 225a, 225b: Metal plugs 224a: third top wire 224b: Fourth top wire PH: Phase Contact Iin1: first current Iin2: second current Iin3: third current Iin4: Fourth current

Claims (10)

A switch capable of reducing parasitic inductance, comprising: a semiconductor element for electrically connecting a current inflow terminal and a current outflow terminal according to a control voltage to turn on the semiconductor element; a first top wire for a power input terminal and the current inflow terminal are electrically connected; and a second top wire is used to electrically connect the power input terminal and the current inflow terminal, wherein the second top wire and the first top wire are formed at the same height, And a first part of the first top layer wire and a second part of the second top layer wire are arranged in parallel and adjacent; wherein, when the semiconductor element is in a conducting operation, an input current flows out from the power input terminal and is divided into a first current and a second current; wherein, the first current and the second current flow through the first part and the second part respectively, and the first current and the second current flow through the first part and the second part respectively The second portions are reversed to each other to reduce the first superimposed parasitic inductance of the first top wire and one of the second top wire. The switch capable of reducing parasitic inductance as claimed in claim 1, further comprising: a third top wire for electrically connecting the current outflow terminal and a node; and a fourth top wire for electrically connecting the current outflow terminal and the node, wherein the fourth top wire and the third top wire are formed at the same height, and a third portion of the third top wire is arranged in parallel and adjacent to a fourth portion of the fourth top wire; wherein, When the semiconductor device is in the conduction operation, a conduction current flows out from the current outflow terminal and is divided into a third current and a fourth current; wherein, the third current and the fourth current respectively flow through the third part and the fourth part, and when the third current and the fourth current flow through the third part and the fourth part respectively, they are opposite to each other, so as to reduce the first level of one of the third top wire and the fourth top wire. Two superimposed parasitic inductances. The switch capable of reducing parasitic inductance as claimed in claim 2, wherein the third top wire and the second top wire are formed at the same height, and the third portion of the third top wire and the second top wire are The second parts are arranged in parallel and adjacent; wherein, when the third current and the second current flow through the third part and the second part respectively, they are opposite to each other, so as to lower the third top wire and the second top wire A third superimposed parasitic inductance. The switch capable of reducing parasitic inductance as claimed in claim 1, wherein the switch capable of reducing parasitic inductance is a high-side switch in a step-down switching power supply circuit. The switch capable of reducing parasitic inductance as claimed in claim 1, wherein the switch capable of reducing parasitic inductance is a low-bridge switch in a boost switching power supply circuit. The switch capable of reducing parasitic inductance as claimed in claim 1, wherein the semiconductor element is a Lateral Diffused Metal Oxide Semiconductor (LDMOS) element. The switch capable of reducing parasitic inductance as claimed in claim 6, wherein the LDMOS device comprises: a well region having a first conductivity type formed in a semiconductor layer; a body region having a second conductivity type formed In the semiconductor layer, the body region and the well region are connected in a channel direction; a gate electrode is formed on the semiconductor layer, and a part of the body region is located directly under the gate electrode and connected to the gate electrode to provide an inversion current path of the semiconductor element during the conduction operation; and a source electrode and a drain electrode having the first conductivity type, the source electrode and the drain electrode are respectively located on the outer side of the gate electrode under the different sides In the body region and the well region, and in the channel direction, a drift region is located in the well region between the drain and the body region, and is used as a drift current of the semiconductor element during the conduction operation aisle. The switch capable of reducing parasitic inductance as claimed in claim 2, wherein the first top wire, the second top wire, the third top wire and the fourth top wire are formed at the same height, and the power input end and the Nodes are formed at the same height. The switch capable of reducing parasitic inductance as claimed in claim 6, wherein the semiconductor element comprises a first LDMOS element and a second LDMOS element, the first LDMOS element and the second LDMOS element share the same body region and the same body pole , and the first LDMOS element and the second LDMOS element are arranged in mirror images of each other. The switch capable of reducing parasitic inductance as claimed in claim 9, wherein the first part and the second part span a well region and the body region of the first LDMOS element and the second LDMOS element in a channel direction respectively , the body electrode, a gate electrode, a source electrode and a drain electrode.

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