TWI684314B - Pwm/pfm dual mode charging system - Google Patents

Abstract

A PWM/PFM dual mode charging system includes a conversion circuit, a current sensor, a constant current mode control unit, a constant voltage mode control unit and a OR gate. The conversion circuit is configured to charge a battery module. The current is configured to sense a current level of the conversion circuit and output a sensing voltage. The constant current mode control unit receives the sensing voltage and outputs a PWM signal. The constant voltage mode control unit outputs a PFM signal. The OR gate receives the PWM signal and the PFM signal and outputs a control signal for controlling the conversion circuit.

Description

PWM/PFM dual-mode charging system

The invention relates to a charging system, in particular to a PWM/PFM dual-mode charging system.

With the rapid development of electric steam locomotives and portable personal devices, the energy storage devices used in electric steam locomotives and portable personal devices have an increasing demand for power capacity. Among them, lithium batteries have high energy density. The advantages are widely used. In addition, in order to provide fast, stable and high-efficiency charging, charging control methods have also received considerable attention. Generally speaking, the charging curve of a lithium battery can be divided into three stages. First, the small current is charged in the pre-charging stage to avoid damage to the low-voltage battery; then when the voltage of the lithium battery rises to a level At the time, switch to constant current mode for charging, charge the lithium battery with the maximum current to speed up the charging speed; finally, when the voltage of the lithium battery reaches the full voltage, switch to constant voltage mode for charging, and charge the lithium battery with a slowly decreasing current Charge the battery to prevent the lithium battery from being overcharged. Among them, the more common charging system is a switching power conversion circuit with PWM (Pulse Width Modulation) control to achieve three-stage charging, which can be regarded as a heavy load in a constant current mode, and can be used in a constant voltage mode Regarded as light load, although PWM control can achieve high efficiency power conversion in constant current mode, but simply using PWM to control in constant voltage mode cannot achieve high efficiency.

The main objective of the present invention is to provide a charging system with dual-mode charging control, which can perform power conversion control by PWM (Pulse-width modulation) in constant current mode and PFM (Pulse-frequency modulation) in constant voltage mode The control of power conversion is performed to overcome the problem of low efficiency in the constant voltage mode simply controlled by PWM in the prior art, and the present invention achieves the combination of PWM and PFM modes through only one OR gate, which can effectively Reduce losses during mode switching and increase overall efficiency.

A PWM/PFM dual-mode charging system of the present invention includes a conversion circuit, a current sensor, a certain current mode control unit, a certain voltage mode control unit, and an OR gate, wherein the conversion circuit has a first power switch, a A second power switch and a charge-discharge unit, the charge-discharge unit is electrically connected to the first power switch and the second power switch, the conversion circuit is used to charge a battery module, wherein the battery module has a battery voltage . The current sensor is coupled to the charge-discharge unit. The current sensor is used to sense a current of the charge-discharge unit. The current sensor outputs a sense voltage. The constant current mode controls the electrical property of the unit The current sensor is connected to receive the sensing voltage, and the constant current mode control unit outputs a pulse width modulation signal according to the sensing voltage of the current sensor, a limiting voltage, and a ripple voltage. The constant voltage mode control unit outputs a pulse frequency modulation signal according to the battery voltage, a full voltage and a clock signal. The OR gate is electrically connected to the constant current mode control unit and the constant voltage mode control unit to receive the pulse width modulation signal and the pulse frequency modulation signal, and the OR gate outputs a control signal to control the first of the conversion circuit A power switch and the second power switch.

The present invention achieves PWM/PFM dual-mode charging control by the constant current mode control unit and the constant voltage mode control unit, and only achieves the switching between the two modes through a single OR gate, which can further reduce the mode The loss that may occur during switching improves the overall charging efficiency of the PWM/PFM dual-mode charging system.

Please refer to FIG. 1, which is a functional block diagram of a PWM/PFM dual-mode charging system 100 according to an embodiment of the invention. The PWM/PFM dual-mode charging system 100 has a conversion circuit 110 and a current sensor 120 , A certain current mode control unit 130, a certain voltage mode control unit 140, and an OR gate 150. The switching circuit 110 receives an input voltage V _in and will be converted into an appropriate current or voltage of a battery module B is charged, the current sensor 120 is coupled to the switching circuit 110 to sense its current size, and the The current sensor 120 outputs a sense voltage V _sense . The constant current mode control unit 130 is electrically connected to the current sensor 120 to receive the sense voltage V _sense , the constant current mode control unit 130 further receives a limit voltage V _limit and a ripple voltage V _ramp , and the constant The current mode control unit 130 outputs a pulse width modulation signal PWM according to the sense voltage V _sense , the limit voltage V _limit and the ripple voltage V _ramp . The constant voltage mode control unit 140 outputs a pulse frequency modulation signal PFM according to a battery voltage V _{BAT of} the battery module B, a full voltage V _full and a clock signal Clk, and the OR gate 150 is electrically connected to the constant current mode the control unit 130, and the constant voltage mode control unit 140 to receive the pulse width modulation signal PWM and the pulse frequency modulation signal PFM, the oR gate 150 outputs a control signal S _C to the switching circuit 110 and controls the switching circuit 110 , So that the conversion circuit 110 can charge the battery module B with a suitable current or voltage at each charging stage. The detailed circuit and operation mode of each circuit unit are described in detail below.

Please refer to FIGS. 1 and 2. In this embodiment, the conversion circuit 110 is a switching power conversion architecture. The conversion circuit 110 has a first power switch 111, a second power switch 112, and a charge-discharge unit 113 , A non-overlapping circuit 114, a zero current detection circuit 115 and a high level shifter 116. The first power switch 111 is a P-type power transistor, the second power switch 112 is an N-type power transistor, the source of the first power switch 111 receives the input voltage V _in , and the first power The drain of the switch 111 is electrically connected to a node V _X , and the gate of the first power switch 111 receives a first control signal S _C1 . The drain of the second power switch 112 is electrically connected to the node V _X , the source of the second power switch 112 is grounded, and the gate of the second power switch 112 receives a second control signal S _C2 . The charging and discharging unit 113 has an inductor 113a, a resistor 113b, and a capacitor 113c. Both ends of the inductor 113a are electrically connected to the node V _X and the battery module B, respectively, and both ends of the resistor 113b are electrically connected to the One end of the battery module B and the capacitor 113c, and the other end of the capacitor 113c are grounded. 114 of the non-overlap circuit electrically connected to the OR gate 150 receives the control signal S _C, the non-overlap circuit 114 and the control signal S _C is divided into the first control signal S _C1 and the second control signal S _C2. The zero current detection circuit 115 is electrically connected to the non-overlapping circuit 114 to transmit the second control signal _{SC 2} to the second power switch 112. The high level shifter 116 is electrically connected to the non-overlapping circuit 114 to raise the level of the first control signal S _C1 and transmit it to the first power switch 111. The conversion circuit 110 controls the duty cycle of the first power switch 111 and the second power switch 112 by the first control signal S _C1 and the second control signal S _C2 , and the input voltage V _in Convert to a suitable current or voltage to charge the battery module B.

Please refer to FIG. 2 and FIG. 3, the current sensor 120 is used to sense the current size of the inductor 113a of the charge-discharge unit 113 to know whether the current of the inductor 113a has been greater than a predetermined value to determine the conversion circuit 110 Whether to switch to constant current mode. Please refer to FIG. 3. In this embodiment, the current sensor 120 has a load 121, a first current mirror 122, a second current mirror 123 and a current-voltage conversion circuit 124. The load 121 has a first transistor 121a and a second transistor 121b, the first current mirror 122 has a third transistor 122a and a fourth transistor 122b, and the second current mirror 123 has a fifth transistor The crystal 123a, a sixth transistor 123b and a seventh transistor 123c, the first transistor 121a, the third transistor 122a and the fifth transistor 123a constitute a first current loop L1, the second transistor 121b, the fourth transistor 122b and the sixth transistor 123b constitute a second current loop L2, and the seventh transistor 123c is used to replicate the current to the first current loop L1 and the second current loop L2, so that the The currents of the first current loop L1 and the second current loop L2 are the same as the current of the seventh transistor 123c, and since the paths of the first current loop L1 and the second current loop L2 are the same, the node V _Y is The voltage at node V _{Z is} the same. In addition, the first current loop L1 is electrically connected to the inductor 113a to extract part of the current from the inductor 113a, and the current-voltage conversion loop 124 is electrically connected to the second transistor 121b to be extracted by the second current loop L2 Take a detection current and convert it to the sense voltage V _sense , where the width ratio of the first transistor 121a is K times the width ratio of the second transistor 121b, the second transistor 121b The current of the first transistor 121a can be duplicated by a factor of K and converted into the sense voltage V _sense by the current-voltage conversion circuit 124, and the inductor 113a can be detected by the potential of the sense voltage V _sense The size of the current.

Please refer to FIGS. 2 and 4, the constant current mode control unit 130 has a first comparator 131, a charge and discharge selection circuit 132, a charging capacitor 133, a second comparator 134, a delay 135 and a low level Bit shifter 136. The first comparator 131 is electrically connected to the current sensor 120 and the low level shifter 136, so that the current sensor 120 receives the sensing voltage V _sense and is received by the low level shifter 136 For the limit voltage V _limit , the first comparator 131 compares the potential levels of the _sense voltage V _sense and the limit voltage V _limit and outputs a first comparison signal comp1. The charge-discharge selection circuit 132 is electrically connected to the first comparator 131 to receive the first comparison signal comp1, and the charge capacitor 133 is electrically connected to the charge-discharge selection circuit 132, wherein the charge-discharge selection circuit 132 is based on the first The comparison signal comp1 selectively charges or discharges the charging capacitor 133 so that a capacitor voltage V _{CC of} the charging capacitor 133 rises or falls. The second comparator 134 is electrically connected to the charging capacitor 133, and the second comparator 134 outputs the pulse width modulation signal according to the potential levels of the capacitor voltage V _CC and the ripple voltage V _ramp of the charging capacitor 133 PWM. The delayer 135 receives the inverted PWM signal PWM for delay, the low level shifter 136 receives a delay signal S _delay output from the delay 135 for level shifting, and the low level shifter 136 The limit voltage V _{limit is} output to the first comparator 131.

Referring to FIG. 4, the charge-discharge selection circuit 132 has a first switch 132a, a second switch 132b, and an inverter 132c. The gate of the first switch 132a is electrically connected to the first comparator 131 to receive The first comparison signal comp1 is controlled by the first comparison signal comp1, the gate of the second switch 132b receives the inverted first comparison signal comp1 through the inverter 132c and receives the inverted first comparison signal Comp1 control. In this embodiment, both the first switch 132a and the second switch 132b are NMOS transistors. Due to the signal control of opposite phases to each other, when the first switch 132a is turned on, the second switch 132b is turned off When the first switch 132a is turned off, the second switch 132b is turned on. When the sense voltage V _{sense is} less than the limit voltage V _limit , the first comparison signal comp1 output by the first comparator 131 is at a high level, turning on the first switch 132a and turning off the second switch 132b. when a charging current I _C of the first switch 132a of the capacitor 133 is charged via the charging, the capacitor voltage V _cc so that the charging capacitor 133 rises slowly. In contrast, when the sense voltage V _{sense is} greater than the limit voltage V _limit , the first comparison signal comp1 output by the first comparator 131 is at a low level, and the first switch 132a is turned off and the second switch 132b is turned on. At this time, the second switch 132b provides a discharge current I _DISS to discharge the charging capacitor 133, so that the rising speed of the capacitor voltage V _{CC of} the charging capacitor 133 is slowed or decreased, and then compared by the second comparator 134 After the magnitudes of the capacitor voltage V _CC and the ripple voltage V _ramp of the charging capacitor 133, the pulse width modulation signal PWM with a variable duty cycle can be output, and the pulse width modulation signal can be modulated by the pulse width The PWM control keeps the output current of the charging and discharging unit 113 at a constant current.

Referring to FIGS. 2 and 5, the constant voltage mode control unit 140 has a third comparator 141, a flip-flop 142, and a certain voltage control or gate 143. The third comparator 141 receives the battery module B The battery voltage V _BAT and the full voltage V _full , wherein the full voltage V _full is set by the rated voltage of the battery module B, the third comparator 141 compares the battery voltage V _BAT with the full voltage V _full And output a third comparison signal comp3. The input terminal of the flip-flop 142 is electrically connected to the third comparator 141 to receive the third comparison signal comp3, the clock input terminal of the flip-flop 142 receives the clock signal Clk, and the flip-flop 142 is based on the The third comparison signal comp3 and the clock signal Clk output a flip-flop output signal S _FF , the constant voltage control or gate 143 is electrically connected to the flip-flop 142, and the constant voltage control or gate 143 is based on the flip-flop The output signal S _FF and the clock signal Clk output the pulse frequency modulation signal PFM.

Please refer to FIGS. 2 and 5, before the battery voltage V _{BAT of} the battery module B has not reached the full voltage V _full , the third comparison signal comp3 output by the third comparator 141 is at a low potential, making the constant The potential change of the pulse frequency modulation signal PFM output by the voltage control or gate 143 is the same as the clock signal Clk, and since the duty cycle of the clock signal Clk is very small, the OR gate 150 receives the pulse width modulation and the PWM signal of the PFM pulse frequency modulation signal, the pulse frequency modulation signal is masked to the PFM pulse width modulation signal PWM, so that the same with the pulse width modulation signal PWM control signal S _C to the potential change. When the battery voltage V _BAT of the battery module B reaches the full voltage V _full , the third comparison signal comp3 output by the third comparator 141 is at a high level, so that the flip-flop output signal S _FF is The long logic 1 signal shields the clock signal Clk, so that the pulse frequency modulation signal PFM output by the constant voltage control or gate 143 is also a longer logic 1 signal, and the OR gate 150 receives the pulse width modulation signal after the PWM and PFM pulse frequency modulation signal, the pulse width modulation signal PWM is a pulse frequency modulation signal of the PFM shield, so that the same frequency of the pulse modulation signal of the PFM control signal S _C of the potential change, thereby In the present invention, only one OR gate 150 can be used to switch between two modes of the charging system, thereby reducing the possible loss caused by switching between the two modes and improving the overall efficiency.

See FIGS. 2 and 6, the non-overlap 114 electrically connected to the OR gate circuit 150 to receive the control signal S _C, and the non-overlap circuit 114 outputs the first control signal S _{a C1} and the second control signal S _C2 to the first power switch 111 and the second power switch 112, wherein the non-overlapping circuit 114 makes the first control signal S _C1 turn on the first power switch 111 longer than the first through the two inverter strings Two control signals S _C2 turn off the time of the second power switch 112, so that the switching times of the first power switch 111 and the second power switch 112 are staggered to avoid the simultaneous operation of the first power switch 111 and the second power switch 112 the conducting a large input voltage V _in the second current switch 111 and power switch 112 is grounded via the first power, the power loss caused problems burning occurs or the power switch.

Please refer to FIGS. 2 and 7, in order to avoid the reverse current generated by the second power switch 112, the PWM/PFM dual-mode charging system 100 detects the voltage of the node V _X by the zero current detection circuit 115, and can When the voltage of the node V _X is zero, the second power switch 112 is turned off. In the present embodiment, the zero current detection circuit 115 is electrically connected to the second power switch 112 and the non-overlap circuit 114, 114 so that the output of the non-overlap circuit of the second control signal S _C2 of the zero current detection via The circuit 115 is transmitted to the second power switch 112. The zero current detection circuit 115 has a flip-flop 115a, a gate 115b and a comparator 115c. The comparator 115c is electrically connected to the node V _X and connects the node The voltage of V _X is compared with the zero potential of ground. One reset terminal of the flip-flop 115a is electrically connected to the comparator 115c, and the gate 115b is electrically connected to the flip-flop 115a and the non-overlapping circuit 114, wherein When the voltage of the node V _X drops to zero, the flip-flop 115a is reset, so that the gate 115b outputs a low potential and immediately closes the second power switch 112, so as to prevent the second power switch 112 from generating a reverse current.

Please refer to FIGS. 2 and 8 for a circuit diagram of a triangular wave and clock generator 160 according to this embodiment. The triangular wave and clock generator 160 has a capacitor 161, a transistor string 162 and a logic circuit 163. The transistor string 162 generates a bias current to charge the capacitor 161 so that the voltage of the capacitor 161 rises, and when the voltage of the capacitor 161 is greater than a high potential level _VH received by the logic circuit 163, the logic circuit 163 A fourth comparator 163a outputs a low potential, so that the clock signal Clk output by the logic circuit 163 is a high potential. At this time, the clock signal Clk turns off one of the PMOS transistors 162a of the transistor string 162 and turns on The NMOS transistor 162b allows the capacitor 161 to quickly discharge and the voltage drops. When the voltage of the capacitor 161 is less than a low potential level V _L received by the logic circuit 163, a fifth comparator 163b of the logic circuit 163 outputs low Potential, making the clock signal Clk output by the logic circuit 163 low, turning on the PMOS transistor 162a of the transistor string 162 and turning off the NMOS transistor 162b, and recharging the capacitor 161 and repeating the above charging In the discharging step, the ripple voltage V _{ramp is} output by the capacitor 161, and the clock signal Clk is output by the logic circuit 163. In addition, the logic circuit 163 also receives a reset signal R to reset the triangle wave and the clock generator 160.

The present invention uses the constant current mode control unit 130 and the constant voltage mode control unit 140 Achieve PWM/PFM dual-mode charging control to avoid the problem of low efficiency in constant voltage mode, and achieve switching between the two modes by only one OR gate 150, which can reduce the loss when switching modes and improve The overall charging efficiency of the PWM/PFM dual-mode charging system 100.

The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. Any changes and modifications made by those who are familiar with this skill without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100‧‧‧PWM/PFM dual-mode charging system

110‧‧‧ Conversion circuit

111‧‧‧ First power switch

112‧‧‧The second power switch

113‧‧‧Charge and discharge unit

113a‧‧‧Inductance

113b‧‧‧Resistance

113c‧‧‧Capacitance

114‧‧‧Non-overlapping circuit

115‧‧‧ Zero current detection circuit

115a‧‧‧Pros and cons

115b‧‧‧ and gate

115c‧‧‧Comparator

116‧‧‧High level shifter

120‧‧‧current sensor

121‧‧‧Load

121a‧‧‧First transistor

121b‧‧‧Second transistor

122‧‧‧First Current Mirror

122a‧‧‧third transistor

122b‧‧‧The fourth transistor

123‧‧‧second current mirror

123a‧‧‧Fifth transistor

123b‧‧‧The sixth transistor

123c‧‧‧The seventh transistor

130‧‧‧ Constant current mode control unit

131‧‧‧ First comparator

132‧‧‧ Charge and discharge selection circuit

132a‧‧‧First switch

132b‧‧‧Second switch

132c‧‧‧Inverter

133‧‧‧Charging capacitor

134‧‧‧ Second Comparator

135‧‧‧delay

136‧‧‧Low level shifter

140‧‧‧ Constant voltage mode control unit

141‧‧‧The third comparator

142‧‧‧Pros and cons

143‧‧‧ Constant voltage control or gate

150‧‧‧ or gate

160‧‧‧triangle wave and clock generator

161‧‧‧Capacitance

162‧‧‧Transistor string

162a‧‧‧PMOS transistor

162b‧‧‧NMOS transistor

163‧‧‧Logic circuit

163a‧‧‧The fourth comparator

163b‧‧‧Fifth comparator

V _X , V _Y , V _Z ‧‧‧ nodes

V _BAT ‧‧‧ Battery voltage

V _sense ‧‧‧ sense voltage

PWM‧‧‧Pulse width modulation signal

PFM‧‧‧Pulse frequency modulation signal

S _C ‧‧‧Control signal

S _C1 ‧‧‧ First control signal

S _C2 ‧‧‧ Second control signal

V _limit ‧‧‧Limit voltage

comp1‧‧‧First comparison signal

V _full ‧‧‧ full voltage

comp3‧‧‧The third comparison signal

Clk‧‧‧clock signal

S _FF ‧‧‧ flip-flop output signal

V _ramp ‧‧‧ ripple voltage

V _CC ‧‧‧ capacitor voltage

B‧‧‧Battery module

L1‧‧‧ First current loop

L2‧‧‧second current loop

S _delay ‧‧‧ Delay signal

I _C ‧‧‧ Charging current

I _DISS ‧‧‧ Discharge current

V _in ‧‧‧ input voltage

R‧‧‧Reset signal

V _H ‧‧‧High potential level

V _L ‧‧‧ Low level

Figure 1: A functional block diagram of a PWM/PFM dual-mode charging system according to an embodiment of the present invention.

Figure 2: According to one embodiment of the present invention, the circuit diagram of the PWM/PFM dual-mode charging system.

Figure 3: A circuit diagram of a current sensor according to an embodiment of the invention.

Fig. 4: A circuit diagram of a constant current mode control unit according to an embodiment of the invention.

Fig. 5: A circuit diagram of a certain voltage mode control unit according to an embodiment of the present invention.

Fig. 6: A circuit diagram of a non-overlapping circuit according to an embodiment of the invention.

Fig. 7: A circuit diagram of a zero current detection circuit according to an embodiment of the invention.

Figure 8: A circuit diagram of a triangle wave and clock generator according to an embodiment of the invention.

100‧‧‧PWM/PFM dual-mode charging system

110‧‧‧ Conversion circuit

120‧‧‧current sensor

130‧‧‧ Constant current mode control unit

140‧‧‧ Constant voltage mode control unit

150‧‧‧ or gate

V _in ‧‧‧ input voltage

B‧‧‧Battery module

S _C ‧‧‧Control signal

PWM‧‧‧Pulse width modulation signal

PFM‧‧‧Pulse frequency modulation signal

V _sense ‧‧‧ sense voltage

V _limit ‧‧‧Limit voltage

V _ramp ‧‧‧ ripple voltage

V _full ‧‧‧ full voltage

V _BAT ‧‧‧ Battery voltage

Clk‧‧‧clock signal

Claims (10)

A PWM/PFM dual-mode charging system, including: A conversion circuit has a first power switch, a second power switch and a charge and discharge unit, the charge and discharge unit is electrically connected to the first power switch and the second power switch, the conversion circuit is used to Group charging, wherein the battery module has a battery voltage; A current sensor coupled to the charge-discharge unit, the current sensor is used to sense a current of the charge-discharge unit, and the current sensor outputs a sense voltage; A certain current mode control unit is electrically connected to the current sensor to receive the sensing voltage, and the constant current mode control unit outputs a pulse according to the sensing voltage of the current sensor, a limiting voltage and a ripple voltage Width modulation signal; The constant voltage mode control unit outputs a pulse frequency modulation signal according to the battery voltage, a full voltage and a clock signal; and An OR gate, electrically connected to the constant current mode control unit and the constant voltage mode control unit to receive the pulse width modulation signal and the pulse frequency modulation signal, the OR gate outputs a control signal to control the conversion circuit The first power switch and the second power switch. The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the constant current mode control unit has a first comparator, a charge and discharge selection circuit, a charging capacitor and a second comparator, the first A comparator receives the sense voltage and the limit voltage, and the first comparator outputs a first comparison signal according to the sense voltage and the limit voltage, and the charge-discharge selection circuit is electrically connected to the first comparator, the The charge capacitor is electrically connected to the charge-discharge selection circuit, wherein the charge-discharge selection circuit selectively charges or discharges the charge capacitor according to the first comparison signal, the second comparator is electrically connected to the charge capacitor, and the second comparison The device outputs the pulse width modulation signal according to a capacitor voltage of the charging capacitor and the ripple voltage. The PWM/PFM dual-mode charging system as described in item 2 of the patent application scope, wherein the constant current mode control unit has a delay and a low level shifter, the delay receives the inverted pulse width modulation signal For delay, the low-level shifter is electrically connected to the delayer to receive a delay signal output by the delayer for level shifting, and the low-level shifter outputs the limiting voltage. The PWM/PFM dual-mode charging system as described in item 2 of the patent scope, wherein the charge-discharge selection circuit has a first switch and a second switch, the first switch receives the first comparison signal and receives the first comparison signal Controlled by a comparison signal, the second switch receives the inverted first comparison signal and is controlled by the inverted first comparison signal, wherein the first switch provides a charging current to charge the charging capacitor when the first switch is turned on, and the second switch When turned on, a discharge current is provided to discharge the charging capacitor. The PWM/PFM dual-mode charging system as described in item 4 of the patent application scope, wherein the charge-discharge selection circuit has an inverter, and the second switch is coupled to the first comparator via the inverter, so that the The inverter receives the inverted first comparison signal. The PWM/PFM dual-mode charging system as described in item 2 of the patent application scope, wherein the constant voltage mode control unit has a third comparator, a flip-flop and a certain voltage control or gate, and the third comparator receives the The battery voltage and the full voltage, the third comparator outputs a third comparison signal according to the battery voltage and the full voltage, the flip-flop is electrically connected to the third comparator, and the flip-flop is based on the third comparison signal And the clock signal outputs a flip-flop output signal, the constant voltage control or gate is electrically connected to the flip-flop, and the constant voltage control or gate outputs the pulse frequency according to the flip-flop output signal and the clock signal Modulation signal. The PWM/PFM dual-mode charging system as described in item 1 of the patent application scope further includes a triangular wave and clock generator with a capacitor, a transistor string and a logic circuit, the transistor string The capacitor is electrically connected, and the transistor string is used to selectively charge or discharge the capacitor, so that the capacitor generates the ripple voltage, the logic circuit is electrically connected to the capacitor, and the logic circuit is based on the capacitance of the capacitor The ripple voltage, a high level and a low level output the clock signal. The clock signal is used to control the transistor string to charge or discharge the capacitor. The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the current sensor has a load, a first current mirror, a second current mirror, and a current-voltage conversion loop, and the load has a first A transistor and a second transistor, the first current mirror has a third transistor and a fourth transistor, the second current mirror has a fifth transistor and a sixth transistor, the first transistor The crystal, the third transistor, and the fifth transistor constitute a first current loop, the second transistor, the fourth transistor, and the sixth transistor constitute a second current loop, and the current-voltage conversion loop electrically The second transistor is connected to the second current loop to capture a detection current and convert it into the sensing voltage, wherein the width ratio of the first transistor is the width ratio of the second transistor K Times. The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the conversion circuit has a non-overlapping circuit, the non-overlapping circuit is electrically connected to the OR gate to receive the control signal, and the non-overlapping circuit Respectively output a first control signal and a second control signal to the first power switch and the second power switch, wherein the first control signal and the second control signal enable the first power switch and the second power The switching times of the switches are staggered. The PWM/PFM dual-mode charging system as described in item 9 of the patent scope, wherein the conversion circuit has a zero current detection circuit, the zero current detection circuit is electrically connected to the second power switch and the non-overlapping circuit, The second control signal is transmitted to the second power switch through the zero current detection circuit.

Images