TWI516011B - Solar inverter and voltage transformation method thereof - Google Patents

Solar inverter and voltage transformation method thereof Download PDF

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TWI516011B
TWI516011B TW102104815A TW102104815A TWI516011B TW I516011 B TWI516011 B TW I516011B TW 102104815 A TW102104815 A TW 102104815A TW 102104815 A TW102104815 A TW 102104815A TW I516011 B TWI516011 B TW I516011B
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buck
voltage
signal
boost
modulation signal
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TW201433076A (en
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羅有綱
邱煌仁
鄭世仁
楊竣宇
陳致穎
劉承凱
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光寶科技股份有限公司
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Description

太陽能逆變器及其電壓轉換方法 Solar inverter and voltage conversion method thereof

本發明有關於一種太陽能逆變器,且特別是關於一種具有降壓模式與升壓模式之單級式太陽能逆變器。 The present invention relates to a solar inverter, and more particularly to a single stage solar inverter having a buck mode and a boost mode.

隨著工業和科技的蓬勃發展,人類對石化能源的消耗與日俱增,而地球的自然資源卻是有限。為了避免過度使用石化能源而造成能源的匱乏和環境生態的嚴重破壞,各國政府開始提倡節約能源。除了節約能源之外,人們也開始積極的尋找替代能源方案,太陽能、風能和生質能都是研究目標。其中,又以太陽能最被大家看好。因為太陽能取之不盡用之不竭,轉換電能的過程乾淨無污染,所以自然而然也最多人投入研究。 With the vigorous development of industry and technology, human consumption of petrochemical energy is increasing day by day, while the earth's natural resources are limited. In order to avoid the lack of energy and the serious damage to the environment and ecology caused by excessive use of petrochemical energy, governments have begun to promote energy conservation. In addition to saving energy, people are also actively looking for alternative energy solutions. Solar energy, wind energy and biomass energy are all research goals. Among them, solar energy is most favored by everyone. Because the inexhaustible use of solar energy, the process of converting electrical energy is clean and pollution-free, so naturally the most people invest in research.

一個典型的太陽能光電系統組成為太陽能電池模組和逆變器。太陽能電池模組將太陽光線以直流電壓的形式轉化為電能;逆變器將太陽能電池模組產生的直流電壓轉換成可送至電網的交流電壓。 A typical solar photovoltaic system consists of a solar cell module and an inverter. The solar cell module converts the sun's rays into electric energy in the form of a direct current voltage; the inverter converts the direct current voltage generated by the solar cell module into an alternating voltage that can be sent to the grid.

太陽能光電系統在高瓦特數的規格需求,會由多塊的太陽能電池模組串並聯起來使用,達到太陽能電池模組所需之輸出規格,後端再串接逆變器將直流電轉換成交流電輸出。而傳統的多階串式逆變器(Multi-String Inverter)可分為兩級,第一級是將太陽能電池模組轉化輸出的直流電壓經過一個升壓轉換器或一個降壓轉換器,目的是將太陽能 電池模組輸出的直流電轉換成第二級所需要的輸入電壓,得到所需的輸入電壓後,第二級再以正弦脈波寬度調變(Sinusoidal Pulse Width Modulation)訊號控制全橋電路,將直流電壓轉換成寬度不依的方波,最後經濾波電路,將交流電壓輸出。 In the high-wattage specification of solar photovoltaic systems, multiple solar cell modules are connected in series to achieve the output specifications required by the solar cell module, and the back-end inverters convert the direct current into alternating current output. . The traditional multi-string inverter (Multi-String Inverter) can be divided into two stages. The first stage is to convert the DC voltage converted by the solar cell module to a boost converter or a buck converter. Is going to solar energy The DC output from the battery module is converted into the input voltage required by the second stage to obtain the required input voltage. The second stage then controls the full bridge circuit with a sinusoidal pulse width modulation (Sinusoidal Pulse Width Modulation) signal. The voltage is converted into a square wave whose width does not depend, and finally the AC voltage is output through the filter circuit.

由於傳統的逆變器需要兩級的電路來達成市電網路所需的交流電壓值,電路迴路經過的元件越多,在元件上的總損耗也就更大,這是造成傳統逆變器效率不高的主要原因,且電路元件數多,成本固然也就提高,也就使太陽能光電系統價格無法有效降低。 Since the traditional inverter requires two stages of circuits to achieve the AC voltage value required by the city grid circuit, the more components the circuit loop passes through, the greater the total loss on the components, which is the efficiency of the conventional inverter. The main reason for not being high, and the number of circuit components is large, the cost is certainly increased, and the price of the solar photovoltaic system cannot be effectively reduced.

有鑑於此,本揭露內容提供一種具有偽直流鏈(pseudo DC link)的太陽能逆變器,太陽能逆變器透過直流/直流轉換器去做最大功率追蹤和調變輸出為全波整流後的全波脈波。之後,再讓後級的交流/直流逆變器(或稱極性選擇器)去簡單的還原成有正負半週的正弦波輸出至交流電網。 In view of this, the present disclosure provides a solar inverter with a pseudo DC link, and the solar inverter performs maximum power tracking and modulation output through a DC/DC converter for full-wave rectification. Wave wave. After that, the AC/DC inverter (or polarity selector) of the latter stage is simply restored to a positive and negative half-cycle sine wave output to the AC grid.

本發明實施例提供一種太陽能逆變器,太陽能逆變器包括升降壓轉換器、隔離變壓器、全波整流器與極性選擇器。升降壓轉換器接收輸入電壓、降壓調變信號與升壓調變信號,其中升降壓轉換器根據降壓調變信號與升壓調變信號來調變輸入電壓,並且據此輸出波形調整信號,當升降壓轉換器在降壓模式下根據降壓調變信號將輸入電壓予以逐步降壓,當升降壓轉換器在升壓模式下根據升壓調變 信號將輸入電壓予以逐步升壓。隔離變壓器具有初級側與次級側,隔離變壓器電性連接升降壓轉換器,隔離變壓器用以電氣隔離,接收波形調整信號且輸出已隔離的波形調整信號。全波整流器電性連接隔離變壓器,全波整流器將已隔離的波形調整信號予以全波整流,並且據此輸出全波脈波信號。極性選擇器電性連接全波整流器,極性選擇器將全波脈波信號之後半週波形予以極性反轉,並且據此輸出市電正弦波信號。 Embodiments of the present invention provide a solar inverter including a buck-boost converter, an isolation transformer, a full-wave rectifier, and a polarity selector. The buck-boost converter receives the input voltage, the buck modulation signal and the boost modulation signal, wherein the buck-boost converter modulates the input voltage according to the buck modulation signal and the boost modulation signal, and outputs a waveform adjustment signal accordingly When the buck-boost converter is stepping down the input voltage according to the buck modulation signal in the buck mode, when the buck-boost converter is in boost mode according to the boost modulation The signal boosts the input voltage step by step. The isolation transformer has a primary side and a secondary side, and the isolation transformer is electrically connected to the buck-boost converter. The isolation transformer is used for electrical isolation, receives the waveform adjustment signal, and outputs the isolated waveform adjustment signal. The full-wave rectifier is electrically connected to the isolation transformer, and the full-wave rectifier rectifies the isolated waveform adjustment signal, and outputs a full-wave pulse signal accordingly. The polarity selector is electrically connected to the full-wave rectifier, and the polarity selector reverses the polarity of the waveform of the half-cycle of the full-wave pulse signal, and outputs a commercial sine wave signal accordingly.

在本發明其中一個實施例中,其中當升降壓轉換器在升壓模式時,則降壓調變信號之責任週期為100%並且升壓調變信號之責任週期大於50%。 In one of the embodiments of the present invention, wherein the buck-boost converter is in the boost mode, the duty cycle of the buck modulation signal is 100% and the duty cycle of the boost modulation signal is greater than 50%.

在本發明其中一個實施例中,其中當升降壓轉換器在降壓模式時,則降壓調變信號之責任週期小於100%並且升壓調變信號之責任週期等於門檻責任週期,其中門檻責任週期為使得升降壓轉換器正常運作之最小責任週期。 In one embodiment of the present invention, wherein when the buck-boost converter is in the buck mode, the duty cycle of the buck modulation signal is less than 100% and the duty cycle of the boost modulation signal is equal to the threshold duty cycle, wherein the threshold responsibility The period is the minimum duty cycle for the buck-boost converter to function properly.

在本發明其中一個實施例中,其中升降壓轉換器更電性連接至數位信號處理晶片,當預設定正弦波之電壓大於邊界電壓時,則升降壓轉換器處於升壓模式,當預設定正弦波之電壓小於邊界電壓時,則升降壓轉換器處於降壓模式。 In one embodiment of the present invention, wherein the buck-boost converter is more electrically connected to the digital signal processing chip, when the voltage of the preset sine wave is greater than the boundary voltage, the buck-boost converter is in the boost mode when the sine is preset. When the voltage of the wave is less than the boundary voltage, the buck-boost converter is in the buck mode.

在本發明其中一個實施例中,其中在升壓模式下,當第一三角波信號之電壓大於預設定正弦波之電壓時,則數位信號處理晶片輸出高準位電壓之升壓調變信號至升降壓轉換器;當第一三角波信號之電壓小於預設定正弦波之電壓時,則數位信號處理晶片輸出低準位電壓之升壓調變信號至升降壓轉換器。 In one embodiment of the present invention, in the boost mode, when the voltage of the first triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a boost signal of the high level voltage to the rise and fall. The voltage converter; when the voltage of the first triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs a boost modulation signal of the low level voltage to the buck-boost converter.

在本發明其中一個實施例中,其中在降壓模式下,當第二三角波信號之電壓大於預設定正弦波之電壓時,則數位信號處理晶片輸出高準位電壓之降壓調變信號至升降壓轉換器;當第二三角波信號之電壓小於預設定正弦波之電壓時,則數位信號處理晶片輸出低準位電壓之降壓調變信號至升降壓轉換器。 In one embodiment of the present invention, in the step-down mode, when the voltage of the second triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a step-down modulated signal of the high level voltage to the rise and fall. The voltage converter; when the voltage of the second triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs a step-down modulation signal of the low level voltage to the buck-boost converter.

在本發明其中一個實施例中,其中極性選擇器之工作頻率為市電頻率,且其所輸出之正弦波信號為市電頻率,其中極性選擇器電性連接至交流電網。 In one embodiment of the invention, wherein the polarity selector operates at a mains frequency and the sine wave signal it outputs is a mains frequency, wherein the polarity selector is electrically coupled to the AC grid.

在本發明其中一個實施例中,升降壓轉換器包括第一電晶體、第二電晶體、第三電晶體與第四電晶體。第一電晶體之閘極接收第一脈寬調變信號,第一電晶體之源極連接隔離變壓器之初級側之繞組。第二電晶體之閘極接收第二脈寬調變信號,第二電晶體之汲極連接至第一電晶體之源極。第三電晶體之閘極接收第三脈寬調變信號,第三電晶體之汲極連接第一電晶體之汲極與升降壓電感之第一端,第三電晶體之源極連接隔離變壓器之初級側之繞組。第四電晶體之閘極接收第四脈寬調變信號,第四電晶體之汲極連接第三電晶體之源極,第四電晶體之源極連接第二電晶體之源極與第一接地電壓。第一至第四脈寬調變信號為升壓調變信號,並且當在升壓模式時,第一至第四脈寬調變信號之所對應的責任週期大於50%,以將輸入電壓逐步升壓;當在降壓模式時,第一至第四脈寬調變信號之所對應的責任週期等於門檻責任週期,以維持升降壓轉換器正常運作。 In one embodiment of the invention, the buck-boost converter includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor receives the first pulse width modulation signal, and the source of the first transistor is connected to the winding of the primary side of the isolation transformer. The gate of the second transistor receives the second pulse width modulation signal, and the drain of the second transistor is coupled to the source of the first transistor. The gate of the third transistor receives the third pulse width modulation signal, and the drain of the third transistor is connected to the first end of the first transistor and the first end of the buck-boost inductor, and the source connection of the third transistor is isolated The winding on the primary side of the transformer. The gate of the fourth transistor receives the fourth pulse width modulation signal, the drain of the fourth transistor is connected to the source of the third transistor, and the source of the fourth transistor is connected to the source of the second transistor and the first Ground voltage. The first to fourth pulse width modulation signals are boost modulation signals, and when in the boost mode, the duty cycle corresponding to the first to fourth pulse width modulation signals is greater than 50% to gradually input the input voltage Boost; when in the buck mode, the duty cycle corresponding to the first to fourth pulse width modulation signals is equal to the threshold duty cycle to maintain the buck-boost converter in normal operation.

在本發明其中一個實施例中,升降壓轉換器更包括降 壓電晶體與降壓二極體。降壓電晶體之閘極接收降壓調變信號,降壓電晶體之汲極連接輸入電壓,降壓電晶體之源極連接升降壓電感之第二端。降壓二極體之陽極連接第一接地電壓,降壓二極體之陰極連接降壓電晶體之源極。當在升壓模式時,降壓調變信號之責任週期為100%以導通降壓電晶體,當在降壓模式時,降壓調變信號之責任週期小於100%以將該輸入電壓逐步降壓。 In one embodiment of the invention, the buck-boost converter further includes a drop Piezoelectric crystals and a step-down diode. The gate of the step-down transistor receives the step-down modulation signal, the drain of the step-down transistor is connected to the input voltage, and the source of the step-down transistor is connected to the second end of the step-up and step-down inductor. The anode of the step-down diode is connected to the first ground voltage, and the cathode of the step-down diode is connected to the source of the step-down transistor. When in the boost mode, the duty cycle of the buck modulation signal is 100% to turn on the buck transistor. When in the buck mode, the duty cycle of the buck modulation signal is less than 100% to gradually reduce the input voltage. Pressure.

在本發明其中一個實施例中,全波整流器包括第一二極體、第二二極體、第三二極體、第四二極體與電容。第一二極體之陽極連接第二接地電壓。第二二極體之陽極連接第一二極體之陽極。第三二極體之陽極連接第一二極體之陰極與隔離變壓器之次級側之繞組。第四二極體之陽極連接第二二極體之陰極與隔離變壓器之次級側之繞組,第四二極體之陰極連接第三二極體之陰極。電容之第一端連接第三二極體之陰極,電容之第二端連接第二接地電壓。其中第一至第四二極體用以將已隔離之波形調整信號予以全波整流,並且據此輸出全波脈波信號。 In one embodiment of the invention, the full wave rectifier includes a first diode, a second diode, a third diode, a fourth diode, and a capacitor. The anode of the first diode is connected to the second ground voltage. The anode of the second diode is connected to the anode of the first diode. The anode of the third diode is connected to the cathode of the first diode and the winding of the secondary side of the isolation transformer. The anode of the fourth diode is connected to the cathode of the second diode and the winding of the secondary side of the isolation transformer, and the cathode of the fourth diode is connected to the cathode of the third diode. The first end of the capacitor is connected to the cathode of the third diode, and the second end of the capacitor is connected to the second ground voltage. The first to fourth diodes are used for full-wave rectifying the isolated waveform adjustment signal, and thereby outputting a full-wave pulse signal.

在本發明其中一個實施例中,極性選擇器包括第一矽控開關、第二矽控開關、第三矽控開關與第四矽控開關。第一矽控開關之第一端連接電容之第一端,第一矽控開關之控制端接收第一控制信號並據此決定導通或斷開狀態。第二矽控開關之第一端連接第一矽控開關之第二端與交流電網之正端,第二矽控開關之第二端連接第二接地電壓,第二矽控開關之控制端接收第二控制信號並據此決定導通或斷開狀態。第三矽控開關之第一端連接電容之第一端,第三矽控開關之控制端接收第三控制信號並據此決定導通 或斷開狀態。第四矽控開關之第一端連接第三矽控開關之第二端與交流電網之負端,第四矽控開關之第二端連接第二接地電壓,第四矽控開關之控制端接收第四控制信號並據此決定導通或斷開狀態。其中該第一與該第四矽控開關之導通或斷開狀態相同,該第二與該第三矽控開關之導通或斷開狀態相同,並且該第一與該第二矽控開關之導通或斷開狀態相反。 In one embodiment of the invention, the polarity selector comprises a first tamper switch, a second tamper switch, a third tamper switch and a fourth tamper switch. The first end of the first switch is connected to the first end of the capacitor, and the control end of the first switch receives the first control signal and determines the on or off state accordingly. The first end of the second control switch is connected to the second end of the first control switch and the positive end of the AC power grid, the second end of the second control switch is connected to the second ground voltage, and the control end of the second control switch receives The second control signal determines the on or off state accordingly. The first end of the third tamping switch is connected to the first end of the capacitor, and the control end of the third tamping switch receives the third control signal and determines the conduction according to the third end Or disconnected state. The first end of the fourth tamper switch is connected to the second end of the third tamper switch and the negative end of the AC power grid, and the second end of the fourth tamper switch is connected to the second ground voltage, and the control end of the fourth tamper switch receives The fourth control signal determines the on or off state accordingly. The first and the fourth switch are in the same state of being turned on or off, the second and the third switch are in the same state of being turned on or off, and the first and the second switch are turned on. Or the reverse state is reversed.

本發明實施例另提供一種電壓轉換方法,用於太陽能逆變器。電壓轉換方法包括以下步驟:接收輸入電壓、降壓調變信號與升壓調變信號,其中根據降壓調變信號與升壓調變信號來調變輸入電壓,並且據此輸出波形調整信號;將已隔離的波形調整信號予以全波整流,並且據此輸出全波脈波信號;以及將全波脈波信號之後半週波形予以極性反轉,並且據此輸出市電正弦波信號。其中在降壓模式,根據降壓調變信號將輸入電壓予以逐步降壓,並且在升壓模式,根據該升壓調變信號將該輸入電壓予以逐步升壓。 Another embodiment of the present invention provides a voltage conversion method for a solar inverter. The voltage conversion method includes the steps of: receiving an input voltage, a step-down modulation signal, and a step-up modulation signal, wherein the input voltage is modulated according to the step-down modulation signal and the step-up modulation signal, and the waveform adjustment signal is output according to the signal; The isolated waveform adjustment signal is full-wave rectified, and the full-wave pulse signal is output according to this; and the waveform of the half-cycle of the full-wave pulse signal is reversed, and the commercial sine wave signal is output accordingly. In the buck mode, the input voltage is stepped down according to the buck modulation signal, and in the boost mode, the input voltage is stepped up according to the boost modulation signal.

綜上所述,本發明實施例所提出之太陽能逆變器及其電壓轉換方法,透過升降壓轉換器的升壓模式與降壓模式,能夠將太陽能逆變器所接收到的輸入電壓轉換為市電正弦波信號,在高功率下達到優良的轉換效率。再者,本揭露內容能夠降低電路設計的複雜度以進一步節省元件數量與電路設計成本。 In summary, the solar inverter and the voltage conversion method thereof according to the embodiments of the present invention can convert the input voltage received by the solar inverter into a boost mode and a buck mode through the buck-boost converter. The mains sine wave signal achieves excellent conversion efficiency at high power. Moreover, the present disclosure can reduce the complexity of circuit design to further save component count and circuit design cost.

為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作 任何的限制。 The detailed description of the present invention and the accompanying drawings are to be understood by the claims Scope Any restrictions.

在下文將參看隨附圖式更充分地描述各種例示性實施例,在隨附圖式中展示一些例示性實施例。然而,本發明概念可能以許多不同形式來體現,且不應解釋為限於本文中所闡述之例示性實施例。確切而言,提供此等例示性實施例使得本發明將為詳盡且完整,且將向熟習此項技術者充分傳達本發明概念的範疇。在諸圖式中,可為了清楚而誇示層及區之大小及相對大小。類似數字始終指示類似元件。 Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

應理解,雖然本文中可能使用術語第一、第二、第三等來描述各種元件,但此等元件不應受此等術語限制。此等術語乃用以區分一元件與另一元件。因此,下文論述之第一元件可稱為第二元件而不偏離本發明概念之教示。如本文中所使用,術語「及/或」包括相關聯之列出項目中之任一者及一或多者之所有組合。 It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

〔太陽能逆變器的實施例〕 [Embodiment of Solar Inverter]

請參照圖1,圖1為根據本發明實施例之太陽能逆變器之區塊示意圖。如圖1所示,太陽能逆變器100包括升降壓轉換器110、隔離變壓器120、全波整流器130與極性選擇器140。升降壓轉換器110電性連接隔離變壓器120。隔離變壓器120電性連接至升降壓轉換器110與全波整流器130之間。全波整流器130電性連接極性選擇器140。 Please refer to FIG. 1. FIG. 1 is a block diagram of a solar inverter according to an embodiment of the invention. As shown in FIG. 1, the solar inverter 100 includes a buck-boost converter 110, an isolation transformer 120, a full-wave rectifier 130, and a polarity selector 140. The buck-boost converter 110 is electrically connected to the isolation transformer 120. The isolation transformer 120 is electrically connected between the buck-boost converter 110 and the full-wave rectifier 130. The full wave rectifier 130 is electrically connected to the polarity selector 140.

關於升壓降轉換器110,升降壓轉換器110接收輸入電壓VIN、降壓調變信號BU與升壓調變信號BST,其中升 降壓轉換器110根據降壓調變信號BU與升壓調變信號BST來調變輸入電壓VIN,並且據此輸出波形調整信號WS,其中升降壓轉換器110在降壓模式下,根據降壓調變信號BU將輸入電壓VIN予以逐步降壓,並且升降壓轉換器110在升壓模式下,根據升壓調變信號BST將輸入電壓VIN予以逐步升壓。在本實施例中,輸入電壓VIN為太陽能面板的輸出電壓。 Regarding the boost converter 110, the buck-boost converter 110 receives the input voltage VIN, the buck modulation signal BU, and the boost modulation signal BST, where The buck converter 110 modulates the input voltage VIN according to the buck modulation signal BU and the boost modulation signal BST, and accordingly outputs the waveform adjustment signal WS, wherein the buck-boost converter 110 is in the buck mode, according to the buck. The modulation signal BU gradually steps down the input voltage VIN, and the step-up and step-down converter 110 gradually boosts the input voltage VIN according to the boost modulation signal BST in the boost mode. In this embodiment, the input voltage VIN is the output voltage of the solar panel.

關於隔離變壓器120,隔離變壓器120具有初級側與次級側,所述隔離變壓器120用以電氣隔離以達到安全之目的,並且隔離變壓器120接收波形調整信號WS且對應地輸出已隔離的波形調整信號WS’。 Regarding the isolation transformer 120, the isolation transformer 120 has a primary side and a secondary side, the isolation transformer 120 is used for electrical isolation for safety purposes, and the isolation transformer 120 receives the waveform adjustment signal WS and correspondingly outputs the isolated waveform adjustment signal. WS'.

關於全波整流器130,全波整流器130將已隔離的波形調整信號WS’予以全波整流,並且據此輸出全波脈波信號AS。 Regarding the full-wave rectifier 130, the full-wave rectifier 130 fully-wave rectifies the isolated waveform adjustment signal WS', and accordingly outputs the full-wave pulse signal AS.

關於極性選擇器140,極性選擇器140將全波脈波信號AS之後半週波形予以極性反轉,並且據此輸出市電正弦波信號VOUT至一交流電網(圖1未繪示),其中極性選擇器140為工作於市電頻率,並且在零點交越時進行切換。 Regarding the polarity selector 140, the polarity selector 140 reverses the polarity of the waveform of the half-cycle of the full-wave pulse signal AS, and outputs the commercial sine wave signal VOUT to an AC power grid (not shown in FIG. 1), wherein the polarity is selected. The device 140 operates at the mains frequency and switches when the zero crossing occurs.

接下來要教示的,是進一步說明太陽能逆變器110的工作原理。 What is to be taught next is to further explain the working principle of the solar inverter 110.

請繼續參照圖1,當升降壓轉換器110接收到太陽能面板的輸出電壓時,亦即升降壓轉換器110接收到輸入電壓VIN時,升降壓轉換器110會利用一電壓調變轉換機制將輸入電壓VIN進行調變。進一步來說,在降壓模式下,升降壓轉換器110會透過其所接收之降壓調變信號BU將輸入電壓VIN逐步降壓,此外,在升壓模式下,升降壓轉換器 110會透過其所接收之升壓調變信號BST將輸入電壓VIN逐步升壓。值得一提的是,在本實施例中,為了使太陽能逆變器100能夠正常運作,當升降壓轉換器110在升壓模式時,則降壓調變信號BU之責任週期為100%並且升壓調變信號BST之責任週期大於50%。當升降壓轉換器110在降壓模式時,則降壓調變信號BU之責任週期小於100%並且升壓調變信號BST之責任週期等於門檻責任週期,其中門檻責任週期是為了使得升降壓轉換器110能夠正常運作之最小責任週期。 Referring to FIG. 1 , when the buck-boost converter 110 receives the output voltage of the solar panel, that is, when the buck-boost converter 110 receives the input voltage VIN, the buck-boost converter 110 uses a voltage modulation conversion mechanism to input the voltage. The voltage VIN is modulated. Further, in the buck mode, the buck-boost converter 110 gradually steps down the input voltage VIN through the buck modulation signal BU it receives. In addition, in the boost mode, the buck-boost converter The 110 will gradually boost the input voltage VIN through the boost modulation signal BST it receives. It is worth mentioning that, in this embodiment, in order to enable the solar inverter 100 to operate normally, when the step-up/down converter 110 is in the boost mode, the duty cycle of the step-down modulation signal BU is 100% and rises. The duty cycle of the pressure modulation signal BST is greater than 50%. When the buck-boost converter 110 is in the buck mode, the duty cycle of the buck modulation signal BU is less than 100% and the duty cycle of the boost modulation signal BST is equal to the threshold duty cycle, wherein the threshold duty cycle is to enable buck-boost conversion The minimum duty cycle for the device 110 to function properly.

值得一提的是,在本實施例中,升壓降轉換器110更電性連接至數位信號處理晶片(圖1未繪示)。數位信號處理晶片中會接收輸入電壓VIN與輸入電流,與全波整流器130的輸出端之輸出電壓VOUT與輸出電流,以進一步調整升降壓轉換器110內部之機制並對應地輸出降壓調變信號BU與升壓調變信號BST,設計者可以透過韌體以便設計實際應用的需求。在數位信號處理晶片中,當預設定正弦波之電壓大於邊界電壓時,則表示升降壓轉換器110進入所謂的升壓模式;當預設定正弦波之電壓小於邊界電壓時,則表示升降壓轉換器110進入所謂的降壓模式。 It is worth mentioning that, in this embodiment, the step-down converter 110 is more electrically connected to the digital signal processing chip (not shown in FIG. 1). The digital signal processing chip receives the input voltage VIN and the input current, and the output voltage VOUT and the output current of the output of the full-wave rectifier 130 to further adjust the mechanism inside the buck-boost converter 110 and correspondingly output the buck modulation signal. BU and boost modulation signal BST, designers can use the firmware to design the needs of the actual application. In the digital signal processing chip, when the voltage of the preset sine wave is greater than the boundary voltage, it means that the buck-boost converter 110 enters a so-called boost mode; when the voltage of the preset sine wave is less than the boundary voltage, it means that the buck-boost conversion The device 110 enters a so-called buck mode.

在升壓模式(boost mode)下,當第一三角波信號之電壓大於預設定正弦波之電壓時,則數位信號處理晶片會輸出高準位電壓之升壓調變信號BST至升降壓轉換器110;當第一三角波信號之電壓小於預設定正弦波之電壓時,則數位信號處理晶片會輸出低準位電壓之升壓調變信號BST至升降壓轉換器110。在降壓模式(buck mode)下,當第二三角波信號之電壓大於預設定正弦波之電壓時,則數位信號處 理晶片輸出高準位電壓之降壓調變信號BU至升降壓轉換器110;當第二三角波信號之電壓小於預設定正弦波之電壓時,則數位信號處理晶片輸出低準位電壓之降壓調變信號BU至升降壓轉換器110。 In the boost mode, when the voltage of the first triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a boost signal BST of the high level voltage to the buck-boost converter 110. When the voltage of the first triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs the boost modulation signal BST of the low level voltage to the buck-boost converter 110. In the buck mode, when the voltage of the second triangular wave signal is greater than the voltage of the preset sine wave, the digital signal is The chip outputs a step-down modulation signal BU of the high-level voltage to the buck-boost converter 110; when the voltage of the second triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs a low-level voltage step-down The signal BU is modulated to the buck-boost converter 110.

須說明的是,邊界電壓、預設定正弦波之電壓、第一三角波之電壓與第二三角波之電壓都是可以透過韌體設計以內建於數位信號處理晶片內部之表格(table),而設計者可以根據實際應用需求來進一步修改。 It should be noted that the boundary voltage, the voltage of the preset sine wave, the voltage of the first triangular wave and the voltage of the second triangular wave are all designed by the firmware design to be built into the table inside the digital signal processing chip. Can be further modified according to actual application needs.

接下來,升降壓轉換器110會輸出一波形調整信號WS至隔離變壓器120,以透過隔離變壓器120來進行電氣隔離之工作。隔離變壓器120會對應地輸出已隔離的波形調整信號WS’至全波整流器130,以透過全波整流器130來將已隔離的波形調整信號WS’進行全波整流的工作,並且據此輸出全波脈波信號AS。之後,極性選擇器140會將全波脈波信號之後半週波形予以換向或極性反轉,並且據此輸出市電正弦波信號VOUT至交流電網以併入交流電網的能量供應系統。據此,本揭露內容能夠在提高電壓準位期間,同時產生弦波波形,因此在高功率下達到優良的轉換效率,亦即將太陽能面板所產生的電壓予以電壓轉換並且產生一正弦波信號以併入交流電網的能量供應系統。所以,本揭露內容能夠降低電路設計的複雜度以進一步節省元件數量與電路設計成本。 Next, the buck-boost converter 110 outputs a waveform adjustment signal WS to the isolation transformer 120 for electrical isolation through the isolation transformer 120. The isolation transformer 120 correspondingly outputs the isolated waveform adjustment signal WS' to the full-wave rectifier 130 to perform full-wave rectification of the isolated waveform adjustment signal WS' through the full-wave rectifier 130, and output a full-wave according thereto. Pulse signal AS. Thereafter, the polarity selector 140 reverses or reverses the waveform of the half-cycle of the full-wave pulse signal, and accordingly outputs the commercial sine wave signal VOUT to the AC grid to be incorporated into the energy supply system of the AC grid. Accordingly, the present disclosure can simultaneously generate a sine wave waveform during the voltage level increase, thereby achieving excellent conversion efficiency at high power, that is, voltage conversion of the voltage generated by the solar panel and generating a sine wave signal to Energy supply system into the AC grid. Therefore, the disclosure can reduce the complexity of the circuit design to further save component count and circuit design cost.

為了更詳細地說明本發明所述之太陽能逆變器100的運作流程,以下將舉多個實施例中至少之一來作更進一步的說明。 In order to explain in more detail the operational flow of the solar inverter 100 of the present invention, at least one of the following embodiments will be further described.

在接下來的多個實施例中,將描述不同於上述圖1實施例 之部分,且其餘省略部分與上述圖1實施例之部分相同。此外,為說明便利起見,相似之參考數字或標號指示相似之元件。 In the following various embodiments, an embodiment different from the above FIG. 1 will be described. Portions, and the remaining omitted portions are the same as those of the embodiment of Fig. 1 described above. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

〔太陽能逆變器的另一實施例〕 [Another embodiment of a solar inverter]

請參照圖2,圖2為根據本發明實施例之太陽能逆變器之區塊示意圖。與上述圖1實施例不同的是,在本實施例中,升降壓轉換器110包括第一電晶體Q1、第二電晶體Q2、第三電晶體Q3、第四電晶體Q4、降壓電晶體Qb、降壓二極體Db與升降壓電感Lb。全波整流器130包括第一二極體D1、第二二極體D2、第三二極體D3、第四二極體D4與電容Cr。極性選擇器140包括第一矽控開關S1、第二矽控開關S2、第三矽控開關S3與第四矽控開關S4。其中,太陽能逆變器200更包括一耦合電容Cin,並聯連接於輸入電壓VIN。 Please refer to FIG. 2. FIG. 2 is a block diagram of a solar inverter according to an embodiment of the present invention. Different from the above embodiment of FIG. 1, in the present embodiment, the buck-boost converter 110 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a step-down transistor. Qb, step-down diode Db and buck-boost inductor Lb. The full-wave rectifier 130 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a capacitor Cr. The polarity selector 140 includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4. The solar inverter 200 further includes a coupling capacitor Cin connected in parallel to the input voltage VIN.

其中,第一電晶體Q1、第二電晶體Q2、第三電晶體Q3、第四電晶體Q4與升降壓電感Lb在本實施例中為完成升壓模式(boost mode)的主要元件,而降壓電晶體Qb、降壓二極體Db與升降壓電感Lb在本實施例中為完成降壓模式(buck mode)的主要元件。 Wherein, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, and the step-up and step-down inductor Lb are main components for completing the boost mode in this embodiment, and The step-down transistor Qb, the step-down diode Db, and the step-up and step-down inductor Lb are the main components for completing the buck mode in this embodiment.

第一電晶體Q1之閘極接收第一脈寬調變信號BST1,第一電晶體Q1之源極連接隔離變壓器120之初級側之繞組。第二電晶體Q2之閘極接收第二脈寬調變信號BST2,第二電晶體Q2之汲極連接至第一電晶體Q1之源極。第三電晶體Q3之閘極接收第三脈寬調變信號BST3,第三電晶體Q3之汲極連接第一電晶體Q1之汲極與升降壓電感Lb之第一端,第三電晶體之源極連接隔離變壓器120之初級側之繞組。第四電晶體Q4之閘極接收第四脈寬調變信號BST4 ,第四電晶體Q4之汲極連接第三電晶體Q3之源極,第四電晶體Q4之源極連接第二電晶體Q2之源極與第一接地電壓GND1。其中,第一脈寬調變信號至第四脈寬調變信號BST1~BST4為升壓調變信號BST,並且當在升壓模式時,第一至第四脈寬調變信號BST1~BST4之所對應的責任週期大於50%以將輸入電壓VIN逐步升壓;當在降壓模式時,第一至第四脈寬調變信號BST1~BST4之所對應的責任週期等於一門檻責任週期,以維持升降壓轉換器110的正常運作。 The gate of the first transistor Q1 receives the first pulse width modulation signal BST1, and the source of the first transistor Q1 is connected to the winding of the primary side of the isolation transformer 120. The gate of the second transistor Q2 receives the second pulse width modulation signal BST2, and the drain of the second transistor Q2 is connected to the source of the first transistor Q1. The gate of the third transistor Q3 receives the third pulse width modulation signal BST3, and the drain of the third transistor Q3 is connected to the first end of the first transistor Q1 and the first end of the step-up and step-down inductor Lb, the third transistor The source is connected to the winding of the primary side of the isolation transformer 120. The gate of the fourth transistor Q4 receives the fourth pulse width modulation signal BST4 The drain of the fourth transistor Q4 is connected to the source of the third transistor Q3, and the source of the fourth transistor Q4 is connected to the source of the second transistor Q2 and the first ground voltage GND1. Wherein, the first pulse width modulation signal to the fourth pulse width modulation signal BST1~BST4 are the boost modulation signal BST, and when in the boost mode, the first to fourth pulse width modulation signals BST1~BST4 The corresponding duty cycle is greater than 50% to gradually increase the input voltage VIN; when in the buck mode, the duty cycle corresponding to the first to fourth pulse width modulation signals BST1 to BST4 is equal to a threshold duty cycle, The normal operation of the buck-boost converter 110 is maintained.

降壓電晶體Qb之閘極接收降壓調變信號BU,降壓電晶體Qb之汲極連接輸入電壓VIN,降壓電晶體Qb之源極連接升降壓電感Lb之第二端。降壓二極體Db之陽極連接第一接地電壓GND1,降壓二極體Db之陰極連接降壓電晶體Qb之源極。當在升壓模式時,降壓調變信號BU之責任週期為100%以導通降壓電晶體Qb,當在降壓模式時,降壓調變信號BU之責任週期小於100%以將輸入電壓VIN逐步降壓。 The gate of the step-down transistor Qb receives the step-down modulation signal BU, the drain of the step-down transistor Qb is connected to the input voltage VIN, and the source of the step-down transistor Qb is connected to the second end of the step-up and step-down inductor Lb. The anode of the step-down diode Db is connected to the first ground voltage GND1, and the cathode of the step-down diode Db is connected to the source of the step-down transistor Qb. When in the boost mode, the duty cycle of the buck modulation signal BU is 100% to turn on the buck transistor Qb, and when in the buck mode, the duty cycle of the buck modulation signal BU is less than 100% to input the voltage. VIN gradually steps down.

第一二極體D1之陽極連接第二接地電壓GND2。第二二極體D2之陽極連接第一二極體D1之陽極。第三二極體D3之陽極連接第一二極體D1之陰極與隔離變壓器120之次級側之繞組。第四二極體D4之陽極連接第二二極體D2之陰極與隔離變壓器120之次級側之繞組,第四二極體D4之陰極連接第三二極體D3之陰極。電容Cr之第一端連接第三二極體D3之陰極,電容Cr之第二端連接第二接地電壓GND2。其中,第一至第四二極體D1~D4用以將已隔離之波形調整信號WS’予以全波整流,並且據此輸出全波脈 波信號AS。 The anode of the first diode D1 is connected to the second ground voltage GND2. The anode of the second diode D2 is connected to the anode of the first diode D1. The anode of the third diode D3 is connected to the cathode of the first diode D1 and the winding of the secondary side of the isolation transformer 120. The anode of the fourth diode D4 is connected to the cathode of the second diode D2 and the winding of the secondary side of the isolation transformer 120, and the cathode of the fourth diode D4 is connected to the cathode of the third diode D3. The first end of the capacitor Cr is connected to the cathode of the third diode D3, and the second end of the capacitor Cr is connected to the second ground voltage GND2. The first to fourth diodes D1 to D4 are used for full-wave rectifying the isolated waveform adjustment signal WS', and according to the output of the full-wave pulse Wave signal AS.

第一矽控開關S1之第一端連接電容Cr之第一端,第一矽控開關S1之控制端接收第一控制信號CS1並據此決定導通或斷開狀態。第二矽控開關S2之第一端連接第一矽控開關S1之第二端與交流電網之正端,第二矽控開關S2之第二端連接第二接地電壓GND2,第二矽控開關S2之控制端接收第二控制信號CS2並據此決定導通或斷開狀態。第三矽控開關S3之第一端連接電容Cr之第一端,第三矽控開關S3之控制端接收第三控制信號CS3並據此決定導通或斷開狀態。第四矽控開關S4之第一端連接第三矽控開關S3之第二端與交流電網之負端,第四矽控開關S4之第二端連接第二接地電壓GND2,第四矽控開關S4之控制端接收第四控制信號CS4並據此決定導通或斷開狀態。其中第一矽控開關S1與第四矽控開關S4之導通或斷開狀態相同,第二矽控開關S2與第三矽控開關S3之導通或斷開狀態相同,並且第一矽控開關S1與第二矽控開關S2之導通或斷開狀態相反。 The first end of the first switch S1 is connected to the first end of the capacitor Cr, and the control end of the first switch S1 receives the first control signal CS1 and determines the on or off state accordingly. The first end of the second switch S2 is connected to the second end of the first switch S1 and the positive end of the AC power grid, and the second end of the second switch S2 is connected to the second ground voltage GND2, the second switch The control terminal of S2 receives the second control signal CS2 and determines the on or off state accordingly. The first end of the third switch S3 is connected to the first end of the capacitor Cr, and the control end of the third switch S3 receives the third control signal CS3 and determines the on or off state accordingly. The first end of the fourth control switch S4 is connected to the second end of the third control switch S3 and the negative end of the AC power grid, and the second end of the fourth control switch S4 is connected to the second ground voltage GND2, the fourth control switch The control terminal of S4 receives the fourth control signal CS4 and determines the on or off state accordingly. The first switch S1 and the fourth switch S4 are in the same state of being turned on or off, and the second switch S2 and the third switch S3 are in the same state of being turned on or off, and the first switch S1 is It is opposite to the on or off state of the second switch S2.

接下來要教示的,是進一步說明太陽能逆變器200的工作原理,並假設所有開關元件皆為理想元件。 What is to be taught next is to further explain the working principle of the solar inverter 200, and assume that all switching elements are ideal components.

請同時參照圖2~圖5,圖3為根據本發明實施例之驅動波形之示意圖。圖4為根據本發明實施例之升壓模式下之太陽能逆變器之電路示意圖。圖5為根據本發明實施例之降壓模式下之太陽能逆變器之電路示意圖。當預設定正弦波Vg的電壓大於邊界電壓Vb時,則升降壓轉換器110處於升壓模式。此時,當第一三角波信號VT1的電壓大於預設定正弦波Vg的電壓時,則數位信號處理晶片會輸出高 準位電壓之第一至第四脈寬調變信號BST1~BST4至對應的第一至第四電晶體Q1~Q4;當第一三角波信號VT1的電壓小於預設定正弦波Vg的電壓時,則數位信號處理晶片會輸出低準位電壓之之第一至第四脈寬調變信號BST1~BST4至對應的第一至第四電晶體Q1~Q4。 Please refer to FIG. 2 to FIG. 5 at the same time. FIG. 3 is a schematic diagram of driving waveforms according to an embodiment of the present invention. 4 is a circuit diagram of a solar inverter in a boost mode according to an embodiment of the invention. FIG. 5 is a circuit diagram of a solar inverter in a buck mode according to an embodiment of the invention. When the voltage of the preset sine wave Vg is greater than the boundary voltage Vb, the step-up and step-down converter 110 is in the boost mode. At this time, when the voltage of the first triangular wave signal VT1 is greater than the voltage of the preset sine wave Vg, the digital signal processing chip outputs a high output. The first to fourth pulse width modulation signals BST1 to BST4 of the level voltage are corresponding to the first to fourth transistors Q1 to Q4; when the voltage of the first triangular wave signal VT1 is less than the voltage of the preset sine wave Vg, The digital signal processing chip outputs first to fourth pulse width modulation signals BST1 to BST4 of the low level voltage to the corresponding first to fourth transistors Q1 to Q4.

當預設定正弦波Vg的電壓小於邊界電壓Vb時,則升降壓轉換器110處於降壓模式。此時,當第二三角波信號VT2的電壓大於預設定正弦波的電壓時,則數位信號處理晶片會輸出高準位電壓之降壓調變信號BU至降壓電晶體Qb,當第二三角波信號VT2的電壓小於預設定正弦波的電壓時,則數位信號處理晶片會輸出低準位電壓之降壓調變信號BU至降壓電晶體Qb。須注意的是,在降壓模式時,降壓調變信號BU之責任週期δbuck小於100%並且傳送至第一至第四電晶體Q1~Q4之的第一至第四脈寬調變信號BST1~BST4的責任週期δboos為一門檻責任週期δmin,而此門檻責任週期δmin而為了讓升降壓轉換器110正常運作的最小責任週期。 When the voltage of the preset sine wave Vg is less than the boundary voltage Vb, the step-up and step-down converter 110 is in the buck mode. At this time, when the voltage of the second triangular wave signal VT2 is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a step-down modulation signal BU of the high level voltage to the step-down transistor Qb, when the second triangular wave signal When the voltage of VT2 is less than the voltage of the preset sine wave, the digital signal processing chip outputs the step-down modulation signal BU of the low level voltage to the step-down transistor Qb. It should be noted that, in the buck mode, the duty cycle δbuck of the buck modulation signal BU is less than 100% and is transmitted to the first to fourth pulse width modulation signals BST1 of the first to fourth transistors Q1 to Q4. ~BST4's duty cycle δboos is a threshold duty cycle δmin, and this threshold duty cycle δmin is the minimum duty cycle for the buck-boost converter 110 to operate normally.

接下來要說明的是,關於太陽能逆變器200在升壓模式下的詳細說明。 Next, a detailed description of the solar inverter 200 in the boost mode will be described.

請同時參照圖6~圖10,圖6為根據本發明實施例之第一至第四脈寬調變信號之驅動波形圖。圖7~圖10為根據本發明實施例之升壓模式下太陽能逆變器之電路示意圖。在進行下述說明前,須說明的是,在此以一個開關週期作為範例說明以方便了解本揭露內容,但本揭露內容並不以一個開關週期作為限制。再者,在升壓模式時,降壓調變信號BU之責任週期δbuck為100%,所以降壓電晶體Qb 一直處於導通狀態,而第一至第四脈寬調變信號BST1~BS4的責任週期δboost大於50%。 Please refer to FIG. 6 to FIG. 10 simultaneously. FIG. 6 is a driving waveform diagram of first to fourth pulse width modulation signals according to an embodiment of the present invention. 7 to 10 are circuit diagrams of a solar inverter in a boost mode according to an embodiment of the present invention. Before the following description is made, it should be noted that a switching cycle is taken as an example to facilitate the understanding of the disclosure, but the disclosure is not limited by one switching cycle. Furthermore, in the boost mode, the duty cycle δbuck of the buck modulation signal BU is 100%, so the buck transistor Qb It is always in the on state, and the duty cycle δboost of the first to fourth pulse width modulation signals BST1 to BS4 is greater than 50%.

如圖7所示,在時間t0至t1的時間區間,第一至第四電晶體Q1~Q4根據所接收到之第一至第四脈寬調變信號BST1~BST4全被導通,因此升降壓電感Lb會開始進行儲能的工作。此時,隔離變壓器120的初級側會因為第一至第四電晶體Q1~Q4全被導通的關係以致於不會有能量傳送到隔離變壓器120的次級側,所以負載的能量全都交由全波整流器130中的電容Cr來提供。如圖8所示,在時間t1至t2的時間區間,在時間t1時,第二電晶體Q2與第三電晶體Q3根據其所接收到之第二與第三脈寬調變信號BST2、BST3而會被截止,而第一電晶體Q1與第四電晶體Q4則保持導通狀態。因此,儲存於升降壓電感Lb的能量會透過隔離變壓器120與全波整流器130中的第二二極體D2與第三二極體D3對電容Cr充電以儲能。接著,如圖9所示,在時間t2至t3的時間區間,第一至第四電晶體Q1~Q4根據所接收到之第一至第四脈寬調變信號BST1~BST4又全被導通,因此升降壓電感Lb又會開始進行儲能的工作。此時,隔離變壓器120的初級側會因為第一至第四電晶體Q1~Q4全被導通的關係以致於不會有能量傳送到隔離變壓器120的次級側,所以負載的能量全都交由全波整流器130中的電容Cr來提供,其中電流路徑與圖7實施例相同。之後,如圖10所示,在時間t3至t4的時間區間,在時間t3時,第一電晶體Q1與第四電晶體Q4會根據其所接收到之第一與第四脈寬調變信號BST1、BST4而會被截止,而第二電晶體Q2與第三電晶體Q3則保持導通狀 態。因此,儲存於升降壓電感Lb的能量會反向地通過隔離變壓器120與全波整流器130中的第四二極體D4與第一二極體D1對電容Cr充電以儲能。在接下來的開關週期中,應可理解太陽能逆變器200會不斷重複如上述圖7~圖10關於升壓模式的作動以調變輸入電壓VIN,在此則不再贅述。 As shown in FIG. 7, in the time interval from time t0 to t1, the first to fourth transistors Q1 to Q4 are all turned on according to the received first to fourth pulse width modulation signals BST1 to BST4, and thus the buck-boost Inductor Lb will begin to work on energy storage. At this time, the primary side of the isolation transformer 120 is due to the fact that the first to fourth transistors Q1 to Q4 are all turned on so that no energy is transmitted to the secondary side of the isolation transformer 120, so the energy of the load is all paid to the whole. The capacitance Cr in the wave rectifier 130 is provided. As shown in FIG. 8, in the time interval from time t1 to t2, at time t1, the second transistor Q2 and the third transistor Q3 are modulated according to the second and third pulse width modulation signals BST2, BST3 received therefrom. It will be turned off, and the first transistor Q1 and the fourth transistor Q4 will remain in an on state. Therefore, the energy stored in the step-up and step-down inductor Lb charges the capacitor Cr through the isolation transformer 120 and the second diode D2 and the third diode D3 in the full-wave rectifier 130 to store energy. Next, as shown in FIG. 9, in the time interval from time t2 to time t3, the first to fourth transistors Q1 to Q4 are all turned on according to the received first to fourth pulse width modulation signals BST1 to BST4. Therefore, the buck-boost inductor Lb will start the energy storage work again. At this time, the primary side of the isolation transformer 120 is due to the fact that the first to fourth transistors Q1 to Q4 are all turned on so that no energy is transmitted to the secondary side of the isolation transformer 120, so the energy of the load is all paid to the whole. The capacitance Cr in the wave rectifier 130 is provided, wherein the current path is the same as in the embodiment of FIG. Thereafter, as shown in FIG. 10, in the time interval from time t3 to t4, at time t3, the first transistor Q1 and the fourth transistor Q4 are modulated according to the first and fourth pulse width modulation signals received therefrom. BST1 and BST4 are turned off, while the second transistor Q2 and the third transistor Q3 are kept on. state. Therefore, the energy stored in the buck-boost inductor Lb reversely charges the capacitor Cr through the isolating transformer 120 and the fourth diode D4 and the first diode D1 in the full-wave rectifier 130 to store energy. In the next switching cycle, it should be understood that the solar inverter 200 will continuously repeat the operation of the boost mode as shown in FIG. 7 to FIG. 10 above to modulate the input voltage VIN, and will not be described herein.

接下來要說明的是,關於太陽能逆變器200在降壓模式下的詳細說明。 Next, a detailed description of the solar inverter 200 in the step-down mode will be described.

請同時參照圖11~圖17,圖11為根據本發明實施例之第一至第四脈寬調變信號與降壓調變信號之驅動波形圖。圖12~圖17為根據本發明實施例之降壓模式下太陽能逆變器之電路示意圖。在進行下述說明前,須說明的是,在此以一個開關週期作為範例說明以方便了解本揭露內容,但本揭露內容並不以一個開關週期作為限制。在降壓模式時,降壓調變信號BU之責任週期δbuck小於100%,並且第一至第四脈寬調變信號BST1~BST4之責任週期δboost為門檻責任週期δmin,其中門檻責任週期δmin為定義為使升降壓轉換器110能夠正常運作之最小責任週期。 Referring to FIG. 11 to FIG. 17, FIG. 11 is a driving waveform diagram of first to fourth pulse width modulation signals and step-down modulation signals according to an embodiment of the present invention. 12 to 17 are circuit diagrams of a solar inverter in a buck mode according to an embodiment of the invention. Before the following description is made, it should be noted that a switching cycle is taken as an example to facilitate the understanding of the disclosure, but the disclosure is not limited by one switching cycle. In the buck mode, the duty cycle δbuck of the buck modulation signal BU is less than 100%, and the duty cycle δboost of the first to fourth pulse width modulation signals BST1 to BST4 is the threshold duty cycle δmin, wherein the threshold duty cycle δmin is Defined as the minimum duty cycle for the buck-boost converter 110 to function properly.

如圖12所示,在時間t0至t1的時間區間,降壓電晶體Qb、第一電晶體Q1與第四電晶體Q4分別受控於降壓調變信號BU、第一脈寬調變信號BST1與第四脈寬調變信號BST4而被導通,並且第二二極體D2與第三二極體D3會被導通。因此,升降壓電感Lb會經由隔離變壓器120會電容Cr進行充電以儲能。接著,如圖13所示,在時間t1至t2的時間區間,受控於降壓調變信號BU之降壓電晶體Qb會被截止,而分別受控於第一脈寬調變信號BST1與第四脈 寬調變信號BST4之第一電晶體Q1與第四電晶體Q4會持續導通,且第二二極體D2與第三二極體D3亦會持續導通。因此,升降壓電感Lb會繼續透過隔離變壓器120對電容Cr進行儲能的工作。接下來,如圖14所示,在時間t2至t3的時間區間,降壓電晶體Qb與第一至第四電晶體Q1~Q4分別受控於降壓調變信號BU與第一至第四脈寬調變信號BST1~BST4而導通。因此輸入電壓VIN(亦即太陽能面板上的能量)會透過降壓電晶體Qb對升降壓電感Lb進行儲能的工作。此時,隔離變壓器120的初級側因為第一至第四電晶體Q1~Q4全部導通的關係而被短路,所以沒有任何能量會被傳送到隔離變壓器120的次級側,而負載能量則由電容Cr來提供。之後,如圖15所示,在時間t3至t4的時間區間,受控於降壓調變信號BU之降壓電晶體Qb會被導通,且分別受控於第一脈寬調變信號BST1與第四脈寬調變信號BST4會被截止,且第一二極體D1與第四二極體D4會被導通。因此,升降壓電感Lb會反向地經由隔離變壓器120對電容Cr進行充電以儲能。接著,如圖16所示,在時間t4至t5的時間區間,受控於降壓調變信號BU之降壓電晶體Qb會被截止,而受控於第二脈寬調變信號BST2與第三脈寬調變信號BST3的第二電晶體Q2與第三電晶體Q3仍會導通,且第四二極體D4與第一二極體D1會持續導通。因此,升降壓電感Lb會透過隔離變壓器120繼續對電容Cr進行儲能的工作。最後,如圖17所示,在時間t5至t6的時間區間,分別受控於降壓調變信號BU與第一至第四脈寬調變信號BST1~BST4的降壓電晶體Qb與第一至第四電晶體Q1~Q4,會全部被導通。因此,輸入 電壓VIN(亦即太陽能面板上的能量)會經由降壓電晶體Qb對升降壓電感Lb進行儲能的工作。此時,隔離變壓器120的初級側會因為第一至第四電晶體Q1~Q4全部導通的關係而被短路,故沒有任何能量會被傳遞到隔離變壓器120的二次側。所以,負載能量則由電容Cr提供,其中電流路徑與圖14實施例相同。在接下來的開關週期中,應可理解太陽能逆變器200會不斷重複如上述圖12~圖17關於降壓模式的作動以調變輸入電壓VIN,在此則不再贅述。 As shown in FIG. 12, in the time interval from time t0 to t1, the step-down transistor Qb, the first transistor Q1 and the fourth transistor Q4 are respectively controlled by the step-down modulation signal BU and the first pulse width modulation signal. The BST1 is turned on with the fourth pulse width modulation signal BST4, and the second diode D2 and the third diode D3 are turned on. Therefore, the step-up and step-down inductor Lb is charged via the isolation transformer 120 with a capacitance Cr to store energy. Next, as shown in FIG. 13, during the time interval from time t1 to t2, the step-down transistor Qb controlled by the buck modulation signal BU is turned off, and is controlled by the first pulse width modulation signal BST1 and Fourth pulse The first transistor Q1 and the fourth transistor Q4 of the wide modulation signal BST4 are continuously turned on, and the second diode D2 and the third diode D3 are also continuously turned on. Therefore, the step-up and step-down inductor Lb continues to store the capacitor Cr through the isolation transformer 120. Next, as shown in FIG. 14, in the time interval from time t2 to t3, the step-down transistor Qb and the first to fourth transistors Q1 to Q4 are respectively controlled by the step-down modulation signal BU and the first to fourth The pulse width modulation signal BST1~BST4 is turned on. Therefore, the input voltage VIN (that is, the energy on the solar panel) will store the buck-boost inductor Lb through the step-down transistor Qb. At this time, the primary side of the isolation transformer 120 is short-circuited because the first to fourth transistors Q1 to Q4 are all turned on, so that no energy is transmitted to the secondary side of the isolation transformer 120, and the load energy is obtained by the capacitance. Cr to provide. Thereafter, as shown in FIG. 15, during the time interval from time t3 to time t4, the step-down transistor Qb controlled by the buck modulation signal BU is turned on, and is controlled by the first pulse width modulation signal BST1 and The fourth pulse width modulation signal BST4 is turned off, and the first diode D1 and the fourth diode D4 are turned on. Therefore, the step-up and step-down inductor Lb reversely charges the capacitor Cr via the isolation transformer 120 to store energy. Next, as shown in FIG. 16, during the time interval from time t4 to t5, the step-down transistor Qb controlled by the buck modulation signal BU is turned off, and is controlled by the second pulse width modulation signal BST2 and The second transistor Q2 and the third transistor Q3 of the three-pulse width modulation signal BST3 are still turned on, and the fourth diode D4 and the first diode D1 are continuously turned on. Therefore, the step-up and step-down inductor Lb continues to store the capacitor Cr through the isolation transformer 120. Finally, as shown in FIG. 17, in the time interval from time t5 to t6, the step-down transistor Qb and the first are controlled by the step-down modulation signal BU and the first to fourth pulse width modulation signals BST1 B BST4, respectively. Until the fourth transistor Q1~Q4, all of them will be turned on. Therefore, enter The voltage VIN (ie, the energy on the solar panel) will store the buck-boost inductor Lb via the buck transistor Qb. At this time, the primary side of the isolation transformer 120 is short-circuited due to the all-on relationship of the first to fourth transistors Q1 to Q4, so that no energy is transmitted to the secondary side of the isolation transformer 120. Therefore, the load energy is provided by the capacitor Cr, wherein the current path is the same as in the embodiment of Fig. 14. In the next switching cycle, it should be understood that the solar inverter 200 will repeatedly repeat the operation of the buck mode as shown in the above-mentioned FIG. 12 to FIG. 17 to modulate the input voltage VIN, which will not be described herein.

接下來要進一步說明的,是關於極性選擇器140的相關細部作動。 Further detailed next is the related detailing of the polarity selector 140.

請同時參照圖18~圖20,圖18為根據本發明實施例之控制信號之驅動波形圖。圖19~圖20為根據本發明實施例之極性選擇器動作之電路示意圖。在進行下述說明前,須說明的是,在此以一個開關週期作為範例說明以方便了解本揭露內容,但本揭露內容並不以一個開關週期作為限制。 Please refer to FIG. 18 to FIG. 20 simultaneously. FIG. 18 is a driving waveform diagram of a control signal according to an embodiment of the present invention. 19 to 20 are circuit diagrams showing the operation of a polarity selector according to an embodiment of the present invention. Before the following description is made, it should be noted that a switching cycle is taken as an example to facilitate the understanding of the disclosure, but the disclosure is not limited by one switching cycle.

如圖19所示,在時間t0至t1的時間區間,受控於第一控制信號CS1與第四控制信號CS4之第一矽控開關S1與第四矽控開關S4會被導通,並且受控於第二控制信號CS2與第三控制信號CS3之第二矽控開關S2與第三矽控開關S3會被截止。因此,電容Cr上的能量會透過如圖19之電流路徑傳送至交流電網以併入交流電網的能量供應系統。接著,如圖20所示,在時間t1至t2的時間區間,受控於第二控制信號CS2與第三控制信號CS3之第二矽控開關S2與第三矽控開關S3會被導通,並且受控於第一控制信號CS1與第四控制信號CS4之第一矽控開關S1與第四矽控開 關S4會被截止。因此,電容Cr上的能量會透過如圖20之電流路徑傳送至交流電網以併入交流電網的能量供應系統。值得一提的是,第一至第四矽控開關S1~S4的工作頻率為市電頻率(如60Hz)並且是在零點交越時切換,因此極性選擇器140的損耗是可以被忽略的,因而可視為單級式架構。 As shown in FIG. 19, during the time interval from time t0 to t1, the first control switch S1 and the fourth control switch S4 controlled by the first control signal CS1 and the fourth control signal CS4 are turned on, and are controlled. The second control switch S2 and the third control switch S3 of the second control signal CS2 and the third control signal CS3 are turned off. Therefore, the energy on the capacitor Cr is transmitted to the AC grid through the current path as shown in FIG. 19 to be incorporated into the energy supply system of the AC grid. Next, as shown in FIG. 20, during the time interval from time t1 to t2, the second switch S2 and the third switch S3 controlled by the second control signal CS2 and the third control signal CS3 are turned on, and The first switch S1 and the fourth switch controlled by the first control signal CS1 and the fourth control signal CS4 are controlled to open Off S4 will be closed. Therefore, the energy on the capacitor Cr is transmitted to the AC grid through the current path as shown in FIG. 20 to be incorporated into the energy supply system of the AC grid. It is worth mentioning that the operating frequencies of the first to fourth tamper switches S1 S S4 are the mains frequency (eg 60 Hz) and are switched at the zero crossing, so the loss of the polarity selector 140 can be ignored, thus Can be considered a single-level architecture.

承上述,本揭露內容所提出之單級式太陽能逆變器透過升降壓轉換器的升壓模式與降壓模式,能夠將太陽能逆變器所接收到的輸入電壓VIN轉換為市電正弦波信號VOUT,在高功率下達到優良的轉換效率。再者,本揭露內容能夠降低電路設計的複雜度以進一步節省元件數量與電路設計成本。 In view of the above, the single-stage solar inverter proposed by the present disclosure can convert the input voltage VIN received by the solar inverter into a commercial sine wave signal VOUT through the boost mode and the buck mode of the buck-boost converter. , achieve excellent conversion efficiency at high power. Moreover, the present disclosure can reduce the complexity of circuit design to further save component count and circuit design cost.

〔電壓轉換方法的一實施例〕 [An embodiment of the voltage conversion method]

請參照圖21,圖21為根據本發明實施例之電壓轉換方法之流程圖。本實施例所述之例示步驟流程可利用如圖1所示的太陽能逆變器100或圖2所示的太陽能逆變器200實施,故請一併參照圖1或圖2以利說明及理解。電壓轉換方法包括以下步驟:接收輸入電壓、降壓調變信號與升壓調變信號,其中根據降壓調變信號與升壓調變信號來調變輸入電壓,並且據此輸出波形調整信號(步驟S10)。將已隔離的波形調整信號予以全波整流,並且據此輸出全波脈波信號(步驟S20)。將全波脈波信號之後半週波形予以極性反轉,並且據此輸出市電正弦波信號(步驟S30)。其中在降壓模式,根據降壓調變信號將輸入電壓予以逐步降壓,並且在升壓模式,根據升壓調變信號將輸入電壓予以逐步升壓。 Please refer to FIG. 21. FIG. 21 is a flowchart of a voltage conversion method according to an embodiment of the present invention. The exemplary step flow described in this embodiment can be implemented by using the solar inverter 100 shown in FIG. 1 or the solar inverter 200 shown in FIG. 2, so please refer to FIG. 1 or FIG. 2 for explanation and understanding. . The voltage conversion method includes the steps of: receiving an input voltage, a step-down modulation signal, and a step-up modulation signal, wherein the input voltage is modulated according to the step-down modulation signal and the step-up modulation signal, and the waveform adjustment signal is output according to the Step S10). The isolated waveform adjustment signal is full-wave rectified, and a full-wave pulse signal is outputted accordingly (step S20). The waveform of the half-cycle of the full-wave pulse signal is inverted in polarity, and the commercial sine wave signal is outputted accordingly (step S30). In the buck mode, the input voltage is stepped down according to the buck modulation signal, and in the boost mode, the input voltage is stepped up according to the boost modulation signal.

關於太陽能逆變器之電壓轉換方法之各步驟的相關細節在上述圖1~圖20實施例已詳細說明,在此恕不贅述。 The details of the steps of the voltage conversion method of the solar inverter are described in detail in the above embodiments of FIGS. 1 to 20, and will not be described herein.

在此須說明的是,圖21實施例之各步驟僅為方便說明之須要,本發明實施例並不以各步驟彼此間的順序作為實施本發明各個實施例的限制條件。 It should be noted that the steps of the embodiment of FIG. 21 are only for convenience of description, and the embodiments of the present invention do not take the steps of the steps as a limitation of implementing various embodiments of the present invention.

〔實施例的可能功效〕 [Possible effects of the examples]

綜上所述,本發明實施例所提出之單級式太陽能逆變器及其電壓轉換方法,透過升降壓轉換器的升壓模式與降壓模式,能夠將太陽能逆變器所接收到的輸入電壓轉換為市電正弦波信號,在高功率下達到優良的轉換效率。再者,本揭露內容能夠降低電路設計的複雜度以進一步節省元件數量與電路設計成本。 In summary, the single-stage solar inverter and the voltage conversion method thereof according to the embodiments of the present invention can input the input of the solar inverter through the boost mode and the buck mode of the buck-boost converter. The voltage is converted to a commercial sine wave signal, achieving excellent conversion efficiency at high power. Moreover, the present disclosure can reduce the complexity of circuit design to further save component count and circuit design cost.

以上所述僅為本發明之實施例,其並非用以侷限本發明之專利範圍。 The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

100、200‧‧‧太陽能逆變器 100,200‧‧‧ solar inverter

110‧‧‧升降壓轉換器 110‧‧‧ buck-boost converter

120‧‧‧隔離變壓器 120‧‧‧Isolation transformer

130‧‧‧全波整流器 130‧‧‧Full-wave rectifier

140‧‧‧極性選擇器 140‧‧‧Polar selector

AS‧‧‧全波脈波信號 AS‧‧‧ full wave signal

BU‧‧‧降壓調變信號 BU‧‧‧Buck modulation signal

BST‧‧‧升壓調變信號 BST‧‧‧Boost modulation signal

BST1‧‧‧第一脈寬調變信號 BST1‧‧‧First pulse width modulation signal

BST2‧‧‧第二脈寬調變信號 BST2‧‧‧Second pulse width modulation signal

BST3‧‧‧第三脈寬調變信號 BST3‧‧‧3rd pulse width modulation signal

BST4‧‧‧第四脈寬調變信號 BST4‧‧‧4th pulse width modulation signal

Cin‧‧‧耦合電容 Cin‧‧‧Coupling Capacitor

Cr‧‧‧電容 Cr‧‧‧ capacitor

CS1‧‧‧第一控制信號 CS1‧‧‧First control signal

CS2‧‧‧第二控制信號 CS2‧‧‧second control signal

CS3‧‧‧第三控制信號 CS3‧‧‧ third control signal

CS4‧‧‧第四控制信號 CS4‧‧‧ fourth control signal

D1‧‧‧第一二極體 D1‧‧‧First Diode

D2‧‧‧第二二極體 D2‧‧‧ second diode

D3‧‧‧第三二極體 D3‧‧‧ third diode

D4‧‧‧第四二極體 D4‧‧‧ fourth diode

Db‧‧‧降壓二極體 Db‧‧‧Bucking diode

GND1‧‧‧第一接地電壓 GND1‧‧‧First ground voltage

GND2‧‧‧第二接地電壓 GND2‧‧‧second ground voltage

Lb‧‧‧升降壓電感 Lb‧‧‧Buck-boost inductor

Qb‧‧‧降壓電晶體 Qb‧‧‧Buck transistor

Q1~Q4‧‧‧電晶體 Q1~Q4‧‧‧Optoelectronics

S10~S30‧‧‧步驟 S10~S30‧‧‧Steps

S1‧‧‧第一矽控開關 S1‧‧‧First control switch

S2‧‧‧第二矽控開關 S2‧‧‧Second control switch

S3‧‧‧第三矽控開關 S3‧‧‧ third control switch

S4‧‧‧第四矽控開關 S4‧‧‧fourth control switch

t0~t6‧‧‧時間 T0~t6‧‧‧Time

Vb‧‧‧邊界電壓 Vb‧‧‧ boundary voltage

Vg‧‧‧預設定正弦波 Vg‧‧‧preset sine wave

VIN‧‧‧輸入電壓 VIN‧‧‧ input voltage

VT1‧‧‧第一三角波信號 VT1‧‧‧first triangular wave signal

VT2‧‧‧第二三角波信號 VT2‧‧‧second triangular wave signal

VOUT‧‧‧市電正弦波信號 VOUT‧‧‧ City electric sine wave signal

WS、WS’‧‧‧波形調整信號 WS, WS’‧‧‧ waveform adjustment signal

δbuck、δboost‧‧‧責任週期 Δbuck, δboost‧‧ ‧ duty cycle

δmin‧‧‧門檻責任週期 Δmin‧‧‧ threshold responsibility cycle

上文已參考隨附圖式來詳細地說明本發明之具體實施例,藉此可對本發明更為明白,在該等圖式中:圖1為根據本發明實施例之太陽能逆變器之區塊示意圖。 The present invention has been described in detail with reference to the accompanying drawings, in which FIG. Block diagram.

圖2為根據本發明實施例之太陽能逆變器之區塊示意圖。 2 is a block diagram of a solar inverter according to an embodiment of the present invention.

圖3為根據本發明實施例之驅動波形之示意圖。 3 is a schematic diagram of a driving waveform in accordance with an embodiment of the present invention.

圖4為根據本發明實施例之升壓模式下之太陽能逆變器之電路示意圖。 4 is a circuit diagram of a solar inverter in a boost mode according to an embodiment of the invention.

圖5為根據本發明實施例之降壓模式下之太陽能逆變 器之電路示意圖。 FIG. 5 is a solar inverter in a buck mode according to an embodiment of the present invention. Schematic diagram of the circuit.

圖6為根據本發明實施例之第一至第四脈寬調變信號之驅動波形圖。 FIG. 6 is a driving waveform diagram of first to fourth pulse width modulation signals according to an embodiment of the present invention.

圖7~圖10為根據本發明實施例之升壓模式下太陽能逆變器之電路示意圖。 7 to 10 are circuit diagrams of a solar inverter in a boost mode according to an embodiment of the present invention.

圖11為根據本發明實施例之第一至第四脈寬調變信號與降壓調變信號之驅動波形圖。 11 is a driving waveform diagram of first to fourth pulse width modulation signals and a step-down modulation signal according to an embodiment of the present invention.

圖12~圖17為根據本發明實施例之降壓模式下太陽能逆變器之電路示意圖。 12 to 17 are circuit diagrams of a solar inverter in a buck mode according to an embodiment of the invention.

圖18為根據本發明實施例之極性選擇器控制信號之驅動波形圖。 Figure 18 is a diagram showing driving waveforms of a polarity selector control signal according to an embodiment of the present invention.

圖19~圖20為根據本發明實施例之極性選擇器動作之電路示意圖。 19 to 20 are circuit diagrams showing the operation of a polarity selector according to an embodiment of the present invention.

圖21為根據本發明實施例之電壓轉換方法之流程圖。 21 is a flow chart of a voltage conversion method in accordance with an embodiment of the present invention.

200‧‧‧太陽能逆變器 200‧‧‧ solar inverter

110‧‧‧升降壓轉換器 110‧‧‧ buck-boost converter

120‧‧‧隔離變壓器 120‧‧‧Isolation transformer

130‧‧‧全波整流器 130‧‧‧Full-wave rectifier

140‧‧‧極性選擇器 140‧‧‧Polar selector

BU‧‧‧降壓調變信號 BU‧‧‧Buck modulation signal

BST1‧‧‧第一脈寬調變信號 BST1‧‧‧First pulse width modulation signal

BST2‧‧‧第二脈寬調變信號 BST2‧‧‧Second pulse width modulation signal

BST3‧‧‧第三脈寬調變信號 BST3‧‧‧3rd pulse width modulation signal

BST4‧‧‧第四脈寬調變信號 BST4‧‧‧4th pulse width modulation signal

CS1‧‧‧第一控制信號 CS1‧‧‧First control signal

CS2‧‧‧第二控制信號 CS2‧‧‧second control signal

CS3‧‧‧第三控制信號 CS3‧‧‧ third control signal

CS4‧‧‧第四控制信號 CS4‧‧‧ fourth control signal

Cin‧‧‧耦合電容 Cin‧‧‧Coupling Capacitor

Cr‧‧‧電容 Cr‧‧‧ capacitor

D1‧‧‧第一二極體 D1‧‧‧First Diode

D2‧‧‧第二二極體 D2‧‧‧ second diode

D3‧‧‧第三二極體 D3‧‧‧ third diode

D4‧‧‧第四二極體 D4‧‧‧ fourth diode

Db‧‧‧降壓二極體 Db‧‧‧Bucking diode

GND1‧‧‧第一接地電壓 GND1‧‧‧First ground voltage

GND2‧‧‧第二接地電壓 GND2‧‧‧second ground voltage

Lb‧‧‧升降壓電感 Lb‧‧‧Buck-boost inductor

Qb‧‧‧降壓電晶體 Qb‧‧‧Buck transistor

Q1~Q4‧‧‧電晶體 Q1~Q4‧‧‧Optoelectronics

S1‧‧‧第一矽控開關 S1‧‧‧First control switch

S2‧‧‧第二矽控開關 S2‧‧‧Second control switch

S3‧‧‧第三矽控開關 S3‧‧‧ third control switch

S4‧‧‧第四矽控開關 S4‧‧‧fourth control switch

VIN‧‧‧輸入電壓 VIN‧‧‧ input voltage

VOUT‧‧‧市電正弦波信號 VOUT‧‧‧ City electric sine wave signal

Claims (16)

一種太陽能逆變器,包括:一升降壓轉換器,接收一輸入電壓、一降壓調變信號與一升壓調變信號,其中該升降壓轉換器根據該降壓調變信號與該升壓調變信號來調變該輸入電壓,並且據此輸出一波形調整信號;一隔離變壓器,具有一初級側與一次級側,該隔離變壓器電性連接該升降壓轉換器,該隔離變壓器用以電氣隔離,接收該波形調整信號且輸出已隔離的該波形調整信號;一全波整流器,電性連接該隔離變壓器,該全波整流器將已隔離的該波形調整信號予以全波整流,並且據此輸出一全波脈波信號;以及一極性選擇器,電性連接該全波整流器,該極性選擇器將該全波脈波信號之後半週波形予以極性反轉,並且據此輸出一市電正弦波信號,其中該升降壓轉換器在一降壓模式下根據降壓調變信號將該輸入電壓予以逐步降壓,並且該升降壓轉換器在一升壓模式下根據升壓調變信號將該輸入電壓予以逐步升壓,據此,能夠在提高電壓準位期間,同時產生弦波波形,其中,該升降壓轉換器更電性連接至一數位信號處理晶片,當一預設定正弦波之電壓大於一邊界電壓時,則該升降壓轉換器處於該升壓模式,當該預設定正弦波之電壓小於該邊界電壓時,則該升降壓轉換器處於該降壓模式。 A solar inverter includes: a buck-boost converter receiving an input voltage, a step-down modulation signal, and a step-up modulation signal, wherein the step-up and step-down converter converts the voltage according to the step-down signal Modulating the signal to modulate the input voltage, and outputting a waveform adjustment signal accordingly; an isolation transformer having a primary side and a primary stage side, the isolation transformer being electrically connected to the buck-boost converter, the isolation transformer being used for electrical Isolating, receiving the waveform adjustment signal and outputting the isolated waveform adjustment signal; a full-wave rectifier electrically connected to the isolation transformer, the full-wave rectifier rectifying the isolated waveform adjustment signal and outputting accordingly a full-wave pulse signal; and a polarity selector electrically connected to the full-wave rectifier, the polarity selector inverts a polarity of the waveform of the full-wave pulse signal after the half-cycle, and outputs a mains sine wave signal accordingly The buck-boost converter gradually steps down the input voltage according to the buck modulation signal in a buck mode, and the buck-boost converter is In the boost mode, the input voltage is stepwise boosted according to the boost modulation signal, whereby the sine wave waveform can be simultaneously generated during the voltage level increase, wherein the buck-boost converter is electrically connected to a digital position. a signal processing chip, when a voltage of a preset sine wave is greater than a boundary voltage, the buck-boost converter is in the boost mode, and when the voltage of the preset sine wave is less than the boundary voltage, the buck-boost converter In this buck mode. 如申請專利範圍第1項所述之太陽能逆變器,其中當該升降壓轉換器在該升壓模式時,則該降壓調變信號之責任週期為 100%並且該升壓調變信號之責任週期大於50%。 The solar inverter of claim 1, wherein when the buck-boost converter is in the boost mode, the duty cycle of the buck modulation signal is 100% and the duty cycle of the boost modulation signal is greater than 50%. 如申請專利範圍第1項所述之太陽能逆變器,其中當該升降壓轉換器在該降壓模式時,則該降壓調變信號之責任週期小於100%並且該升壓調變信號之責任週期等於一門檻責任週期,其中該門檻責任週期為使得該升降壓轉換器正常運作之最小責任週期。 The solar inverter of claim 1, wherein when the buck-boost converter is in the buck mode, the duty cycle of the buck modulation signal is less than 100% and the boost modulation signal is The duty cycle is equal to a threshold period of responsibility, where the threshold duty cycle is the minimum duty cycle for the buck-boost converter to function properly. 如申請專利範圍第1項所述之太陽能逆變器,其中在該升壓模式下,當一第一三角波信號之電壓大於該預設定正弦波之電壓時,則該數位信號處理晶片輸出高準位電壓之該升壓調變信號至該升降壓轉換器;當該第一三角波信號之電壓小於該預設定正弦波之電壓時,則該數位信號處理晶片輸出低準位電壓之該升壓調變信號至該升降壓轉換器。 The solar inverter of claim 1, wherein in the boost mode, when the voltage of a first triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a high standard The step-up modulation signal of the bit voltage is applied to the buck-boost converter; when the voltage of the first triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs the boosting tone of the low-level voltage The signal is changed to the buck-boost converter. 如申請專利範圍第1項所述之太陽能逆變器,其中在該降壓模式下,當一第二三角波信號之電壓大於該預設定正弦波之電壓時,則該數位信號處理晶片輸出高準位電壓之該降壓調變信號至該升降壓轉換器;當該第二三角波信號之電壓小於該預設定正弦波之電壓時,則該數位信號處理晶片輸出低準位電壓之該降壓調變信號至該升降壓轉換器。 The solar inverter of claim 1, wherein in the step-down mode, when the voltage of a second triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a high standard The step-down modulation signal of the bit voltage is applied to the buck-boost converter; when the voltage of the second triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs the buck tone of the low level voltage The signal is changed to the buck-boost converter. 如申請專利範圍第1項所述之太陽能逆變器,其中該極性選擇器之工作頻率為一市電頻率,且其所輸出之該正弦波信號為該市電頻率,其中該極性選擇器更電性連接至一交流電網。 The solar inverter of claim 1, wherein the polarity selector operates at a mains frequency, and the sine wave signal outputted by the polarity selector is the mains frequency, wherein the polarity selector is more electrically Connected to an AC grid. 如申請專利範圍第1項所述之太陽能逆變器,其中該升降壓轉換器包括:一第一電晶體,其閘極接收一第一脈寬調變信號,其源極連 接該隔離變壓器之該初級側之繞組;一第二電晶體,其閘極接收一第二脈寬調變信號,其汲極連接至該第一電晶體之源極;一第三電晶體,其閘極接收一第三脈寬調變信號,其汲極連接該第一電晶體之汲極與一升降壓電感之第一端;其源極連接該隔離變壓器之該初級側之繞組;以及一第四電晶體,其閘極接收一第四脈寬調變信號,其汲極連接該第三電晶體之源極,其源極連接該第二電晶體之源極與一第一接地電壓,其中該第一至該第四脈寬調變信號為該升壓調變信號,並且當在該升壓模式時,該第一至該第四脈寬調變信號之所對應的責任週期大於50%以將該輸入電壓逐步升壓;當在該降壓模式時,該第一至該第四脈寬調變信號之所對應的責任週期等於一門檻責任週期,以維持該升降壓轉換器正常運作。 The solar inverter of claim 1, wherein the buck-boost converter comprises: a first transistor, the gate receiving a first pulse width modulation signal, and the source thereof Connected to the winding of the primary side of the isolation transformer; a second transistor whose gate receives a second pulse width modulation signal, the drain of which is connected to the source of the first transistor; a third transistor, The gate receives a third pulse width modulation signal, the drain is connected to the first end of the first transistor and the first end of a step-up and step-down inductor; the source is connected to the winding of the primary side of the isolation transformer; And a fourth transistor, the gate receiving a fourth pulse width modulation signal, the drain is connected to the source of the third transistor, and the source is connected to the source of the second transistor and a first ground a voltage, wherein the first to the fourth pulse width modulation signals are the boost modulation signals, and when in the boost mode, the duty cycle corresponding to the first to the fourth pulse width modulation signals More than 50% to gradually boost the input voltage; when in the buck mode, the duty cycle corresponding to the first to the fourth pulse width modulation signals is equal to a threshold duty cycle to maintain the buck-boost conversion The device works normally. 如申請專利範圍第7項所述之太陽能逆變器,其中該升降壓轉換器更包括:一降壓電晶體,其閘極接收該降壓調變信號,其汲極連接該輸入電壓,其源極連接該升降壓電感之第二端;以及一降壓二極體,其陽極連接該第一接地電壓,其陰極連接該降壓電晶體之源極,其中當在該升壓模式時,該降壓調變信號之責任週期為100%以導通該降壓電晶體,當在該降壓模式時,該降壓調變信號之責任週期小於100%以將該輸入電壓逐步降壓。 The solar inverter of claim 7, wherein the step-up and step-down converter further comprises: a step-down transistor, wherein the gate receives the step-down modulation signal, and the drain thereof is connected to the input voltage, a source connected to the second end of the buck-boost inductor; and a step-down diode having an anode connected to the first ground voltage and a cathode connected to a source of the buck transistor, wherein when in the boost mode The duty cycle of the buck modulation signal is 100% to turn on the buck transistor. When in the buck mode, the duty cycle of the buck modulation signal is less than 100% to step down the input voltage. 如申請專利範圍第1項所述之太陽能逆變器,其中該全波整 流器包括:一第一二極體,其陽極連接一第二接地電壓;一第二二極體,其陽極連接該第一二極體之陽極;一第三二極體,其陽極連接該第一二極體之陰極與該隔離變壓器之該次級側之繞組;一第四二極體,其陽極連接該第二二極體之陰極與該隔離變壓器之該次級側之繞組,其陰極連接該第三二極體之陰極;以及一電容,其第一端連接該第三二極體之陰極,其第二端連接該第二接地電壓,其中該第一至該第四二極體用以將已隔離之波形調整信號予以全波整流,並且據此輸出該全波脈波信號。 The solar inverter according to claim 1, wherein the full wave is integrated The flow device comprises: a first diode having an anode connected to a second ground voltage; a second diode having an anode connected to the anode of the first diode; and a third diode connected to the anode a cathode of the first diode and a winding of the secondary side of the isolation transformer; a fourth diode having an anode connected to the cathode of the second diode and the winding of the secondary side of the isolation transformer, a cathode connected to the cathode of the third diode; and a capacitor having a first end connected to the cathode of the third diode and a second end connected to the second ground voltage, wherein the first to the fourth pole The body is used for full-wave rectifying the isolated waveform adjustment signal, and the full-wave pulse signal is output accordingly. 如申請專利範圍第9項所述之太陽能逆變器,其中該極性選擇器包括:一第一矽控開關,其第一端連接該電容之第一端,其控制端接收一第一控制信號並據此決定導通或斷開狀態;一第二矽控開關,其第一端連接該第一矽控開關之第二端與一交流電網之正端,其第二端連接該第二接地電壓,其控制端接收一第二控制信號並據此決定導通或斷開狀態;一第三矽控開關,其第一端連接該電容之第一端,其控制端接收一第三控制信號並據此決定導通或斷開狀態;以及一第四矽控開關,其第一端連接該第三矽控開關之第二端與該交流電網之負端,其第二端連接該第二接地電壓,其控制端接收一第四控制信號並據此決定導通或斷開狀態, 其中該第一與該第四矽控開關之導通或斷開狀態相同,該第二與該第三矽控開關之導通或斷開狀態相同,並且該第一與該第二矽控開關之導通或斷開狀態相反。 The solar inverter of claim 9, wherein the polarity selector comprises: a first switch, the first end of which is connected to the first end of the capacitor, and the control end receives a first control signal And determining a conduction or disconnection state; a second control switch, the first end of which is connected to the second end of the first control switch and the positive end of an AC power grid, and the second end is connected to the second ground voltage The control terminal receives a second control signal and determines an on or off state according to the second control switch, the first end of which is connected to the first end of the capacitor, and the control end receives a third control signal according to Determining the on or off state; and a fourth switch, the first end of which is connected to the second end of the third switch and the negative end of the AC grid, and the second end is connected to the second ground voltage, The control terminal receives a fourth control signal and determines the on or off state according to the control terminal. The first and the fourth switch are in the same state of being turned on or off, the second and the third switch are in the same state of being turned on or off, and the first and the second switch are turned on. Or the reverse state is reversed. 一種電壓轉換方法,包括:接收一輸入電壓、一降壓調變信號與一升壓調變信號,其中根據該降壓調變信號與該升壓調變信號來調變該輸入電壓,並且據此輸出一波形調整信號;將已隔離的該波形調整信號予以全波整流,並且據此輸出一全波脈波信號;以及將該全波脈波信號之後半週波形予以極性反轉,並且據此輸出一市電正弦波信號;其中在一降壓模式,根據該降壓調變信號將該輸入電壓予以逐步降壓,並且在一升壓模式,根據該升壓調變信號將該輸入電壓予以逐步升壓,其中該電壓轉換方法用於如申請專利範圍第1項所述之太陽能逆變器,其中該升降壓轉換器更電性連接至一數位信號處理晶片,當一預設定正弦波之電壓大於一邊界電壓時,則該升降壓轉換器處於該升壓模式,當該預設定正弦波之電壓小於該邊界電壓時,則該升降壓轉換器處於該降壓模式。 A voltage conversion method includes: receiving an input voltage, a step-down modulation signal, and a step-up modulation signal, wherein the input voltage is modulated according to the step-down modulation signal and the step-up modulation signal, and The output is a waveform adjustment signal; the isolated waveform adjustment signal is full-wave rectified, and a full-wave pulse signal is output according to the waveform; and the waveform of the full-wave pulse signal is reversed in the second half of the waveform, and The output is a mains sine wave signal; wherein in a buck mode, the input voltage is stepped down according to the buck modulation signal, and in a boost mode, the input voltage is given according to the boost modulation signal Step-up boosting, wherein the voltage conversion method is used in a solar inverter as described in claim 1, wherein the buck-boost converter is more electrically connected to a digital signal processing chip when a pre-set sine wave When the voltage is greater than a boundary voltage, the buck-boost converter is in the boost mode, and when the voltage of the preset sine wave is less than the boundary voltage, the buck-boost converter is in the Buck mode. 如申請專利範圍第11項所述之電壓轉換方法,其中當該升降壓轉換器在該升壓模式時,則該降壓調變信號之責任週期為100%並且該升壓調變信號之責任週期大於50%。 The voltage conversion method of claim 11, wherein when the buck-boost converter is in the boost mode, the duty cycle of the buck modulation signal is 100% and the boost modulation signal is responsible The period is greater than 50%. 如申請專利範圍第11項所述之電壓轉換方法,其中當該升降壓轉換器在該降壓模式時,則該降壓調變信號之責任週期小於100%並且該升壓調變信號之責任週期等於一門檻責任 週期,其中該門檻責任週期為使得該升降壓轉換器正常運作之最小責任週期。 The voltage conversion method of claim 11, wherein when the buck-boost converter is in the buck mode, the duty cycle of the buck modulation signal is less than 100% and the step of the boost modulation signal is Cycle equals one responsibility The cycle, wherein the threshold duty cycle is the minimum duty cycle for the buck-boost converter to function properly. 如申請專利範圍第11項所述之電壓轉換方法,其中在升壓模式下,當一第一三角波信號之電壓大於該預設定正弦波之電壓時,則該數位信號處理晶片輸出高準位電壓之該升壓調變信號至該升降壓轉換器;當該第一三角波信號之電壓小於該預設定正弦波之電壓時,則該數位信號處理晶片輸出低準位電壓之該升壓調變信號至該升降壓轉換器。 The voltage conversion method of claim 11, wherein in the boost mode, when the voltage of a first triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a high level voltage. The step-up modulation signal is sent to the buck-boost converter; when the voltage of the first triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs the boost modulation signal of the low level voltage To the buck-boost converter. 如申請專利範圍第11項所述之電壓轉換方法,其中在降壓模式下,當一第二三角波信號之電壓大於該預設定正弦波之電壓時,則該數位信號處理晶片輸出高準位電壓之該降壓調變信號至該升降壓轉換器;當該第二三角波信號之電壓小於該預設定正弦波之電壓時,則該數位信號處理晶片輸出低準位電壓之該降壓調變信號至該升降壓轉換器。 The voltage conversion method according to claim 11, wherein in the step-down mode, when the voltage of a second triangular wave signal is greater than the voltage of the preset sine wave, the digital signal processing chip outputs a high level voltage. The step-down modulation signal is sent to the buck-boost converter; when the voltage of the second triangular wave signal is less than the voltage of the preset sine wave, the digital signal processing chip outputs the buck modulation signal of the low level voltage To the buck-boost converter. 如申請專利範圍第11項所述之電壓轉換方法,其中該極性選擇器之工作頻率為一市電頻率,且其所輸出之該正弦波信號為該市電頻率,其中該極性選擇器更電性連接至一交流電網。 The voltage conversion method of claim 11, wherein the polarity selector operates at a mains frequency, and the sine wave signal outputted by the polarity selector is the mains frequency, wherein the polarity selector is electrically connected. To an AC grid.
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