TWI502207B - Method for testing electrical connection status of a plurality of data lines connected to a panel and associated integrated circuit and display panel module - Google Patents
Method for testing electrical connection status of a plurality of data lines connected to a panel and associated integrated circuit and display panel module Download PDFInfo
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本發明係有關於一種用來測試面板上所連結之複數個訊號傳輸線之電性連接狀態的方法,尤指一種利用製作於積體電路中的邏輯閘群組來測試面板上複數個訊號傳輸線之電性連接狀態的方法。 The invention relates to a method for testing the electrical connection state of a plurality of signal transmission lines connected to a panel, in particular to testing a plurality of signal transmission lines on a panel by using a logic gate group formed in the integrated circuit. The method of electrically connecting the state.
在面板模組中,數位訊號會由控制板產生,並經由複數個訊號傳輸線將數位訊號傳送至面板上的驅動積體電路,然而,訊號傳輸線上可能會有斷路或是短路的情形發生,因此,在面板模組出廠前,需要進行測試以判斷訊號傳輸線是否正常。一般來說,通常需要透過實際的操作才能夠判斷訊號傳輸線上是否有斷路或是短路,然而,若是顯示資料的數量過於龐大,則斷路或是短路很難被發現,因此會無法確實檢測出訊號傳輸線的問題,而使得不良品流出至客戶端。 In the panel module, the digital signal is generated by the control board, and the digital signal is transmitted to the driving integrated circuit on the panel through a plurality of signal transmission lines. However, there may be an open circuit or a short circuit on the signal transmission line. Before the panel module is shipped from the factory, it needs to be tested to determine whether the signal transmission line is normal. Generally speaking, it is usually necessary to determine whether there is an open or short circuit on the signal transmission line through actual operation. However, if the amount of displayed data is too large, it is difficult to find an open circuit or a short circuit, so the signal cannot be detected. The problem of the transmission line causes the defective product to flow out to the client.
因此,本發明的目的之一在於提供一種用來測試一面板上所連結之複數個訊號傳輸線之電性連接狀態的方法以及相關的積體電路與顯示面板模組,以解決上述的問題。 Accordingly, it is an object of the present invention to provide a method for testing the electrical connection state of a plurality of signal transmission lines connected to one panel and related integrated circuit and display panel modules to solve the above problems.
依據本發明一實施例,一積體電路包含有複數個接點、一邏輯 閘群組以及一輸出單元。該複數個接點分別連接至複數個外部訊號傳輸線;該邏輯閘群組具有複數個輸入端,其於一測試模式下分別耦接於該複數個接點;該輸出單元耦接於該邏輯閘群組之至少一輸出端,且用來依據該邏輯閘群組之至少一輸出訊號以產生至少一測試結果訊號,並將該至少一測試結果訊號傳送至該積體電路的一輸出端,以供判斷該複數個外部訊號傳輸線之電性連接狀態。 According to an embodiment of the invention, an integrated circuit includes a plurality of contacts and a logic Gate group and an output unit. The plurality of contacts are respectively connected to the plurality of external signal transmission lines; the logic gate group has a plurality of input terminals coupled to the plurality of contacts in a test mode; the output unit is coupled to the logic gate At least one output of the group, and configured to generate at least one test result signal according to the at least one output signal of the logic gate group, and transmit the at least one test result signal to an output end of the integrated circuit to For judging the electrical connection state of the plurality of external signal transmission lines.
依據本發明另一實施例,一顯示面板模組包含有一面板以及一積體電路,其中該面板上連結有複數個訊號傳輸線,且該積體電路包含有複數個接點、一邏輯閘群組以及一輸出單元。該複數個接點分別連接至複數個訊號傳輸線;該邏輯閘群組具有複數個輸入端,其於一測試模式下分別耦接於該複數個接點;該輸出單元耦接於該邏輯閘群組之至少一輸出端,且用來依據該邏輯閘群組之至少一輸出訊號以產生至少一測試結果訊號,並將該至少一測試結果訊號傳送至該積體電路的一輸出端,以供判斷該複數個訊號傳輸線之電性連接狀態。 According to another embodiment of the present invention, a display panel module includes a panel and an integrated circuit, wherein the panel is coupled with a plurality of signal transmission lines, and the integrated circuit includes a plurality of contacts and a logic gate group. And an output unit. The plurality of contacts are respectively connected to the plurality of signal transmission lines; the logic gate group has a plurality of input terminals coupled to the plurality of contacts in a test mode; the output unit is coupled to the logic gate group At least one output of the group, and configured to generate at least one test result signal according to the at least one output signal of the logic gate group, and transmit the at least one test result signal to an output end of the integrated circuit for Determining the electrical connection state of the plurality of signal transmission lines.
依據本發明另一實施例,一種用來測試一面板上所連結之複數個訊號傳輸線之電性連接狀態的方法,包含有:提供一積體電路,其中該積體電路包含有:複數個接點,分別連接至複數個訊號傳輸線;一邏輯閘群組,具有複數個輸入端,其於一測試模式下分別耦接於該複數個接點;以及一輸出單元,耦接於該邏輯閘群組之至少一輸出端,用來依據該邏輯閘群組之至少一輸出訊號以產生至少一 測試結果訊號,並將該至少一測試結果訊號傳送至該積體電路的一輸出端,以供判斷該複數個訊號傳輸線之電性連接狀態;以及於一測試模式之下:將該邏輯閘群組之該複數個輸入端分別耦接於該複數個接點;將一第一組測試訊號輸入至該複數個訊號傳輸線;於該第一測試訊號輸入至該複數個訊號傳輸線之後,量測該積體電路之該輸出端以得到一第一測試結果;將一第二組測試訊號輸入至該複數個訊號傳輸線;於該第二測試訊號輸入至該複數個訊號傳輸線之後,量測該積體電路之該輸出端以得到一第二測試結果;以及依據該第一測試結果以及該第二測試結果以判斷該複數個訊號傳輸線之電性連接狀態。 According to another embodiment of the present invention, a method for testing an electrical connection state of a plurality of signal transmission lines connected to a board includes: providing an integrated circuit, wherein the integrated circuit includes: a plurality of connections The plurality of signal transmission lines are respectively connected to the plurality of signal transmission lines; the plurality of input terminals are respectively coupled to the plurality of contacts in a test mode; and an output unit coupled to the logic gate group At least one output of the group, configured to generate at least one according to at least one output signal of the logic gate group Testing the result signal, and transmitting the at least one test result signal to an output end of the integrated circuit for determining the electrical connection state of the plurality of signal transmission lines; and in a test mode: the logic gate group The plurality of input terminals are respectively coupled to the plurality of contacts; a first set of test signals are input to the plurality of signal transmission lines; after the first test signal is input to the plurality of signal transmission lines, the measurement is performed The output of the integrated circuit is used to obtain a first test result; a second set of test signals is input to the plurality of signal transmission lines; after the second test signal is input to the plurality of signal transmission lines, the integrated body is measured The output of the circuit is used to obtain a second test result; and the electrical connection state of the plurality of signal transmission lines is determined according to the first test result and the second test result.
請參考第1圖,第1圖為依據本發明一實施例之顯示面板模組100的示意圖。如第1圖所示,顯示面板模組100包含有面板110、驅動積體電路120以及軟性電路板(Flexible Printed Circuit,FPC)130,其中軟性電路板130係壓合在面板110上,且面板110連結有M條訊號傳輸線L1~LM,亦即M條訊號傳輸線L1~LM包含有製作於面板110上的複數條氧化銦錫(Indium Tin Oxide,ITO)訊號傳輸線以及軟性電路板130上的訊號傳輸線。此外,驅動積體電路120具有連接於複數條訊號傳輸線L1~LM的M個接點P1~PM,其中M為大於1的正整數。 Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a display panel module 100 according to an embodiment of the invention. As shown in FIG. 1 , the display panel module 100 includes a panel 110 , a driving integrated circuit 120 , and a flexible printed circuit (FPC) 130 , wherein the flexible circuit board 130 is pressed onto the panel 110 , and the panel 110 is connected to M signal transmission lines L1 LM, that is, M signal transmission lines L1 LM LM include a plurality of Indium Tin Oxide (ITO) signal transmission lines fabricated on the panel 110 and signals on the flexible circuit board 130 Transmission line. Further, the drive integrated circuit 120 has M contacts P1 to PM connected to the plurality of signal transmission lines L1 to LM, where M is a positive integer greater than one.
請參考第2圖,第2圖為依據本發明一第一實施例之驅動積體 電路200的示意圖。如第2圖所示,驅動積體電路200包含有多工器210、邏輯閘群組220以及輸出單元230,其中多工器210具有兩個輸出端OUT_1以及OUT_2,且輸出端OUT_1連接至驅動積體電路200於正常操作時的工作元件,而輸出端OUT_2連接到邏輯閘群組220的輸入端;此外,邏輯閘群組220包含有四個反互斥或閘(XNOR gate)222~228、以及一個或閘(OR gate)229。在以下有關驅動積體電路200的說明中,係假設驅動積體電路200分別自複數個接點P1~P8接收經由複數條訊號傳輸線L1~L8所傳送的數位訊號DB0~DB7,然而,接點與訊號傳輸線的數量以及數位訊號的位元數僅為一範例說明,而並非作為本發明的限制。 Please refer to FIG. 2, which is a driving integrated body according to a first embodiment of the present invention. A schematic diagram of circuit 200. As shown in FIG. 2, the driving integrated circuit 200 includes a multiplexer 210, a logic gate group 220, and an output unit 230, wherein the multiplexer 210 has two output terminals OUT_1 and OUT_2, and the output terminal OUT_1 is connected to the driver. The integrated circuit 200 is connected to the input terminal of the logic gate group 220; and the logic gate group 220 includes four XNOR gates 222~228. And an OR gate 229. In the following description of the driving integrated circuit 200, it is assumed that the driving integrated circuit 200 receives the digital signals DB0 to DB7 transmitted through the plurality of signal transmission lines L1 to L8 from the plurality of contacts P1 to P8, respectively, however, the contacts The number of signal transmission lines and the number of bits of the digital signal are merely illustrative and are not intended to be limiting of the invention.
在驅動積體電路200的操作上,首先,驅動積體電路200中的多工器210分別自複數個接點P1~P8接收經由複數條訊號傳輸線L1~L8所傳送的數位訊號DB0~DB7,此時,多工器210藉由一控制訊號Vc的控制以切換到一測試模式,亦即多工器210會將所接收的數位訊號DB0~DB7經由輸出端OUT_2傳送至四個反互斥或閘222~228的輸入端。 In the operation of driving the integrated circuit 200, first, the multiplexer 210 in the driving integrated circuit 200 receives the digital signals DB0~DB7 transmitted through the plurality of signal transmission lines L1 to L8 from the plurality of contacts P1 to P8, respectively. At this time, the multiplexer 210 is switched to a test mode by the control of a control signal Vc, that is, the multiplexer 210 transmits the received digital signals DB0~DB7 to the four anti-mutation or output via the output terminal OUT_2. Inputs of gates 222~228.
接著,四個反互斥或閘222~228分別對數位訊號DB0~DB7進行邏輯操作,而或閘229對反互斥或閘222~228的輸出訊號進行邏輯操作以產生輸出訊號Dout。最後,輸出單元230接收輸出訊號Dout並產生測試結果Dout’,並將測試結果Dout’藉由驅動積體電路200的一接點傳送至外部以供判斷訊號傳輸線L1~L8是否有斷路或 是短路。 Then, the four anti-mutation gates 222-228 respectively perform logical operations on the digital signals DB0~DB7, and the OR gate 229 logically operates the output signals of the anti-mutation or gates 222-228 to generate an output signal Dout. Finally, the output unit 230 receives the output signal Dout and generates a test result Dout', and transmits the test result Dout' to the outside by driving a contact of the integrated circuit 200 for determining whether the signal transmission line L1~L8 has an open circuit or It is a short circuit.
詳細來說,驅動積體電路200會接收兩組不同的數位訊號DB0~DB7,並依據對應至該兩組不同之數位訊號DB0~DB7的輸出訊號Dout來判斷訊號傳輸線L1~L8是否有斷路或是短路,其中該兩組不同之數位訊號DB0~DB7分別為“10101010”以及“01010101”。當數位訊號DB0~DB7分別為“10101010”以及“01010101”時,且或閘229的輸出訊號Dout均為“0”的時候,則代表訊號傳輸線L1~L8的電性連接狀態正常(沒有斷路或是短路);而若是或閘229的輸出訊號Dout有一次為“1”的時候,則代表訊號傳輸線L1~L8存在有斷路或是短路。 In detail, the driving integrated circuit 200 receives two sets of different digital signals DB0~DB7, and determines whether the signal transmission lines L1~L8 have an open circuit or according to the output signals Dout corresponding to the two different digital signals DB0~DB7. It is a short circuit, wherein the two different digital signals DB0~DB7 are "10101010" and "01010101" respectively. When the digital signals DB0~DB7 are "10101010" and "01010101" respectively, and the output signal Dout of the gate 229 is "0", the electrical connection state of the signal transmission lines L1~L8 is normal (no open circuit or If the output signal Dout of the gate 229 is "1" once, it means that there is an open circuit or a short circuit in the signal transmission line L1~L8.
舉例來說,參考第3圖以及第4圖,假設當訊號傳輸線L1~L8發生如第3圖(A)的斷路情形(訊號傳輸線L2及L5發生斷路),則當數位訊號“10101010”以及“01010101”先後輸入至訊號傳輸線L1~L8之後,驅動積體電路200之接點P1~P8上的電壓準位(亦即驅動積體電路200所接收到的數位訊號DB0~DB7)分別為“10100010”以及“00010101”(參見第4圖),因此,邏輯閘群組220的輸出訊號Dout為“1”;另一方面,假設當訊號傳輸線L1~L8發生如第3圖(B)的短路情形(訊號傳輸線L1與L2之間以及L4與L5之間發生短路),則當數位訊號“10101010”以及“01010101”先後輸入至訊號傳輸線L1~L8之後,驅動積體電路200之接點P1~P8上的電壓準位(亦即驅動積體電路200所接收到的數位訊號DB0~DB7) 分別為“11111010”以及“11011101”(參見第4圖),因此,邏輯閘群組220的輸出訊號Dout為“1”。 For example, referring to FIG. 3 and FIG. 4, it is assumed that when the signal transmission lines L1 to L8 are disconnected as in FIG. 3(A) (the signal transmission lines L2 and L5 are disconnected), the digital signals "10101010" and " After 01010101" is input to the signal transmission lines L1 to L8, the voltage levels on the contacts P1 to P8 of the integrated circuit 200 are driven (that is, the digital signals DB0 to DB7 received by the driving integrated circuit 200) are respectively "10100010". And "00010101" (see Fig. 4), therefore, the output signal Dout of the logic gate group 220 is "1"; on the other hand, it is assumed that a short circuit condition occurs as shown in Fig. 3(B) when the signal transmission lines L1 to L8 occur. (A short circuit occurs between the signal transmission lines L1 and L2 and between L4 and L5), and when the digital signals "10101010" and "01010101" are sequentially input to the signal transmission lines L1 to L8, the contacts P1 to P8 of the integrated circuit 200 are driven. The upper voltage level (that is, the digital signal DB0~DB7 received by the driving integrated circuit 200) They are "11111010" and "11011101" (see Fig. 4), respectively, and therefore, the output signal Dout of the logic gate group 220 is "1".
如上所述,只要訊號傳輸線L1~L8上有短路或是斷路的情形發生,則邏輯閘群組220的輸出訊號Dout就會為“1”,因此,只要判斷邏輯閘群組220之輸出訊號Dout的電壓準位便可以輕易得知訊號傳輸線L1~L8上的電性連接狀態。此外,上述檢測方式簡單且僅需要很短的測試時間,因此便於產線操作,且不需要額外的檢測設備,可以降低測試成本。 As described above, as long as a short circuit or an open circuit occurs on the signal transmission lines L1 to L8, the output signal Dout of the logic gate group 220 will be "1". Therefore, it is only necessary to judge the output signal Dout of the logic gate group 220. The voltage level can easily know the electrical connection state on the signal transmission lines L1~L8. In addition, the above detection method is simple and requires only a short test time, so that the production line operation is convenient, and no additional inspection equipment is required, and the test cost can be reduced.
此外,上述有關第2圖所示之驅動積體電路200僅可以判斷出訊號傳輸線L1~L8上有短路或是斷路的情形,利用本發明之亦可以進一步的判斷出哪一條訊號傳輸線有電性連接狀態上的問題。第5圖為依據本發明一第二實施例之驅動積體電路500的示意圖。如第5圖所示,驅動積體電路500包含有多工器510、邏輯閘群組520以及輸出單元530,其中多工器510具有兩個輸出端OUT_1以及OUT_2,且輸出端OUT_1連接至驅動積體電路500於正常操作時的工作元件,而輸出端OUT_2連接到邏輯閘群組520的輸入端;此外,邏輯閘群組520包含有四個互斥或閘(XOR gate)522~528,且輸出單元530包含有四個輸出子單元532~538。在以下有關驅動積體電路500的說明中,係假設驅動積體電路500分別自複數個接點P1~P8接收經由複數條訊號傳輸線L1~L8所傳送的數位訊號DB0~DB7,然而,此僅為一範例說明,而並非作為本發明的限制。 In addition, the driving integrated circuit 200 shown in FIG. 2 can only determine whether there is a short circuit or an open circuit on the signal transmission lines L1 to L8, and the present invention can further determine which signal transmission line is electrically connected. The problem with the connection status. Figure 5 is a schematic diagram of a driving integrated circuit 500 in accordance with a second embodiment of the present invention. As shown in FIG. 5, the driving integrated circuit 500 includes a multiplexer 510, a logic gate group 520, and an output unit 530, wherein the multiplexer 510 has two output terminals OUT_1 and OUT_2, and the output terminal OUT_1 is connected to the driver. The integrated circuit 500 is connected to the input terminal of the logic gate group 520; and the logic gate group 520 includes four XOR gates 522 to 528. And the output unit 530 includes four output subunits 532-538. In the following description of the driving integrated circuit 500, it is assumed that the driving integrated circuit 500 receives the digital signals DB0 to DB7 transmitted through the plurality of signal transmission lines L1 to L8 from the plurality of contacts P1 to P8, respectively. It is illustrated by way of example and not as a limitation of the invention.
在驅動積體電路500的操作上,首先,驅動積體電路500中的多工器510分別自複數個接點P1~P8接收經由複數條訊號傳輸線L1~L8所傳送的數位訊號DB0~DB7,此時,多工器510藉由一控制訊號Vc的控制以切換到一測試模式,亦即多工器510會將所接收的數位訊號DB0~DB7經由輸出端OUT_2傳送至四個互斥或閘522~528的輸入端。 In the operation of driving the integrated circuit 500, first, the multiplexer 510 in the driving integrated circuit 500 receives the digital signals DB0~DB7 transmitted through the plurality of signal transmission lines L1 to L8 from the plurality of contacts P1 to P8, respectively. At this time, the multiplexer 510 is switched to a test mode by the control of a control signal Vc, that is, the multiplexer 510 transmits the received digital signals DB0~DB7 to the four mutually exclusive or gates via the output terminal OUT_2. The input of 522~528.
接著,四個互斥或閘522~528分別對數位訊號DB0~DB7進行邏輯操作,以產生四個輸出訊號Dout1~Dout4。最後,四個輸出子單元532~538分別接收四個輸出訊號Dout1~Dout4並產生四個測試結果Dout1’~Dout4’,並將四個測試結果Dout1’~Dout4’藉由驅動積體電路500的至少一接點傳送至外部以供判斷訊號傳輸線L1~L8是否有斷路或是短路。 Then, four mutually exclusive gates 522-528 respectively perform logical operations on the digital signals DB0~DB7 to generate four output signals Dout1~Dout4. Finally, the four output sub-units 532-538 respectively receive four output signals Dout1~Dout4 and generate four test results Dout1'~Dout4', and drive the four test results Dout1'~Dout4' by driving the integrated circuit 500. At least one contact is transmitted to the outside for judging whether the signal transmission lines L1 to L8 are open or shorted.
詳細來說,驅動積體電路500會接收兩組不同的數位訊號DB0~DB7,並依據對應至該兩組不同之數位訊號DB0~DB7的輸出訊號Dout來判斷訊號傳輸線L1~L8是否有斷路或是短路,其中該兩組不同之數位訊號DB0~DB7分別為“10101010”以及“01010101”,而當數位訊號DB0~DB7分別為“10101010”以及“01010101”時,輸出訊號Dout1~Dout4均為“1”的時候,則代表訊號傳輸線L1~L8的電性連接狀態正常(沒有斷路或是短路);而若是有其中一個輸出訊號Dout1~Dout4有一次為“0”的時候,則代表相對 應的訊號傳輸線存在有斷路或是短路。舉例來說,假設輸出訊號Dout1的值為“0”,則代表訊號傳輸線L1或是L2其中之一有斷路或是短路。 In detail, the driving integrated circuit 500 receives two sets of different digital signals DB0~DB7, and determines whether the signal transmission lines L1~L8 have an open circuit or according to the output signals Dout corresponding to the two different digital signals DB0~DB7. It is a short circuit, in which the two different digital signals DB0~DB7 are "10101010" and "01010101" respectively, and when the digital signals DB0~DB7 are "10101010" and "01010101" respectively, the output signals Dout1~Dout4 are " 1", it means that the electrical connection state of the signal transmission line L1~L8 is normal (no open circuit or short circuit); and if one of the output signals Dout1~Dout4 has "0" once, it means relative There should be an open or short circuit in the signal transmission line. For example, if the value of the output signal Dout1 is “0”, it means that one of the signal transmission lines L1 or L2 has an open circuit or a short circuit.
此外,需注意的是,上述有關驅動積體電路200以及驅動積體電路500均假設只有8筆數位資料,然而,於本發明之其他實施例中,可以藉由多個訊號傳輸線來接收多筆數位資料,因為本領域中具有通常知識者可以依據上述實施例的教導而輕易應用於本發明,因此細節不再贅述。 In addition, it should be noted that the above-mentioned driving integrated circuit 200 and the driving integrated circuit 500 all assume that there are only eight digits of data. However, in other embodiments of the present invention, multiple signals can be received by multiple signal transmission lines. The digital data can be easily applied to the present invention based on the teachings of the above embodiments, and the details will not be described again.
簡要歸納本發明,於本發明之一種用來測試一面板上所連結之複數個訊號傳輸線之電性連接狀態的方法以及相關的積體電路與顯示面板模組中,係藉由設置於驅動積體電路中的一邏輯閘群組來判斷訊號傳輸線的電性連接狀態,如此一來,可以很簡單的進行測試且僅需要很短的測試時間,因此便於產線操作,且不需要額外的檢測設備,可以降低測試成本。 Briefly summarized, the present invention is a method for testing the electrical connection state of a plurality of signal transmission lines connected to one side of the board, and the related integrated circuit and display panel module, which are arranged in the driving product. A logic gate group in the body circuit determines the electrical connection state of the signal transmission line, so that the test can be easily performed and only a short test time is required, so that the production line operation is convenient and no additional detection is required. Equipment can reduce test costs.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100‧‧‧顯示面板模組 100‧‧‧Display panel module
120、200、500‧‧‧驅動積體電路 120, 200, 500‧‧‧ drive integrated circuits
130‧‧‧軟性電路板 130‧‧‧Soft circuit board
210、510‧‧‧多工器 210, 510‧‧‧ multiplexers
220、520‧‧‧邏輯閘群組 220, 520‧‧‧ logical gate group
222、224、226、228‧‧‧反互斥或閘 222, 224, 226, 228‧‧‧ anti-mutation or gate
522、524、526、528‧‧‧互斥或閘 522, 524, 526, 528‧‧‧ mutually exclusive or gate
229‧‧‧或閘 229‧‧‧ or gate
230、530‧‧‧輸出單元 230, 530‧‧‧ Output unit
532、534、536、538‧‧‧輸出子單元 532, 534, 536, 538‧‧‧ output subunits
P1~PM‧‧‧接點 P1~PM‧‧‧Contact
L1~LM‧‧‧訊號傳輸線 L1~LM‧‧‧ signal transmission line
DB0~DBN‧‧‧數位訊號 DB0~DBN‧‧‧ digital signal
第1圖為依據本發明一實施例之顯示面板模組的示意圖。 FIG. 1 is a schematic diagram of a display panel module according to an embodiment of the invention.
第2圖為依據本發明一第一實施例之驅動積體電路的示意圖。 Fig. 2 is a schematic view showing a driving integrated circuit according to a first embodiment of the present invention.
第3圖為訊號傳輸線發生斷路以及短路的示意圖。 Figure 3 is a schematic diagram of the open and short circuit of the signal transmission line.
第4圖為當訊號傳輸線發生如第3圖之斷路以及短路情形時,驅動積體電路所接收到之數位訊號的示意圖。 Fig. 4 is a schematic diagram of the digital signal received by the driving integrated circuit when the signal transmission line is broken and short-circuited as shown in Fig. 3.
第5圖為依據本發明一第二實施例之驅動積體電路的示意圖。 Fig. 5 is a schematic view showing a driving integrated circuit according to a second embodiment of the present invention.
200‧‧‧驅動積體電路 200‧‧‧Drive integrated circuit
210‧‧‧多工器 210‧‧‧Multiplexer
220‧‧‧邏輯閘群組 220‧‧‧Logic gate group
222、224、226、228‧‧‧反互斥或閘 222, 224, 226, 228‧‧‧ anti-mutation or gate
229‧‧‧或閘 229‧‧‧ or gate
230‧‧‧輸出單元 230‧‧‧Output unit
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CN200965682Y (en) * | 2006-11-07 | 2007-10-24 | 英业达股份有限公司 | Mainboard data signal display device |
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CN101707432A (en) * | 2006-08-22 | 2010-05-12 | 株式会社日立制作所 | Electric power switching device and its abnormal test method |
CN200965682Y (en) * | 2006-11-07 | 2007-10-24 | 英业达股份有限公司 | Mainboard data signal display device |
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