TWI492537B - Use the quasi - random code to control the power transistor on and off timing Random delay device - Google Patents

Description

Control the power transistor turn-on and turn-off timing using quasi-random codes Randomly delayed device

The present invention relates to a device for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code, in particular to a random-timing random sequence to drive a tree-like timing delay transfer device to control randomization of sub-components in a power transistor. A device that turns on or off.

Referring to the first figure, a conventional power transistor circuit architecture diagram includes a plurality of power transistor sub-elements (1), and each power transistor sub-element (1) is further composed of a plurality of N-type or P-type MOSs. (MOS) transistor (11). The sources (111) of each of the MOS transistors (11) of the respective power transistor sub-elements (1) are joined together to become the common source terminal (12) of the power transistor sub-element, and Each of the gates (112) is joined together to become the common gate terminal (13) of the power transistor sub-element, and each of the drain electrodes (113) is connected together to become the common terminal of the power transistor sub-element. (14). The common source extreme output point (12) in each power transistor sub-element is connected together to become a power transistor common source terminal (2), and the common gate extreme output point (13) is connected together to become a power transistor common gate terminal (3). The conjugate extreme output point (14) is connected together to become the power transistor conjugate terminal (4).

Conventional power transistors have thousands of gold-oxygen (MOS) transistors (11) contained in all of the power transistor sub-elements (1), and these MOS transistors (11) The metal wiring between the source (111) and the source (111), between the gate (112) and the gate (112), and between the drain (113) and the drain (113) is too long, so there is A large amount of parasitic capacitance and parasitic resistance. In the prior art, the control signal or power source is directly connected to the transistor common source output point (2), the common gate output point (3), and the common drain output point (4), and each of these is connected to each of the long metal wires. Gold oxide half (MOS) transistor (11). Wherein the control signal controls the turn-on or turn-off of each of the MOS transistors (11) via the gate metal connection line, and the parasitic resistance (RC) effect caused by the excessive metal connection line causes a signal delay. The control signal cannot reach the gate (112) of each MOS transistor (11) at the same time, and all the MOS transistors (11) cannot be turned on and off at the same time, and the signal is off. The closer the source of the MOS transistor (11) is turned on and off, the farther the MOS transistor (11) turns on and off, so the closer and closer the source is. The far-end gold-oxide half (MOS) transistor (11) has a large power loss and is more susceptible to damage. The power supply is directly connected to each of the metal oxide half (MOS) transistors (11) via a source or drain metal connection, and the metal connection line produces a parasitic resistance capacitance (RC) effect, such that each gold oxide half ( MOS) The source (111) and the drain (113) voltage, the source (111) and the gate (112) voltage are different between the transistors, causing conduction between each of the MOS transistors (11). The current is different, and the closer the metal-oxygen (MOS) transistor (11) is closer to the power supply terminal, the larger the on-current is, and the more power is consumed, so that it is more susceptible to damage.

The control signal transmission delay caused by the parasitic resistance and capacitance effect of these metal connection lines and the source-to-gate-to-drain supply voltage distribution are different, so that each MOS transistor (11) power loss in the power transistor Uneven, causing some of the gold oxide half (MOS) transistors (11) in the power transistor to be damaged due to excessive power consumption, and finally Causes damage to the entire power transistor.

The present invention proposes a device for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code, comprising: a power transistor having a plurality of power transistor sub-elements (1); a power transistor common source terminal (2); A power transistor common gate extreme (3); a power transistor common 汲 extreme (4); a power transistor turn-on and turn-off timing random delay control device (5).

In this case, the quasi-random code generator (52) is used to control the timing delay controller (51) to generate a random delay effect after the timing control signal generator (6) of the timing delay controller (51) turns on or off the control signal. And then output to a plurality of power transistor sub-elements (1).

One of the pseudo-random code generators (52) of the power transistor turn-on and turn-off timing random delay control device (5) is composed of a plurality of shift registers of length M, a plurality of mutually exclusive or logic gates or a plurality of mutually exclusive ones. And a logic gate composition, wherein M is an integer greater than 3, generating 2 ^M -1 sets of different combinations of M-bit binary code output signals (522) for driving a tree-like timing delay controller (51) a plurality of output terminals (513) of the power transistor turn-on and turn-off timing random delay control device (5) and a plurality of power transistor sub-elements (1) of the power transistor (10) having a common gate extreme ( 13) Electrical connection by which the chronological sequence of turning on or off of a plurality of power transistor sub-elements (1) is randomly controlled.

A device for controlling power transistor turn-on and turn-off random delay using a pseudo-random code, wherein each power transistor sub-element (1) comprises a plurality of N-types or P-type metal oxide semiconductor (Metal Oxide Semiconductor, MOS, gold oxide semi-transistor) (11). For each of the plurality of power transistor sub-elements (1), the power transistor can be randomly generated by designing a timing delay controller (51) having a tree structure driven by the pseudo random code generator (52). The sub-element (1) turns on and off different control signal timings, whereby the sub-element (1) of each power transistor is subjected to the same power consumption.

Referring to FIG. 2A, a schematic diagram of a random delay control device for controlling power transistor turn-on and turn-off timing using a pseudo random code according to a preferred embodiment of the present invention includes power composed of a plurality of power transistor sub-elements (1) The transistor, the power transistor is turned on and off, the timing random delay control device (5), the timing control signal generator (6), and the pulse signal generator (7). The power transistor turn-on and turn-off timing random delay control device (5) consists of a set of timing delay controllers (51) and a set of a plurality of shift registers of length M, a plurality of mutually exclusive or logic gates or complex numbers A quasi-random code generator (52) consisting of mutually exclusive and logical gates, where M is an integer greater than three. The power transistor sub-element (1) of each main component in the power transistor is composed of a plurality of N-type or P-type MOS transistors (11), and each power transistor sub-element (1) The gate terminal (13) of the ) is connected to each of the different control signal outputs (513) in the timing delay controller (51) in the time-series random delay control device (5).

A clock signal generator (7) controls the pseudo random code generator (52) to output a M bit binary code having a total combination of 2 ^M -1 groups. The input terminal (511) of the timing delay controller (51) in the power transistor turn-on and turn-off timing random delay control device (5) is electrically connected to the timing control signal generator (6), and the other M inputs (512) are The M pseudo-random code generator outputs are electrically connected (522).

Referring to FIG. 2B, a timing delay controller (51) is a schematic diagram of a preferred embodiment of the present invention. The timing delay controller (51) is composed of a plurality of hierarchical delay elements (514) in a plurality of hierarchical tree architectures. The timing delay signal input terminal (5142) of the first layer is connected to the timing control signal generator (6) through the timing delay controller control signal input terminal (511), and the timing delays of the remaining layers are The timing signal input terminal (5142) of the component (514) is connected to the timing signal output terminal (5143) of the timing delay component (514) of the previous layer, and the timing signal output terminal (5143) of the lowest layer timing delay component (514) is transmitted through the timing sequence. The delay controller (51) control signal output (513) connects the common gate terminals (13) of the different power transistor sub-elements (1), respectively. Each stage timing delay element (514) timing delay control input (5141) is coupled to any one of the quasi-random code generator (52) M-bit binary random code output (522) to control each timing. The priority of the transfer speed of the conduction and closing paths in the delay element (514).

Because the pseudo-random code generator (52) performs the power transistor turn-on or turn-off every time, it outputs 2 ^M -1 sets of M-bit binary quasi-random code each time, with the clock signal generator (7) The output clock sequence is randomly generated, and the timing random delay control of the transfer path of the tree structure timing delay controller (51) is used to randomly control each power transistor sub-component in the power transistor. (1) The turn-on or turn-off sequence allows the sub-elements (1) of each power transistor to withstand the same power consumption, reducing the damage rate of each power transistor sub-element (1) and extending the life of the power transistor .

In short, the case uses the clock signal generator (7) to output the clock to the pseudo-random code generator (52) to control the timing delay controller (51); the timing control of the timing delay controller (51) is performed. After the signal generator (6) turns on or off the control signal to generate a random delay effect, it is output to a plurality of power transistor sub-elements (1), thereby equalizing the power consumption of the sub-element (1) of each power transistor. .

The present invention has the following advantages: 1. The random delay control device for controlling the power transistor turn-on and turn-off timing using the pseudo-random code proposed in the present invention can effectively improve the transfer delay of the sub-element of the power transistor due to the parasitic resistance and capacitance effect of the metal connection line. The problem of uneven power consumption is caused. 2. The circuit design is very easy to control the power transistor turn-on and turn-off timing random delay control device using the pseudo random code. 3. The power crystal controlled by the pseudo random code is proposed in this case. Turning on and off the timing random delay control device allows the sub-components of each power transistor to withstand the same power consumption, reducing the damage rate of each power transistor sub-element and prolonging the service life of the power transistor.

In summary, the use of pseudo-random code control power transistor turn-on and turn-off timing random delay control device in this case can improve the power consumption unevenness caused by the transmission delay caused by the parasitic resistance and capacitance effect of the metal connection line. Novel and practical, such as its modified design, for example applied to various types of power transistor random delay Control, as long as the timing delay element composed of the pseudo random code or the architecture type having a plurality of hierarchical trees is used to control the turn-on or turn-off of the sub-components of the power transistor, and is intended to be disclosed in this case. protector.

The technology disclosed in this case can be implemented by a person familiar with the technology, and its unprecedented practice is also patentable, and the application for patent is filed according to law. However, the above embodiments are not sufficient to cover the scope of patents to be protected in this case. Therefore, the scope of the patent application is attached.

10‧‧‧Power transistor

1‧‧‧Power transistor subcomponents

11‧‧‧N-type or P-type gold oxide half (MOS) transistors

111‧‧‧N-type or P-type MOS transistor source extremes

112‧‧‧N-type or P-type MOS transistor gate extremes

113‧‧‧N-type or P-type MOS transistor 汲 extreme

12‧‧‧Power transistor sub-components

13‧‧‧Power transistor sub-component common gate extreme

14‧‧‧Power transistor sub-components

2‧‧‧Power transistor common source extreme

3‧‧‧Power transistor common gate extreme

4‧‧‧Power transistor 汲 extreme

5‧‧‧Power transistor turn-on and turn-off timing random delay control device

51‧‧‧Time Delay Controller

511‧‧‧Sequence delay controller control signal input

512‧‧‧Time Delay Controller Mbit Binary Random Code Input

513‧‧‧Sequence delay controller control signal output

514‧‧‧Time delay components

5141‧‧‧ Timing delay control input

5142‧‧‧ Timing signal input

5143‧‧‧ Timing signal output

52‧‧‧ Quasi-random code generator

521‧‧‧ Quasi-random code generator clock signal input

522‧‧‧ Quasi-random code generator M-bit binary random code output

6‧‧‧Sequence Control Signal Generator

7‧‧‧ Clock signal generator

S1‧‧‧ control signal input

L1‧‧‧ first floor

L2‧‧‧ second floor

L3‧‧‧ third floor

The first figure is a conventional power transistor circuit architecture diagram; the second figure is a schematic diagram of a power transistor timing random delay control device according to a preferred embodiment of the present invention.

10‧‧‧Power transistor

1‧‧‧Power transistor subcomponents

2‧‧‧Power transistor common source extreme

3‧‧‧Power transistor common gate extreme

4‧‧‧Power transistor 汲 extreme

5‧‧‧Power transistor timing random delay control device

6‧‧‧Sequence Control Signal Generator

7‧‧‧ Clock signal generator

Claims (8)

A device for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code, wherein the power cell system is composed of a plurality of power transistor sub-components, including: a pseudo-random code generator; a timing control signal generator, Generating a turn-on or turn-off control signal; a clock signal generator electrically connecting the clock input of the pseudo-random code generator; a timing delay controller electrically connecting the pseudo-random code generator, the timing control signal a generator and the plurality of power transistor sub-components; wherein the pseudo-random code generator controls the timing delay controller to cause a random or closed control signal of the timing control signal generator of the timing delay controller to generate a random After the effect of the delay, it is output to a plurality of power transistor sub-elements. The apparatus for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code as described in claim 1, wherein the plurality of power transistor sub-elements are composed of a plurality of N-type or P-type metal oxide semiconductor transistors The source and source of each N-type or P-type metal oxide semiconductor transistor in each power transistor sub-element are electrically connected together, the drain and the drain are electrically connected together, and the gate and gate are electrically connected. Connect together. A device for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code as described in claim 1, wherein the pseudo-random code generator consists of a plurality of shift registers of length M, and a plurality of mutually exclusive registers. Or a logic gate or a plurality of mutually exclusive and logic gates, M signal outputs, at most 2 ^M -1 sets of different combinations of M-bit binary code output signals, where M is an integer greater than 3. The apparatus for controlling the power transistor turn-on and turn-off timing random delay using the pseudo-random code described in claim 1 of the patent application, the timing delay controller is a method for timing delay control, which is superimposed by a plurality of hierarchical tree structures. The components of each layer in the tree structure are composed of a plurality of timing delay elements. The apparatus for controlling power transistor turn-on and turn-off random delay using a pseudo-random code as described in claim 4, wherein the timing delay component includes a timing delay control input terminal, a timing signal input terminal, and a timing signal output. end. The apparatus for controlling power transistor turn-on and turn-off timing random delay using a pseudo-random code as described in claim 1, wherein the timing delay controller has a control signal input electrically connected to a control signal generator output; M two The carry signal input terminal is electrically connected to the output of the M-bit quasi-random code generator; a plurality of output terminals, each of which is connected to a plurality of power transistor sub-components in the plurality of power transistor sub-elements Connected to control the turn-on or turn-off sequence of the power transistor sub-element. The device for controlling power transistor turn-on and turn-off timing random delay using pseudo-random code according to item 3 of the patent application scope includes a method for timing delay control, which is formed by stacking a plurality of hierarchical tree structures; The plurality of timing delay component timing signal input terminals are electrically connected to the timing control signal generator; the plurality of timing delay component timing signal input terminals of the remaining layers are connected to a timing delay component timing signal output terminal of the plurality of timing delay components of the previous layer The timing signal output of each of the bottommost plurality of timing delay elements is electrically connected to the gate terminal of one of the plurality of power transistor sub-elements; the plurality of timings of the same layer The timing delay control input of the delay element electrically interconnects one of the binary code outputs of the M-bit of the quasi-random control code. A device for controlling power transistor turn-on and turn-off random delay using a pseudo-random code as described in claim 5, wherein the timing delay component is a buffer, an inverter, a transmission logic gate, and a A metal connection line, a passive component resistor-capacitor circuit, or an active component resistor-capacitor circuit.