TWI468923B - Level shifter adaptive for use in a power-saving operation mode - Google Patents

Description

Level shifter for power saving operation mode

The present invention relates to a level shifter, and more particularly to a level shifter suitable for use in a power saving mode of operation.

In order to reduce the power consumption of electronic circuits, research on techniques for reducing the power supply voltage has been a major development focus. Advanced electronic technology has developed a low-power, high-speed integrated circuit that uses a 1.8 volt power supply voltage, but how to couple an integrated circuit using a low power supply voltage with an integrated circuit using a high power supply voltage, or how to make it low The output signal of the integrated circuit of the voltage operating range can drive an integrated circuit with a high voltage operating range, which is another important issue. Therefore, when an integrated circuit with a low voltage operating range is coupled to an integrated circuit having a high voltage operating range, it is necessary to utilize a voltage conversion interface to provide an output signal with a high voltage operating range.

Please refer to FIG. 1 , which is a circuit diagram showing a conventional level shifter. As shown in FIG. 1, the level shifter 100 includes a first transistor 112, a second transistor 114, a third transistor 116, a fourth transistor 118, a fifth transistor 120, and an inverter 190. The level shifter 100 is configured to convert the input signal Vin generated by the first circuit unit 181 with the first voltage operating range into the first output signal Vout and the second output signal Voutb having the second voltage operating range. The second circuit unit 182, the second output signal Voutb is inverted to the first output signal Vout.

In the circuit operation of the level shifter 100, it is necessary to simultaneously use the first supply voltage Vdd1 and the second supply voltage Vdd2 to perform voltage operation range conversion processing. However, at the beginning of the power-on, due to the difference in power supply delay time, the first supply voltage Vdd1 is not supplied to the level shifter 100 before the second supply voltage Vdd2, that is, the second supply voltage Vdd2 is greater than the first supply voltage Vdd1. First supplied to the level shifter 100. For example, in the transient process in which the second supply voltage Vdd2 is first supplied and the first supply voltage Vdd1 is not yet supplied, the third transistor 116 and the fourth transistor 118 are in an off state, and the first transistor 112 is in the off state. In the on state, at this time, the second supply voltage Vdd2 can be transmitted to the node A via the first transistor 112, and the fifth transistor 120 is turned on, thereby pulling the voltage of the node B to a low voltage level. Therefore, in the above-mentioned power-on condition, the second output signal Voutb is first set to a high level signal with a voltage Vdd2, and the first output signal Vout is first set to a low level signal with a ground voltage, that is, Before the first supply voltage Vdd1 is not supplied, the level shifter 100 can set the first output signal Vout and the second output signal Voutb to be mutually inverted signals. However, if the fifth transistor 120 is omitted, the node B will be in a floating state before the first supply voltage Vdd1 has been supplied, thus causing a malfunction of the circuit. Therefore, the level shifter 100 can avoid circuit malfunction when the circuit is turned on.

However, after the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to cause the level shifter 100 to operate normally, if the first output signal Vout is at a high voltage level and the second output signal Voutb is at a low voltage level When the supply of the first supply voltage Vdd1 is stopped to perform the power-saving mode operation to cause the third transistor 116 to enter the off state, the node A may be in a floating state, thereby causing a malfunction of the circuit. Therefore, the level shifter 100 is not suitable for performing the power saving mode operation.

In accordance with an embodiment of the present invention, a level shifter suitable for use in a power saving mode of operation is disclosed for coupling a first circuit unit using a first supply voltage to a second circuit unit using a second supply voltage. Such a level shifter includes a pre-position shift circuit and an output auxiliary circuit. The pre-position shifting circuit is coupled to the first circuit unit to receive an input signal having a first voltage operating range, and the pre-level shifting circuit is configured to convert the input signal according to the first supply voltage and the second supply voltage The first output signal having the second voltage operating range and the second output signal inverted to the first output signal. The output auxiliary circuit is coupled between the pre-position shift circuit and the second circuit unit for maintaining the voltage level of the first output signal according to the second supply voltage.

In order to make the present invention more comprehensible, the following is applicable to a level shifter of a power saving operation mode according to the present invention. The specific embodiments are described in detail in conjunction with the drawings, but the embodiments provided are not intended to be limiting. The scope of the invention is covered.

Fig. 2 is a schematic view showing a level shifter of the first embodiment of the present invention. As shown in FIG. 2, the level shifter 200 includes a pre-position shift circuit 210 and an output auxiliary circuit 270. The level shifter 200 is configured to couple the first circuit unit 281 using the first supply voltage Vdd1 and the second circuit unit 282 using the second supply voltage Vdd2. The pre-position shifting circuit 210 is coupled to the first circuit unit 281 to receive the input signal Vin having the first voltage operating range, and the pre-level shifting circuit 210 is configured to use the first supply voltage Vdd1 and the second supply. The voltage Vdd2 converts the input signal Vin into a first output signal Vout1 and a second output signal Vout2 having a second voltage operation range, wherein the second output signal Vout2 is inverted to the first output signal Vout1. The output auxiliary circuit 270 is coupled to the pre-position shift circuit 210 to receive the first output signal Vout1 and the second output signal Vout2. The output auxiliary circuit 270 is powered by the second supply voltage Vdd2, and is configured to generate a third output signal Vout3 according to the first output signal Vout1, wherein the voltage level of the third output signal Vout3 is substantially the same as the voltage of the first output signal Vout1. Level.

The output auxiliary circuit 270 includes a buffer 271, a first auxiliary transistor 273, and a second auxiliary transistor 275. The first auxiliary transistor 273 and the second auxiliary transistor 275 are N-type Metal Oxide Semiconductor Field Effect Transistor and N-type Junction Field Effect (N-type Junction Field Effect). Transistor, N-JFET), or Thin Film Transistor. The buffer 271 includes an input end, an output end, and a power supply end, wherein the input end is coupled to the pre-position shift circuit 210 to receive the first output signal Vout1, and the output end is configured to output the third output signal Vout3 to the second circuit unit. 282. The power terminal is configured to receive the second supply voltage Vdd2. The first auxiliary transistor 273 includes a first end, a second end, and a gate. The first end is coupled to the input end of the buffer 271, the second end is coupled to the ground end, and the gate is coupled to the pre-position. The shift circuit 210 receives the second output signal Vout2. The second auxiliary transistor 275 includes a first end, a second end, and a gate. The first end is coupled to the gate of the first auxiliary transistor 273, the second end is coupled to the ground, and the gate is coupled to the buffer. The output of the 271. The circuit operation of the output auxiliary circuit 270 is detailed below.

After the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to operate the level shifter 200, if the first output signal Vout1 is at the high voltage level Vdd2 and the second output signal Vout2 is at the low voltage level, When the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 271, and the high voltage level Vdd2 of the first output signal Vout1 is provided by the second supply voltage Vdd2. Therefore, the first output signal Vout1 still maintains the high voltage level Vdd2, and the buffer 271 can maintain the high voltage level Vdd2 of the third output signal Vout3 according to the first output signal Vout1. At this time, the high voltage level Vdd2 of the third output signal Vout3 turns on the second auxiliary transistor 275, thereby pulling down the second output signal Vout2 to the ground voltage. In other words, after the supply of the first supply voltage Vdd1 is stopped in order to perform the power saving mode operation, the low voltage level of the second output signal Vout2 and the high voltage level Vdd2 of the third output signal Vout3 can be maintained, so The circuit malfunctions.

In addition, after the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to make the level shifter 200 operate normally, if the first output signal Vout1 is at a low voltage level, the second output signal Vout2 is at a high voltage level Vdd2. When the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 271, and the high voltage level Vdd2 of the second output signal Vout2 is the second supply voltage Vdd2. Provided, so the second output signal Vout2 remains at the high voltage level Vdd2. At this time, the high voltage level Vdd2 of the second output signal Vout2 turns on the first auxiliary transistor 273, and then pulls the first output signal Vout1 to the ground voltage, and then the buffer 271 maintains the first output signal Vout1. The low voltage level of the three output signals Vout3. In other words, after the supply of the first supply voltage Vdd1 is stopped in order to perform the power saving mode operation, the low voltage level of the high voltage level Vdd2 and the third output signal Vout3 of the second output signal Vout2 can still be maintained, so that no The circuit malfunctions.

3 is a circuit diagram of a level shifter according to a second embodiment of the present invention. As shown in FIG. 3, the level shifter 300 includes a pre-position shift circuit 310 and an output auxiliary circuit 370. The circuit functions of the pre-position shift circuit 310 and the output auxiliary circuit 370 are the same as those of the pre-position shift circuit 210 and the output auxiliary circuit 270 shown in FIG. Basically, the internal circuit structure of the output auxiliary circuit 370 is the same as the output auxiliary circuit 270. The buffer 271 of the output auxiliary circuit 370 includes an operational amplifier 361. The operational amplifier 361 includes a positive input terminal, a negative input terminal, an output terminal, and a power supply terminal. The positive input terminal is coupled to the pre-position shifting circuit 310 to receive the first output signal Vout1, and the negative input terminal is coupled to the output terminal. The output terminal is configured to output a third output signal Vout3 to the second circuit unit 282, and the power terminal is configured to receive the second supply voltage Vdd2.

The pre-position shift circuit 310 includes a first transistor 312, a second transistor 314, a third transistor 322, a fourth transistor 324, a fifth transistor 316, a sixth transistor 318, and an inverter 390. . The first transistor 312 includes a first end, a second end, and a gate, wherein the first end is configured to receive the second supply voltage Vdd2. The second transistor 314 includes a first end, a second end, and a gate, wherein the first end is configured to receive the second supply voltage Vdd2. The third transistor 322 includes a first end, a second end, and a gate, wherein the first end is coupled to the second end of the first transistor 312, and the gate is coupled to the first circuit unit 281 to receive the input signal Vin. The second end is coupled to the gate of the second transistor 314. The second output signal Vout2 is extracted from the second end of the third transistor 322. The fourth transistor 324 includes a first end, a second end, and a gate, wherein the first end is coupled to the second end of the second transistor 314, and the second end is coupled to the gate of the first transistor 312. The first output signal Vout1 is extracted from the second end of the fourth transistor 324. The first transistor 312, the second transistor 314, the third transistor 322, and the fourth transistor 324 are P-type MOS field effect transistors, P-type junction field effect transistors, or thin film transistors.

The fifth transistor 316 includes a first end, a second end, and a gate, wherein the first end is coupled to the second end of the third transistor 322, the second end is coupled to the ground end, and the gate is coupled to the first end The circuit unit 281 receives the input signal Vin. The sixth transistor 318 includes a first end, a second end, and a gate, wherein the first end is coupled to the second end of the fourth transistor 324, the second end is coupled to the ground end, and the gate is coupled to the fourth end. The gate of transistor 324. The fifth transistor 316 and the sixth transistor 318 are N-type gold oxide half field effect transistors, N-type junction field effect transistors, or thin film transistors. The inverter 390 includes an input end, an output end, and a power supply end, wherein the input end is coupled to the first circuit unit 281 to receive the input signal Vin, the output end is coupled to the gate of the sixth transistor 318, and the power end is configured to receive The first supply voltage Vdd1.

In an embodiment, the inverter 390 includes a seventh transistor 332 and an eighth transistor 334. The seventh transistor 332 includes a first end, a second end, and a gate, wherein the first end is configured to receive the first supply voltage Vdd1, the gate is coupled to the first circuit unit 281 to receive the input signal Vin, and the second end is coupled Connected to the gate of the sixth transistor 318. The eighth transistor 334 includes a first end, a second end, and a gate, wherein the first end is coupled to the second end of the seventh transistor 332, the gate is coupled to the gate of the seventh transistor 332, and the second The end is coupled to the ground. The seventh transistor 332 is a P-type gold oxide half field effect transistor, a P-type junction field effect transistor, or a thin film transistor. The eighth transistor 334 is an N-type gold oxide half field effect transistor, an N-type junction field effect transistor, or a thin film transistor. The circuit operation of the level shifter 300 is detailed below.

When the power is turned on, the second supply voltage Vdd2 is supplied first, and during the transient process in which the first supply voltage Vdd1 is not yet supplied, the fifth transistor 316 and the sixth transistor 318 are both in an off state, at this time, although the node X1 and the node are The voltage of X2 is pulled up to the second supply voltage Vdd2 almost simultaneously, but due to the delay of the buffer 271, the voltage of the node X2 can first turn on the first auxiliary transistor 273, thereby pulling down the voltage of the node X1 to the ground voltage. That is, during the booting process, the first output signal Vout1 and the third output signal Vout3 are first set to a low level signal with a ground voltage, and the second output signal Vout2 is first set to a voltage Vdd2. Level signal.

After the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided, when the input signal Vin is at the high voltage level Vdd1, the input signal Vin turns off the third transistor 322 and turns on the fifth transistor 316 for A second output signal Vout2 having a low voltage level is generated, thereby turning on the second transistor 314 and turning off the first auxiliary transistor 273. In this case, the inverter 390 outputs the internal signal VX3 having a low voltage level, turns on the fourth transistor 324, and turns off the sixth transistor 318 to generate a first output signal Vout1 having a high voltage level Vdd2. The first transistor 312 is turned off. The buffer 271 receives the first output signal Vout1 and outputs a third output signal Vout3 having a high voltage level Vdd2 to the second circuit unit 282. The third output signal Vout3 having the high voltage level Vdd2 can further turn on the second auxiliary transistor 275 to maintain the second output signal Vout2 at a low voltage level.

After the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided, when the input signal Vin is at a low voltage level, the input signal Vin turns on the third transistor 322 and turns off the fifth transistor 316. At this time, the inverter 390 outputs the internal signal VX3 having the high voltage level Vdd1, turns off the fourth transistor 324, and turns on the sixth transistor 318 to generate the first output signal Vout1 with a low voltage level. Further, the first transistor 312 is turned on. When the first transistor 312 and the third transistor 322 are turned on, the second output signal Vout2 having the high voltage level Vdd2 can be generated, thereby turning off the second transistor 314 and turning on the first auxiliary transistor 273. The first output signal Vout1 is maintained at a low voltage level. The buffer 271 receives the first output signal Vout1 and outputs a third output signal Vout3 having a low voltage level to the second circuit unit 282. The third output signal Vout3 having a low voltage level can also turn off the second auxiliary transistor 275.

After the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to operate the level shifter 300, if the first output signal Vout1 is at the high voltage level Vdd2 and the second output signal Vout2 is at the low voltage level, When the supply of the first supply voltage Vdd1 is stopped to perform the power-saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 271, and the high voltage level Vdd2 of the first output signal Vout1 is passed by the second supply voltage Vdd2. The second transistor 314 and the fourth transistor 324 are provided, so that the first output signal Vout1 remains at the high voltage level Vdd2, and the buffer 271 can maintain the high voltage of the third output signal Vout3 according to the first output signal Vout1. Bit Vdd2. At this time, the high voltage level Vdd2 of the third output signal Vout3 turns on the second auxiliary transistor 275, thereby pulling down the second output signal Vout2 to the ground voltage. In other words, after the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, although the fifth transistor 316 is turned off, the first end of the fifth transistor 316 can be turned on via the second auxiliary transistor 275. To the ground. That is, the power saving mode operation does not cause the floating state of the node X2, and the voltage levels of the second output signal Vout2 and the third output signal Vout3 can be maintained, so that the circuit does not malfunction.

In addition, after the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to make the level shifter 300 operate normally, if the first output signal Vout1 is at a low voltage level and the second output signal Vout2 is at a high voltage level Vdd2 When the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 271, and the high voltage level Vdd2 of the second output signal Vout2 is the second supply voltage Vdd2. Provided by the first transistor 312 and the third transistor 322, the second output signal Vout2 remains at the high voltage level Vdd2. At this time, the high voltage level Vdd2 of the second output signal Vout2 turns on the first auxiliary transistor 273, and then pulls the first output signal Vout1 to the ground voltage, and then the buffer 271 maintains the first output signal Vout1. The low voltage level of the three output signals Vout3. In other words, after the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, although the sixth transistor 318 is turned off, the first end of the sixth transistor 318 can be turned on via the first auxiliary transistor 273. To the ground. That is to say, the power saving mode operation does not cause the floating state of the node X1, and the voltage levels of the second output signal Vout2 and the third output signal Vout3 can be maintained, so that the circuit does not malfunction.

In another embodiment, the third transistor 322 can be omitted, that is, the second end of the first transistor 312 can be directly coupled to the first end of the fifth transistor 316. Similarly, the fourth transistor 324 can also be omitted, that is, the second end of the second transistor 314 can be directly coupled to the first end of the sixth transistor 318.

4 is a circuit diagram of a level shifter according to a third embodiment of the present invention. As shown in FIG. 4, the level shifter 400 includes a pre-position shift circuit 410 and an output auxiliary circuit 470. The internal circuit structure of the pre-position shift circuit 410 is the same as that of the pre-position shift circuit 310 shown in FIG. 3, and therefore will not be described again.

The output auxiliary circuit 470 includes a buffer 471, a first auxiliary transistor 473, and a second auxiliary transistor 475. The first auxiliary transistor 473 and the second auxiliary transistor 475 are N-type gold oxide half field effect transistors, N-type junction field effect transistors, or thin film transistors. The buffer 471 includes an input terminal, an output terminal, and a power terminal. The input terminal is coupled to the pre-position shifting circuit 410 to receive the second output signal Vout2, and the output terminal is configured to output the third output signal Vout3. The second supply voltage Vdd2 is received. The circuit structure of the buffer 471 can be the same as that of the buffer 271 including the operational amplifier 361 shown in FIG. The first auxiliary transistor 473 includes a first end, a second end, and a gate. The first end is coupled to the input end of the buffer 471, the second end is coupled to the ground end, and the gate is coupled to the pre-position. The shift circuit 410 receives the first output signal Vout1. The second auxiliary transistor 475 includes a first end, a second end, and a gate. The first end is coupled to the gate of the first auxiliary transistor 473, the second end is coupled to the ground, and the gate is coupled to the buffer. The output of the device 471 receives the third output signal Vout3. The circuit operation of the level shifter 400 is outlined below.

When the power is turned on, the second supply voltage Vdd2 is supplied first, and during the transient process in which the first supply voltage Vdd1 is not yet supplied, the fifth transistor 316 and the sixth transistor 318 are both in an off state, at this time, although the node X1 and the node are The voltage of X2 is pulled up to the second supply voltage Vdd2 at the same time, but due to the delay of the buffer 471, the voltage of the node X1 can first turn on the first auxiliary transistor 473, thereby pulling down the voltage of the node X2 to the ground voltage. That is, during the booting process, the first output signal Vout1 is first set to a high level signal with a voltage Vdd2, and the second output signal Vout2 and the third output signal Vout3 are first set to have a low ground voltage. Level signal.

After the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to operate the level shifter 400, if the first output signal Vout1 is at a low voltage level and the second output signal Vout2 is at a high voltage level Vdd2, When the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 471, and the high voltage level Vdd2 of the second output signal Vout2 is passed by the second supply voltage Vdd2. A transistor 312 and a third transistor 322 are provided, so that the second output signal Vout2 remains at the high voltage level Vdd2, and the buffer 471 maintains the high voltage level of the third output signal Vout3 according to the second output signal Vout2. Vdd2. At this time, the high voltage level Vdd2 of the third output signal Vout3 turns on the second auxiliary transistor 475, thereby pulling down the first output signal Vout1 to the ground voltage. In other words, after the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, although the sixth transistor 318 is turned off, the first end of the sixth transistor 318 can be turned on via the second auxiliary transistor 475. To the ground. That is, the power saving mode operation does not cause the floating state of the node X1, and the voltage levels of the first output signal Vout1 and the third output signal Vout3 can be maintained, so that the circuit does not malfunction.

In addition, after the first supply voltage Vdd1 and the second supply voltage Vdd2 are provided to make the level shifter 300 operate normally, if the first output signal Vout1 is at the high voltage level Vdd2 and the second output signal Vout2 is at the low voltage level When the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, the second supply voltage Vdd2 is still supplied to the buffer 471, and the high voltage level Vdd2 of the first output signal Vout1 is determined by the second supply voltage Vdd2. Provided by the second transistor 314 and the fourth transistor 324, the first output signal Vout1 remains at the high voltage level Vdd2. At this time, the high voltage level Vdd2 of the first output signal Vout1 turns on the first auxiliary transistor 473, and then pulls the second output signal Vout2 to the ground voltage, and then the buffer 471 maintains the second output signal Vout2 according to the second output signal Vout2. The low voltage level of the three output signals Vout3. In other words, after the supply of the first supply voltage Vdd1 is stopped to perform the power saving mode operation, although the fifth transistor 316 is turned off, the first end of the fifth transistor 316 can be turned on via the first auxiliary transistor 473. To the ground. That is to say, the power saving mode operation does not cause the floating state of the node X2, and the voltage levels of the first output signal Vout1 and the third output signal Vout3 can be maintained, so that the circuit does not malfunction.

Figure 5 is a circuit diagram of a level shifter according to a fourth embodiment of the present invention. As shown in FIG. 5, the level shifter 500 includes a pre-position shift circuit 510 and an output auxiliary circuit 570. The internal circuit structure of the pre-position shift circuit 510 is the same as that of the pre-position shift circuit 310 shown in FIG. 3, and therefore will not be described again.

The output auxiliary circuit 570 further includes a transfer gate 274 and a transfer gate 276 as compared to the output auxiliary circuit 370 shown in FIG. The transfer gate 274 and the transfer gate 276 are complementary metal oxide semiconductor transmission gates (Complementary Metal Oxide Semiconductor Transmission Gate). The transmission gate 274 includes a first end, a second end, and a gate, wherein the first end is coupled to the pre-position shifting circuit 510 to receive the second output signal Vout2, and the second end is coupled to the first auxiliary transistor 273. The gate is used to receive the gate signal SG3. The gate signal SG3 is an internal signal VX3 or a first supply voltage Vdd1. The transmission gate 276 includes a first end, a second end, and a gate, wherein the first end is coupled to the output end of the buffer 271, the second end is coupled to the gate of the second auxiliary transistor 275, and the gate is configured to receive Gate signal SG4. The gate signal SG4 is the input signal Vin or the first supply voltage Vdd1.

In providing the first supply voltage Vdd1 and the second supply voltage Vdd2 to cause the level shifter 500 to operate normally, the operational function of the transfer gate 274 is to maintain the first auxiliary transistor 273 in an off state to reduce power consumption. Similarly, the operational function of the transfer gate 276 is to maintain the second auxiliary transistor 275 in an off state to reduce power consumption. That is, the first auxiliary transistor 273 and the second auxiliary transistor 275 are operated to maintain the second output signal Vout2 and the third output signal Vout3 only after the supply of the first supply voltage Vdd1 is stopped to enter the power-saving operation mode. Voltage level to avoid circuit malfunction.

Figure 6 is a circuit diagram of a level shifter according to a fifth embodiment of the present invention. As shown in FIG. 6, the level shifter 600 includes a pre-position shift circuit 610 and an output assist circuit 670. The internal circuit structure of the pre-position shift circuit 610 is the same as that of the pre-position shift circuit 310 shown in FIG. 3, and therefore will not be described again.

The output auxiliary circuit 670 further includes a transfer gate 474 and a transfer gate 476 as compared to the output auxiliary circuit 470 shown in FIG. The transfer gate 474 and the transfer gate 476 are complementary gold-oxygen semi-transmission gates. The transmission gate 474 includes a first end, a second end, and a gate. The first end is coupled to the pre-position shifting circuit 610 to receive the first output signal Vout1, and the second end is coupled to the first auxiliary transistor 473. The gate is used to receive the gate signal SGx3. The gate signal SGx3 is an input signal Vin or a first supply voltage Vdd1. The transmission gate 476 includes a first end, a second end, and a gate, wherein the first end is coupled to the output end of the buffer 471, the second end is coupled to the gate of the second auxiliary transistor 475, and the gate is configured to receive Gate signal SGx4. The gate signal SGx4 is the internal signal VX3 or the first supply voltage Vdd1.

In providing the first supply voltage Vdd1 and the second supply voltage Vdd2 to cause the level shifter 600 to operate normally, the operational function of the transfer gate 474 is to maintain the first auxiliary transistor 473 in an off state to reduce power consumption. Similarly, the operational function of the transfer gate 476 is to maintain the second auxiliary transistor 475 in an off state to reduce power consumption. That is, the first auxiliary transistor 473 and the second auxiliary transistor 475 operate to maintain the first output signal Vout1 and the third output signal Vout3 only after the supply of the first supply voltage Vdd1 is stopped to enter the power-saving operation mode. Voltage level to avoid circuit malfunction.

In summary, the level shifter of the present invention can prevent any node from floating in an undesired power supply condition to ensure normal operation of the circuit. In addition, if the supply voltage of the pre-stage circuit unit is stopped for performing the power-saving mode operation, the voltage level of the output signal can also be maintained, that is, the level shifter of the present invention is suitable for performing the power-saving operation mode. Circuit system.

While the present invention has been described above by way of example, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500, 600. . . Level shifter

112, 312. . . First transistor

114, 314. . . Second transistor

116, 322. . . Third transistor

118, 324. . . Fourth transistor

120, 316. . . Fifth transistor

181, 281. . . First circuit unit

182, 282. . . Second circuit unit

190, 390. . . inverter

210, 310, 410, 510, 610. . . Pre-position shift circuit

270, 370, 470, 570, 670. . . Output auxiliary circuit

271, 471. . . buffer

273, 473. . . First auxiliary transistor

274, 276, 474, 476. . . Transmission gate

275, 475. . . Second auxiliary transistor

318. . . Sixth transistor

332. . . Seventh transistor

334. . . Eighth transistor

361. . . Operational Amplifier

A, B, X1, X2. . . node

Vdd1. . . First supply voltage

Vdd2. . . Second supply voltage

Vin. . . Input signal

Vout, Vout1. . . First output signal

Vout2, Voutb. . . Second output signal

Vout3. . . Third output signal

VX3. . . Internal signal

Figure 1 is a circuit diagram showing a conventional level shifter.

Fig. 2 is a schematic view showing a level shifter of the first embodiment of the present invention.

3 is a circuit diagram of a level shifter according to a second embodiment of the present invention.

4 is a circuit diagram of a level shifter according to a third embodiment of the present invention.

Figure 5 is a circuit diagram of a level shifter according to a fourth embodiment of the present invention.

Figure 6 is a circuit diagram of a level shifter according to a fifth embodiment of the present invention.

200. . . Level shifter

210. . . Pre-position shift circuit

270. . . Output auxiliary circuit

271. . . buffer

273. . . First auxiliary transistor

275. . . Second auxiliary transistor

281. . . First circuit unit

282. . . Second circuit unit

Vdd1. . . First supply voltage

Vdd2. . . Second supply voltage

Vin. . . Input signal

Vout1. . . First output signal

Vout2. . . Second output signal

Vout3. . . Third output signal

Claims (17)

A level shifter suitable for a power saving operation mode, comprising: a pre-position shift circuit for receiving an input signal having a first voltage operating range, and according to a first supply voltage and a The second supply voltage converts the input signal into a first output signal having a second voltage operating range and a second output signal inverted to the first output signal; and an output auxiliary circuit coupled to the front Positioning a quasi-shift circuit for maintaining a voltage level of the first output signal according to the second supply voltage, the output auxiliary circuit comprising: a buffer including an input end of the buffer, and an output of the buffer And the power supply end of the buffer, wherein the input end of the buffer is coupled to the pre-position shifting circuit to receive the first output signal, and the output end of the buffer is configured to output a third output signal, The power supply end of the buffer is configured to receive the second supply voltage, and a voltage level of the third output signal is substantially the same as a voltage level of a first output voltage; a first transistor includes the first a transistor a first end, a second end of the first transistor, and a gate of the first transistor, wherein a first end of the first transistor is coupled to an input end of the buffer, and the first transistor is The second transistor is coupled to the grounding end, the gate of the first transistor is coupled to the pre-position shifting circuit to receive the second output signal; and the second transistor includes the second transistor a first end, a second end of the second transistor, and a gate of the second transistor, wherein the first end of the second transistor is coupled to the gate of the first transistor, and the second transistor Second end coupling Connected to the ground, the gate of the second transistor is coupled to the output end of the buffer; and a transmission gate includes a first end of the transmission gate, a second end of the transmission gate, and the transmission gate a gate, wherein the first end of the transmission gate is coupled to the output end of the buffer, the second end of the transmission gate is coupled to the gate of the second transistor, and the gate of the transmission gate is configured to receive the gate Input signal or the first supply voltage. A level shifter suitable for a power saving operation mode, comprising: a pre-position shift circuit for receiving an input signal having a first voltage operating range, and according to a first supply voltage and a The second supply voltage converts the input signal into a first output signal having a second voltage operating range and a second output signal inverted to the first output signal; and an output auxiliary circuit coupled to the front Positioning a quasi-shift circuit for maintaining a voltage level of the first output signal according to the second supply voltage, the output auxiliary circuit comprising: a buffer including an input end of the buffer, and an output of the buffer And the power supply end of the buffer, wherein the input end of the buffer is coupled to the pre-position shifting circuit to receive the first output signal, and the output end of the buffer is configured to output a third output signal, The power supply end of the buffer is configured to receive the second supply voltage, and a voltage level of the third output signal is substantially the same as a voltage level of a first output voltage; a first transistor includes the first a transistor A first end, a second end of the gate of the first transistor and the first electrode of the transistor, wherein the first transistor of The first end is coupled to the input end of the buffer, the second end of the first transistor is coupled to a ground, and the gate of the first transistor is coupled to the pre-position shift circuit for receiving a second output signal; a second transistor comprising a first end of the second transistor, a second end of the second transistor, and a gate of the second transistor, wherein the second transistor One end is coupled to the gate of the first transistor, the second end of the second transistor is coupled to the ground, the gate of the second transistor is coupled to the output of the buffer; The transmission gate includes a first end of the transmission gate, a second end of the transmission gate, and a gate of the transmission gate, wherein the first end of the transmission gate is coupled to the first end of the second transistor, the transmission The second end of the gate is coupled to the gate of the first transistor, and the gate of the gate is configured to receive the first supply voltage or an inverted signal of the input signal. The level shifter of claim 1 or 2, wherein the first transistor and the second transistor system are N-type Metal Oxide Semiconductor Field Effect Transistors, N N-type Junction Field Effect Transistor (N-JFET), or Thin Film Transistor. The level shifter of claim 1 or 2, wherein the buffer includes an operational amplifier (Operational Amplifier), the operational amplifier includes: a positive input terminal of the operational amplifier coupled to the pre-position shift Bit circuit to receive the first An output signal of the operational amplifier is configured to output the third output signal; a negative input end of the operational amplifier is coupled to an output end of the operational amplifier; and a power supply end of the operational amplifier is configured to receive the output signal Second supply voltage. A level shifter suitable for a power saving operation mode, comprising: a pre-position shift circuit for receiving an input signal having a first voltage operating range, and according to a first supply voltage and a The second supply voltage converts the input signal into a first output signal having a second voltage operating range and a second output signal inverted to the first output signal; and an output auxiliary circuit coupled to the front Positioning a quasi-shift circuit for maintaining a voltage level of the first output signal according to the second supply voltage, the output auxiliary circuit comprising: a first transistor, including a first end of the first transistor, a second end of the first transistor and a gate of the first transistor, wherein the first end of the first transistor is coupled to the pre-position shift circuit to receive the second output signal, the first a second end of the transistor is coupled to a ground, a gate of the first transistor is coupled to the pre-position shift circuit to receive the first output signal, and a second transistor includes the a first end of the second transistor, the second transistor a second end and a gate of the second transistor, wherein the first end of the second transistor is coupled to the gate of the first transistor, and the second end of the second transistor is coupled to the ground end; And a buffer including an input of the buffer, an output of the buffer, and the buffer The power supply end, wherein the input end of the buffer is coupled to the first end of the first transistor, and the output end of the buffer is coupled to the gate of the second transistor, and the power end of the buffer is used Receiving the second supply voltage. The level shifter of claim 5, wherein the first transistor and the second transistor system are N-type gold oxide half field effect transistors, N-type junction field effect transistors, or thin film transistors. The level shifter of claim 5, wherein the output auxiliary circuit further comprises: a transmission gate comprising a first end of the transmission gate, a second end of the transmission gate, and a gate of the transmission gate, wherein The first end of the transmission gate is coupled to the output end of the buffer, the second end of the transmission gate is coupled to the gate of the second transistor, and the gate of the transmission gate is configured to receive the first supply voltage Or one of the input signals is an inverted signal. The level shifter of claim 5, wherein the output auxiliary circuit further comprises: a transmission gate comprising a first end of the transmission gate, a second end of the transmission gate, and a gate of the transmission gate, wherein The first end of the transmission gate is coupled to the first end of the second transistor, the second end of the transmission gate is coupled to the gate of the first transistor, and the gate of the transmission gate is configured to receive the input Signal or the first supply voltage. The level shifter of claim 5, wherein the buffer includes an operational amplifier (Operational Amplifier), the operational amplifier includes: a positive input terminal of the operational amplifier coupled to the first of the first transistor The output end of the operational amplifier is coupled to the gate of the second transistor; The negative input terminal of the operational amplifier is coupled to the output end of the operational amplifier; and the power terminal of the operational amplifier is configured to receive the second supply voltage. A level shifter suitable for a power saving operation mode, comprising: a pre-position shift circuit for receiving an input signal having a first voltage operating range, and according to a first supply voltage and a The second supply voltage converts the input signal into a first output signal having a second voltage operating range and a second output signal inverted to the first output signal; and an output auxiliary circuit coupled to the front Positioning a quasi-shift circuit for maintaining a voltage level of the first output signal according to the second supply voltage, the pre-position shift circuit comprising: a first transistor, including the first transistor a first end, a second end of the first transistor, and a gate of the first transistor, wherein a first end of the first transistor is configured to receive the second supply voltage; a second transistor includes the a first end of the second transistor, a second end of the second transistor, and a gate of the second transistor, wherein the first end of the second transistor is configured to receive the second supply voltage; a transistor comprising a first end of the third transistor, the third a second end of the crystal and a gate of the third transistor, wherein the first end of the third transistor is coupled to the second end of the first transistor and the gate of the second transistor, the third The second end of the transistor is coupled to a ground, the gate of the third transistor is configured to receive the input signal, the first end is configured to output the second output signal, and the fourth transistor is configured to include the second output signal a first end of the fourth transistor, and a second end of the fourth transistor And a gate of the fourth transistor, wherein the first end of the fourth transistor is coupled to the second end of the second transistor and the gate of the first transistor, the fourth transistor The second end is coupled to the ground, the first end of the fourth transistor is configured to output the first output signal, and an inverter includes an input end of the inverter and an output end of the inverter And an input end of the inverter, wherein an input end of the inverter is configured to receive the input signal, and an output end of the inverter is coupled to a gate of the fourth transistor, and a power end of the inverter Receiving the first supply voltage, the inverter includes: a fifth transistor, including a first end of the fifth transistor, a second end of the fifth transistor, and a gate of the fifth transistor The first end of the fifth transistor is configured to receive the first supply voltage, the gate of the fifth transistor is configured to receive the input signal, and the second end of the fifth transistor is coupled to the fourth a gate of the transistor; and a sixth transistor comprising a first end of the sixth transistor, a second end of the sixth transistor, and a gate of the sixth transistor, wherein the first end of the sixth transistor is coupled to the second end of the fifth transistor, and the gate of the sixth transistor is coupled to the gate of the fifth transistor The second end of the sixth transistor is coupled to the ground. The level shifter of claim 10, wherein the first transistor and the second transistor system are a P-type MOS field effect transistor, a P-type junction field effect transistor, or a thin film transistor. The level shifter of claim 10, wherein the third transistor and the fourth transistor system are N-type gold oxide half field effect transistors, N-type junction field effect transistors, or thin film transistors. The level shifter of claim 10, wherein the fifth electro-crystalline system is a P-type MOS field effect transistor, a P-type junction field effect transistor, or a thin film transistor. The level shifter of claim 10, wherein the sixth electro-crystalline system is an N-type MOS field effect transistor, an N-type junction field effect transistor, or a thin film transistor. The level shifter of claim 10, wherein the pre-position shifting circuit further comprises: a seventh transistor comprising a first end of the seventh transistor and a second end of the seventh transistor And a gate of the seventh transistor, wherein the first end of the seventh transistor is coupled to the second end of the first transistor, and the gate of the seventh transistor is configured to receive the input signal, a second end of the seventh transistor is coupled to the first end of the third transistor; and an eighth transistor includes a first end of the eighth transistor, a second end of the eighth transistor, and the a gate of the eighth transistor, wherein the first end of the eighth transistor is coupled to the second end of the second transistor, and the second end of the eighth transistor is coupled to the fourth transistor At one end, the gate of the eighth transistor is coupled to the output of the inverter. The level shifter according to claim 15, wherein the seventh transistor and the eighth electro-crystal system are P-type MOS field-effect transistors, P-type junction field effect transistors, or thin film electro-crystals. body. 2. The level shifter of 2, 5 or 10, wherein the output auxiliary circuit is further configured to maintain a voltage level of the second output signal according to the second supply voltage.